drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42
  43 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  44
  45 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  46 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  47 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  48 static int uvd_v7_0_start(struct amdgpu_device *adev);
  49 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  50 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  51
  52 static int amdgpu_ih_clientid_uvds[] = {
  53         SOC15_IH_CLIENTID_UVD,
  54         SOC15_IH_CLIENTID_UVD1
  55 };
  56
  57 /**
  58  * uvd_v7_0_ring_get_rptr - get read pointer
  59  *
  60  * @ring: amdgpu_ring pointer
  61  *
  62  * Returns the current hardware read pointer
  63  */
  64 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  65 {
  66         struct amdgpu_device *adev = ring->adev;
  67
  68         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  69 }
  70
  71 /**
  72  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  73  *
  74  * @ring: amdgpu_ring pointer
  75  *
  76  * Returns the current hardware enc read pointer
  77  */
  78 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  79 {
  80         struct amdgpu_device *adev = ring->adev;
  81
  82         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  83                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  84         else
  85                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  86 }
  87
  88 /**
  89  * uvd_v7_0_ring_get_wptr - get write pointer
  90  *
  91  * @ring: amdgpu_ring pointer
  92  *
  93  * Returns the current hardware write pointer
  94  */
  95 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
  96 {
  97         struct amdgpu_device *adev = ring->adev;
  98
  99         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 100 }
 101
 102 /**
 103  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 104  *
 105  * @ring: amdgpu_ring pointer
 106  *
 107  * Returns the current hardware enc write pointer
 108  */
 109 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 110 {
 111         struct amdgpu_device *adev = ring->adev;
 112
 113         if (ring->use_doorbell)
 114                 return adev->wb.wb[ring->wptr_offs];
 115
 116         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 117                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 118         else
 119                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 120 }
 121
 122 /**
 123  * uvd_v7_0_ring_set_wptr - set write pointer
 124  *
 125  * @ring: amdgpu_ring pointer
 126  *
 127  * Commits the write pointer to the hardware
 128  */
 129 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 130 {
 131         struct amdgpu_device *adev = ring->adev;
 132
 133         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 134 }
 135
 136 /**
 137  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 138  *
 139  * @ring: amdgpu_ring pointer
 140  *
 141  * Commits the enc write pointer to the hardware
 142  */
 143 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 144 {
 145         struct amdgpu_device *adev = ring->adev;
 146
 147         if (ring->use_doorbell) {
 148                 /* XXX check if swapping is necessary on BE */
 149                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 150                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 151                 return;
 152         }
 153
 154         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 155                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 156                         lower_32_bits(ring->wptr));
 157         else
 158                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 159                         lower_32_bits(ring->wptr));
 160 }
 161
 162 /**
 163  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 164  *
 165  * @ring: the engine to test on
 166  *
 167  */
 168 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 172         unsigned i;
 173         int r;
 174
 175         if (amdgpu_sriov_vf(adev))
 176                 return 0;
 177
 178         r = amdgpu_ring_alloc(ring, 16);
 179         if (r) {
 180                 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
 181                           ring->me, ring->idx, r);
 182                 return r;
 183         }
 184         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 185         amdgpu_ring_commit(ring);
 186
 187         for (i = 0; i < adev->usec_timeout; i++) {
 188                 if (amdgpu_ring_get_rptr(ring) != rptr)
 189                         break;
 190                 DRM_UDELAY(1);
 191         }
 192
 193         if (i < adev->usec_timeout) {
 194                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
 195                          ring->me, ring->idx, i);
 196         } else {
 197                 DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
 198                           ring->me, ring->idx);
 199                 r = -ETIMEDOUT;
 200         }
 201
 202         return r;
 203 }
 204
 205 /**
 206  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 207  *
 208  * @adev: amdgpu_device pointer
 209  * @ring: ring we should submit the msg to
 210  * @handle: session handle to use
 211  * @fence: optional fence to return
 212  *
 213  * Open up a stream for HW test
 214  */
 215 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 216                                        struct dma_fence **fence)
 217 {
 218         const unsigned ib_size_dw = 16;
 219         struct amdgpu_job *job;
 220         struct amdgpu_ib *ib;
 221         struct dma_fence *f = NULL;
 222         uint64_t dummy;
 223         int i, r;
 224
 225         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 226         if (r)
 227                 return r;
 228
 229         ib = &job->ibs[0];
 230         dummy = ib->gpu_addr + 1024;
 231
 232         ib->length_dw = 0;
 233         ib->ptr[ib->length_dw++] = 0x00000018;
 234         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 235         ib->ptr[ib->length_dw++] = handle;
 236         ib->ptr[ib->length_dw++] = 0x00000000;
 237         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 238         ib->ptr[ib->length_dw++] = dummy;
 239
 240         ib->ptr[ib->length_dw++] = 0x00000014;
 241         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 242         ib->ptr[ib->length_dw++] = 0x0000001c;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244         ib->ptr[ib->length_dw++] = 0x00000000;
 245
 246         ib->ptr[ib->length_dw++] = 0x00000008;
 247         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 248
 249         for (i = ib->length_dw; i < ib_size_dw; ++i)
 250                 ib->ptr[i] = 0x0;
 251
 252         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 253         job->fence = dma_fence_get(f);
 254         if (r)
 255                 goto err;
 256
 257         amdgpu_job_free(job);
 258         if (fence)
 259                 *fence = dma_fence_get(f);
 260         dma_fence_put(f);
 261         return 0;
 262
 263 err:
 264         amdgpu_job_free(job);
 265         return r;
 266 }
 267
 268 /**
 269  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 270  *
 271  * @adev: amdgpu_device pointer
 272  * @ring: ring we should submit the msg to
 273  * @handle: session handle to use
 274  * @fence: optional fence to return
 275  *
 276  * Close up a stream for HW test or if userspace failed to do so
 277  */
 278 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 279                                  bool direct, struct dma_fence **fence)
 280 {
 281         const unsigned ib_size_dw = 16;
 282         struct amdgpu_job *job;
 283         struct amdgpu_ib *ib;
 284         struct dma_fence *f = NULL;
 285         uint64_t dummy;
 286         int i, r;
 287
 288         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 289         if (r)
 290                 return r;
 291
 292         ib = &job->ibs[0];
 293         dummy = ib->gpu_addr + 1024;
 294
 295         ib->length_dw = 0;
 296         ib->ptr[ib->length_dw++] = 0x00000018;
 297         ib->ptr[ib->length_dw++] = 0x00000001;
 298         ib->ptr[ib->length_dw++] = handle;
 299         ib->ptr[ib->length_dw++] = 0x00000000;
 300         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 301         ib->ptr[ib->length_dw++] = dummy;
 302
 303         ib->ptr[ib->length_dw++] = 0x00000014;
 304         ib->ptr[ib->length_dw++] = 0x00000002;
 305         ib->ptr[ib->length_dw++] = 0x0000001c;
 306         ib->ptr[ib->length_dw++] = 0x00000000;
 307         ib->ptr[ib->length_dw++] = 0x00000000;
 308
 309         ib->ptr[ib->length_dw++] = 0x00000008;
 310         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 311
 312         for (i = ib->length_dw; i < ib_size_dw; ++i)
 313                 ib->ptr[i] = 0x0;
 314
 315         if (direct) {
 316                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 317                 job->fence = dma_fence_get(f);
 318                 if (r)
 319                         goto err;
 320
 321                 amdgpu_job_free(job);
 322         } else {
 323                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 324                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 325                 if (r)
 326                         goto err;
 327         }
 328
 329         if (fence)
 330                 *fence = dma_fence_get(f);
 331         dma_fence_put(f);
 332         return 0;
 333
 334 err:
 335         amdgpu_job_free(job);
 336         return r;
 337 }
 338
 339 /**
 340  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 341  *
 342  * @ring: the engine to test on
 343  *
 344  */
 345 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 346 {
 347         struct dma_fence *fence = NULL;
 348         long r;
 349
 350         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 351         if (r) {
 352                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 353                 goto error;
 354         }
 355
 356         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 357         if (r) {
 358                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 359                 goto error;
 360         }
 361
 362         r = dma_fence_wait_timeout(fence, false, timeout);
 363         if (r == 0) {
 364                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 365                 r = -ETIMEDOUT;
 366         } else if (r < 0) {
 367                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 368         } else {
 369                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 370                 r = 0;
 371         }
 372 error:
 373         dma_fence_put(fence);
 374         return r;
 375 }
 376
 377 static int uvd_v7_0_early_init(void *handle)
 378 {
 379         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 380         if (adev->asic_type == CHIP_VEGA20)
 381                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 382         else
 383                 adev->uvd.num_uvd_inst = 1;
 384
 385         if (amdgpu_sriov_vf(adev))
 386                 adev->uvd.num_enc_rings = 1;
 387         else
 388                 adev->uvd.num_enc_rings = 2;
 389         uvd_v7_0_set_ring_funcs(adev);
 390         uvd_v7_0_set_enc_ring_funcs(adev);
 391         uvd_v7_0_set_irq_funcs(adev);
 392
 393         return 0;
 394 }
 395
 396 static int uvd_v7_0_sw_init(void *handle)
 397 {
 398         struct amdgpu_ring *ring;
 399         struct drm_sched_rq *rq;
 400         int i, j, r;
 401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 402
 403         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 404                 /* UVD TRAP */
 405                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], 124, &adev->uvd.inst[j].irq);
 406                 if (r)
 407                         return r;
 408
 409                 /* UVD ENC TRAP */
 410                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 411                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + 119, &adev->uvd.inst[j].irq);
 412                         if (r)
 413                                 return r;
 414                 }
 415         }
 416
 417         r = amdgpu_uvd_sw_init(adev);
 418         if (r)
 419                 return r;
 420
 421         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 422                 const struct common_firmware_header *hdr;
 423                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 424                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 425                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 426                 adev->firmware.fw_size +=
 427                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 428                 DRM_INFO("PSP loading UVD firmware\n");
 429         }
 430
 431         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 432                 ring = &adev->uvd.inst[j].ring_enc[0];
 433                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 434                 r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst[j].entity_enc,
 435                                           rq, NULL);
 436                 if (r) {
 437                         DRM_ERROR("(%d)Failed setting up UVD ENC run queue.\n", j);
 438                         return r;
 439                 }
 440         }
 441
 442         r = amdgpu_uvd_resume(adev);
 443         if (r)
 444                 return r;
 445
 446         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 447                 if (!amdgpu_sriov_vf(adev)) {
 448                         ring = &adev->uvd.inst[j].ring;
 449                         sprintf(ring->name, "uvd<%d>", j);
 450                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 451                         if (r)
 452                                 return r;
 453                 }
 454
 455                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 456                         ring = &adev->uvd.inst[j].ring_enc[i];
 457                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 458                         if (amdgpu_sriov_vf(adev)) {
 459                                 ring->use_doorbell = true;
 460
 461                                 /* currently only use the first enconding ring for
 462                                  * sriov, so set unused location for other unused rings.
 463                                  */
 464                                 if (i == 0)
 465                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 466                                 else
 467                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 468                         }
 469                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 470                         if (r)
 471                                 return r;
 472                 }
 473         }
 474
 475         r = amdgpu_virt_alloc_mm_table(adev);
 476         if (r)
 477                 return r;
 478
 479         return r;
 480 }
 481
 482 static int uvd_v7_0_sw_fini(void *handle)
 483 {
 484         int i, j, r;
 485         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 486
 487         amdgpu_virt_free_mm_table(adev);
 488
 489         r = amdgpu_uvd_suspend(adev);
 490         if (r)
 491                 return r;
 492
 493         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 494                 drm_sched_entity_fini(&adev->uvd.inst[j].ring_enc[0].sched, &adev->uvd.inst[j].entity_enc);
 495
 496                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 497                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 498         }
 499         return amdgpu_uvd_sw_fini(adev);
 500 }
 501
 502 /**
 503  * uvd_v7_0_hw_init - start and test UVD block
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Initialize the hardware, boot up the VCPU and do some testing
 508  */
 509 static int uvd_v7_0_hw_init(void *handle)
 510 {
 511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 512         struct amdgpu_ring *ring;
 513         uint32_t tmp;
 514         int i, j, r;
 515
 516         if (amdgpu_sriov_vf(adev))
 517                 r = uvd_v7_0_sriov_start(adev);
 518         else
 519                 r = uvd_v7_0_start(adev);
 520         if (r)
 521                 goto done;
 522
 523         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 524                 ring = &adev->uvd.inst[j].ring;
 525
 526                 if (!amdgpu_sriov_vf(adev)) {
 527                         ring->ready = true;
 528                         r = amdgpu_ring_test_ring(ring);
 529                         if (r) {
 530                                 ring->ready = false;
 531                                 goto done;
 532                         }
 533
 534                         r = amdgpu_ring_alloc(ring, 10);
 535                         if (r) {
 536                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 537                                 goto done;
 538                         }
 539
 540                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 541                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 542                         amdgpu_ring_write(ring, tmp);
 543                         amdgpu_ring_write(ring, 0xFFFFF);
 544
 545                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 546                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 547                         amdgpu_ring_write(ring, tmp);
 548                         amdgpu_ring_write(ring, 0xFFFFF);
 549
 550                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 551                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 552                         amdgpu_ring_write(ring, tmp);
 553                         amdgpu_ring_write(ring, 0xFFFFF);
 554
 555                         /* Clear timeout status bits */
 556                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 557                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 558                         amdgpu_ring_write(ring, 0x8);
 559
 560                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 561                                 mmUVD_SEMA_CNTL), 0));
 562                         amdgpu_ring_write(ring, 3);
 563
 564                         amdgpu_ring_commit(ring);
 565                 }
 566
 567                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 568                         ring = &adev->uvd.inst[j].ring_enc[i];
 569                         ring->ready = true;
 570                         r = amdgpu_ring_test_ring(ring);
 571                         if (r) {
 572                                 ring->ready = false;
 573                                 goto done;
 574                         }
 575                 }
 576         }
 577 done:
 578         if (!r)
 579                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 580
 581         return r;
 582 }
 583
 584 /**
 585  * uvd_v7_0_hw_fini - stop the hardware block
 586  *
 587  * @adev: amdgpu_device pointer
 588  *
 589  * Stop the UVD block, mark ring as not ready any more
 590  */
 591 static int uvd_v7_0_hw_fini(void *handle)
 592 {
 593         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 594         int i;
 595
 596         if (!amdgpu_sriov_vf(adev))
 597                 uvd_v7_0_stop(adev);
 598         else {
 599                 /* full access mode, so don't touch any UVD register */
 600                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 601         }
 602
 603         for (i = 0; i < adev->uvd.num_uvd_inst; ++i)
 604                 adev->uvd.inst[i].ring.ready = false;
 605
 606         return 0;
 607 }
 608
 609 static int uvd_v7_0_suspend(void *handle)
 610 {
 611         int r;
 612         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 613
 614         r = uvd_v7_0_hw_fini(adev);
 615         if (r)
 616                 return r;
 617
 618         return amdgpu_uvd_suspend(adev);
 619 }
 620
 621 static int uvd_v7_0_resume(void *handle)
 622 {
 623         int r;
 624         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 625
 626         r = amdgpu_uvd_resume(adev);
 627         if (r)
 628                 return r;
 629
 630         return uvd_v7_0_hw_init(adev);
 631 }
 632
 633 /**
 634  * uvd_v7_0_mc_resume - memory controller programming
 635  *
 636  * @adev: amdgpu_device pointer
 637  *
 638  * Let the UVD memory controller know it's offsets
 639  */
 640 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 641 {
 642         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 643         uint32_t offset;
 644         int i;
 645
 646         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 647                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 648                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 649                                 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 650                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 651                                 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 652                         offset = 0;
 653                 } else {
 654                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 655                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 656                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 657                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 658                         offset = size;
 659                 }
 660
 661                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 662                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 663                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 664
 665                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 666                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 667                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 668                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 669                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 670                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 671
 672                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 673                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 674                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 675                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 676                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 677                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 678                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 679
 680                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 681                                 adev->gfx.config.gb_addr_config);
 682                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 683                                 adev->gfx.config.gb_addr_config);
 684                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 685                                 adev->gfx.config.gb_addr_config);
 686
 687                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 688         }
 689 }
 690
 691 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 692                                 struct amdgpu_mm_table *table)
 693 {
 694         uint32_t data = 0, loop;
 695         uint64_t addr = table->gpu_addr;
 696         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 697         uint32_t size;
 698         int i;
 699
 700         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 701
 702         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 703         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 704         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 705
 706         /* 2, update vmid of descriptor */
 707         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 708         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 709         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 710         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 711
 712         /* 3, notify mmsch about the size of this descriptor */
 713         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 714
 715         /* 4, set resp to zero */
 716         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 717
 718         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 719                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 720                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 721                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 722                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 723         }
 724         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 725         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 726
 727         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 728         loop = 1000;
 729         while ((data & 0x10000002) != 0x10000002) {
 730                 udelay(10);
 731                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 732                 loop--;
 733                 if (!loop)
 734                         break;
 735         }
 736
 737         if (!loop) {
 738                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 739                 return -EBUSY;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 746 {
 747         struct amdgpu_ring *ring;
 748         uint32_t offset, size, tmp;
 749         uint32_t table_size = 0;
 750         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 751         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 752         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 753         struct mmsch_v1_0_cmd_end end = { {0} };
 754         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 755         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 756         uint8_t i = 0;
 757
 758         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 759         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 760         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 761         end.cmd_header.command_type = MMSCH_COMMAND__END;
 762
 763         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 764                 header->version = MMSCH_VERSION;
 765                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 766
 767                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 768                         header->uvd_table_offset = header->header_size;
 769                 else
 770                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 771
 772                 init_table += header->uvd_table_offset;
 773
 774                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 775                         ring = &adev->uvd.inst[i].ring;
 776                         ring->wptr = 0;
 777                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 778
 779                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 780                                                            0xFFFFFFFF, 0x00000004);
 781                         /* mc resume*/
 782                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 783                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 784                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 785                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 786                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 787                                 offset = 0;
 788                         } else {
 789                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 790                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 791                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 792                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 793                                 offset = size;
 794                         }
 795
 796                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 797                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 798                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 799
 800                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 801                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 802                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 803                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 804                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 805                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 806
 807                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 808                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 809                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 810                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 811                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 812                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 813                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 814
 815                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 816                         /* mc resume end*/
 817
 818                         /* disable clock gating */
 819                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 820                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 821
 822                         /* disable interupt */
 823                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 824                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 825
 826                         /* stall UMC and register bus before resetting VCPU */
 827                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 828                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 829                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 830
 831                         /* put LMI, VCPU, RBC etc... into reset */
 832                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 833                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 834                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 835                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 836                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 837                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 838                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 839                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 840                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 841
 842                         /* initialize UVD memory controller */
 843                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 844                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 845                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 846                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 847                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 848                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 849                                                                0x00100000L));
 850
 851                         /* take all subblocks out of reset, except VCPU */
 852                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 853                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 854
 855                         /* enable VCPU clock */
 856                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 857                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 858
 859                         /* enable master interrupt */
 860                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 861                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 862                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 863
 864                         /* clear the bit 4 of UVD_STATUS */
 865                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 866                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 867
 868                         /* force RBC into idle state */
 869                         size = order_base_2(ring->ring_size);
 870                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 871                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 872                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 873
 874                         ring = &adev->uvd.inst[i].ring_enc[0];
 875                         ring->wptr = 0;
 876                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 877                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 878                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 879
 880                         /* boot up the VCPU */
 881                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 882
 883                         /* enable UMC */
 884                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 885                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 886
 887                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 888                 }
 889                 /* add end packet */
 890                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 891                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 892                 header->uvd_table_size = table_size;
 893
 894         }
 895         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 896 }
 897
 898 /**
 899  * uvd_v7_0_start - start UVD block
 900  *
 901  * @adev: amdgpu_device pointer
 902  *
 903  * Setup and start the UVD block
 904  */
 905 static int uvd_v7_0_start(struct amdgpu_device *adev)
 906 {
 907         struct amdgpu_ring *ring;
 908         uint32_t rb_bufsz, tmp;
 909         uint32_t lmi_swap_cntl;
 910         uint32_t mp_swap_cntl;
 911         int i, j, k, r;
 912
 913         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 914                 /* disable DPG */
 915                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 916                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 917         }
 918
 919         /* disable byte swapping */
 920         lmi_swap_cntl = 0;
 921         mp_swap_cntl = 0;
 922
 923         uvd_v7_0_mc_resume(adev);
 924
 925         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 926                 ring = &adev->uvd.inst[k].ring;
 927                 /* disable clock gating */
 928                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 929                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 930
 931                 /* disable interupt */
 932                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 933                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 934
 935                 /* stall UMC and register bus before resetting VCPU */
 936                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 937                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 938                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 939                 mdelay(1);
 940
 941                 /* put LMI, VCPU, RBC etc... into reset */
 942                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 943                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 944                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 945                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 946                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 947                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 948                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 949                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 950                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 951                 mdelay(5);
 952
 953                 /* initialize UVD memory controller */
 954                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 955                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 956                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 957                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 958                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 959                         UVD_LMI_CTRL__REQ_MODE_MASK |
 960                         0x00100000L);
 961
 962 #ifdef __BIG_ENDIAN
 963                 /* swap (8 in 32) RB and IB */
 964                 lmi_swap_cntl = 0xa;
 965                 mp_swap_cntl = 0;
 966 #endif
 967                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 968                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 969
 970                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 971                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
 972                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 973                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
 974                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
 975                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 976
 977                 /* take all subblocks out of reset, except VCPU */
 978                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 979                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 980                 mdelay(5);
 981
 982                 /* enable VCPU clock */
 983                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
 984                                 UVD_VCPU_CNTL__CLK_EN_MASK);
 985
 986                 /* enable UMC */
 987                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
 988                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 989
 990                 /* boot up the VCPU */
 991                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
 992                 mdelay(10);
 993
 994                 for (i = 0; i < 10; ++i) {
 995                         uint32_t status;
 996
 997                         for (j = 0; j < 100; ++j) {
 998                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
 999                                 if (status & 2)
1000                                         break;
1001                                 mdelay(10);
1002                         }
1003                         r = 0;
1004                         if (status & 2)
1005                                 break;
1006
1007                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1008                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1009                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1010                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1011                         mdelay(10);
1012                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1013                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1014                         mdelay(10);
1015                         r = -1;
1016                 }
1017
1018                 if (r) {
1019                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1020                         return r;
1021                 }
1022                 /* enable master interrupt */
1023                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1024                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1025                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1026
1027                 /* clear the bit 4 of UVD_STATUS */
1028                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1029                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1030
1031                 /* force RBC into idle state */
1032                 rb_bufsz = order_base_2(ring->ring_size);
1033                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1034                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1035                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1036                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1037                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1038                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1039                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1040
1041                 /* set the write pointer delay */
1042                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1043
1044                 /* set the wb address */
1045                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1046                                 (upper_32_bits(ring->gpu_addr) >> 2));
1047
1048                 /* programm the RB_BASE for ring buffer */
1049                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1050                                 lower_32_bits(ring->gpu_addr));
1051                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1052                                 upper_32_bits(ring->gpu_addr));
1053
1054                 /* Initialize the ring buffer's read and write pointers */
1055                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1056
1057                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1058                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1059                                 lower_32_bits(ring->wptr));
1060
1061                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1062                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1063
1064                 ring = &adev->uvd.inst[k].ring_enc[0];
1065                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1066                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1067                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1068                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1069                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1070
1071                 ring = &adev->uvd.inst[k].ring_enc[1];
1072                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1073                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1074                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1075                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1076                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1077         }
1078         return 0;
1079 }
1080
1081 /**
1082  * uvd_v7_0_stop - stop UVD block
1083  *
1084  * @adev: amdgpu_device pointer
1085  *
1086  * stop the UVD block
1087  */
1088 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1089 {
1090         uint8_t i = 0;
1091
1092         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1093                 /* force RBC into idle state */
1094                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1095
1096                 /* Stall UMC and register bus before resetting VCPU */
1097                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1098                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1099                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1100                 mdelay(1);
1101
1102                 /* put VCPU into reset */
1103                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1104                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1105                 mdelay(5);
1106
1107                 /* disable VCPU clock */
1108                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1109
1110                 /* Unstall UMC and register bus */
1111                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1112                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1113         }
1114 }
1115
1116 /**
1117  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1118  *
1119  * @ring: amdgpu_ring pointer
1120  * @fence: fence to emit
1121  *
1122  * Write a fence and a trap command to the ring.
1123  */
1124 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1125                                      unsigned flags)
1126 {
1127         struct amdgpu_device *adev = ring->adev;
1128
1129         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1130
1131         amdgpu_ring_write(ring,
1132                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1133         amdgpu_ring_write(ring, seq);
1134         amdgpu_ring_write(ring,
1135                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1136         amdgpu_ring_write(ring, addr & 0xffffffff);
1137         amdgpu_ring_write(ring,
1138                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1139         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1140         amdgpu_ring_write(ring,
1141                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1142         amdgpu_ring_write(ring, 0);
1143
1144         amdgpu_ring_write(ring,
1145                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1146         amdgpu_ring_write(ring, 0);
1147         amdgpu_ring_write(ring,
1148                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1149         amdgpu_ring_write(ring, 0);
1150         amdgpu_ring_write(ring,
1151                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1152         amdgpu_ring_write(ring, 2);
1153 }
1154
1155 /**
1156  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1157  *
1158  * @ring: amdgpu_ring pointer
1159  * @fence: fence to emit
1160  *
1161  * Write enc a fence and a trap command to the ring.
1162  */
1163 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1164                         u64 seq, unsigned flags)
1165 {
1166
1167         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1168
1169         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1170         amdgpu_ring_write(ring, addr);
1171         amdgpu_ring_write(ring, upper_32_bits(addr));
1172         amdgpu_ring_write(ring, seq);
1173         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1174 }
1175
1176 /**
1177  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1178  *
1179  * @ring: amdgpu_ring pointer
1180  */
1181 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1182 {
1183         /* The firmware doesn't seem to like touching registers at this point. */
1184 }
1185
1186 /**
1187  * uvd_v7_0_ring_test_ring - register write test
1188  *
1189  * @ring: amdgpu_ring pointer
1190  *
1191  * Test if we can successfully write to the context register
1192  */
1193 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1194 {
1195         struct amdgpu_device *adev = ring->adev;
1196         uint32_t tmp = 0;
1197         unsigned i;
1198         int r;
1199
1200         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1201         r = amdgpu_ring_alloc(ring, 3);
1202         if (r) {
1203                 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
1204                           ring->me, ring->idx, r);
1205                 return r;
1206         }
1207         amdgpu_ring_write(ring,
1208                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1209         amdgpu_ring_write(ring, 0xDEADBEEF);
1210         amdgpu_ring_commit(ring);
1211         for (i = 0; i < adev->usec_timeout; i++) {
1212                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1213                 if (tmp == 0xDEADBEEF)
1214                         break;
1215                 DRM_UDELAY(1);
1216         }
1217
1218         if (i < adev->usec_timeout) {
1219                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
1220                          ring->me, ring->idx, i);
1221         } else {
1222                 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
1223                           ring->me, ring->idx, tmp);
1224                 r = -EINVAL;
1225         }
1226         return r;
1227 }
1228
1229 /**
1230  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1231  *
1232  * @ring: amdgpu_ring pointer
1233  * @ib: indirect buffer to execute
1234  *
1235  * Write ring commands to execute the indirect buffer
1236  */
1237 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1238                                   struct amdgpu_ib *ib,
1239                                   unsigned vmid, bool ctx_switch)
1240 {
1241         struct amdgpu_device *adev = ring->adev;
1242
1243         amdgpu_ring_write(ring,
1244                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1245         amdgpu_ring_write(ring, vmid);
1246
1247         amdgpu_ring_write(ring,
1248                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1249         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1250         amdgpu_ring_write(ring,
1251                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1252         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1253         amdgpu_ring_write(ring,
1254                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1255         amdgpu_ring_write(ring, ib->length_dw);
1256 }
1257
1258 /**
1259  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1260  *
1261  * @ring: amdgpu_ring pointer
1262  * @ib: indirect buffer to execute
1263  *
1264  * Write enc ring commands to execute the indirect buffer
1265  */
1266 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1267                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1268 {
1269         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1270         amdgpu_ring_write(ring, vmid);
1271         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1272         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1273         amdgpu_ring_write(ring, ib->length_dw);
1274 }
1275
1276 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1277                                     uint32_t reg, uint32_t val)
1278 {
1279         struct amdgpu_device *adev = ring->adev;
1280
1281         amdgpu_ring_write(ring,
1282                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1283         amdgpu_ring_write(ring, reg << 2);
1284         amdgpu_ring_write(ring,
1285                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1286         amdgpu_ring_write(ring, val);
1287         amdgpu_ring_write(ring,
1288                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1289         amdgpu_ring_write(ring, 8);
1290 }
1291
1292 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1293                                         uint32_t val, uint32_t mask)
1294 {
1295         struct amdgpu_device *adev = ring->adev;
1296
1297         amdgpu_ring_write(ring,
1298                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1299         amdgpu_ring_write(ring, reg << 2);
1300         amdgpu_ring_write(ring,
1301                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1302         amdgpu_ring_write(ring, val);
1303         amdgpu_ring_write(ring,
1304                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1305         amdgpu_ring_write(ring, mask);
1306         amdgpu_ring_write(ring,
1307                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1308         amdgpu_ring_write(ring, 12);
1309 }
1310
1311 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1312                                         unsigned vmid, uint64_t pd_addr)
1313 {
1314         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1315         uint32_t data0, data1, mask;
1316
1317         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1318
1319         /* wait for reg writes */
1320         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1321         data1 = lower_32_bits(pd_addr);
1322         mask = 0xffffffff;
1323         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1324 }
1325
1326 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1327 {
1328         struct amdgpu_device *adev = ring->adev;
1329         int i;
1330
1331         WARN_ON(ring->wptr % 2 || count % 2);
1332
1333         for (i = 0; i < count / 2; i++) {
1334                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1335                 amdgpu_ring_write(ring, 0);
1336         }
1337 }
1338
1339 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1340 {
1341         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1342 }
1343
1344 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1345                                             uint32_t reg, uint32_t val,
1346                                             uint32_t mask)
1347 {
1348         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1349         amdgpu_ring_write(ring, reg << 2);
1350         amdgpu_ring_write(ring, mask);
1351         amdgpu_ring_write(ring, val);
1352 }
1353
1354 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1355                                             unsigned int vmid, uint64_t pd_addr)
1356 {
1357         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1358
1359         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1360
1361         /* wait for reg writes */
1362         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1363                                         lower_32_bits(pd_addr), 0xffffffff);
1364 }
1365
1366 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1367                                         uint32_t reg, uint32_t val)
1368 {
1369         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1370         amdgpu_ring_write(ring, reg << 2);
1371         amdgpu_ring_write(ring, val);
1372 }
1373
1374 #if 0
1375 static bool uvd_v7_0_is_idle(void *handle)
1376 {
1377         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378
1379         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1380 }
1381
1382 static int uvd_v7_0_wait_for_idle(void *handle)
1383 {
1384         unsigned i;
1385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386
1387         for (i = 0; i < adev->usec_timeout; i++) {
1388                 if (uvd_v7_0_is_idle(handle))
1389                         return 0;
1390         }
1391         return -ETIMEDOUT;
1392 }
1393
1394 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1395 static bool uvd_v7_0_check_soft_reset(void *handle)
1396 {
1397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398         u32 srbm_soft_reset = 0;
1399         u32 tmp = RREG32(mmSRBM_STATUS);
1400
1401         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1402             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1403             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1404                     AMDGPU_UVD_STATUS_BUSY_MASK))
1405                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1406                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1407
1408         if (srbm_soft_reset) {
1409                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1410                 return true;
1411         } else {
1412                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1413                 return false;
1414         }
1415 }
1416
1417 static int uvd_v7_0_pre_soft_reset(void *handle)
1418 {
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1422                 return 0;
1423
1424         uvd_v7_0_stop(adev);
1425         return 0;
1426 }
1427
1428 static int uvd_v7_0_soft_reset(void *handle)
1429 {
1430         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1431         u32 srbm_soft_reset;
1432
1433         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1434                 return 0;
1435         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1436
1437         if (srbm_soft_reset) {
1438                 u32 tmp;
1439
1440                 tmp = RREG32(mmSRBM_SOFT_RESET);
1441                 tmp |= srbm_soft_reset;
1442                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1443                 WREG32(mmSRBM_SOFT_RESET, tmp);
1444                 tmp = RREG32(mmSRBM_SOFT_RESET);
1445
1446                 udelay(50);
1447
1448                 tmp &= ~srbm_soft_reset;
1449                 WREG32(mmSRBM_SOFT_RESET, tmp);
1450                 tmp = RREG32(mmSRBM_SOFT_RESET);
1451
1452                 /* Wait a little for things to settle down */
1453                 udelay(50);
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int uvd_v7_0_post_soft_reset(void *handle)
1460 {
1461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
1463         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1464                 return 0;
1465
1466         mdelay(5);
1467
1468         return uvd_v7_0_start(adev);
1469 }
1470 #endif
1471
1472 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1473                                         struct amdgpu_irq_src *source,
1474                                         unsigned type,
1475                                         enum amdgpu_interrupt_state state)
1476 {
1477         // TODO
1478         return 0;
1479 }
1480
1481 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1482                                       struct amdgpu_irq_src *source,
1483                                       struct amdgpu_iv_entry *entry)
1484 {
1485         uint32_t ip_instance;
1486
1487         switch (entry->client_id) {
1488         case SOC15_IH_CLIENTID_UVD:
1489                 ip_instance = 0;
1490                 break;
1491         case SOC15_IH_CLIENTID_UVD1:
1492                 ip_instance = 1;
1493                 break;
1494         default:
1495                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1496                 return 0;
1497         }
1498
1499         DRM_DEBUG("IH: UVD TRAP\n");
1500
1501         switch (entry->src_id) {
1502         case 124:
1503                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1504                 break;
1505         case 119:
1506                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1507                 break;
1508         case 120:
1509                 if (!amdgpu_sriov_vf(adev))
1510                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1511                 break;
1512         default:
1513                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1514                           entry->src_id, entry->src_data[0]);
1515                 break;
1516         }
1517
1518         return 0;
1519 }
1520
1521 #if 0
1522 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1523 {
1524         uint32_t data, data1, data2, suvd_flags;
1525
1526         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1527         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1528         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1529
1530         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1531                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1532
1533         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1534                      UVD_SUVD_CGC_GATE__SIT_MASK |
1535                      UVD_SUVD_CGC_GATE__SMP_MASK |
1536                      UVD_SUVD_CGC_GATE__SCM_MASK |
1537                      UVD_SUVD_CGC_GATE__SDB_MASK;
1538
1539         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1540                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1541                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1542
1543         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1544                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1545                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1546                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1547                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1548                         UVD_CGC_CTRL__SYS_MODE_MASK |
1549                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1550                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1551                         UVD_CGC_CTRL__REGS_MODE_MASK |
1552                         UVD_CGC_CTRL__RBC_MODE_MASK |
1553                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1554                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1555                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1556                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1557                         UVD_CGC_CTRL__MPC_MODE_MASK |
1558                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1559                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1560                         UVD_CGC_CTRL__WCB_MODE_MASK |
1561                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1562                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1563                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1564                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1565         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1566                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1567                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1568                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1569                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1570         data1 |= suvd_flags;
1571
1572         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1573         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1574         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1575         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1576 }
1577
1578 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1579 {
1580         uint32_t data, data1, cgc_flags, suvd_flags;
1581
1582         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1583         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1584
1585         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1586                 UVD_CGC_GATE__UDEC_MASK |
1587                 UVD_CGC_GATE__MPEG2_MASK |
1588                 UVD_CGC_GATE__RBC_MASK |
1589                 UVD_CGC_GATE__LMI_MC_MASK |
1590                 UVD_CGC_GATE__IDCT_MASK |
1591                 UVD_CGC_GATE__MPRD_MASK |
1592                 UVD_CGC_GATE__MPC_MASK |
1593                 UVD_CGC_GATE__LBSI_MASK |
1594                 UVD_CGC_GATE__LRBBM_MASK |
1595                 UVD_CGC_GATE__UDEC_RE_MASK |
1596                 UVD_CGC_GATE__UDEC_CM_MASK |
1597                 UVD_CGC_GATE__UDEC_IT_MASK |
1598                 UVD_CGC_GATE__UDEC_DB_MASK |
1599                 UVD_CGC_GATE__UDEC_MP_MASK |
1600                 UVD_CGC_GATE__WCB_MASK |
1601                 UVD_CGC_GATE__VCPU_MASK |
1602                 UVD_CGC_GATE__SCPU_MASK |
1603                 UVD_CGC_GATE__JPEG_MASK |
1604                 UVD_CGC_GATE__JPEG2_MASK;
1605
1606         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1607                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1608                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1609                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1610                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1611
1612         data |= cgc_flags;
1613         data1 |= suvd_flags;
1614
1615         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1616         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1617 }
1618
1619 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1620 {
1621         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1622
1623         if (enable)
1624                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1625                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1626         else
1627                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1628                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1629
1630         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1631 }
1632
1633
1634 static int uvd_v7_0_set_clockgating_state(void *handle,
1635                                           enum amd_clockgating_state state)
1636 {
1637         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1638         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1639
1640         uvd_v7_0_set_bypass_mode(adev, enable);
1641
1642         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1643                 return 0;
1644
1645         if (enable) {
1646                 /* disable HW gating and enable Sw gating */
1647                 uvd_v7_0_set_sw_clock_gating(adev);
1648         } else {
1649                 /* wait for STATUS to clear */
1650                 if (uvd_v7_0_wait_for_idle(handle))
1651                         return -EBUSY;
1652
1653                 /* enable HW gates because UVD is idle */
1654                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int uvd_v7_0_set_powergating_state(void *handle,
1661                                           enum amd_powergating_state state)
1662 {
1663         /* This doesn't actually powergate the UVD block.
1664          * That's done in the dpm code via the SMC.  This
1665          * just re-inits the block as necessary.  The actual
1666          * gating still happens in the dpm code.  We should
1667          * revisit this when there is a cleaner line between
1668          * the smc and the hw blocks
1669          */
1670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1671
1672         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1673                 return 0;
1674
1675         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1676
1677         if (state == AMD_PG_STATE_GATE) {
1678                 uvd_v7_0_stop(adev);
1679                 return 0;
1680         } else {
1681                 return uvd_v7_0_start(adev);
1682         }
1683 }
1684 #endif
1685
1686 static int uvd_v7_0_set_clockgating_state(void *handle,
1687                                           enum amd_clockgating_state state)
1688 {
1689         /* needed for driver unload*/
1690         return 0;
1691 }
1692
1693 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1694         .name = "uvd_v7_0",
1695         .early_init = uvd_v7_0_early_init,
1696         .late_init = NULL,
1697         .sw_init = uvd_v7_0_sw_init,
1698         .sw_fini = uvd_v7_0_sw_fini,
1699         .hw_init = uvd_v7_0_hw_init,
1700         .hw_fini = uvd_v7_0_hw_fini,
1701         .suspend = uvd_v7_0_suspend,
1702         .resume = uvd_v7_0_resume,
1703         .is_idle = NULL /* uvd_v7_0_is_idle */,
1704         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1705         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1706         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1707         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1708         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1709         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1710         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1711 };
1712
1713 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1714         .type = AMDGPU_RING_TYPE_UVD,
1715         .align_mask = 0xf,
1716         .support_64bit_ptrs = false,
1717         .vmhub = AMDGPU_MMHUB,
1718         .get_rptr = uvd_v7_0_ring_get_rptr,
1719         .get_wptr = uvd_v7_0_ring_get_wptr,
1720         .set_wptr = uvd_v7_0_ring_set_wptr,
1721         .emit_frame_size =
1722                 6 + /* hdp invalidate */
1723                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1724                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1725                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1726                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1727         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1728         .emit_ib = uvd_v7_0_ring_emit_ib,
1729         .emit_fence = uvd_v7_0_ring_emit_fence,
1730         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1731         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1732         .test_ring = uvd_v7_0_ring_test_ring,
1733         .test_ib = amdgpu_uvd_ring_test_ib,
1734         .insert_nop = uvd_v7_0_ring_insert_nop,
1735         .pad_ib = amdgpu_ring_generic_pad_ib,
1736         .begin_use = amdgpu_uvd_ring_begin_use,
1737         .end_use = amdgpu_uvd_ring_end_use,
1738         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1739         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1740         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1741 };
1742
1743 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1744         .type = AMDGPU_RING_TYPE_UVD_ENC,
1745         .align_mask = 0x3f,
1746         .nop = HEVC_ENC_CMD_NO_OP,
1747         .support_64bit_ptrs = false,
1748         .vmhub = AMDGPU_MMHUB,
1749         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1750         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1751         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1752         .emit_frame_size =
1753                 3 + 3 + /* hdp flush / invalidate */
1754                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1755                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1756                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1757                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1758                 1, /* uvd_v7_0_enc_ring_insert_end */
1759         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1760         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1761         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1762         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1763         .test_ring = uvd_v7_0_enc_ring_test_ring,
1764         .test_ib = uvd_v7_0_enc_ring_test_ib,
1765         .insert_nop = amdgpu_ring_insert_nop,
1766         .insert_end = uvd_v7_0_enc_ring_insert_end,
1767         .pad_ib = amdgpu_ring_generic_pad_ib,
1768         .begin_use = amdgpu_uvd_ring_begin_use,
1769         .end_use = amdgpu_uvd_ring_end_use,
1770         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1771         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1772         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1773 };
1774
1775 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1776 {
1777         int i;
1778
1779         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1780                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1781                 adev->uvd.inst[i].ring.me = i;
1782                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1783         }
1784 }
1785
1786 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1787 {
1788         int i, j;
1789
1790         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1791                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1792                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1793                         adev->uvd.inst[j].ring_enc[i].me = j;
1794                 }
1795
1796                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1797         }
1798 }
1799
1800 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1801         .set = uvd_v7_0_set_interrupt_state,
1802         .process = uvd_v7_0_process_interrupt,
1803 };
1804
1805 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1806 {
1807         int i;
1808
1809         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1810                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1811                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1812         }
1813 }
1814
1815 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1816 {
1817                 .type = AMD_IP_BLOCK_TYPE_UVD,
1818                 .major = 7,
1819                 .minor = 0,
1820                 .rev = 0,
1821                 .funcs = &uvd_v7_0_ip_funcs,
1822 };