drivers/gpu/host1x/dev.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Tegra host1x driver
   4  *
   5  * Copyright (c) 2010-2013, NVIDIA Corporation.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/io.h>
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #include <soc/tegra/common.h>
  21
  22 #define CREATE_TRACE_POINTS
  23 #include <trace/events/host1x.h>
  24 #undef CREATE_TRACE_POINTS
  25
  26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  27 #include <asm/dma-iommu.h>
  28 #endif
  29
  30 #include "bus.h"
  31 #include "channel.h"
  32 #include "context.h"
  33 #include "debug.h"
  34 #include "dev.h"
  35 #include "intr.h"
  36
  37 #include "hw/host1x01.h"
  38 #include "hw/host1x02.h"
  39 #include "hw/host1x04.h"
  40 #include "hw/host1x05.h"
  41 #include "hw/host1x06.h"
  42 #include "hw/host1x07.h"
  43 #include "hw/host1x08.h"
  44
  45 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
  46 {
  47         writel(v, host1x->common_regs + r);
  48 }
  49
  50 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
  51 {
  52         writel(v, host1x->hv_regs + r);
  53 }
  54
  55 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
  56 {
  57         return readl(host1x->hv_regs + r);
  58 }
  59
  60 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  61 {
  62         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  63
  64         writel(v, sync_regs + r);
  65 }
  66
  67 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  68 {
  69         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  70
  71         return readl(sync_regs + r);
  72 }
  73
  74 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  75 {
  76         writel(v, ch->regs + r);
  77 }
  78
  79 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  80 {
  81         return readl(ch->regs + r);
  82 }
  83
  84 static const struct host1x_info host1x01_info = {
  85         .nb_channels = 8,
  86         .nb_pts = 32,
  87         .nb_mlocks = 16,
  88         .nb_bases = 8,
  89         .init = host1x01_init,
  90         .sync_offset = 0x3000,
  91         .dma_mask = DMA_BIT_MASK(32),
  92         .has_wide_gather = false,
  93         .has_hypervisor = false,
  94         .num_sid_entries = 0,
  95         .sid_table = NULL,
  96         .reserve_vblank_syncpts = true,
  97 };
  98
  99 static const struct host1x_info host1x02_info = {
 100         .nb_channels = 9,
 101         .nb_pts = 32,
 102         .nb_mlocks = 16,
 103         .nb_bases = 12,
 104         .init = host1x02_init,
 105         .sync_offset = 0x3000,
 106         .dma_mask = DMA_BIT_MASK(32),
 107         .has_wide_gather = false,
 108         .has_hypervisor = false,
 109         .num_sid_entries = 0,
 110         .sid_table = NULL,
 111         .reserve_vblank_syncpts = true,
 112 };
 113
 114 static const struct host1x_info host1x04_info = {
 115         .nb_channels = 12,
 116         .nb_pts = 192,
 117         .nb_mlocks = 16,
 118         .nb_bases = 64,
 119         .init = host1x04_init,
 120         .sync_offset = 0x2100,
 121         .dma_mask = DMA_BIT_MASK(34),
 122         .has_wide_gather = false,
 123         .has_hypervisor = false,
 124         .num_sid_entries = 0,
 125         .sid_table = NULL,
 126         .reserve_vblank_syncpts = false,
 127 };
 128
 129 static const struct host1x_info host1x05_info = {
 130         .nb_channels = 14,
 131         .nb_pts = 192,
 132         .nb_mlocks = 16,
 133         .nb_bases = 64,
 134         .init = host1x05_init,
 135         .sync_offset = 0x2100,
 136         .dma_mask = DMA_BIT_MASK(34),
 137         .has_wide_gather = false,
 138         .has_hypervisor = false,
 139         .num_sid_entries = 0,
 140         .sid_table = NULL,
 141         .reserve_vblank_syncpts = false,
 142 };
 143
 144 static const struct host1x_sid_entry tegra186_sid_table[] = {
 145         {
 146                 /* VIC */
 147                 .base = 0x1af0,
 148                 .offset = 0x30,
 149                 .limit = 0x34
 150         },
 151         {
 152                 /* NVDEC */
 153                 .base = 0x1b00,
 154                 .offset = 0x30,
 155                 .limit = 0x34
 156         },
 157 };
 158
 159 static const struct host1x_info host1x06_info = {
 160         .nb_channels = 63,
 161         .nb_pts = 576,
 162         .nb_mlocks = 24,
 163         .nb_bases = 16,
 164         .init = host1x06_init,
 165         .sync_offset = 0x0,
 166         .dma_mask = DMA_BIT_MASK(40),
 167         .has_wide_gather = true,
 168         .has_hypervisor = true,
 169         .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
 170         .sid_table = tegra186_sid_table,
 171         .reserve_vblank_syncpts = false,
 172         .skip_reset_assert = true,
 173 };
 174
 175 static const struct host1x_sid_entry tegra194_sid_table[] = {
 176         {
 177                 /* VIC */
 178                 .base = 0x1af0,
 179                 .offset = 0x30,
 180                 .limit = 0x34
 181         },
 182         {
 183                 /* NVDEC */
 184                 .base = 0x1b00,
 185                 .offset = 0x30,
 186                 .limit = 0x34
 187         },
 188         {
 189                 /* NVDEC1 */
 190                 .base = 0x1bc0,
 191                 .offset = 0x30,
 192                 .limit = 0x34
 193         },
 194 };
 195
 196 static const struct host1x_info host1x07_info = {
 197         .nb_channels = 63,
 198         .nb_pts = 704,
 199         .nb_mlocks = 32,
 200         .nb_bases = 0,
 201         .init = host1x07_init,
 202         .sync_offset = 0x0,
 203         .dma_mask = DMA_BIT_MASK(40),
 204         .has_wide_gather = true,
 205         .has_hypervisor = true,
 206         .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
 207         .sid_table = tegra194_sid_table,
 208         .reserve_vblank_syncpts = false,
 209 };
 210
 211 /*
 212  * Tegra234 has two stream ID protection tables, one for setting stream IDs
 213  * through the channel path via SETSTREAMID, and one for setting them via
 214  * MMIO. We program each engine's data stream ID in the channel path table
 215  * and firmware stream ID in the MMIO path table.
 216  */
 217 static const struct host1x_sid_entry tegra234_sid_table[] = {
 218         {
 219                 /* SE2 MMIO */
 220                 .base = 0x1658,
 221                 .offset = 0x90,
 222                 .limit = 0x90
 223         },
 224         {
 225                 /* SE4 MMIO */
 226                 .base = 0x1660,
 227                 .offset = 0x90,
 228                 .limit = 0x90
 229         },
 230         {
 231                 /* SE2 channel */
 232                 .base = 0x1738,
 233                 .offset = 0x90,
 234                 .limit = 0x90
 235         },
 236         {
 237                 /* SE4 channel */
 238                 .base = 0x1740,
 239                 .offset = 0x90,
 240                 .limit = 0x90
 241         },
 242         {
 243                 /* VIC channel */
 244                 .base = 0x17b8,
 245                 .offset = 0x30,
 246                 .limit = 0x30
 247         },
 248         {
 249                 /* VIC MMIO */
 250                 .base = 0x1688,
 251                 .offset = 0x34,
 252                 .limit = 0x34
 253         },
 254         {
 255                 /* NVDEC channel */
 256                 .base = 0x17c8,
 257                 .offset = 0x30,
 258                 .limit = 0x30,
 259         },
 260         {
 261                 /* NVDEC MMIO */
 262                 .base = 0x1698,
 263                 .offset = 0x34,
 264                 .limit = 0x34,
 265         },
 266 };
 267
 268 static const struct host1x_info host1x08_info = {
 269         .nb_channels = 63,
 270         .nb_pts = 1024,
 271         .nb_mlocks = 24,
 272         .nb_bases = 0,
 273         .init = host1x08_init,
 274         .sync_offset = 0x0,
 275         .dma_mask = DMA_BIT_MASK(40),
 276         .has_wide_gather = true,
 277         .has_hypervisor = true,
 278         .has_common = true,
 279         .num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
 280         .sid_table = tegra234_sid_table,
 281         .streamid_vm_table = { 0x1004, 128 },
 282         .classid_vm_table = { 0x1404, 25 },
 283         .mmio_vm_table = { 0x1504, 25 },
 284         .reserve_vblank_syncpts = false,
 285 };
 286
 287 static const struct of_device_id host1x_of_match[] = {
 288         { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
 289         { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
 290         { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
 291         { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
 292         { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
 293         { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
 294         { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
 295         { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
 296         { },
 297 };
 298 MODULE_DEVICE_TABLE(of, host1x_of_match);
 299
 300 static void host1x_setup_virtualization_tables(struct host1x *host)
 301 {
 302         const struct host1x_info *info = host->info;
 303         unsigned int i;
 304
 305         if (!info->has_hypervisor)
 306                 return;
 307
 308         for (i = 0; i < info->num_sid_entries; i++) {
 309                 const struct host1x_sid_entry *entry = &info->sid_table[i];
 310
 311                 host1x_hypervisor_writel(host, entry->offset, entry->base);
 312                 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
 313         }
 314
 315         for (i = 0; i < info->streamid_vm_table.count; i++) {
 316                 /* Allow access to all stream IDs to all VMs. */
 317                 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
 318         }
 319
 320         for (i = 0; i < info->classid_vm_table.count; i++) {
 321                 /* Allow access to all classes to all VMs. */
 322                 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
 323         }
 324
 325         for (i = 0; i < info->mmio_vm_table.count; i++) {
 326                 /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
 327                 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
 328         }
 329 }
 330
 331 static bool host1x_wants_iommu(struct host1x *host1x)
 332 {
 333         /* Our IOMMU usage policy doesn't currently play well with GART */
 334         if (of_machine_is_compatible("nvidia,tegra20"))
 335                 return false;
 336
 337         /*
 338          * If we support addressing a maximum of 32 bits of physical memory
 339          * and if the host1x firewall is enabled, there's no need to enable
 340          * IOMMU support. This can happen for example on Tegra20, Tegra30
 341          * and Tegra114.
 342          *
 343          * Tegra124 and later can address up to 34 bits of physical memory and
 344          * many platforms come equipped with more than 2 GiB of system memory,
 345          * which requires crossing the 4 GiB boundary. But there's a catch: on
 346          * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
 347          * only address up to 32 bits of memory in GATHER opcodes, which means
 348          * that command buffers need to either be in the first 2 GiB of system
 349          * memory (which could quickly lead to memory exhaustion), or command
 350          * buffers need to be treated differently from other buffers (which is
 351          * not possible with the current ABI).
 352          *
 353          * A third option is to use the IOMMU in these cases to make sure all
 354          * buffers will be mapped into a 32-bit IOVA space that host1x can
 355          * address. This allows all of the system memory to be used and works
 356          * within the limitations of the host1x on these SoCs.
 357          *
 358          * In summary, default to enable IOMMU on Tegra124 and later. For any
 359          * of the earlier SoCs, only use the IOMMU for additional safety when
 360          * the host1x firewall is disabled.
 361          */
 362         if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
 363                 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
 364                         return false;
 365         }
 366
 367         return true;
 368 }
 369
 370 static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
 371 {
 372         struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
 373         int err;
 374
 375 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
 376         if (host->dev->archdata.mapping) {
 377                 struct dma_iommu_mapping *mapping =
 378                                 to_dma_iommu_mapping(host->dev);
 379                 arm_iommu_detach_device(host->dev);
 380                 arm_iommu_release_mapping(mapping);
 381
 382                 domain = iommu_get_domain_for_dev(host->dev);
 383         }
 384 #endif
 385
 386         /*
 387          * We may not always want to enable IOMMU support (for example if the
 388          * host1x firewall is already enabled and we don't support addressing
 389          * more than 32 bits of physical memory), so check for that first.
 390          *
 391          * Similarly, if host1x is already attached to an IOMMU (via the DMA
 392          * API), don't try to attach again.
 393          */
 394         if (!host1x_wants_iommu(host) || domain)
 395                 return domain;
 396
 397         host->group = iommu_group_get(host->dev);
 398         if (host->group) {
 399                 struct iommu_domain_geometry *geometry;
 400                 dma_addr_t start, end;
 401                 unsigned long order;
 402
 403                 err = iova_cache_get();
 404                 if (err < 0)
 405                         goto put_group;
 406
 407                 host->domain = iommu_domain_alloc(&platform_bus_type);
 408                 if (!host->domain) {
 409                         err = -ENOMEM;
 410                         goto put_cache;
 411                 }
 412
 413                 err = iommu_attach_group(host->domain, host->group);
 414                 if (err) {
 415                         if (err == -ENODEV)
 416                                 err = 0;
 417
 418                         goto free_domain;
 419                 }
 420
 421                 geometry = &host->domain->geometry;
 422                 start = geometry->aperture_start & host->info->dma_mask;
 423                 end = geometry->aperture_end & host->info->dma_mask;
 424
 425                 order = __ffs(host->domain->pgsize_bitmap);
 426                 init_iova_domain(&host->iova, 1UL << order, start >> order);
 427                 host->iova_end = end;
 428
 429                 domain = host->domain;
 430         }
 431
 432         return domain;
 433
 434 free_domain:
 435         iommu_domain_free(host->domain);
 436         host->domain = NULL;
 437 put_cache:
 438         iova_cache_put();
 439 put_group:
 440         iommu_group_put(host->group);
 441         host->group = NULL;
 442
 443         return ERR_PTR(err);
 444 }
 445
 446 static int host1x_iommu_init(struct host1x *host)
 447 {
 448         u64 mask = host->info->dma_mask;
 449         struct iommu_domain *domain;
 450         int err;
 451
 452         domain = host1x_iommu_attach(host);
 453         if (IS_ERR(domain)) {
 454                 err = PTR_ERR(domain);
 455                 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
 456                 return err;
 457         }
 458
 459         /*
 460          * If we're not behind an IOMMU make sure we don't get push buffers
 461          * that are allocated outside of the range addressable by the GATHER
 462          * opcode.
 463          *
 464          * Newer generations of Tegra (Tegra186 and later) support a wide
 465          * variant of the GATHER opcode that allows addressing more bits.
 466          */
 467         if (!domain && !host->info->has_wide_gather)
 468                 mask = DMA_BIT_MASK(32);
 469
 470         err = dma_coerce_mask_and_coherent(host->dev, mask);
 471         if (err < 0) {
 472                 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
 473                 return err;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static void host1x_iommu_exit(struct host1x *host)
 480 {
 481         if (host->domain) {
 482                 put_iova_domain(&host->iova);
 483                 iommu_detach_group(host->domain, host->group);
 484
 485                 iommu_domain_free(host->domain);
 486                 host->domain = NULL;
 487
 488                 iova_cache_put();
 489
 490                 iommu_group_put(host->group);
 491                 host->group = NULL;
 492         }
 493 }
 494
 495 static int host1x_get_resets(struct host1x *host)
 496 {
 497         int err;
 498
 499         host->resets[0].id = "mc";
 500         host->resets[1].id = "host1x";
 501         host->nresets = ARRAY_SIZE(host->resets);
 502
 503         err = devm_reset_control_bulk_get_optional_exclusive_released(
 504                                 host->dev, host->nresets, host->resets);
 505         if (err) {
 506                 dev_err(host->dev, "failed to get reset: %d\n", err);
 507                 return err;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int host1x_probe(struct platform_device *pdev)
 514 {
 515         struct host1x *host;
 516         int err, i;
 517
 518         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 519         if (!host)
 520                 return -ENOMEM;
 521
 522         host->info = of_device_get_match_data(&pdev->dev);
 523
 524         if (host->info->has_hypervisor) {
 525                 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
 526                 if (IS_ERR(host->regs))
 527                         return PTR_ERR(host->regs);
 528
 529                 host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
 530                 if (IS_ERR(host->hv_regs))
 531                         return PTR_ERR(host->hv_regs);
 532
 533                 if (host->info->has_common) {
 534                         host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
 535                         if (IS_ERR(host->common_regs))
 536                                 return PTR_ERR(host->common_regs);
 537                 }
 538         } else {
 539                 host->regs = devm_platform_ioremap_resource(pdev, 0);
 540                 if (IS_ERR(host->regs))
 541                         return PTR_ERR(host->regs);
 542         }
 543
 544         for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) {
 545                 char irq_name[] = "syncptX";
 546
 547                 sprintf(irq_name, "syncpt%d", i);
 548
 549                 err = platform_get_irq_byname_optional(pdev, irq_name);
 550                 if (err == -ENXIO)
 551                         break;
 552                 if (err < 0)
 553                         return err;
 554
 555                 host->syncpt_irqs[i] = err;
 556         }
 557
 558         host->num_syncpt_irqs = i;
 559
 560         /* Device tree without irq names */
 561         if (i == 0) {
 562                 host->syncpt_irqs[0] = platform_get_irq(pdev, 0);
 563                 if (host->syncpt_irqs[0] < 0)
 564                         return host->syncpt_irqs[0];
 565
 566                 host->num_syncpt_irqs = 1;
 567         }
 568
 569         mutex_init(&host->devices_lock);
 570         INIT_LIST_HEAD(&host->devices);
 571         INIT_LIST_HEAD(&host->list);
 572         host->dev = &pdev->dev;
 573
 574         /* set common host1x device data */
 575         platform_set_drvdata(pdev, host);
 576
 577         host->dev->dma_parms = &host->dma_parms;
 578         dma_set_max_seg_size(host->dev, UINT_MAX);
 579
 580         if (host->info->init) {
 581                 err = host->info->init(host);
 582                 if (err)
 583                         return err;
 584         }
 585
 586         host->clk = devm_clk_get(&pdev->dev, NULL);
 587         if (IS_ERR(host->clk)) {
 588                 err = PTR_ERR(host->clk);
 589
 590                 if (err != -EPROBE_DEFER)
 591                         dev_err(&pdev->dev, "failed to get clock: %d\n", err);
 592
 593                 return err;
 594         }
 595
 596         err = host1x_get_resets(host);
 597         if (err)
 598                 return err;
 599
 600         host1x_bo_cache_init(&host->cache);
 601
 602         err = host1x_iommu_init(host);
 603         if (err < 0) {
 604                 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
 605                 goto destroy_cache;
 606         }
 607
 608         err = host1x_channel_list_init(&host->channel_list,
 609                                        host->info->nb_channels);
 610         if (err) {
 611                 dev_err(&pdev->dev, "failed to initialize channel list\n");
 612                 goto iommu_exit;
 613         }
 614
 615         err = host1x_memory_context_list_init(host);
 616         if (err) {
 617                 dev_err(&pdev->dev, "failed to initialize context list\n");
 618                 goto free_channels;
 619         }
 620
 621         err = host1x_syncpt_init(host);
 622         if (err) {
 623                 dev_err(&pdev->dev, "failed to initialize syncpts\n");
 624                 goto free_contexts;
 625         }
 626
 627         err = host1x_intr_init(host);
 628         if (err) {
 629                 dev_err(&pdev->dev, "failed to initialize interrupts\n");
 630                 goto deinit_syncpt;
 631         }
 632
 633         pm_runtime_enable(&pdev->dev);
 634
 635         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
 636         if (err)
 637                 goto pm_disable;
 638
 639         /* the driver's code isn't ready yet for the dynamic RPM */
 640         err = pm_runtime_resume_and_get(&pdev->dev);
 641         if (err)
 642                 goto pm_disable;
 643
 644         host1x_debug_init(host);
 645
 646         err = host1x_register(host);
 647         if (err < 0)
 648                 goto deinit_debugfs;
 649
 650         err = devm_of_platform_populate(&pdev->dev);
 651         if (err < 0)
 652                 goto unregister;
 653
 654         return 0;
 655
 656 unregister:
 657         host1x_unregister(host);
 658 deinit_debugfs:
 659         host1x_debug_deinit(host);
 660
 661         pm_runtime_put_sync_suspend(&pdev->dev);
 662 pm_disable:
 663         pm_runtime_disable(&pdev->dev);
 664
 665         host1x_intr_deinit(host);
 666 deinit_syncpt:
 667         host1x_syncpt_deinit(host);
 668 free_contexts:
 669         host1x_memory_context_list_free(&host->context_list);
 670 free_channels:
 671         host1x_channel_list_free(&host->channel_list);
 672 iommu_exit:
 673         host1x_iommu_exit(host);
 674 destroy_cache:
 675         host1x_bo_cache_destroy(&host->cache);
 676
 677         return err;
 678 }
 679
 680 static void host1x_remove(struct platform_device *pdev)
 681 {
 682         struct host1x *host = platform_get_drvdata(pdev);
 683
 684         host1x_unregister(host);
 685         host1x_debug_deinit(host);
 686
 687         pm_runtime_force_suspend(&pdev->dev);
 688
 689         host1x_intr_deinit(host);
 690         host1x_syncpt_deinit(host);
 691         host1x_memory_context_list_free(&host->context_list);
 692         host1x_channel_list_free(&host->channel_list);
 693         host1x_iommu_exit(host);
 694         host1x_bo_cache_destroy(&host->cache);
 695 }
 696
 697 static int __maybe_unused host1x_runtime_suspend(struct device *dev)
 698 {
 699         struct host1x *host = dev_get_drvdata(dev);
 700         int err;
 701
 702         host1x_channel_stop_all(host);
 703         host1x_intr_stop(host);
 704         host1x_syncpt_save(host);
 705
 706         if (!host->info->skip_reset_assert) {
 707                 err = reset_control_bulk_assert(host->nresets, host->resets);
 708                 if (err) {
 709                         dev_err(dev, "failed to assert reset: %d\n", err);
 710                         goto resume_host1x;
 711                 }
 712
 713                 usleep_range(1000, 2000);
 714         }
 715
 716         clk_disable_unprepare(host->clk);
 717         reset_control_bulk_release(host->nresets, host->resets);
 718
 719         return 0;
 720
 721 resume_host1x:
 722         host1x_setup_virtualization_tables(host);
 723         host1x_syncpt_restore(host);
 724         host1x_intr_start(host);
 725
 726         return err;
 727 }
 728
 729 static int __maybe_unused host1x_runtime_resume(struct device *dev)
 730 {
 731         struct host1x *host = dev_get_drvdata(dev);
 732         int err;
 733
 734         err = reset_control_bulk_acquire(host->nresets, host->resets);
 735         if (err) {
 736                 dev_err(dev, "failed to acquire reset: %d\n", err);
 737                 return err;
 738         }
 739
 740         err = clk_prepare_enable(host->clk);
 741         if (err) {
 742                 dev_err(dev, "failed to enable clock: %d\n", err);
 743                 goto release_reset;
 744         }
 745
 746         err = reset_control_bulk_deassert(host->nresets, host->resets);
 747         if (err < 0) {
 748                 dev_err(dev, "failed to deassert reset: %d\n", err);
 749                 goto disable_clk;
 750         }
 751
 752         host1x_setup_virtualization_tables(host);
 753         host1x_syncpt_restore(host);
 754         host1x_intr_start(host);
 755
 756         return 0;
 757
 758 disable_clk:
 759         clk_disable_unprepare(host->clk);
 760 release_reset:
 761         reset_control_bulk_release(host->nresets, host->resets);
 762
 763         return err;
 764 }
 765
 766 static const struct dev_pm_ops host1x_pm_ops = {
 767         SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume,
 768                            NULL)
 769         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
 770 };
 771
 772 static struct platform_driver tegra_host1x_driver = {
 773         .driver = {
 774                 .name = "tegra-host1x",
 775                 .of_match_table = host1x_of_match,
 776                 .pm = &host1x_pm_ops,
 777         },
 778         .probe = host1x_probe,
 779         .remove_new = host1x_remove,
 780 };
 781
 782 static struct platform_driver * const drivers[] = {
 783         &tegra_host1x_driver,
 784         &tegra_mipi_driver,
 785 };
 786
 787 static int __init tegra_host1x_init(void)
 788 {
 789         int err;
 790
 791         err = bus_register(&host1x_bus_type);
 792         if (err < 0)
 793                 return err;
 794
 795         err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 796         if (err < 0)
 797                 bus_unregister(&host1x_bus_type);
 798
 799         return err;
 800 }
 801 module_init(tegra_host1x_init);
 802
 803 static void __exit tegra_host1x_exit(void)
 804 {
 805         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 806         bus_unregister(&host1x_bus_type);
 807 }
 808 module_exit(tegra_host1x_exit);
 809
 810 /**
 811  * host1x_get_dma_mask() - query the supported DMA mask for host1x
 812  * @host1x: host1x instance
 813  *
 814  * Note that this returns the supported DMA mask for host1x, which can be
 815  * different from the applicable DMA mask under certain circumstances.
 816  */
 817 u64 host1x_get_dma_mask(struct host1x *host1x)
 818 {
 819         return host1x->info->dma_mask;
 820 }
 821 EXPORT_SYMBOL(host1x_get_dma_mask);
 822
 823 MODULE_AUTHOR("Thierry Reding <[email protected]>");
 824 MODULE_AUTHOR("Terje Bergstrom <[email protected]>");
 825 MODULE_DESCRIPTION("Host1x driver for Tegra products");
 826 MODULE_LICENSE("GPL");