drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/io.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include <drm/display/drm_dp_helper.h>
  20 #include <drm/display/drm_scdc_helper.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_debugfs.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_simple_kms_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_lvds;
 375         bool supports_hdmi;
 376         bool supports_dp;
 377         bool supports_audio;
 378         bool supports_hdcp;
 379
 380         const struct tegra_sor_regs *regs;
 381         bool has_nvdisplay;
 382
 383         const struct tegra_sor_hdmi_settings *settings;
 384         unsigned int num_settings;
 385
 386         const u8 *xbar_cfg;
 387         const u8 *lane_map;
 388
 389         const u8 (*voltage_swing)[4][4];
 390         const u8 (*pre_emphasis)[4][4];
 391         const u8 (*post_cursor)[4][4];
 392         const u8 (*tx_pu)[4][4];
 393 };
 394
 395 struct tegra_sor;
 396
 397 struct tegra_sor_ops {
 398         const char *name;
 399         int (*probe)(struct tegra_sor *sor);
 400         void (*audio_enable)(struct tegra_sor *sor);
 401         void (*audio_disable)(struct tegra_sor *sor);
 402 };
 403
 404 struct tegra_sor {
 405         struct host1x_client client;
 406         struct tegra_output output;
 407         struct device *dev;
 408
 409         const struct tegra_sor_soc *soc;
 410         void __iomem *regs;
 411         unsigned int index;
 412         unsigned int irq;
 413
 414         struct reset_control *rst;
 415         struct clk *clk_parent;
 416         struct clk *clk_safe;
 417         struct clk *clk_out;
 418         struct clk *clk_pad;
 419         struct clk *clk_dp;
 420         struct clk *clk;
 421
 422         u8 xbar_cfg[5];
 423
 424         struct drm_dp_link link;
 425         struct drm_dp_aux *aux;
 426
 427         struct drm_info_list *debugfs_files;
 428
 429         const struct tegra_sor_ops *ops;
 430         enum tegra_io_pad pad;
 431
 432         /* for HDMI 2.0 */
 433         struct tegra_sor_hdmi_settings *settings;
 434         unsigned int num_settings;
 435
 436         struct regulator *avdd_io_supply;
 437         struct regulator *vdd_pll_supply;
 438         struct regulator *hdmi_supply;
 439
 440         struct delayed_work scdc;
 441         bool scdc_enabled;
 442
 443         struct tegra_hda_format format;
 444 };
 445
 446 struct tegra_sor_state {
 447         struct drm_connector_state base;
 448
 449         unsigned int link_speed;
 450         unsigned long pclk;
 451         unsigned int bpc;
 452 };
 453
 454 static inline struct tegra_sor_state *
 455 to_sor_state(struct drm_connector_state *state)
 456 {
 457         return container_of(state, struct tegra_sor_state, base);
 458 }
 459
 460 struct tegra_sor_config {
 461         u32 bits_per_pixel;
 462
 463         u32 active_polarity;
 464         u32 active_count;
 465         u32 tu_size;
 466         u32 active_frac;
 467         u32 watermark;
 468
 469         u32 hblank_symbols;
 470         u32 vblank_symbols;
 471 };
 472
 473 static inline struct tegra_sor *
 474 host1x_client_to_sor(struct host1x_client *client)
 475 {
 476         return container_of(client, struct tegra_sor, client);
 477 }
 478
 479 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 480 {
 481         return container_of(output, struct tegra_sor, output);
 482 }
 483
 484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 485 {
 486         u32 value = readl(sor->regs + (offset << 2));
 487
 488         trace_sor_readl(sor->dev, offset, value);
 489
 490         return value;
 491 }
 492
 493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 494                                     unsigned int offset)
 495 {
 496         trace_sor_writel(sor->dev, offset, value);
 497         writel(value, sor->regs + (offset << 2));
 498 }
 499
 500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 501 {
 502         int err;
 503
 504         clk_disable_unprepare(sor->clk);
 505
 506         err = clk_set_parent(sor->clk_out, parent);
 507         if (err < 0)
 508                 return err;
 509
 510         err = clk_prepare_enable(sor->clk);
 511         if (err < 0)
 512                 return err;
 513
 514         return 0;
 515 }
 516
 517 struct tegra_clk_sor_pad {
 518         struct clk_hw hw;
 519         struct tegra_sor *sor;
 520 };
 521
 522 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 523 {
 524         return container_of(hw, struct tegra_clk_sor_pad, hw);
 525 }
 526
 527 static const char * const tegra_clk_sor_pad_parents[2][2] = {
 528         { "pll_d_out0", "pll_dp" },
 529         { "pll_d2_out0", "pll_dp" },
 530 };
 531
 532 /*
 533  * Implementing ->set_parent() here isn't really required because the parent
 534  * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 535  * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 536  * Tegra186 and later SoC generations where the BPMP implements this clock
 537  * and doesn't expose the mux via the common clock framework.
 538  */
 539
 540 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 541 {
 542         struct tegra_clk_sor_pad *pad = to_pad(hw);
 543         struct tegra_sor *sor = pad->sor;
 544         u32 value;
 545
 546         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 547         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 548
 549         switch (index) {
 550         case 0:
 551                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 552                 break;
 553
 554         case 1:
 555                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 556                 break;
 557         }
 558
 559         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 560
 561         return 0;
 562 }
 563
 564 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 565 {
 566         struct tegra_clk_sor_pad *pad = to_pad(hw);
 567         struct tegra_sor *sor = pad->sor;
 568         u8 parent = U8_MAX;
 569         u32 value;
 570
 571         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 572
 573         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 574         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 575         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 576                 parent = 0;
 577                 break;
 578
 579         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 580         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 581                 parent = 1;
 582                 break;
 583         }
 584
 585         return parent;
 586 }
 587
 588 static const struct clk_ops tegra_clk_sor_pad_ops = {
 589         .set_parent = tegra_clk_sor_pad_set_parent,
 590         .get_parent = tegra_clk_sor_pad_get_parent,
 591 };
 592
 593 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 594                                               const char *name)
 595 {
 596         struct tegra_clk_sor_pad *pad;
 597         struct clk_init_data init;
 598         struct clk *clk;
 599
 600         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 601         if (!pad)
 602                 return ERR_PTR(-ENOMEM);
 603
 604         pad->sor = sor;
 605
 606         init.name = name;
 607         init.flags = 0;
 608         init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 609         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 610         init.ops = &tegra_clk_sor_pad_ops;
 611
 612         pad->hw.init = &init;
 613
 614         clk = devm_clk_register(sor->dev, &pad->hw);
 615
 616         return clk;
 617 }
 618
 619 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 620 {
 621         struct drm_dp_link *link = &sor->link;
 622         unsigned int i;
 623
 624         /* Tegra only supports RBR, HBR and HBR2 */
 625         for (i = 0; i < link->num_rates; i++) {
 626                 switch (link->rates[i]) {
 627                 case 1620000:
 628                 case 2700000:
 629                 case 5400000:
 630                         break;
 631
 632                 default:
 633                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 634                                       link->rates[i]);
 635                         link->rates[i] = 0;
 636                         break;
 637                 }
 638         }
 639
 640         drm_dp_link_update_rates(link);
 641 }
 642
 643 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 644 {
 645         unsigned long timeout;
 646         u32 value;
 647
 648         /*
 649          * Clear or set the PD_TXD bit corresponding to each lane, depending
 650          * on whether it is used or not.
 651          */
 652         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 653
 654         if (lanes <= 2)
 655                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 656                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 657         else
 658                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 659                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 660
 661         if (lanes <= 1)
 662                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 663         else
 664                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 665
 666         if (lanes == 0)
 667                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 668         else
 669                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 670
 671         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 672
 673         /* start lane sequencer */
 674         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 675                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 676         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 677
 678         timeout = jiffies + msecs_to_jiffies(250);
 679
 680         while (time_before(jiffies, timeout)) {
 681                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 682                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 683                         break;
 684
 685                 usleep_range(250, 1000);
 686         }
 687
 688         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 689                 return -ETIMEDOUT;
 690
 691         return 0;
 692 }
 693
 694 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 695 {
 696         unsigned long timeout;
 697         u32 value;
 698
 699         /* power down all lanes */
 700         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 701         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 702                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 703         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 704
 705         /* start lane sequencer */
 706         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 707                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 708         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 709
 710         timeout = jiffies + msecs_to_jiffies(250);
 711
 712         while (time_before(jiffies, timeout)) {
 713                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 714                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 715                         break;
 716
 717                 usleep_range(25, 100);
 718         }
 719
 720         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 721                 return -ETIMEDOUT;
 722
 723         return 0;
 724 }
 725
 726 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 727 {
 728         u32 value;
 729
 730         /* pre-charge all used lanes */
 731         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 732
 733         if (lanes <= 2)
 734                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 735                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 736         else
 737                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 738                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 739
 740         if (lanes <= 1)
 741                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 742         else
 743                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 744
 745         if (lanes == 0)
 746                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 747         else
 748                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 749
 750         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 751
 752         usleep_range(15, 100);
 753
 754         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 755         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 756                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 757         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 758 }
 759
 760 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 761 {
 762         u32 mask = 0x08, adj = 0, value;
 763
 764         /* enable pad calibration logic */
 765         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 766         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 767         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 768
 769         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 770         value |= SOR_PLL1_TMDS_TERM;
 771         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 772
 773         while (mask) {
 774                 adj |= mask;
 775
 776                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 777                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 778                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 779                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 780
 781                 usleep_range(100, 200);
 782
 783                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 784                 if (value & SOR_PLL1_TERM_COMPOUT)
 785                         adj &= ~mask;
 786
 787                 mask >>= 1;
 788         }
 789
 790         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 791         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 792         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 793         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 794
 795         /* disable pad calibration logic */
 796         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 797         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 798         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 799 }
 800
 801 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 802 {
 803         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 804         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 805         const struct tegra_sor_soc *soc = sor->soc;
 806         u32 pattern = 0, tx_pu = 0, value;
 807         unsigned int i;
 808
 809         for (value = 0, i = 0; i < link->lanes; i++) {
 810                 u8 vs = link->train.request.voltage_swing[i];
 811                 u8 pe = link->train.request.pre_emphasis[i];
 812                 u8 pc = link->train.request.post_cursor[i];
 813                 u8 shift = sor->soc->lane_map[i] << 3;
 814
 815                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 816                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 817                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 818
 819                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 820                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 821
 822                 switch (link->train.pattern) {
 823                 case DP_TRAINING_PATTERN_DISABLE:
 824                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 825                                 SOR_DP_TPG_PATTERN_NONE;
 826                         break;
 827
 828                 case DP_TRAINING_PATTERN_1:
 829                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 830                                 SOR_DP_TPG_PATTERN_TRAIN1;
 831                         break;
 832
 833                 case DP_TRAINING_PATTERN_2:
 834                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 835                                 SOR_DP_TPG_PATTERN_TRAIN2;
 836                         break;
 837
 838                 case DP_TRAINING_PATTERN_3:
 839                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 840                                 SOR_DP_TPG_PATTERN_TRAIN3;
 841                         break;
 842
 843                 default:
 844                         return -EINVAL;
 845                 }
 846
 847                 if (link->caps.channel_coding)
 848                         value |= SOR_DP_TPG_CHANNEL_CODING;
 849
 850                 pattern = pattern << 8 | value;
 851         }
 852
 853         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 854         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 855
 856         if (link->caps.tps3_supported)
 857                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 858
 859         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 860
 861         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 862         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 863         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 864         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 865         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 866
 867         usleep_range(20, 100);
 868
 869         return 0;
 870 }
 871
 872 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 873 {
 874         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 875         unsigned int rate, lanes;
 876         u32 value;
 877         int err;
 878
 879         rate = drm_dp_link_rate_to_bw_code(link->rate);
 880         lanes = link->lanes;
 881
 882         /* configure link speed and lane count */
 883         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 884         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 885         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 886         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 887
 888         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 889         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 890         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 891
 892         if (link->caps.enhanced_framing)
 893                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 894
 895         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 896
 897         usleep_range(400, 1000);
 898
 899         /* configure load pulse position adjustment */
 900         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 901         value &= ~SOR_PLL1_LOADADJ_MASK;
 902
 903         switch (rate) {
 904         case DP_LINK_BW_1_62:
 905                 value |= SOR_PLL1_LOADADJ(0x3);
 906                 break;
 907
 908         case DP_LINK_BW_2_7:
 909                 value |= SOR_PLL1_LOADADJ(0x4);
 910                 break;
 911
 912         case DP_LINK_BW_5_4:
 913                 value |= SOR_PLL1_LOADADJ(0x6);
 914                 break;
 915         }
 916
 917         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 918
 919         /* use alternate scrambler reset for eDP */
 920         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 921
 922         if (link->edp == 0)
 923                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 924         else
 925                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 926
 927         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 928
 929         err = tegra_sor_power_down_lanes(sor);
 930         if (err < 0) {
 931                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 932                 return err;
 933         }
 934
 935         /* power up and pre-charge lanes */
 936         err = tegra_sor_power_up_lanes(sor, lanes);
 937         if (err < 0) {
 938                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 939                         lanes, (lanes != 1) ? "s" : "", err);
 940                 return err;
 941         }
 942
 943         tegra_sor_dp_precharge(sor, lanes);
 944
 945         return 0;
 946 }
 947
 948 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 949         .apply_training = tegra_sor_dp_link_apply_training,
 950         .configure = tegra_sor_dp_link_configure,
 951 };
 952
 953 static void tegra_sor_super_update(struct tegra_sor *sor)
 954 {
 955         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 956         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 957         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 958 }
 959
 960 static void tegra_sor_update(struct tegra_sor *sor)
 961 {
 962         tegra_sor_writel(sor, 0, SOR_STATE0);
 963         tegra_sor_writel(sor, 1, SOR_STATE0);
 964         tegra_sor_writel(sor, 0, SOR_STATE0);
 965 }
 966
 967 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 968 {
 969         u32 value;
 970
 971         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 972         value &= ~SOR_PWM_DIV_MASK;
 973         value |= 0x400; /* period */
 974         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 975
 976         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 977         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 978         value |= 0x400; /* duty cycle */
 979         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 980         value |= SOR_PWM_CTL_TRIGGER;
 981         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 982
 983         timeout = jiffies + msecs_to_jiffies(timeout);
 984
 985         while (time_before(jiffies, timeout)) {
 986                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 987                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 988                         return 0;
 989
 990                 usleep_range(25, 100);
 991         }
 992
 993         return -ETIMEDOUT;
 994 }
 995
 996 static int tegra_sor_attach(struct tegra_sor *sor)
 997 {
 998         unsigned long value, timeout;
 999
1000         /* wake up in normal mode */
1001         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1002         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1003         value |= SOR_SUPER_STATE_MODE_NORMAL;
1004         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1005         tegra_sor_super_update(sor);
1006
1007         /* attach */
1008         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1009         value |= SOR_SUPER_STATE_ATTACHED;
1010         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1011         tegra_sor_super_update(sor);
1012
1013         timeout = jiffies + msecs_to_jiffies(250);
1014
1015         while (time_before(jiffies, timeout)) {
1016                 value = tegra_sor_readl(sor, SOR_TEST);
1017                 if ((value & SOR_TEST_ATTACHED) != 0)
1018                         return 0;
1019
1020                 usleep_range(25, 100);
1021         }
1022
1023         return -ETIMEDOUT;
1024 }
1025
1026 static int tegra_sor_wakeup(struct tegra_sor *sor)
1027 {
1028         unsigned long value, timeout;
1029
1030         timeout = jiffies + msecs_to_jiffies(250);
1031
1032         /* wait for head to wake up */
1033         while (time_before(jiffies, timeout)) {
1034                 value = tegra_sor_readl(sor, SOR_TEST);
1035                 value &= SOR_TEST_HEAD_MODE_MASK;
1036
1037                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1038                         return 0;
1039
1040                 usleep_range(25, 100);
1041         }
1042
1043         return -ETIMEDOUT;
1044 }
1045
1046 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1047 {
1048         u32 value;
1049
1050         value = tegra_sor_readl(sor, SOR_PWR);
1051         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1052         tegra_sor_writel(sor, value, SOR_PWR);
1053
1054         timeout = jiffies + msecs_to_jiffies(timeout);
1055
1056         while (time_before(jiffies, timeout)) {
1057                 value = tegra_sor_readl(sor, SOR_PWR);
1058                 if ((value & SOR_PWR_TRIGGER) == 0)
1059                         return 0;
1060
1061                 usleep_range(25, 100);
1062         }
1063
1064         return -ETIMEDOUT;
1065 }
1066
1067 struct tegra_sor_params {
1068         /* number of link clocks per line */
1069         unsigned int num_clocks;
1070         /* ratio between input and output */
1071         u64 ratio;
1072         /* precision factor */
1073         u64 precision;
1074
1075         unsigned int active_polarity;
1076         unsigned int active_count;
1077         unsigned int active_frac;
1078         unsigned int tu_size;
1079         unsigned int error;
1080 };
1081
1082 static int tegra_sor_compute_params(struct tegra_sor *sor,
1083                                     struct tegra_sor_params *params,
1084                                     unsigned int tu_size)
1085 {
1086         u64 active_sym, active_count, frac, approx;
1087         u32 active_polarity, active_frac = 0;
1088         const u64 f = params->precision;
1089         s64 error;
1090
1091         active_sym = params->ratio * tu_size;
1092         active_count = div_u64(active_sym, f) * f;
1093         frac = active_sym - active_count;
1094
1095         /* fraction < 0.5 */
1096         if (frac >= (f / 2)) {
1097                 active_polarity = 1;
1098                 frac = f - frac;
1099         } else {
1100                 active_polarity = 0;
1101         }
1102
1103         if (frac != 0) {
1104                 frac = div_u64(f * f,  frac); /* 1/fraction */
1105                 if (frac <= (15 * f)) {
1106                         active_frac = div_u64(frac, f);
1107
1108                         /* round up */
1109                         if (active_polarity)
1110                                 active_frac++;
1111                 } else {
1112                         active_frac = active_polarity ? 1 : 15;
1113                 }
1114         }
1115
1116         if (active_frac == 1)
1117                 active_polarity = 0;
1118
1119         if (active_polarity == 1) {
1120                 if (active_frac) {
1121                         approx = active_count + (active_frac * (f - 1)) * f;
1122                         approx = div_u64(approx, active_frac * f);
1123                 } else {
1124                         approx = active_count + f;
1125                 }
1126         } else {
1127                 if (active_frac)
1128                         approx = active_count + div_u64(f, active_frac);
1129                 else
1130                         approx = active_count;
1131         }
1132
1133         error = div_s64(active_sym - approx, tu_size);
1134         error *= params->num_clocks;
1135
1136         if (error <= 0 && abs(error) < params->error) {
1137                 params->active_count = div_u64(active_count, f);
1138                 params->active_polarity = active_polarity;
1139                 params->active_frac = active_frac;
1140                 params->error = abs(error);
1141                 params->tu_size = tu_size;
1142
1143                 if (error == 0)
1144                         return true;
1145         }
1146
1147         return false;
1148 }
1149
1150 static int tegra_sor_compute_config(struct tegra_sor *sor,
1151                                     const struct drm_display_mode *mode,
1152                                     struct tegra_sor_config *config,
1153                                     struct drm_dp_link *link)
1154 {
1155         const u64 f = 100000, link_rate = link->rate * 1000;
1156         const u64 pclk = (u64)mode->clock * 1000;
1157         u64 input, output, watermark, num;
1158         struct tegra_sor_params params;
1159         u32 num_syms_per_line;
1160         unsigned int i;
1161
1162         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1163                 return -EINVAL;
1164
1165         input = pclk * config->bits_per_pixel;
1166         output = link_rate * 8 * link->lanes;
1167
1168         if (input >= output)
1169                 return -ERANGE;
1170
1171         memset(&params, 0, sizeof(params));
1172         params.ratio = div64_u64(input * f, output);
1173         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1174         params.precision = f;
1175         params.error = 64 * f;
1176         params.tu_size = 64;
1177
1178         for (i = params.tu_size; i >= 32; i--)
1179                 if (tegra_sor_compute_params(sor, &params, i))
1180                         break;
1181
1182         if (params.active_frac == 0) {
1183                 config->active_polarity = 0;
1184                 config->active_count = params.active_count;
1185
1186                 if (!params.active_polarity)
1187                         config->active_count--;
1188
1189                 config->tu_size = params.tu_size;
1190                 config->active_frac = 1;
1191         } else {
1192                 config->active_polarity = params.active_polarity;
1193                 config->active_count = params.active_count;
1194                 config->active_frac = params.active_frac;
1195                 config->tu_size = params.tu_size;
1196         }
1197
1198         dev_dbg(sor->dev,
1199                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1200                 config->active_polarity, config->active_count,
1201                 config->tu_size, config->active_frac);
1202
1203         watermark = params.ratio * config->tu_size * (f - params.ratio);
1204         watermark = div_u64(watermark, f);
1205
1206         watermark = div_u64(watermark + params.error, f);
1207         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1208         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1209                             (link->lanes * 8);
1210
1211         if (config->watermark > 30) {
1212                 config->watermark = 30;
1213                 dev_err(sor->dev,
1214                         "unable to compute TU size, forcing watermark to %u\n",
1215                         config->watermark);
1216         } else if (config->watermark > num_syms_per_line) {
1217                 config->watermark = num_syms_per_line;
1218                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1219                         config->watermark);
1220         }
1221
1222         /* compute the number of symbols per horizontal blanking interval */
1223         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1224         config->hblank_symbols = div_u64(num, pclk);
1225
1226         if (link->caps.enhanced_framing)
1227                 config->hblank_symbols -= 3;
1228
1229         config->hblank_symbols -= 12 / link->lanes;
1230
1231         /* compute the number of symbols per vertical blanking interval */
1232         num = (mode->hdisplay - 25) * link_rate;
1233         config->vblank_symbols = div_u64(num, pclk);
1234         config->vblank_symbols -= 36 / link->lanes + 4;
1235
1236         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1237                 config->vblank_symbols);
1238
1239         return 0;
1240 }
1241
1242 static void tegra_sor_apply_config(struct tegra_sor *sor,
1243                                    const struct tegra_sor_config *config)
1244 {
1245         u32 value;
1246
1247         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1248         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1249         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1250         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1251
1252         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1253         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1254         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1255
1256         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1257         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1258
1259         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1260         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1261
1262         if (config->active_polarity)
1263                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1264         else
1265                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1266
1267         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1268         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1269         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1270
1271         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1272         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1273         value |= config->hblank_symbols & 0xffff;
1274         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1275
1276         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1277         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1278         value |= config->vblank_symbols & 0xffff;
1279         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1280 }
1281
1282 static void tegra_sor_mode_set(struct tegra_sor *sor,
1283                                const struct drm_display_mode *mode,
1284                                struct tegra_sor_state *state)
1285 {
1286         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1287         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1288         u32 value;
1289
1290         value = tegra_sor_readl(sor, SOR_STATE1);
1291         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1292         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1293         value &= ~SOR_STATE_ASY_OWNER_MASK;
1294
1295         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1296                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1297
1298         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1299                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1300
1301         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1302                 value |= SOR_STATE_ASY_HSYNCPOL;
1303
1304         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1305                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1306
1307         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1308                 value |= SOR_STATE_ASY_VSYNCPOL;
1309
1310         switch (state->bpc) {
1311         case 16:
1312                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1313                 break;
1314
1315         case 12:
1316                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1317                 break;
1318
1319         case 10:
1320                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1321                 break;
1322
1323         case 8:
1324                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1325                 break;
1326
1327         case 6:
1328                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1329                 break;
1330
1331         default:
1332                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1333                 break;
1334         }
1335
1336         tegra_sor_writel(sor, value, SOR_STATE1);
1337
1338         /*
1339          * TODO: The video timing programming below doesn't seem to match the
1340          * register definitions.
1341          */
1342
1343         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1344         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1345
1346         /* sync end = sync width - 1 */
1347         vse = mode->vsync_end - mode->vsync_start - 1;
1348         hse = mode->hsync_end - mode->hsync_start - 1;
1349
1350         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1351         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1352
1353         /* blank end = sync end + back porch */
1354         vbe = vse + (mode->vtotal - mode->vsync_end);
1355         hbe = hse + (mode->htotal - mode->hsync_end);
1356
1357         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1358         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1359
1360         /* blank start = blank end + active */
1361         vbs = vbe + mode->vdisplay;
1362         hbs = hbe + mode->hdisplay;
1363
1364         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1365         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1366
1367         /* XXX interlacing support */
1368         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1369 }
1370
1371 static int tegra_sor_detach(struct tegra_sor *sor)
1372 {
1373         unsigned long value, timeout;
1374
1375         /* switch to safe mode */
1376         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1377         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1378         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1379         tegra_sor_super_update(sor);
1380
1381         timeout = jiffies + msecs_to_jiffies(250);
1382
1383         while (time_before(jiffies, timeout)) {
1384                 value = tegra_sor_readl(sor, SOR_PWR);
1385                 if (value & SOR_PWR_MODE_SAFE)
1386                         break;
1387         }
1388
1389         if ((value & SOR_PWR_MODE_SAFE) == 0)
1390                 return -ETIMEDOUT;
1391
1392         /* go to sleep */
1393         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1394         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1395         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1396         tegra_sor_super_update(sor);
1397
1398         /* detach */
1399         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1400         value &= ~SOR_SUPER_STATE_ATTACHED;
1401         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1402         tegra_sor_super_update(sor);
1403
1404         timeout = jiffies + msecs_to_jiffies(250);
1405
1406         while (time_before(jiffies, timeout)) {
1407                 value = tegra_sor_readl(sor, SOR_TEST);
1408                 if ((value & SOR_TEST_ATTACHED) == 0)
1409                         break;
1410
1411                 usleep_range(25, 100);
1412         }
1413
1414         if ((value & SOR_TEST_ATTACHED) != 0)
1415                 return -ETIMEDOUT;
1416
1417         return 0;
1418 }
1419
1420 static int tegra_sor_power_down(struct tegra_sor *sor)
1421 {
1422         unsigned long value, timeout;
1423         int err;
1424
1425         value = tegra_sor_readl(sor, SOR_PWR);
1426         value &= ~SOR_PWR_NORMAL_STATE_PU;
1427         value |= SOR_PWR_TRIGGER;
1428         tegra_sor_writel(sor, value, SOR_PWR);
1429
1430         timeout = jiffies + msecs_to_jiffies(250);
1431
1432         while (time_before(jiffies, timeout)) {
1433                 value = tegra_sor_readl(sor, SOR_PWR);
1434                 if ((value & SOR_PWR_TRIGGER) == 0)
1435                         return 0;
1436
1437                 usleep_range(25, 100);
1438         }
1439
1440         if ((value & SOR_PWR_TRIGGER) != 0)
1441                 return -ETIMEDOUT;
1442
1443         /* switch to safe parent clock */
1444         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1445         if (err < 0) {
1446                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1447                 return err;
1448         }
1449
1450         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1451         value |= SOR_PLL2_PORT_POWERDOWN;
1452         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1453
1454         usleep_range(20, 100);
1455
1456         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1457         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1458         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1459
1460         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1461         value |= SOR_PLL2_SEQ_PLLCAPPD;
1462         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1463         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1464
1465         usleep_range(20, 100);
1466
1467         return 0;
1468 }
1469
1470 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1471 {
1472         u32 value;
1473
1474         timeout = jiffies + msecs_to_jiffies(timeout);
1475
1476         while (time_before(jiffies, timeout)) {
1477                 value = tegra_sor_readl(sor, SOR_CRCA);
1478                 if (value & SOR_CRCA_VALID)
1479                         return 0;
1480
1481                 usleep_range(100, 200);
1482         }
1483
1484         return -ETIMEDOUT;
1485 }
1486
1487 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1488 {
1489         struct drm_info_node *node = s->private;
1490         struct tegra_sor *sor = node->info_ent->data;
1491         struct drm_crtc *crtc = sor->output.encoder.crtc;
1492         struct drm_device *drm = node->minor->dev;
1493         int err = 0;
1494         u32 value;
1495
1496         drm_modeset_lock_all(drm);
1497
1498         if (!crtc || !crtc->state->active) {
1499                 err = -EBUSY;
1500                 goto unlock;
1501         }
1502
1503         value = tegra_sor_readl(sor, SOR_STATE1);
1504         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1505         tegra_sor_writel(sor, value, SOR_STATE1);
1506
1507         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1508         value |= SOR_CRC_CNTRL_ENABLE;
1509         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1510
1511         value = tegra_sor_readl(sor, SOR_TEST);
1512         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1513         tegra_sor_writel(sor, value, SOR_TEST);
1514
1515         err = tegra_sor_crc_wait(sor, 100);
1516         if (err < 0)
1517                 goto unlock;
1518
1519         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1520         value = tegra_sor_readl(sor, SOR_CRCB);
1521
1522         seq_printf(s, "%08x\n", value);
1523
1524 unlock:
1525         drm_modeset_unlock_all(drm);
1526         return err;
1527 }
1528
1529 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1530
1531 static const struct debugfs_reg32 tegra_sor_regs[] = {
1532         DEBUGFS_REG32(SOR_CTXSW),
1533         DEBUGFS_REG32(SOR_SUPER_STATE0),
1534         DEBUGFS_REG32(SOR_SUPER_STATE1),
1535         DEBUGFS_REG32(SOR_STATE0),
1536         DEBUGFS_REG32(SOR_STATE1),
1537         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1538         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1539         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1540         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1541         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1542         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1543         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1544         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1545         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1546         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1547         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1548         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1549         DEBUGFS_REG32(SOR_CRC_CNTRL),
1550         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1551         DEBUGFS_REG32(SOR_CLK_CNTRL),
1552         DEBUGFS_REG32(SOR_CAP),
1553         DEBUGFS_REG32(SOR_PWR),
1554         DEBUGFS_REG32(SOR_TEST),
1555         DEBUGFS_REG32(SOR_PLL0),
1556         DEBUGFS_REG32(SOR_PLL1),
1557         DEBUGFS_REG32(SOR_PLL2),
1558         DEBUGFS_REG32(SOR_PLL3),
1559         DEBUGFS_REG32(SOR_CSTM),
1560         DEBUGFS_REG32(SOR_LVDS),
1561         DEBUGFS_REG32(SOR_CRCA),
1562         DEBUGFS_REG32(SOR_CRCB),
1563         DEBUGFS_REG32(SOR_BLANK),
1564         DEBUGFS_REG32(SOR_SEQ_CTL),
1565         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1566         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1567         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1568         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1571         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1572         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1573         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1574         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1575         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1576         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1577         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1578         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1579         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1580         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1581         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1582         DEBUGFS_REG32(SOR_PWM_DIV),
1583         DEBUGFS_REG32(SOR_PWM_CTL),
1584         DEBUGFS_REG32(SOR_VCRC_A0),
1585         DEBUGFS_REG32(SOR_VCRC_A1),
1586         DEBUGFS_REG32(SOR_VCRC_B0),
1587         DEBUGFS_REG32(SOR_VCRC_B1),
1588         DEBUGFS_REG32(SOR_CCRC_A0),
1589         DEBUGFS_REG32(SOR_CCRC_A1),
1590         DEBUGFS_REG32(SOR_CCRC_B0),
1591         DEBUGFS_REG32(SOR_CCRC_B1),
1592         DEBUGFS_REG32(SOR_EDATA_A0),
1593         DEBUGFS_REG32(SOR_EDATA_A1),
1594         DEBUGFS_REG32(SOR_EDATA_B0),
1595         DEBUGFS_REG32(SOR_EDATA_B1),
1596         DEBUGFS_REG32(SOR_COUNT_A0),
1597         DEBUGFS_REG32(SOR_COUNT_A1),
1598         DEBUGFS_REG32(SOR_COUNT_B0),
1599         DEBUGFS_REG32(SOR_COUNT_B1),
1600         DEBUGFS_REG32(SOR_DEBUG_A0),
1601         DEBUGFS_REG32(SOR_DEBUG_A1),
1602         DEBUGFS_REG32(SOR_DEBUG_B0),
1603         DEBUGFS_REG32(SOR_DEBUG_B1),
1604         DEBUGFS_REG32(SOR_TRIG),
1605         DEBUGFS_REG32(SOR_MSCHECK),
1606         DEBUGFS_REG32(SOR_XBAR_CTRL),
1607         DEBUGFS_REG32(SOR_XBAR_POL),
1608         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1609         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1610         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1611         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1612         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1613         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1614         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1615         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1616         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1617         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1618         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1619         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1620         DEBUGFS_REG32(SOR_DP_CONFIG0),
1621         DEBUGFS_REG32(SOR_DP_CONFIG1),
1622         DEBUGFS_REG32(SOR_DP_MN0),
1623         DEBUGFS_REG32(SOR_DP_MN1),
1624         DEBUGFS_REG32(SOR_DP_PADCTL0),
1625         DEBUGFS_REG32(SOR_DP_PADCTL1),
1626         DEBUGFS_REG32(SOR_DP_PADCTL2),
1627         DEBUGFS_REG32(SOR_DP_DEBUG0),
1628         DEBUGFS_REG32(SOR_DP_DEBUG1),
1629         DEBUGFS_REG32(SOR_DP_SPARE0),
1630         DEBUGFS_REG32(SOR_DP_SPARE1),
1631         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1632         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1633         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1634         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1635         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1636         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1637         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1638         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1639         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1640         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1641         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1642         DEBUGFS_REG32(SOR_DP_TPG),
1643         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1644         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1645         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1646         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1647 };
1648
1649 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1650 {
1651         struct drm_info_node *node = s->private;
1652         struct tegra_sor *sor = node->info_ent->data;
1653         struct drm_crtc *crtc = sor->output.encoder.crtc;
1654         struct drm_device *drm = node->minor->dev;
1655         unsigned int i;
1656         int err = 0;
1657
1658         drm_modeset_lock_all(drm);
1659
1660         if (!crtc || !crtc->state->active) {
1661                 err = -EBUSY;
1662                 goto unlock;
1663         }
1664
1665         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1666                 unsigned int offset = tegra_sor_regs[i].offset;
1667
1668                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1669                            offset, tegra_sor_readl(sor, offset));
1670         }
1671
1672 unlock:
1673         drm_modeset_unlock_all(drm);
1674         return err;
1675 }
1676
1677 static const struct drm_info_list debugfs_files[] = {
1678         { "crc", tegra_sor_show_crc, 0, NULL },
1679         { "regs", tegra_sor_show_regs, 0, NULL },
1680 };
1681
1682 static int tegra_sor_late_register(struct drm_connector *connector)
1683 {
1684         struct tegra_output *output = connector_to_output(connector);
1685         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1686         struct drm_minor *minor = connector->dev->primary;
1687         struct dentry *root = connector->debugfs_entry;
1688         struct tegra_sor *sor = to_sor(output);
1689
1690         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1691                                      GFP_KERNEL);
1692         if (!sor->debugfs_files)
1693                 return -ENOMEM;
1694
1695         for (i = 0; i < count; i++)
1696                 sor->debugfs_files[i].data = sor;
1697
1698         drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1699
1700         return 0;
1701 }
1702
1703 static void tegra_sor_early_unregister(struct drm_connector *connector)
1704 {
1705         struct tegra_output *output = connector_to_output(connector);
1706         unsigned int count = ARRAY_SIZE(debugfs_files);
1707         struct tegra_sor *sor = to_sor(output);
1708
1709         drm_debugfs_remove_files(sor->debugfs_files, count,
1710                                  connector->dev->primary);
1711         kfree(sor->debugfs_files);
1712         sor->debugfs_files = NULL;
1713 }
1714
1715 static void tegra_sor_connector_reset(struct drm_connector *connector)
1716 {
1717         struct tegra_sor_state *state;
1718
1719         state = kzalloc(sizeof(*state), GFP_KERNEL);
1720         if (!state)
1721                 return;
1722
1723         if (connector->state) {
1724                 __drm_atomic_helper_connector_destroy_state(connector->state);
1725                 kfree(connector->state);
1726         }
1727
1728         __drm_atomic_helper_connector_reset(connector, &state->base);
1729 }
1730
1731 static enum drm_connector_status
1732 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1733 {
1734         struct tegra_output *output = connector_to_output(connector);
1735         struct tegra_sor *sor = to_sor(output);
1736
1737         if (sor->aux)
1738                 return drm_dp_aux_detect(sor->aux);
1739
1740         return tegra_output_connector_detect(connector, force);
1741 }
1742
1743 static struct drm_connector_state *
1744 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1745 {
1746         struct tegra_sor_state *state = to_sor_state(connector->state);
1747         struct tegra_sor_state *copy;
1748
1749         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1750         if (!copy)
1751                 return NULL;
1752
1753         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1754
1755         return &copy->base;
1756 }
1757
1758 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1759         .reset = tegra_sor_connector_reset,
1760         .detect = tegra_sor_connector_detect,
1761         .fill_modes = drm_helper_probe_single_connector_modes,
1762         .destroy = tegra_output_connector_destroy,
1763         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1764         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1765         .late_register = tegra_sor_late_register,
1766         .early_unregister = tegra_sor_early_unregister,
1767 };
1768
1769 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1770 {
1771         struct tegra_output *output = connector_to_output(connector);
1772         struct tegra_sor *sor = to_sor(output);
1773         int err;
1774
1775         if (sor->aux)
1776                 drm_dp_aux_enable(sor->aux);
1777
1778         err = tegra_output_connector_get_modes(connector);
1779
1780         if (sor->aux)
1781                 drm_dp_aux_disable(sor->aux);
1782
1783         return err;
1784 }
1785
1786 static enum drm_mode_status
1787 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1788                                struct drm_display_mode *mode)
1789 {
1790         return MODE_OK;
1791 }
1792
1793 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1794         .get_modes = tegra_sor_connector_get_modes,
1795         .mode_valid = tegra_sor_connector_mode_valid,
1796 };
1797
1798 static int
1799 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1800                                struct drm_crtc_state *crtc_state,
1801                                struct drm_connector_state *conn_state)
1802 {
1803         struct tegra_output *output = encoder_to_output(encoder);
1804         struct tegra_sor_state *state = to_sor_state(conn_state);
1805         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1806         unsigned long pclk = crtc_state->mode.clock * 1000;
1807         struct tegra_sor *sor = to_sor(output);
1808         struct drm_display_info *info;
1809         int err;
1810
1811         info = &output->connector.display_info;
1812
1813         /*
1814          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1815          * the pixel clock must be corrected accordingly.
1816          */
1817         if (pclk >= 340000000) {
1818                 state->link_speed = 20;
1819                 state->pclk = pclk / 2;
1820         } else {
1821                 state->link_speed = 10;
1822                 state->pclk = pclk;
1823         }
1824
1825         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1826                                          pclk, 0);
1827         if (err < 0) {
1828                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1829                 return err;
1830         }
1831
1832         switch (info->bpc) {
1833         case 8:
1834         case 6:
1835                 state->bpc = info->bpc;
1836                 break;
1837
1838         default:
1839                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1840                 state->bpc = 8;
1841                 break;
1842         }
1843
1844         return 0;
1845 }
1846
1847 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1848 {
1849         u32 value = 0;
1850         size_t i;
1851
1852         for (i = size; i > 0; i--)
1853                 value = (value << 8) | ptr[i - 1];
1854
1855         return value;
1856 }
1857
1858 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1859                                           const void *data, size_t size)
1860 {
1861         const u8 *ptr = data;
1862         unsigned long offset;
1863         size_t i, j;
1864         u32 value;
1865
1866         switch (ptr[0]) {
1867         case HDMI_INFOFRAME_TYPE_AVI:
1868                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1869                 break;
1870
1871         case HDMI_INFOFRAME_TYPE_AUDIO:
1872                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1873                 break;
1874
1875         case HDMI_INFOFRAME_TYPE_VENDOR:
1876                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1877                 break;
1878
1879         default:
1880                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1881                         ptr[0]);
1882                 return;
1883         }
1884
1885         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1886                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1887                 INFOFRAME_HEADER_LEN(ptr[2]);
1888         tegra_sor_writel(sor, value, offset);
1889         offset++;
1890
1891         /*
1892          * Each subpack contains 7 bytes, divided into:
1893          * - subpack_low: bytes 0 - 3
1894          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1895          */
1896         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1897                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1898
1899                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1900                 tegra_sor_writel(sor, value, offset++);
1901
1902                 num = min_t(size_t, rem - num, 3);
1903
1904                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1905                 tegra_sor_writel(sor, value, offset++);
1906         }
1907 }
1908
1909 static int
1910 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1911                                    const struct drm_display_mode *mode)
1912 {
1913         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1914         struct hdmi_avi_infoframe frame;
1915         u32 value;
1916         int err;
1917
1918         /* disable AVI infoframe */
1919         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1920         value &= ~INFOFRAME_CTRL_SINGLE;
1921         value &= ~INFOFRAME_CTRL_OTHER;
1922         value &= ~INFOFRAME_CTRL_ENABLE;
1923         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1924
1925         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1926                                                        &sor->output.connector, mode);
1927         if (err < 0) {
1928                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1929                 return err;
1930         }
1931
1932         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1933         if (err < 0) {
1934                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1935                 return err;
1936         }
1937
1938         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1939
1940         /* enable AVI infoframe */
1941         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1942         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1943         value |= INFOFRAME_CTRL_ENABLE;
1944         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1945
1946         return 0;
1947 }
1948
1949 static void tegra_sor_write_eld(struct tegra_sor *sor)
1950 {
1951         size_t length = drm_eld_size(sor->output.connector.eld), i;
1952
1953         for (i = 0; i < length; i++)
1954                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1955                                  SOR_AUDIO_HDA_ELD_BUFWR);
1956
1957         /*
1958          * The HDA codec will always report an ELD buffer size of 96 bytes and
1959          * the HDA codec driver will check that each byte read from the buffer
1960          * is valid. Therefore every byte must be written, even if no 96 bytes
1961          * were parsed from EDID.
1962          */
1963         for (i = length; i < 96; i++)
1964                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1965 }
1966
1967 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1968 {
1969         u32 value;
1970
1971         /*
1972          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1973          * is used for interoperability between the HDA codec driver and the
1974          * HDMI/DP driver.
1975          */
1976         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1977         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1978         tegra_sor_writel(sor, value, SOR_INT_MASK);
1979
1980         tegra_sor_write_eld(sor);
1981
1982         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1983         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1984 }
1985
1986 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1987 {
1988         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1989         tegra_sor_writel(sor, 0, SOR_INT_MASK);
1990         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1991 }
1992
1993 static void tegra_sor_audio_enable(struct tegra_sor *sor)
1994 {
1995         u32 value;
1996
1997         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
1998
1999         /* select HDA audio input */
2000         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2001         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2002
2003         /* inject null samples */
2004         if (sor->format.channels != 2)
2005                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2006         else
2007                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2008
2009         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2010
2011         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2012
2013         /* enable advertising HBR capability */
2014         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2015 }
2016
2017 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2018 {
2019         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2020         struct hdmi_audio_infoframe frame;
2021         u32 value;
2022         int err;
2023
2024         err = hdmi_audio_infoframe_init(&frame);
2025         if (err < 0) {
2026                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2027                 return err;
2028         }
2029
2030         frame.channels = sor->format.channels;
2031
2032         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2033         if (err < 0) {
2034                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2035                 return err;
2036         }
2037
2038         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2039
2040         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2041         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2042         value |= INFOFRAME_CTRL_ENABLE;
2043         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2044
2045         return 0;
2046 }
2047
2048 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2049 {
2050         u32 value;
2051
2052         tegra_sor_audio_enable(sor);
2053
2054         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2055
2056         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2057                 SOR_HDMI_SPARE_CTS_RESET(1) |
2058                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2059         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2060
2061         /* enable HW CTS */
2062         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2063         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2064
2065         /* allow packet to be sent */
2066         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2067         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2068
2069         /* reset N counter and enable lookup */
2070         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2071         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2072
2073         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2074         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2075         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2076
2077         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2078         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2079
2080         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2081         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2082
2083         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2084         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2085
2086         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2087         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2088         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2089
2090         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2091         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2092         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2093
2094         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2095         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2096         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2097
2098         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2099         value &= ~SOR_HDMI_AUDIO_N_RESET;
2100         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2101
2102         tegra_sor_hdmi_enable_audio_infoframe(sor);
2103 }
2104
2105 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2106 {
2107         u32 value;
2108
2109         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2110         value &= ~INFOFRAME_CTRL_ENABLE;
2111         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2112 }
2113
2114 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2115 {
2116         tegra_sor_hdmi_disable_audio_infoframe(sor);
2117 }
2118
2119 static struct tegra_sor_hdmi_settings *
2120 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2121 {
2122         unsigned int i;
2123
2124         for (i = 0; i < sor->num_settings; i++)
2125                 if (frequency <= sor->settings[i].frequency)
2126                         return &sor->settings[i];
2127
2128         return NULL;
2129 }
2130
2131 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2132 {
2133         u32 value;
2134
2135         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2136         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2137         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2138         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2139 }
2140
2141 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2142 {
2143         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2144         drm_scdc_set_scrambling(&sor->output.connector, false);
2145
2146         tegra_sor_hdmi_disable_scrambling(sor);
2147 }
2148
2149 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2150 {
2151         if (sor->scdc_enabled) {
2152                 cancel_delayed_work_sync(&sor->scdc);
2153                 tegra_sor_hdmi_scdc_disable(sor);
2154         }
2155 }
2156
2157 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2158 {
2159         u32 value;
2160
2161         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2162         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2163         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2164         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2165 }
2166
2167 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2168 {
2169         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2170         drm_scdc_set_scrambling(&sor->output.connector, true);
2171
2172         tegra_sor_hdmi_enable_scrambling(sor);
2173 }
2174
2175 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2176 {
2177         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2178
2179         if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2180                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2181                 tegra_sor_hdmi_scdc_enable(sor);
2182         }
2183
2184         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2185 }
2186
2187 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2188 {
2189         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2190         struct drm_display_mode *mode;
2191
2192         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2193
2194         if (mode->clock >= 340000 && scdc->supported) {
2195                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2196                 tegra_sor_hdmi_scdc_enable(sor);
2197                 sor->scdc_enabled = true;
2198         }
2199 }
2200
2201 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2202 {
2203         struct tegra_output *output = encoder_to_output(encoder);
2204         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2205         struct tegra_sor *sor = to_sor(output);
2206         u32 value;
2207         int err;
2208
2209         tegra_sor_audio_unprepare(sor);
2210         tegra_sor_hdmi_scdc_stop(sor);
2211
2212         err = tegra_sor_detach(sor);
2213         if (err < 0)
2214                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2215
2216         tegra_sor_writel(sor, 0, SOR_STATE1);
2217         tegra_sor_update(sor);
2218
2219         /* disable display to SOR clock */
2220         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2221
2222         if (!sor->soc->has_nvdisplay)
2223                 value &= ~SOR1_TIMING_CYA;
2224
2225         value &= ~SOR_ENABLE(sor->index);
2226
2227         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2228
2229         tegra_dc_commit(dc);
2230
2231         err = tegra_sor_power_down(sor);
2232         if (err < 0)
2233                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2234
2235         err = tegra_io_pad_power_disable(sor->pad);
2236         if (err < 0)
2237                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2238
2239         host1x_client_suspend(&sor->client);
2240 }
2241
2242 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2243 {
2244         struct tegra_output *output = encoder_to_output(encoder);
2245         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2246         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2247         struct tegra_sor_hdmi_settings *settings;
2248         struct tegra_sor *sor = to_sor(output);
2249         struct tegra_sor_state *state;
2250         struct drm_display_mode *mode;
2251         unsigned long rate, pclk;
2252         unsigned int div, i;
2253         u32 value;
2254         int err;
2255
2256         state = to_sor_state(output->connector.state);
2257         mode = &encoder->crtc->state->adjusted_mode;
2258         pclk = mode->clock * 1000;
2259
2260         err = host1x_client_resume(&sor->client);
2261         if (err < 0) {
2262                 dev_err(sor->dev, "failed to resume: %d\n", err);
2263                 return;
2264         }
2265
2266         /* switch to safe parent clock */
2267         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2268         if (err < 0) {
2269                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2270                 return;
2271         }
2272
2273         div = clk_get_rate(sor->clk) / 1000000 * 4;
2274
2275         err = tegra_io_pad_power_enable(sor->pad);
2276         if (err < 0)
2277                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2278
2279         usleep_range(20, 100);
2280
2281         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2282         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2283         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2284
2285         usleep_range(20, 100);
2286
2287         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2288         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2289         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2290
2291         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2292         value &= ~SOR_PLL0_VCOPD;
2293         value &= ~SOR_PLL0_PWR;
2294         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2295
2296         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2297         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2298         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2299
2300         usleep_range(200, 400);
2301
2302         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2303         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2304         value &= ~SOR_PLL2_PORT_POWERDOWN;
2305         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2306
2307         usleep_range(20, 100);
2308
2309         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2310         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2311                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2312         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2313
2314         while (true) {
2315                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2316                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2317                         break;
2318
2319                 usleep_range(250, 1000);
2320         }
2321
2322         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2323                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2324         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2325
2326         while (true) {
2327                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2328                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2329                         break;
2330
2331                 usleep_range(250, 1000);
2332         }
2333
2334         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2335         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2336         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2337
2338         if (mode->clock < 340000) {
2339                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2340                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2341         } else {
2342                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2343                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2344         }
2345
2346         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2347         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2348
2349         /* SOR pad PLL stabilization time */
2350         usleep_range(250, 1000);
2351
2352         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2353         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2354         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2355         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2356
2357         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2358         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2359         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2360         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2361         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2362         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2363
2364         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2365                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2366         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2367
2368         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2369                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2370         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2371         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2372
2373         if (!sor->soc->has_nvdisplay) {
2374                 /* program the reference clock */
2375                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2376                 tegra_sor_writel(sor, value, SOR_REFCLK);
2377         }
2378
2379         /* XXX not in TRM */
2380         for (value = 0, i = 0; i < 5; i++)
2381                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2382                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2383
2384         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2385         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2386
2387         /*
2388          * Switch the pad clock to the DP clock. Note that we cannot actually
2389          * do this because Tegra186 and later don't support clk_set_parent()
2390          * on the sorX_pad_clkout clocks. We already do the equivalent above
2391          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2392          */
2393 #if 0
2394         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2395         if (err < 0) {
2396                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2397                         err);
2398                 return;
2399         }
2400 #endif
2401
2402         /* switch the SOR clock to the pad clock */
2403         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2404         if (err < 0) {
2405                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2406                         err);
2407                 return;
2408         }
2409
2410         /* switch the output clock to the parent pixel clock */
2411         err = clk_set_parent(sor->clk, sor->clk_parent);
2412         if (err < 0) {
2413                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2414                         err);
2415                 return;
2416         }
2417
2418         /* adjust clock rate for HDMI 2.0 modes */
2419         rate = clk_get_rate(sor->clk_parent);
2420
2421         if (mode->clock >= 340000)
2422                 rate /= 2;
2423
2424         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2425
2426         clk_set_rate(sor->clk, rate);
2427
2428         if (!sor->soc->has_nvdisplay) {
2429                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2430
2431                 /* XXX is this the proper check? */
2432                 if (mode->clock < 75000)
2433                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2434
2435                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2436         }
2437
2438         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2439
2440         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2441                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2442         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2443
2444         if (!dc->soc->has_nvdisplay) {
2445                 /* H_PULSE2 setup */
2446                 pulse_start = h_ref_to_sync +
2447                               (mode->hsync_end - mode->hsync_start) +
2448                               (mode->htotal - mode->hsync_end) - 10;
2449
2450                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2451                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2452                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2453
2454                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2455                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2456
2457                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2458                 value |= H_PULSE2_ENABLE;
2459                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2460         }
2461
2462         /* infoframe setup */
2463         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2464         if (err < 0)
2465                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2466
2467         /* XXX HDMI audio support not implemented yet */
2468         tegra_sor_hdmi_disable_audio_infoframe(sor);
2469
2470         /* use single TMDS protocol */
2471         value = tegra_sor_readl(sor, SOR_STATE1);
2472         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2473         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2474         tegra_sor_writel(sor, value, SOR_STATE1);
2475
2476         /* power up pad calibration */
2477         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2478         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2479         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2480
2481         /* production settings */
2482         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2483         if (!settings) {
2484                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2485                         mode->clock * 1000);
2486                 return;
2487         }
2488
2489         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2490         value &= ~SOR_PLL0_ICHPMP_MASK;
2491         value &= ~SOR_PLL0_FILTER_MASK;
2492         value &= ~SOR_PLL0_VCOCAP_MASK;
2493         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2494         value |= SOR_PLL0_FILTER(settings->filter);
2495         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2496         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2497
2498         /* XXX not in TRM */
2499         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2500         value &= ~SOR_PLL1_LOADADJ_MASK;
2501         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2502         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2503         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2504         value |= SOR_PLL1_TMDS_TERM;
2505         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2506
2507         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2508         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2509         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2510         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2511         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2512         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2513         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2514         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2515         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2516         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2517
2518         value = settings->drive_current[3] << 24 |
2519                 settings->drive_current[2] << 16 |
2520                 settings->drive_current[1] <<  8 |
2521                 settings->drive_current[0] <<  0;
2522         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2523
2524         value = settings->preemphasis[3] << 24 |
2525                 settings->preemphasis[2] << 16 |
2526                 settings->preemphasis[1] <<  8 |
2527                 settings->preemphasis[0] <<  0;
2528         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2529
2530         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2531         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2532         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2533         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2534         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2535
2536         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2537         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2538         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2539         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2540
2541         /* power down pad calibration */
2542         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2543         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2544         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2545
2546         if (!dc->soc->has_nvdisplay) {
2547                 /* miscellaneous display controller settings */
2548                 value = VSYNC_H_POSITION(1);
2549                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2550         }
2551
2552         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2553         value &= ~DITHER_CONTROL_MASK;
2554         value &= ~BASE_COLOR_SIZE_MASK;
2555
2556         switch (state->bpc) {
2557         case 6:
2558                 value |= BASE_COLOR_SIZE_666;
2559                 break;
2560
2561         case 8:
2562                 value |= BASE_COLOR_SIZE_888;
2563                 break;
2564
2565         case 10:
2566                 value |= BASE_COLOR_SIZE_101010;
2567                 break;
2568
2569         case 12:
2570                 value |= BASE_COLOR_SIZE_121212;
2571                 break;
2572
2573         default:
2574                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2575                 value |= BASE_COLOR_SIZE_888;
2576                 break;
2577         }
2578
2579         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2580
2581         /* XXX set display head owner */
2582         value = tegra_sor_readl(sor, SOR_STATE1);
2583         value &= ~SOR_STATE_ASY_OWNER_MASK;
2584         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2585         tegra_sor_writel(sor, value, SOR_STATE1);
2586
2587         err = tegra_sor_power_up(sor, 250);
2588         if (err < 0)
2589                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2590
2591         /* configure dynamic range of output */
2592         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2593         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2594         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2595         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2596
2597         /* configure colorspace */
2598         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2599         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2600         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2601         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2602
2603         tegra_sor_mode_set(sor, mode, state);
2604
2605         tegra_sor_update(sor);
2606
2607         /* program preamble timing in SOR (XXX) */
2608         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2609         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2610         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2611
2612         err = tegra_sor_attach(sor);
2613         if (err < 0)
2614                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2615
2616         /* enable display to SOR clock and generate HDMI preamble */
2617         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2618
2619         if (!sor->soc->has_nvdisplay)
2620                 value |= SOR1_TIMING_CYA;
2621
2622         value |= SOR_ENABLE(sor->index);
2623
2624         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2625
2626         if (dc->soc->has_nvdisplay) {
2627                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2628                 value &= ~PROTOCOL_MASK;
2629                 value |= PROTOCOL_SINGLE_TMDS_A;
2630                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2631         }
2632
2633         tegra_dc_commit(dc);
2634
2635         err = tegra_sor_wakeup(sor);
2636         if (err < 0)
2637                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2638
2639         tegra_sor_hdmi_scdc_start(sor);
2640         tegra_sor_audio_prepare(sor);
2641 }
2642
2643 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2644         .disable = tegra_sor_hdmi_disable,
2645         .enable = tegra_sor_hdmi_enable,
2646         .atomic_check = tegra_sor_encoder_atomic_check,
2647 };
2648
2649 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2650 {
2651         struct tegra_output *output = encoder_to_output(encoder);
2652         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2653         struct tegra_sor *sor = to_sor(output);
2654         u32 value;
2655         int err;
2656
2657         if (output->panel)
2658                 drm_panel_disable(output->panel);
2659
2660         /*
2661          * Do not attempt to power down a DP link if we're not connected since
2662          * the AUX transactions would just be timing out.
2663          */
2664         if (output->connector.status != connector_status_disconnected) {
2665                 err = drm_dp_link_power_down(sor->aux, &sor->link);
2666                 if (err < 0)
2667                         dev_err(sor->dev, "failed to power down link: %d\n",
2668                                 err);
2669         }
2670
2671         err = tegra_sor_detach(sor);
2672         if (err < 0)
2673                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2674
2675         tegra_sor_writel(sor, 0, SOR_STATE1);
2676         tegra_sor_update(sor);
2677
2678         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2679         value &= ~SOR_ENABLE(sor->index);
2680         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2681         tegra_dc_commit(dc);
2682
2683         value = tegra_sor_readl(sor, SOR_STATE1);
2684         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2685         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2686         value &= ~SOR_STATE_ASY_OWNER_MASK;
2687         tegra_sor_writel(sor, value, SOR_STATE1);
2688         tegra_sor_update(sor);
2689
2690         /* switch to safe parent clock */
2691         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2692         if (err < 0)
2693                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2694
2695         err = tegra_sor_power_down(sor);
2696         if (err < 0)
2697                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2698
2699         err = tegra_io_pad_power_disable(sor->pad);
2700         if (err < 0)
2701                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2702
2703         err = drm_dp_aux_disable(sor->aux);
2704         if (err < 0)
2705                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2706
2707         if (output->panel)
2708                 drm_panel_unprepare(output->panel);
2709
2710         host1x_client_suspend(&sor->client);
2711 }
2712
2713 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2714 {
2715         struct tegra_output *output = encoder_to_output(encoder);
2716         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2717         struct tegra_sor *sor = to_sor(output);
2718         struct tegra_sor_config config;
2719         struct tegra_sor_state *state;
2720         struct drm_display_mode *mode;
2721         struct drm_display_info *info;
2722         unsigned int i;
2723         u32 value;
2724         int err;
2725
2726         state = to_sor_state(output->connector.state);
2727         mode = &encoder->crtc->state->adjusted_mode;
2728         info = &output->connector.display_info;
2729
2730         err = host1x_client_resume(&sor->client);
2731         if (err < 0) {
2732                 dev_err(sor->dev, "failed to resume: %d\n", err);
2733                 return;
2734         }
2735
2736         /* switch to safe parent clock */
2737         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2738         if (err < 0)
2739                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2740
2741         err = tegra_io_pad_power_enable(sor->pad);
2742         if (err < 0)
2743                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2744
2745         usleep_range(20, 100);
2746
2747         err = drm_dp_aux_enable(sor->aux);
2748         if (err < 0)
2749                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2750
2751         err = drm_dp_link_probe(sor->aux, &sor->link);
2752         if (err < 0)
2753                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2754
2755         tegra_sor_filter_rates(sor);
2756
2757         err = drm_dp_link_choose(&sor->link, mode, info);
2758         if (err < 0)
2759                 dev_err(sor->dev, "failed to choose link: %d\n", err);
2760
2761         if (output->panel)
2762                 drm_panel_prepare(output->panel);
2763
2764         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2765         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2766         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2767
2768         usleep_range(20, 40);
2769
2770         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2771         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2772         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2773
2774         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2775         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2776         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2777
2778         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2779         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2780         value |= SOR_PLL2_SEQ_PLLCAPPD;
2781         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2782
2783         usleep_range(200, 400);
2784
2785         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2786         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2787         value &= ~SOR_PLL2_PORT_POWERDOWN;
2788         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2789
2790         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2791         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2792
2793         if (output->panel)
2794                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2795         else
2796                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2797
2798         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2799
2800         usleep_range(200, 400);
2801
2802         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2803         /* XXX not in TRM */
2804         if (output->panel)
2805                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2806         else
2807                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2808
2809         value |= SOR_DP_SPARE_SEQ_ENABLE;
2810         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2811
2812         /* XXX not in TRM */
2813         tegra_sor_writel(sor, 0, SOR_LVDS);
2814
2815         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2816         value &= ~SOR_PLL0_ICHPMP_MASK;
2817         value &= ~SOR_PLL0_VCOCAP_MASK;
2818         value |= SOR_PLL0_ICHPMP(0x1);
2819         value |= SOR_PLL0_VCOCAP(0x3);
2820         value |= SOR_PLL0_RESISTOR_EXT;
2821         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2822
2823         /* XXX not in TRM */
2824         for (value = 0, i = 0; i < 5; i++)
2825                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2826                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2827
2828         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2829         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2830
2831         /*
2832          * Switch the pad clock to the DP clock. Note that we cannot actually
2833          * do this because Tegra186 and later don't support clk_set_parent()
2834          * on the sorX_pad_clkout clocks. We already do the equivalent above
2835          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2836          */
2837 #if 0
2838         err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2839         if (err < 0) {
2840                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2841                         err);
2842                 return;
2843         }
2844 #endif
2845
2846         /* switch the SOR clock to the pad clock */
2847         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2848         if (err < 0) {
2849                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2850                         err);
2851                 return;
2852         }
2853
2854         /* switch the output clock to the parent pixel clock */
2855         err = clk_set_parent(sor->clk, sor->clk_parent);
2856         if (err < 0) {
2857                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2858                         err);
2859                 return;
2860         }
2861
2862         /* use DP-A protocol */
2863         value = tegra_sor_readl(sor, SOR_STATE1);
2864         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2865         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2866         tegra_sor_writel(sor, value, SOR_STATE1);
2867
2868         /* enable port */
2869         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2870         value |= SOR_DP_LINKCTL_ENABLE;
2871         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2872
2873         tegra_sor_dp_term_calibrate(sor);
2874
2875         err = drm_dp_link_train(&sor->link);
2876         if (err < 0)
2877                 dev_err(sor->dev, "link training failed: %d\n", err);
2878         else
2879                 dev_dbg(sor->dev, "link training succeeded\n");
2880
2881         err = drm_dp_link_power_up(sor->aux, &sor->link);
2882         if (err < 0)
2883                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2884
2885         /* compute configuration */
2886         memset(&config, 0, sizeof(config));
2887         config.bits_per_pixel = state->bpc * 3;
2888
2889         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2890         if (err < 0)
2891                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2892
2893         tegra_sor_apply_config(sor, &config);
2894         tegra_sor_mode_set(sor, mode, state);
2895
2896         if (output->panel) {
2897                 /* CSTM (LVDS, link A/B, upper) */
2898                 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2899                         SOR_CSTM_UPPER;
2900                 tegra_sor_writel(sor, value, SOR_CSTM);
2901
2902                 /* PWM setup */
2903                 err = tegra_sor_setup_pwm(sor, 250);
2904                 if (err < 0)
2905                         dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2906         }
2907
2908         tegra_sor_update(sor);
2909
2910         err = tegra_sor_power_up(sor, 250);
2911         if (err < 0)
2912                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2913
2914         /* attach and wake up */
2915         err = tegra_sor_attach(sor);
2916         if (err < 0)
2917                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2918
2919         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2920         value |= SOR_ENABLE(sor->index);
2921         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2922
2923         tegra_dc_commit(dc);
2924
2925         err = tegra_sor_wakeup(sor);
2926         if (err < 0)
2927                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2928
2929         if (output->panel)
2930                 drm_panel_enable(output->panel);
2931 }
2932
2933 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2934         .disable = tegra_sor_dp_disable,
2935         .enable = tegra_sor_dp_enable,
2936         .atomic_check = tegra_sor_encoder_atomic_check,
2937 };
2938
2939 static void tegra_sor_disable_regulator(void *data)
2940 {
2941         struct regulator *reg = data;
2942
2943         regulator_disable(reg);
2944 }
2945
2946 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2947 {
2948         int err;
2949
2950         err = regulator_enable(reg);
2951         if (err)
2952                 return err;
2953
2954         return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2955 }
2956
2957 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2958 {
2959         int err;
2960
2961         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2962         if (IS_ERR(sor->avdd_io_supply))
2963                 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2964                                      "cannot get AVDD I/O supply\n");
2965
2966         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2967         if (err < 0) {
2968                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2969                         err);
2970                 return err;
2971         }
2972
2973         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2974         if (IS_ERR(sor->vdd_pll_supply))
2975                 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2976                                      "cannot get VDD PLL supply\n");
2977
2978         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2979         if (err < 0) {
2980                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2981                         err);
2982                 return err;
2983         }
2984
2985         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2986         if (IS_ERR(sor->hdmi_supply))
2987                 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2988                                      "cannot get HDMI supply\n");
2989
2990         err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2991         if (err < 0) {
2992                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2993                 return err;
2994         }
2995
2996         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
2997
2998         return 0;
2999 }
3000
3001 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3002         .name = "HDMI",
3003         .probe = tegra_sor_hdmi_probe,
3004         .audio_enable = tegra_sor_hdmi_audio_enable,
3005         .audio_disable = tegra_sor_hdmi_audio_disable,
3006 };
3007
3008 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3009 {
3010         int err;
3011
3012         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3013         if (IS_ERR(sor->avdd_io_supply))
3014                 return PTR_ERR(sor->avdd_io_supply);
3015
3016         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3017         if (err < 0)
3018                 return err;
3019
3020         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3021         if (IS_ERR(sor->vdd_pll_supply))
3022                 return PTR_ERR(sor->vdd_pll_supply);
3023
3024         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3025         if (err < 0)
3026                 return err;
3027
3028         return 0;
3029 }
3030
3031 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3032         .name = "DP",
3033         .probe = tegra_sor_dp_probe,
3034 };
3035
3036 static int tegra_sor_init(struct host1x_client *client)
3037 {
3038         struct drm_device *drm = dev_get_drvdata(client->host);
3039         const struct drm_encoder_helper_funcs *helpers = NULL;
3040         struct tegra_sor *sor = host1x_client_to_sor(client);
3041         int connector = DRM_MODE_CONNECTOR_Unknown;
3042         int encoder = DRM_MODE_ENCODER_NONE;
3043         int err;
3044
3045         if (!sor->aux) {
3046                 if (sor->ops == &tegra_sor_hdmi_ops) {
3047                         connector = DRM_MODE_CONNECTOR_HDMIA;
3048                         encoder = DRM_MODE_ENCODER_TMDS;
3049                         helpers = &tegra_sor_hdmi_helpers;
3050                 } else if (sor->soc->supports_lvds) {
3051                         connector = DRM_MODE_CONNECTOR_LVDS;
3052                         encoder = DRM_MODE_ENCODER_LVDS;
3053                 }
3054         } else {
3055                 if (sor->output.panel) {
3056                         connector = DRM_MODE_CONNECTOR_eDP;
3057                         encoder = DRM_MODE_ENCODER_TMDS;
3058                         helpers = &tegra_sor_dp_helpers;
3059                 } else {
3060                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3061                         encoder = DRM_MODE_ENCODER_TMDS;
3062                         helpers = &tegra_sor_dp_helpers;
3063                 }
3064
3065                 sor->link.ops = &tegra_sor_dp_link_ops;
3066                 sor->link.aux = sor->aux;
3067         }
3068
3069         sor->output.dev = sor->dev;
3070
3071         drm_connector_init_with_ddc(drm, &sor->output.connector,
3072                                     &tegra_sor_connector_funcs,
3073                                     connector,
3074                                     sor->output.ddc);
3075         drm_connector_helper_add(&sor->output.connector,
3076                                  &tegra_sor_connector_helper_funcs);
3077         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3078
3079         drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3080         drm_encoder_helper_add(&sor->output.encoder, helpers);
3081
3082         drm_connector_attach_encoder(&sor->output.connector,
3083                                           &sor->output.encoder);
3084         drm_connector_register(&sor->output.connector);
3085
3086         err = tegra_output_init(drm, &sor->output);
3087         if (err < 0) {
3088                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3089                 return err;
3090         }
3091
3092         tegra_output_find_possible_crtcs(&sor->output, drm);
3093
3094         if (sor->aux) {
3095                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3096                 if (err < 0) {
3097                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3098                         return err;
3099                 }
3100         }
3101
3102         /*
3103          * XXX: Remove this reset once proper hand-over from firmware to
3104          * kernel is possible.
3105          */
3106         if (sor->rst) {
3107                 err = pm_runtime_resume_and_get(sor->dev);
3108                 if (err < 0) {
3109                         dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3110                         return err;
3111                 }
3112
3113                 err = reset_control_acquire(sor->rst);
3114                 if (err < 0) {
3115                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3116                                 err);
3117                         goto rpm_put;
3118                 }
3119
3120                 err = reset_control_assert(sor->rst);
3121                 if (err < 0) {
3122                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3123                                 err);
3124                         goto rpm_put;
3125                 }
3126         }
3127
3128         err = clk_prepare_enable(sor->clk);
3129         if (err < 0) {
3130                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3131                 goto rpm_put;
3132         }
3133
3134         usleep_range(1000, 3000);
3135
3136         if (sor->rst) {
3137                 err = reset_control_deassert(sor->rst);
3138                 if (err < 0) {
3139                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3140                                 err);
3141                         clk_disable_unprepare(sor->clk);
3142                         goto rpm_put;
3143                 }
3144
3145                 reset_control_release(sor->rst);
3146                 pm_runtime_put(sor->dev);
3147         }
3148
3149         err = clk_prepare_enable(sor->clk_safe);
3150         if (err < 0) {
3151                 clk_disable_unprepare(sor->clk);
3152                 return err;
3153         }
3154
3155         err = clk_prepare_enable(sor->clk_dp);
3156         if (err < 0) {
3157                 clk_disable_unprepare(sor->clk_safe);
3158                 clk_disable_unprepare(sor->clk);
3159                 return err;
3160         }
3161
3162         return 0;
3163
3164 rpm_put:
3165         if (sor->rst)
3166                 pm_runtime_put(sor->dev);
3167
3168         return err;
3169 }
3170
3171 static int tegra_sor_exit(struct host1x_client *client)
3172 {
3173         struct tegra_sor *sor = host1x_client_to_sor(client);
3174         int err;
3175
3176         tegra_output_exit(&sor->output);
3177
3178         if (sor->aux) {
3179                 err = drm_dp_aux_detach(sor->aux);
3180                 if (err < 0) {
3181                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3182                         return err;
3183                 }
3184         }
3185
3186         clk_disable_unprepare(sor->clk_safe);
3187         clk_disable_unprepare(sor->clk_dp);
3188         clk_disable_unprepare(sor->clk);
3189
3190         return 0;
3191 }
3192
3193 static int tegra_sor_runtime_suspend(struct host1x_client *client)
3194 {
3195         struct tegra_sor *sor = host1x_client_to_sor(client);
3196         struct device *dev = client->dev;
3197         int err;
3198
3199         if (sor->rst) {
3200                 err = reset_control_assert(sor->rst);
3201                 if (err < 0) {
3202                         dev_err(dev, "failed to assert reset: %d\n", err);
3203                         return err;
3204                 }
3205
3206                 reset_control_release(sor->rst);
3207         }
3208
3209         usleep_range(1000, 2000);
3210
3211         clk_disable_unprepare(sor->clk);
3212         pm_runtime_put_sync(dev);
3213
3214         return 0;
3215 }
3216
3217 static int tegra_sor_runtime_resume(struct host1x_client *client)
3218 {
3219         struct tegra_sor *sor = host1x_client_to_sor(client);
3220         struct device *dev = client->dev;
3221         int err;
3222
3223         err = pm_runtime_resume_and_get(dev);
3224         if (err < 0) {
3225                 dev_err(dev, "failed to get runtime PM: %d\n", err);
3226                 return err;
3227         }
3228
3229         err = clk_prepare_enable(sor->clk);
3230         if (err < 0) {
3231                 dev_err(dev, "failed to enable clock: %d\n", err);
3232                 goto put_rpm;
3233         }
3234
3235         usleep_range(1000, 2000);
3236
3237         if (sor->rst) {
3238                 err = reset_control_acquire(sor->rst);
3239                 if (err < 0) {
3240                         dev_err(dev, "failed to acquire reset: %d\n", err);
3241                         goto disable_clk;
3242                 }
3243
3244                 err = reset_control_deassert(sor->rst);
3245                 if (err < 0) {
3246                         dev_err(dev, "failed to deassert reset: %d\n", err);
3247                         goto release_reset;
3248                 }
3249         }
3250
3251         return 0;
3252
3253 release_reset:
3254         reset_control_release(sor->rst);
3255 disable_clk:
3256         clk_disable_unprepare(sor->clk);
3257 put_rpm:
3258         pm_runtime_put_sync(dev);
3259         return err;
3260 }
3261
3262 static const struct host1x_client_ops sor_client_ops = {
3263         .init = tegra_sor_init,
3264         .exit = tegra_sor_exit,
3265         .suspend = tegra_sor_runtime_suspend,
3266         .resume = tegra_sor_runtime_resume,
3267 };
3268
3269 static const u8 tegra124_sor_xbar_cfg[5] = {
3270         0, 1, 2, 3, 4
3271 };
3272
3273 static const struct tegra_sor_regs tegra124_sor_regs = {
3274         .head_state0 = 0x05,
3275         .head_state1 = 0x07,
3276         .head_state2 = 0x09,
3277         .head_state3 = 0x0b,
3278         .head_state4 = 0x0d,
3279         .head_state5 = 0x0f,
3280         .pll0 = 0x17,
3281         .pll1 = 0x18,
3282         .pll2 = 0x19,
3283         .pll3 = 0x1a,
3284         .dp_padctl0 = 0x5c,
3285         .dp_padctl2 = 0x73,
3286 };
3287
3288 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3289 static const u8 tegra124_sor_lane_map[4] = {
3290         2, 1, 0, 3,
3291 };
3292
3293 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3294         {
3295                 { 0x13, 0x19, 0x1e, 0x28 },
3296                 { 0x1e, 0x25, 0x2d, },
3297                 { 0x28, 0x32, },
3298                 { 0x3c, },
3299         }, {
3300                 { 0x12, 0x17, 0x1b, 0x25 },
3301                 { 0x1c, 0x23, 0x2a, },
3302                 { 0x25, 0x2f, },
3303                 { 0x39, }
3304         }, {
3305                 { 0x12, 0x16, 0x1a, 0x22 },
3306                 { 0x1b, 0x20, 0x27, },
3307                 { 0x24, 0x2d, },
3308                 { 0x36, },
3309         }, {
3310                 { 0x11, 0x14, 0x17, 0x1f },
3311                 { 0x19, 0x1e, 0x24, },
3312                 { 0x22, 0x2a, },
3313                 { 0x32, },
3314         },
3315 };
3316
3317 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3318         {
3319                 { 0x00, 0x09, 0x13, 0x25 },
3320                 { 0x00, 0x0f, 0x1e, },
3321                 { 0x00, 0x14, },
3322                 { 0x00, },
3323         }, {
3324                 { 0x00, 0x0a, 0x14, 0x28 },
3325                 { 0x00, 0x0f, 0x1e, },
3326                 { 0x00, 0x14, },
3327                 { 0x00 },
3328         }, {
3329                 { 0x00, 0x0a, 0x14, 0x28 },
3330                 { 0x00, 0x0f, 0x1e, },
3331                 { 0x00, 0x14, },
3332                 { 0x00, },
3333         }, {
3334                 { 0x00, 0x0a, 0x14, 0x28 },
3335                 { 0x00, 0x0f, 0x1e, },
3336                 { 0x00, 0x14, },
3337                 { 0x00, },
3338         },
3339 };
3340
3341 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3342         {
3343                 { 0x00, 0x00, 0x00, 0x00 },
3344                 { 0x00, 0x00, 0x00, },
3345                 { 0x00, 0x00, },
3346                 { 0x00, },
3347         }, {
3348                 { 0x02, 0x02, 0x04, 0x05 },
3349                 { 0x02, 0x04, 0x05, },
3350                 { 0x04, 0x05, },
3351                 { 0x05, },
3352         }, {
3353                 { 0x04, 0x05, 0x08, 0x0b },
3354                 { 0x05, 0x09, 0x0b, },
3355                 { 0x08, 0x0a, },
3356                 { 0x0b, },
3357         }, {
3358                 { 0x05, 0x09, 0x0b, 0x12 },
3359                 { 0x09, 0x0d, 0x12, },
3360                 { 0x0b, 0x0f, },
3361                 { 0x12, },
3362         },
3363 };
3364
3365 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3366         {
3367                 { 0x20, 0x30, 0x40, 0x60 },
3368                 { 0x30, 0x40, 0x60, },
3369                 { 0x40, 0x60, },
3370                 { 0x60, },
3371         }, {
3372                 { 0x20, 0x20, 0x30, 0x50 },
3373                 { 0x30, 0x40, 0x50, },
3374                 { 0x40, 0x50, },
3375                 { 0x60, },
3376         }, {
3377                 { 0x20, 0x20, 0x30, 0x40, },
3378                 { 0x30, 0x30, 0x40, },
3379                 { 0x40, 0x50, },
3380                 { 0x60, },
3381         }, {
3382                 { 0x20, 0x20, 0x20, 0x40, },
3383                 { 0x30, 0x30, 0x40, },
3384                 { 0x40, 0x40, },
3385                 { 0x60, },
3386         },
3387 };
3388
3389 static const struct tegra_sor_soc tegra124_sor = {
3390         .supports_lvds = true,
3391         .supports_hdmi = false,
3392         .supports_dp = true,
3393         .supports_audio = false,
3394         .supports_hdcp = false,
3395         .regs = &tegra124_sor_regs,
3396         .has_nvdisplay = false,
3397         .xbar_cfg = tegra124_sor_xbar_cfg,
3398         .lane_map = tegra124_sor_lane_map,
3399         .voltage_swing = tegra124_sor_voltage_swing,
3400         .pre_emphasis = tegra124_sor_pre_emphasis,
3401         .post_cursor = tegra124_sor_post_cursor,
3402         .tx_pu = tegra124_sor_tx_pu,
3403 };
3404
3405 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3406         {
3407                 { 0x00, 0x08, 0x12, 0x24 },
3408                 { 0x01, 0x0e, 0x1d, },
3409                 { 0x01, 0x13, },
3410                 { 0x00, },
3411         }, {
3412                 { 0x00, 0x08, 0x12, 0x24 },
3413                 { 0x00, 0x0e, 0x1d, },
3414                 { 0x00, 0x13, },
3415                 { 0x00 },
3416         }, {
3417                 { 0x00, 0x08, 0x12, 0x24 },
3418                 { 0x00, 0x0e, 0x1d, },
3419                 { 0x00, 0x13, },
3420                 { 0x00, },
3421         }, {
3422                 { 0x00, 0x08, 0x12, 0x24 },
3423                 { 0x00, 0x0e, 0x1d, },
3424                 { 0x00, 0x13, },
3425                 { 0x00, },
3426         },
3427 };
3428
3429 static const struct tegra_sor_soc tegra132_sor = {
3430         .supports_lvds = true,
3431         .supports_hdmi = false,
3432         .supports_dp = true,
3433         .supports_audio = false,
3434         .supports_hdcp = false,
3435         .regs = &tegra124_sor_regs,
3436         .has_nvdisplay = false,
3437         .xbar_cfg = tegra124_sor_xbar_cfg,
3438         .lane_map = tegra124_sor_lane_map,
3439         .voltage_swing = tegra124_sor_voltage_swing,
3440         .pre_emphasis = tegra132_sor_pre_emphasis,
3441         .post_cursor = tegra124_sor_post_cursor,
3442         .tx_pu = tegra124_sor_tx_pu,
3443 };
3444
3445 static const struct tegra_sor_regs tegra210_sor_regs = {
3446         .head_state0 = 0x05,
3447         .head_state1 = 0x07,
3448         .head_state2 = 0x09,
3449         .head_state3 = 0x0b,
3450         .head_state4 = 0x0d,
3451         .head_state5 = 0x0f,
3452         .pll0 = 0x17,
3453         .pll1 = 0x18,
3454         .pll2 = 0x19,
3455         .pll3 = 0x1a,
3456         .dp_padctl0 = 0x5c,
3457         .dp_padctl2 = 0x73,
3458 };
3459
3460 static const u8 tegra210_sor_xbar_cfg[5] = {
3461         2, 1, 0, 3, 4
3462 };
3463
3464 static const u8 tegra210_sor_lane_map[4] = {
3465         0, 1, 2, 3,
3466 };
3467
3468 static const struct tegra_sor_soc tegra210_sor = {
3469         .supports_lvds = false,
3470         .supports_hdmi = false,
3471         .supports_dp = true,
3472         .supports_audio = false,
3473         .supports_hdcp = false,
3474
3475         .regs = &tegra210_sor_regs,
3476         .has_nvdisplay = false,
3477
3478         .xbar_cfg = tegra210_sor_xbar_cfg,
3479         .lane_map = tegra210_sor_lane_map,
3480         .voltage_swing = tegra124_sor_voltage_swing,
3481         .pre_emphasis = tegra124_sor_pre_emphasis,
3482         .post_cursor = tegra124_sor_post_cursor,
3483         .tx_pu = tegra124_sor_tx_pu,
3484 };
3485
3486 static const struct tegra_sor_soc tegra210_sor1 = {
3487         .supports_lvds = false,
3488         .supports_hdmi = true,
3489         .supports_dp = true,
3490         .supports_audio = true,
3491         .supports_hdcp = true,
3492
3493         .regs = &tegra210_sor_regs,
3494         .has_nvdisplay = false,
3495
3496         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3497         .settings = tegra210_sor_hdmi_defaults,
3498         .xbar_cfg = tegra210_sor_xbar_cfg,
3499         .lane_map = tegra210_sor_lane_map,
3500         .voltage_swing = tegra124_sor_voltage_swing,
3501         .pre_emphasis = tegra124_sor_pre_emphasis,
3502         .post_cursor = tegra124_sor_post_cursor,
3503         .tx_pu = tegra124_sor_tx_pu,
3504 };
3505
3506 static const struct tegra_sor_regs tegra186_sor_regs = {
3507         .head_state0 = 0x151,
3508         .head_state1 = 0x154,
3509         .head_state2 = 0x157,
3510         .head_state3 = 0x15a,
3511         .head_state4 = 0x15d,
3512         .head_state5 = 0x160,
3513         .pll0 = 0x163,
3514         .pll1 = 0x164,
3515         .pll2 = 0x165,
3516         .pll3 = 0x166,
3517         .dp_padctl0 = 0x168,
3518         .dp_padctl2 = 0x16a,
3519 };
3520
3521 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3522         {
3523                 { 0x13, 0x19, 0x1e, 0x28 },
3524                 { 0x1e, 0x25, 0x2d, },
3525                 { 0x28, 0x32, },
3526                 { 0x39, },
3527         }, {
3528                 { 0x12, 0x16, 0x1b, 0x25 },
3529                 { 0x1c, 0x23, 0x2a, },
3530                 { 0x25, 0x2f, },
3531                 { 0x37, }
3532         }, {
3533                 { 0x12, 0x16, 0x1a, 0x22 },
3534                 { 0x1b, 0x20, 0x27, },
3535                 { 0x24, 0x2d, },
3536                 { 0x35, },
3537         }, {
3538                 { 0x11, 0x14, 0x17, 0x1f },
3539                 { 0x19, 0x1e, 0x24, },
3540                 { 0x22, 0x2a, },
3541                 { 0x32, },
3542         },
3543 };
3544
3545 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3546         {
3547                 { 0x00, 0x08, 0x12, 0x24 },
3548                 { 0x01, 0x0e, 0x1d, },
3549                 { 0x01, 0x13, },
3550                 { 0x00, },
3551         }, {
3552                 { 0x00, 0x08, 0x12, 0x24 },
3553                 { 0x00, 0x0e, 0x1d, },
3554                 { 0x00, 0x13, },
3555                 { 0x00 },
3556         }, {
3557                 { 0x00, 0x08, 0x14, 0x24 },
3558                 { 0x00, 0x0e, 0x1d, },
3559                 { 0x00, 0x13, },
3560                 { 0x00, },
3561         }, {
3562                 { 0x00, 0x08, 0x12, 0x24 },
3563                 { 0x00, 0x0e, 0x1d, },
3564                 { 0x00, 0x13, },
3565                 { 0x00, },
3566         },
3567 };
3568
3569 static const struct tegra_sor_soc tegra186_sor = {
3570         .supports_lvds = false,
3571         .supports_hdmi = true,
3572         .supports_dp = true,
3573         .supports_audio = true,
3574         .supports_hdcp = true,
3575
3576         .regs = &tegra186_sor_regs,
3577         .has_nvdisplay = true,
3578
3579         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3580         .settings = tegra186_sor_hdmi_defaults,
3581         .xbar_cfg = tegra124_sor_xbar_cfg,
3582         .lane_map = tegra124_sor_lane_map,
3583         .voltage_swing = tegra186_sor_voltage_swing,
3584         .pre_emphasis = tegra186_sor_pre_emphasis,
3585         .post_cursor = tegra124_sor_post_cursor,
3586         .tx_pu = tegra124_sor_tx_pu,
3587 };
3588
3589 static const struct tegra_sor_regs tegra194_sor_regs = {
3590         .head_state0 = 0x151,
3591         .head_state1 = 0x155,
3592         .head_state2 = 0x159,
3593         .head_state3 = 0x15d,
3594         .head_state4 = 0x161,
3595         .head_state5 = 0x165,
3596         .pll0 = 0x169,
3597         .pll1 = 0x16a,
3598         .pll2 = 0x16b,
3599         .pll3 = 0x16c,
3600         .dp_padctl0 = 0x16e,
3601         .dp_padctl2 = 0x16f,
3602 };
3603
3604 static const struct tegra_sor_soc tegra194_sor = {
3605         .supports_lvds = false,
3606         .supports_hdmi = true,
3607         .supports_dp = true,
3608         .supports_audio = true,
3609         .supports_hdcp = true,
3610
3611         .regs = &tegra194_sor_regs,
3612         .has_nvdisplay = true,
3613
3614         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3615         .settings = tegra194_sor_hdmi_defaults,
3616
3617         .xbar_cfg = tegra210_sor_xbar_cfg,
3618         .lane_map = tegra124_sor_lane_map,
3619         .voltage_swing = tegra186_sor_voltage_swing,
3620         .pre_emphasis = tegra186_sor_pre_emphasis,
3621         .post_cursor = tegra124_sor_post_cursor,
3622         .tx_pu = tegra124_sor_tx_pu,
3623 };
3624
3625 static const struct of_device_id tegra_sor_of_match[] = {
3626         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3627         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3628         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3629         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3630         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3631         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3632         { },
3633 };
3634 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3635
3636 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3637 {
3638         struct device_node *np = sor->dev->of_node;
3639         u32 xbar_cfg[5];
3640         unsigned int i;
3641         u32 value;
3642         int err;
3643
3644         if (sor->soc->has_nvdisplay) {
3645                 err = of_property_read_u32(np, "nvidia,interface", &value);
3646                 if (err < 0)
3647                         return err;
3648
3649                 sor->index = value;
3650
3651                 /*
3652                  * override the default that we already set for Tegra210 and
3653                  * earlier
3654                  */
3655                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3656         } else {
3657                 if (!sor->soc->supports_audio)
3658                         sor->index = 0;
3659                 else
3660                         sor->index = 1;
3661         }
3662
3663         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3664         if (err < 0) {
3665                 /* fall back to default per-SoC XBAR configuration */
3666                 for (i = 0; i < 5; i++)
3667                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3668         } else {
3669                 /* copy cells to SOR XBAR configuration */
3670                 for (i = 0; i < 5; i++)
3671                         sor->xbar_cfg[i] = xbar_cfg[i];
3672         }
3673
3674         return 0;
3675 }
3676
3677 static irqreturn_t tegra_sor_irq(int irq, void *data)
3678 {
3679         struct tegra_sor *sor = data;
3680         u32 value;
3681
3682         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3683         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3684
3685         if (value & SOR_INT_CODEC_SCRATCH0) {
3686                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3687
3688                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3689                         unsigned int format;
3690
3691                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3692
3693                         tegra_hda_parse_format(format, &sor->format);
3694
3695                         if (sor->ops->audio_enable)
3696                                 sor->ops->audio_enable(sor);
3697                 } else {
3698                         if (sor->ops->audio_disable)
3699                                 sor->ops->audio_disable(sor);
3700                 }
3701         }
3702
3703         return IRQ_HANDLED;
3704 }
3705
3706 static int tegra_sor_probe(struct platform_device *pdev)
3707 {
3708         struct device_node *np;
3709         struct tegra_sor *sor;
3710         struct resource *regs;
3711         int err;
3712
3713         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3714         if (!sor)
3715                 return -ENOMEM;
3716
3717         sor->soc = of_device_get_match_data(&pdev->dev);
3718         sor->output.dev = sor->dev = &pdev->dev;
3719
3720         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3721                                      sor->soc->num_settings *
3722                                         sizeof(*sor->settings),
3723                                      GFP_KERNEL);
3724         if (!sor->settings)
3725                 return -ENOMEM;
3726
3727         sor->num_settings = sor->soc->num_settings;
3728
3729         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3730         if (np) {
3731                 sor->aux = drm_dp_aux_find_by_of_node(np);
3732                 of_node_put(np);
3733
3734                 if (!sor->aux)
3735                         return -EPROBE_DEFER;
3736
3737                 if (get_device(sor->aux->dev))
3738                         sor->output.ddc = &sor->aux->ddc;
3739         }
3740
3741         if (!sor->aux) {
3742                 if (sor->soc->supports_hdmi) {
3743                         sor->ops = &tegra_sor_hdmi_ops;
3744                         sor->pad = TEGRA_IO_PAD_HDMI;
3745                 } else if (sor->soc->supports_lvds) {
3746                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3747                         return -ENODEV;
3748                 } else {
3749                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3750                         return -ENODEV;
3751                 }
3752         } else {
3753                 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3754                 /*
3755                  * No need to keep this around since we only use it as a check
3756                  * to see if a panel is connected (eDP) or not (DP).
3757                  */
3758                 of_node_put(np);
3759
3760                 sor->ops = &tegra_sor_dp_ops;
3761                 sor->pad = TEGRA_IO_PAD_LVDS;
3762         }
3763
3764         err = tegra_sor_parse_dt(sor);
3765         if (err < 0)
3766                 goto put_aux;
3767
3768         err = tegra_output_probe(&sor->output);
3769         if (err < 0) {
3770                 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3771                 goto put_aux;
3772         }
3773
3774         if (sor->ops && sor->ops->probe) {
3775                 err = sor->ops->probe(sor);
3776                 if (err < 0) {
3777                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3778                                 sor->ops->name, err);
3779                         goto remove;
3780                 }
3781         }
3782
3783         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3784         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3785         if (IS_ERR(sor->regs)) {
3786                 err = PTR_ERR(sor->regs);
3787                 goto remove;
3788         }
3789
3790         err = platform_get_irq(pdev, 0);
3791         if (err < 0)
3792                 goto remove;
3793
3794         sor->irq = err;
3795
3796         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3797                                dev_name(sor->dev), sor);
3798         if (err < 0) {
3799                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3800                 goto remove;
3801         }
3802
3803         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3804         if (IS_ERR(sor->rst)) {
3805                 err = PTR_ERR(sor->rst);
3806
3807                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3808                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3809                                 err);
3810                         goto remove;
3811                 }
3812
3813                 /*
3814                  * At this point, the reset control is most likely being used
3815                  * by the generic power domain implementation. With any luck
3816                  * the power domain will have taken care of resetting the SOR
3817                  * and we don't have to do anything.
3818                  */
3819                 sor->rst = NULL;
3820         }
3821
3822         sor->clk = devm_clk_get(&pdev->dev, NULL);
3823         if (IS_ERR(sor->clk)) {
3824                 err = PTR_ERR(sor->clk);
3825                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3826                 goto remove;
3827         }
3828
3829         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3830                 struct device_node *np = pdev->dev.of_node;
3831                 const char *name;
3832
3833                 /*
3834                  * For backwards compatibility with Tegra210 device trees,
3835                  * fall back to the old clock name "source" if the new "out"
3836                  * clock is not available.
3837                  */
3838                 if (of_property_match_string(np, "clock-names", "out") < 0)
3839                         name = "source";
3840                 else
3841                         name = "out";
3842
3843                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3844                 if (IS_ERR(sor->clk_out)) {
3845                         err = PTR_ERR(sor->clk_out);
3846                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3847                                 name, err);
3848                         goto remove;
3849                 }
3850         } else {
3851                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3852                 sor->clk_out = sor->clk;
3853         }
3854
3855         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3856         if (IS_ERR(sor->clk_parent)) {
3857                 err = PTR_ERR(sor->clk_parent);
3858                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3859                 goto remove;
3860         }
3861
3862         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3863         if (IS_ERR(sor->clk_safe)) {
3864                 err = PTR_ERR(sor->clk_safe);
3865                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3866                 goto remove;
3867         }
3868
3869         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3870         if (IS_ERR(sor->clk_dp)) {
3871                 err = PTR_ERR(sor->clk_dp);
3872                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3873                 goto remove;
3874         }
3875
3876         /*
3877          * Starting with Tegra186, the BPMP provides an implementation for
3878          * the pad output clock, so we have to look it up from device tree.
3879          */
3880         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3881         if (IS_ERR(sor->clk_pad)) {
3882                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3883                         err = PTR_ERR(sor->clk_pad);
3884                         goto remove;
3885                 }
3886
3887                 /*
3888                  * If the pad output clock is not available, then we assume
3889                  * we're on Tegra210 or earlier and have to provide our own
3890                  * implementation.
3891                  */
3892                 sor->clk_pad = NULL;
3893         }
3894
3895         /*
3896          * The bootloader may have set up the SOR such that it's module clock
3897          * is sourced by one of the display PLLs. However, that doesn't work
3898          * without properly having set up other bits of the SOR.
3899          */
3900         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3901         if (err < 0) {
3902                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3903                 goto remove;
3904         }
3905
3906         platform_set_drvdata(pdev, sor);
3907         pm_runtime_enable(&pdev->dev);
3908
3909         host1x_client_init(&sor->client);
3910         sor->client.ops = &sor_client_ops;
3911         sor->client.dev = &pdev->dev;
3912
3913         /*
3914          * On Tegra210 and earlier, provide our own implementation for the
3915          * pad output clock.
3916          */
3917         if (!sor->clk_pad) {
3918                 char *name;
3919
3920                 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3921                                       sor->index);
3922                 if (!name) {
3923                         err = -ENOMEM;
3924                         goto uninit;
3925                 }
3926
3927                 err = host1x_client_resume(&sor->client);
3928                 if (err < 0) {
3929                         dev_err(sor->dev, "failed to resume: %d\n", err);
3930                         goto uninit;
3931                 }
3932
3933                 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3934                 host1x_client_suspend(&sor->client);
3935         }
3936
3937         if (IS_ERR(sor->clk_pad)) {
3938                 err = PTR_ERR(sor->clk_pad);
3939                 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3940                         err);
3941                 goto uninit;
3942         }
3943
3944         err = __host1x_client_register(&sor->client);
3945         if (err < 0) {
3946                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3947                         err);
3948                 goto uninit;
3949         }
3950
3951         return 0;
3952
3953 uninit:
3954         host1x_client_exit(&sor->client);
3955         pm_runtime_disable(&pdev->dev);
3956 remove:
3957         if (sor->aux)
3958                 sor->output.ddc = NULL;
3959
3960         tegra_output_remove(&sor->output);
3961 put_aux:
3962         if (sor->aux)
3963                 put_device(sor->aux->dev);
3964
3965         return err;
3966 }
3967
3968 static void tegra_sor_remove(struct platform_device *pdev)
3969 {
3970         struct tegra_sor *sor = platform_get_drvdata(pdev);
3971
3972         host1x_client_unregister(&sor->client);
3973
3974         pm_runtime_disable(&pdev->dev);
3975
3976         if (sor->aux) {
3977                 put_device(sor->aux->dev);
3978                 sor->output.ddc = NULL;
3979         }
3980
3981         tegra_output_remove(&sor->output);
3982 }
3983
3984 static int __maybe_unused tegra_sor_suspend(struct device *dev)
3985 {
3986         struct tegra_sor *sor = dev_get_drvdata(dev);
3987         int err;
3988
3989         err = tegra_output_suspend(&sor->output);
3990         if (err < 0) {
3991                 dev_err(dev, "failed to suspend output: %d\n", err);
3992                 return err;
3993         }
3994
3995         if (sor->hdmi_supply) {
3996                 err = regulator_disable(sor->hdmi_supply);
3997                 if (err < 0) {
3998                         tegra_output_resume(&sor->output);
3999                         return err;
4000                 }
4001         }
4002
4003         return 0;
4004 }
4005
4006 static int __maybe_unused tegra_sor_resume(struct device *dev)
4007 {
4008         struct tegra_sor *sor = dev_get_drvdata(dev);
4009         int err;
4010
4011         if (sor->hdmi_supply) {
4012                 err = regulator_enable(sor->hdmi_supply);
4013                 if (err < 0)
4014                         return err;
4015         }
4016
4017         err = tegra_output_resume(&sor->output);
4018         if (err < 0) {
4019                 dev_err(dev, "failed to resume output: %d\n", err);
4020
4021                 if (sor->hdmi_supply)
4022                         regulator_disable(sor->hdmi_supply);
4023
4024                 return err;
4025         }
4026
4027         return 0;
4028 }
4029
4030 static const struct dev_pm_ops tegra_sor_pm_ops = {
4031         SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4032 };
4033
4034 struct platform_driver tegra_sor_driver = {
4035         .driver = {
4036                 .name = "tegra-sor",
4037                 .of_match_table = tegra_sor_of_match,
4038                 .pm = &tegra_sor_pm_ops,
4039         },
4040         .probe = tegra_sor_probe,
4041         .remove_new = tegra_sor_remove,
4042 };