drivers/gpu/drm/amd/display/modules/power/power_helpers.c

   1 /* Copyright 2018 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24
  25 #include "power_helpers.h"
  26 #include "dc/inc/hw/dmcu.h"
  27 #include "dc/inc/hw/abm.h"
  28 #include "dc.h"
  29 #include "core_types.h"
  30 #include "dmub_cmd.h"
  31
  32 #define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
  33 #define bswap16_based_on_endian(big_endian, value) \
  34         (big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)
  35
  36 /* Possible Min Reduction config from least aggressive to most aggressive
  37  *  0    1     2     3     4     5     6     7     8     9     10    11   12
  38  * 100  98.0 94.1  94.1  85.1  80.3  75.3  69.4  60.0  57.6  50.2  49.8  40.0 %
  39  */
  40 static const unsigned char min_reduction_table[13] = {
  41 0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66};
  42
  43 /* Possible Max Reduction configs from least aggressive to most aggressive
  44  *  0    1     2     3     4     5     6     7     8     9     10    11   12
  45  * 96.1 89.8 85.1  80.3  69.4  64.7  64.7  50.2  39.6  30.2  30.2  30.2  19.6 %
  46  */
  47 static const unsigned char max_reduction_table[13] = {
  48 0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
  49
  50 /* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive
  51  *  0    1     2     3     4     5     6     7     8     9     10    11   12
  52  * 100  100   100   100   100   100   100   100  100  92.2  83.1  75.3  75.3 %
  53  */
  54 static const unsigned char min_reduction_table_v_2_2[13] = {
  55 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0};
  56
  57 /* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
  58  *  0    1     2     3     4     5     6     7     8     9     10    11   12
  59  * 96.1 89.8 74.9  69.4  64.7  52.2  48.6  39.6  30.2  25.1  19.6  12.5  12.5 %
  60  */
  61 static const unsigned char max_reduction_table_v_2_2[13] = {
  62 0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20};
  63
  64 /* Predefined ABM configuration sets. We may have different configuration sets
  65  * in order to satisfy different power/quality requirements.
  66  */
  67 static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = {
  68 /*  ABM Level 1,    ABM Level 2,    ABM Level 3,    ABM Level 4 */
  69 {       2,              5,              7,              8       },      /* Default - Medium aggressiveness */
  70 {       2,              5,              8,              11      },      /* Alt #1  - Increased aggressiveness */
  71 {       0,              2,              4,              8       },      /* Alt #2  - Minimal aggressiveness */
  72 {       3,              6,              10,             12      },      /* Alt #3  - Super aggressiveness */
  73 };
  74
  75 struct abm_parameters {
  76         unsigned char min_reduction;
  77         unsigned char max_reduction;
  78         unsigned char bright_pos_gain;
  79         unsigned char dark_pos_gain;
  80         unsigned char brightness_gain;
  81         unsigned char contrast_factor;
  82         unsigned char deviation_gain;
  83         unsigned char min_knee;
  84         unsigned char max_knee;
  85         unsigned short blRampReduction;
  86         unsigned short blRampStart;
  87 };
  88
  89 static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
  90 //  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blRed    blStart
  91         {0xff,   0xbf,    0x20,       0x00,     0xff,        0x99,     0xb3, 0x40,     0xe0,     0xf777,  0xcccc},
  92         {0xde,   0x85,    0x20,       0x00,     0xe0,        0x90,     0xa8, 0x40,     0xc8,     0xf777,  0xcccc},
  93         {0xb0,   0x50,    0x20,       0x00,     0xc0,        0x88,     0x78, 0x70,     0xa0,     0xeeee,  0x9999},
  94         {0x82,   0x40,    0x20,       0x00,     0x00,        0xb8,     0xb3, 0x70,     0x70,     0xe333,  0xb333},
  95 };
  96
  97 static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
  98 //  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blRed  blStart
  99         {0xf0,   0xd9,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
 100         {0xcd,   0xa5,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
 101         {0x99,   0x65,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
 102         {0x82,   0x4d,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
 103 };
 104
 105 static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = {
 106 //  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blRed    blStart
 107         {0xf0,   0xbf,    0x20,       0x00,     0x88,        0x99,     0xb3, 0x40,     0xe0,    0x0000,  0xcccc},
 108         {0xd8,   0x85,    0x20,       0x00,     0x70,        0x90,     0xa8, 0x40,     0xc8,    0x0700,  0xb333},
 109         {0xb8,   0x58,    0x20,       0x00,     0x64,        0x88,     0x78, 0x70,     0xa0,    0x7000,  0x9999},
 110         {0x82,   0x40,    0x20,       0x00,     0x00,        0xb8,     0xb3, 0x70,     0x70,    0xc333,  0xb333},
 111 };
 112
 113 static const struct abm_parameters * const abm_settings[] = {
 114         abm_settings_config0,
 115         abm_settings_config1,
 116         abm_settings_config2,
 117 };
 118
 119 #define NUM_AMBI_LEVEL    5
 120 #define NUM_AGGR_LEVEL    4
 121 #define NUM_POWER_FN_SEGS 8
 122 #define NUM_BL_CURVE_SEGS 16
 123 #define IRAM_SIZE 256
 124
 125 #define IRAM_RESERVE_AREA_START_V2 0xF0  // reserve 0xF0~0xF6 are write by DMCU only
 126 #define IRAM_RESERVE_AREA_END_V2 0xF6  // reserve 0xF0~0xF6 are write by DMCU only
 127
 128 #define IRAM_RESERVE_AREA_START_V2_2 0xF0  // reserve 0xF0~0xFF are write by DMCU only
 129 #define IRAM_RESERVE_AREA_END_V2_2 0xFF  // reserve 0xF0~0xFF are write by DMCU only
 130
 131 #pragma pack(push, 1)
 132 /* NOTE: iRAM is 256B in size */
 133 struct iram_table_v_2 {
 134         /* flags                      */
 135         uint16_t min_abm_backlight;                                     /* 0x00 U16  */
 136
 137         /* parameters for ABM2.0 algorithm */
 138         uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x02 U0.8 */
 139         uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x16 U0.8 */
 140         uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x2a U2.6 */
 141         uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x3e U2.6 */
 142         uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x52 U2.6 */
 143         uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x66 U2.6 */
 144         uint8_t iir_curve[NUM_AMBI_LEVEL];                              /* 0x7a U0.8 */
 145         uint8_t deviation_gain;                                         /* 0x7f U0.8 */
 146
 147         /* parameters for crgb conversion */
 148         uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                        /* 0x80 U3.13 */
 149         uint16_t crgb_offset[NUM_POWER_FN_SEGS];                        /* 0x90 U1.15 */
 150         uint16_t crgb_slope[NUM_POWER_FN_SEGS];                         /* 0xa0 U4.12 */
 151
 152         /* parameters for custom curve */
 153         /* thresholds for brightness --> backlight */
 154         uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];               /* 0xb0 U16.0 */
 155         /* offsets for brightness --> backlight */
 156         uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];                  /* 0xd0 U16.0 */
 157
 158         /* For reading PSR State directly from IRAM */
 159         uint8_t psr_state;                                              /* 0xf0       */
 160         uint8_t dmcu_mcp_interface_version;                             /* 0xf1       */
 161         uint8_t dmcu_abm_feature_version;                               /* 0xf2       */
 162         uint8_t dmcu_psr_feature_version;                               /* 0xf3       */
 163         uint16_t dmcu_version;                                          /* 0xf4       */
 164         uint8_t dmcu_state;                                             /* 0xf6       */
 165
 166         uint16_t blRampReduction;                                       /* 0xf7       */
 167         uint16_t blRampStart;                                           /* 0xf9       */
 168         uint8_t dummy5;                                                 /* 0xfb       */
 169         uint8_t dummy6;                                                 /* 0xfc       */
 170         uint8_t dummy7;                                                 /* 0xfd       */
 171         uint8_t dummy8;                                                 /* 0xfe       */
 172         uint8_t dummy9;                                                 /* 0xff       */
 173 };
 174
 175 struct iram_table_v_2_2 {
 176         /* flags                      */
 177         uint16_t flags;                                                 /* 0x00 U16  */
 178
 179         /* parameters for ABM2.2 algorithm */
 180         uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x02 U0.8 */
 181         uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x16 U0.8 */
 182         uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x2a U2.6 */
 183         uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x3e U2.6 */
 184         uint8_t hybrid_factor[NUM_AGGR_LEVEL];                          /* 0x52 U0.8 */
 185         uint8_t contrast_factor[NUM_AGGR_LEVEL];                        /* 0x56 U0.8 */
 186         uint8_t deviation_gain[NUM_AGGR_LEVEL];                         /* 0x5a U0.8 */
 187         uint8_t iir_curve[NUM_AMBI_LEVEL];                              /* 0x5e U0.8 */
 188         uint8_t min_knee[NUM_AGGR_LEVEL];                               /* 0x63 U0.8 */
 189         uint8_t max_knee[NUM_AGGR_LEVEL];                               /* 0x67 U0.8 */
 190         uint16_t min_abm_backlight;                                     /* 0x6b U16  */
 191         uint8_t pad[19];                                                /* 0x6d U0.8 */
 192
 193         /* parameters for crgb conversion */
 194         uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                        /* 0x80 U3.13 */
 195         uint16_t crgb_offset[NUM_POWER_FN_SEGS];                        /* 0x90 U1.15 */
 196         uint16_t crgb_slope[NUM_POWER_FN_SEGS];                         /* 0xa0 U4.12 */
 197
 198         /* parameters for custom curve */
 199         /* thresholds for brightness --> backlight */
 200         uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];               /* 0xb0 U16.0 */
 201         /* offsets for brightness --> backlight */
 202         uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];                  /* 0xd0 U16.0 */
 203
 204         /* For reading PSR State directly from IRAM */
 205         uint8_t psr_state;                                              /* 0xf0       */
 206         uint8_t dmcu_mcp_interface_version;                             /* 0xf1       */
 207         uint8_t dmcu_abm_feature_version;                               /* 0xf2       */
 208         uint8_t dmcu_psr_feature_version;                               /* 0xf3       */
 209         uint16_t dmcu_version;                                          /* 0xf4       */
 210         uint8_t dmcu_state;                                             /* 0xf6       */
 211
 212         uint8_t dummy1;                                                 /* 0xf7       */
 213         uint8_t dummy2;                                                 /* 0xf8       */
 214         uint8_t dummy3;                                                 /* 0xf9       */
 215         uint8_t dummy4;                                                 /* 0xfa       */
 216         uint8_t dummy5;                                                 /* 0xfb       */
 217         uint8_t dummy6;                                                 /* 0xfc       */
 218         uint8_t dummy7;                                                 /* 0xfd       */
 219         uint8_t dummy8;                                                 /* 0xfe       */
 220         uint8_t dummy9;                                                 /* 0xff       */
 221 };
 222 #pragma pack(pop)
 223
 224 static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
 225                 struct iram_table_v_2 *table)
 226 {
 227         unsigned int i;
 228         unsigned int num_entries = NUM_BL_CURVE_SEGS;
 229         unsigned int lut_index;
 230
 231         table->backlight_thresholds[0] = 0;
 232         table->backlight_offsets[0] = params.backlight_lut_array[0];
 233         table->backlight_thresholds[num_entries-1] = 0xFFFF;
 234         table->backlight_offsets[num_entries-1] =
 235                 params.backlight_lut_array[params.backlight_lut_array_size - 1];
 236
 237         /* Setup all brightness levels between 0% and 100% exclusive
 238          * Fills brightness-to-backlight transform table. Backlight custom curve
 239          * describes transform from brightness to backlight. It will be defined
 240          * as set of thresholds and set of offsets, together, implying
 241          * extrapolation of custom curve into 16 uniformly spanned linear
 242          * segments.  Each threshold/offset represented by 16 bit entry in
 243          * format U4.10.
 244          */
 245         for (i = 1; i+1 < num_entries; i++) {
 246                 lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
 247                 ASSERT(lut_index < params.backlight_lut_array_size);
 248
 249                 table->backlight_thresholds[i] =
 250                         cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries));
 251                 table->backlight_offsets[i] =
 252                         cpu_to_be16(params.backlight_lut_array[lut_index]);
 253         }
 254 }
 255
 256 static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,
 257                 struct iram_table_v_2_2 *table, bool big_endian)
 258 {
 259         unsigned int i;
 260         unsigned int num_entries = NUM_BL_CURVE_SEGS;
 261         unsigned int lut_index;
 262
 263         table->backlight_thresholds[0] = 0;
 264         table->backlight_offsets[0] = params.backlight_lut_array[0];
 265         table->backlight_thresholds[num_entries-1] = 0xFFFF;
 266         table->backlight_offsets[num_entries-1] =
 267                 params.backlight_lut_array[params.backlight_lut_array_size - 1];
 268
 269         /* Setup all brightness levels between 0% and 100% exclusive
 270          * Fills brightness-to-backlight transform table. Backlight custom curve
 271          * describes transform from brightness to backlight. It will be defined
 272          * as set of thresholds and set of offsets, together, implying
 273          * extrapolation of custom curve into 16 uniformly spanned linear
 274          * segments.  Each threshold/offset represented by 16 bit entry in
 275          * format U4.10.
 276          */
 277         for (i = 1; i+1 < num_entries; i++) {
 278                 lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries);
 279                 ASSERT(lut_index < params.backlight_lut_array_size);
 280
 281                 table->backlight_thresholds[i] = (big_endian) ?
 282                         cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries)) :
 283                         cpu_to_le16(DIV_ROUNDUP((i * 65536), num_entries));
 284                 table->backlight_offsets[i] = (big_endian) ?
 285                         cpu_to_be16(params.backlight_lut_array[lut_index]) :
 286                         cpu_to_le16(params.backlight_lut_array[lut_index]);
 287         }
 288 }
 289
 290 static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params)
 291 {
 292         unsigned int set = params.set;
 293
 294         ram_table->min_abm_backlight =
 295                         cpu_to_be16(params.min_abm_backlight);
 296         ram_table->deviation_gain = 0xb3;
 297
 298         ram_table->blRampReduction =
 299                 cpu_to_be16(params.backlight_ramping_reduction);
 300         ram_table->blRampStart =
 301                 cpu_to_be16(params.backlight_ramping_start);
 302
 303         ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
 304         ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
 305         ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
 306         ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
 307         ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
 308         ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
 309         ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
 310         ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
 311         ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
 312         ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
 313
 314         ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
 315         ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
 316         ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
 317         ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
 318         ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
 319         ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
 320         ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
 321         ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
 322         ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
 323         ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
 324
 325         ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
 326         ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
 327         ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
 328         ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
 329         ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
 330         ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
 331         ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
 332         ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
 333         ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
 334         ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
 335
 336         ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
 337         ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
 338         ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
 339         ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
 340         ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
 341         ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
 342         ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
 343         ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
 344         ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
 345         ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
 346
 347         ram_table->bright_pos_gain[0][0] = 0x20;
 348         ram_table->bright_pos_gain[0][1] = 0x20;
 349         ram_table->bright_pos_gain[0][2] = 0x20;
 350         ram_table->bright_pos_gain[0][3] = 0x20;
 351         ram_table->bright_pos_gain[1][0] = 0x20;
 352         ram_table->bright_pos_gain[1][1] = 0x20;
 353         ram_table->bright_pos_gain[1][2] = 0x20;
 354         ram_table->bright_pos_gain[1][3] = 0x20;
 355         ram_table->bright_pos_gain[2][0] = 0x20;
 356         ram_table->bright_pos_gain[2][1] = 0x20;
 357         ram_table->bright_pos_gain[2][2] = 0x20;
 358         ram_table->bright_pos_gain[2][3] = 0x20;
 359         ram_table->bright_pos_gain[3][0] = 0x20;
 360         ram_table->bright_pos_gain[3][1] = 0x20;
 361         ram_table->bright_pos_gain[3][2] = 0x20;
 362         ram_table->bright_pos_gain[3][3] = 0x20;
 363         ram_table->bright_pos_gain[4][0] = 0x20;
 364         ram_table->bright_pos_gain[4][1] = 0x20;
 365         ram_table->bright_pos_gain[4][2] = 0x20;
 366         ram_table->bright_pos_gain[4][3] = 0x20;
 367         ram_table->bright_neg_gain[0][0] = 0x00;
 368         ram_table->bright_neg_gain[0][1] = 0x00;
 369         ram_table->bright_neg_gain[0][2] = 0x00;
 370         ram_table->bright_neg_gain[0][3] = 0x00;
 371         ram_table->bright_neg_gain[1][0] = 0x00;
 372         ram_table->bright_neg_gain[1][1] = 0x00;
 373         ram_table->bright_neg_gain[1][2] = 0x00;
 374         ram_table->bright_neg_gain[1][3] = 0x00;
 375         ram_table->bright_neg_gain[2][0] = 0x00;
 376         ram_table->bright_neg_gain[2][1] = 0x00;
 377         ram_table->bright_neg_gain[2][2] = 0x00;
 378         ram_table->bright_neg_gain[2][3] = 0x00;
 379         ram_table->bright_neg_gain[3][0] = 0x00;
 380         ram_table->bright_neg_gain[3][1] = 0x00;
 381         ram_table->bright_neg_gain[3][2] = 0x00;
 382         ram_table->bright_neg_gain[3][3] = 0x00;
 383         ram_table->bright_neg_gain[4][0] = 0x00;
 384         ram_table->bright_neg_gain[4][1] = 0x00;
 385         ram_table->bright_neg_gain[4][2] = 0x00;
 386         ram_table->bright_neg_gain[4][3] = 0x00;
 387         ram_table->dark_pos_gain[0][0] = 0x00;
 388         ram_table->dark_pos_gain[0][1] = 0x00;
 389         ram_table->dark_pos_gain[0][2] = 0x00;
 390         ram_table->dark_pos_gain[0][3] = 0x00;
 391         ram_table->dark_pos_gain[1][0] = 0x00;
 392         ram_table->dark_pos_gain[1][1] = 0x00;
 393         ram_table->dark_pos_gain[1][2] = 0x00;
 394         ram_table->dark_pos_gain[1][3] = 0x00;
 395         ram_table->dark_pos_gain[2][0] = 0x00;
 396         ram_table->dark_pos_gain[2][1] = 0x00;
 397         ram_table->dark_pos_gain[2][2] = 0x00;
 398         ram_table->dark_pos_gain[2][3] = 0x00;
 399         ram_table->dark_pos_gain[3][0] = 0x00;
 400         ram_table->dark_pos_gain[3][1] = 0x00;
 401         ram_table->dark_pos_gain[3][2] = 0x00;
 402         ram_table->dark_pos_gain[3][3] = 0x00;
 403         ram_table->dark_pos_gain[4][0] = 0x00;
 404         ram_table->dark_pos_gain[4][1] = 0x00;
 405         ram_table->dark_pos_gain[4][2] = 0x00;
 406         ram_table->dark_pos_gain[4][3] = 0x00;
 407         ram_table->dark_neg_gain[0][0] = 0x00;
 408         ram_table->dark_neg_gain[0][1] = 0x00;
 409         ram_table->dark_neg_gain[0][2] = 0x00;
 410         ram_table->dark_neg_gain[0][3] = 0x00;
 411         ram_table->dark_neg_gain[1][0] = 0x00;
 412         ram_table->dark_neg_gain[1][1] = 0x00;
 413         ram_table->dark_neg_gain[1][2] = 0x00;
 414         ram_table->dark_neg_gain[1][3] = 0x00;
 415         ram_table->dark_neg_gain[2][0] = 0x00;
 416         ram_table->dark_neg_gain[2][1] = 0x00;
 417         ram_table->dark_neg_gain[2][2] = 0x00;
 418         ram_table->dark_neg_gain[2][3] = 0x00;
 419         ram_table->dark_neg_gain[3][0] = 0x00;
 420         ram_table->dark_neg_gain[3][1] = 0x00;
 421         ram_table->dark_neg_gain[3][2] = 0x00;
 422         ram_table->dark_neg_gain[3][3] = 0x00;
 423         ram_table->dark_neg_gain[4][0] = 0x00;
 424         ram_table->dark_neg_gain[4][1] = 0x00;
 425         ram_table->dark_neg_gain[4][2] = 0x00;
 426         ram_table->dark_neg_gain[4][3] = 0x00;
 427
 428         ram_table->iir_curve[0] = 0x65;
 429         ram_table->iir_curve[1] = 0x65;
 430         ram_table->iir_curve[2] = 0x65;
 431         ram_table->iir_curve[3] = 0x65;
 432         ram_table->iir_curve[4] = 0x65;
 433
 434         //Gamma 2.4
 435         ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6);
 436         ram_table->crgb_thresh[1] = cpu_to_be16(0x1648);
 437         ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3);
 438         ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41);
 439         ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46);
 440         ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21);
 441         ram_table->crgb_thresh[6] = cpu_to_be16(0x2167);
 442         ram_table->crgb_thresh[7] = cpu_to_be16(0x2384);
 443         ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
 444         ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
 445         ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
 446         ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
 447         ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
 448         ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
 449         ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
 450         ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
 451         ram_table->crgb_slope[0]  = cpu_to_be16(0x3147);
 452         ram_table->crgb_slope[1]  = cpu_to_be16(0x2978);
 453         ram_table->crgb_slope[2]  = cpu_to_be16(0x23a2);
 454         ram_table->crgb_slope[3]  = cpu_to_be16(0x1f55);
 455         ram_table->crgb_slope[4]  = cpu_to_be16(0x1c63);
 456         ram_table->crgb_slope[5]  = cpu_to_be16(0x1a0f);
 457         ram_table->crgb_slope[6]  = cpu_to_be16(0x178d);
 458         ram_table->crgb_slope[7]  = cpu_to_be16(0x15ab);
 459
 460         fill_backlight_transform_table(
 461                         params, ram_table);
 462 }
 463
 464 static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
 465 {
 466         unsigned int set = params.set;
 467
 468         ram_table->flags = 0x0;
 469
 470         ram_table->min_abm_backlight =
 471                         cpu_to_be16(params.min_abm_backlight);
 472
 473         ram_table->deviation_gain[0] = 0xb3;
 474         ram_table->deviation_gain[1] = 0xa8;
 475         ram_table->deviation_gain[2] = 0x98;
 476         ram_table->deviation_gain[3] = 0x68;
 477
 478         ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
 479         ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
 480         ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
 481         ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]];
 482         ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]];
 483         ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]];
 484         ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]];
 485         ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]];
 486         ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]];
 487         ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]];
 488
 489         ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]];
 490         ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]];
 491         ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]];
 492         ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]];
 493         ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]];
 494         ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]];
 495         ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]];
 496         ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]];
 497         ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]];
 498         ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]];
 499
 500         ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]];
 501         ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]];
 502         ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]];
 503         ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]];
 504         ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]];
 505         ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]];
 506         ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]];
 507         ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]];
 508         ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]];
 509         ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]];
 510
 511         ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]];
 512         ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]];
 513         ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]];
 514         ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]];
 515         ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]];
 516         ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]];
 517         ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]];
 518         ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]];
 519         ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]];
 520         ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]];
 521
 522         ram_table->bright_pos_gain[0][0] = 0x20;
 523         ram_table->bright_pos_gain[0][1] = 0x20;
 524         ram_table->bright_pos_gain[0][2] = 0x20;
 525         ram_table->bright_pos_gain[0][3] = 0x20;
 526         ram_table->bright_pos_gain[1][0] = 0x20;
 527         ram_table->bright_pos_gain[1][1] = 0x20;
 528         ram_table->bright_pos_gain[1][2] = 0x20;
 529         ram_table->bright_pos_gain[1][3] = 0x20;
 530         ram_table->bright_pos_gain[2][0] = 0x20;
 531         ram_table->bright_pos_gain[2][1] = 0x20;
 532         ram_table->bright_pos_gain[2][2] = 0x20;
 533         ram_table->bright_pos_gain[2][3] = 0x20;
 534         ram_table->bright_pos_gain[3][0] = 0x20;
 535         ram_table->bright_pos_gain[3][1] = 0x20;
 536         ram_table->bright_pos_gain[3][2] = 0x20;
 537         ram_table->bright_pos_gain[3][3] = 0x20;
 538         ram_table->bright_pos_gain[4][0] = 0x20;
 539         ram_table->bright_pos_gain[4][1] = 0x20;
 540         ram_table->bright_pos_gain[4][2] = 0x20;
 541         ram_table->bright_pos_gain[4][3] = 0x20;
 542
 543         ram_table->dark_pos_gain[0][0] = 0x00;
 544         ram_table->dark_pos_gain[0][1] = 0x00;
 545         ram_table->dark_pos_gain[0][2] = 0x00;
 546         ram_table->dark_pos_gain[0][3] = 0x00;
 547         ram_table->dark_pos_gain[1][0] = 0x00;
 548         ram_table->dark_pos_gain[1][1] = 0x00;
 549         ram_table->dark_pos_gain[1][2] = 0x00;
 550         ram_table->dark_pos_gain[1][3] = 0x00;
 551         ram_table->dark_pos_gain[2][0] = 0x00;
 552         ram_table->dark_pos_gain[2][1] = 0x00;
 553         ram_table->dark_pos_gain[2][2] = 0x00;
 554         ram_table->dark_pos_gain[2][3] = 0x00;
 555         ram_table->dark_pos_gain[3][0] = 0x00;
 556         ram_table->dark_pos_gain[3][1] = 0x00;
 557         ram_table->dark_pos_gain[3][2] = 0x00;
 558         ram_table->dark_pos_gain[3][3] = 0x00;
 559         ram_table->dark_pos_gain[4][0] = 0x00;
 560         ram_table->dark_pos_gain[4][1] = 0x00;
 561         ram_table->dark_pos_gain[4][2] = 0x00;
 562         ram_table->dark_pos_gain[4][3] = 0x00;
 563
 564         ram_table->hybrid_factor[0] = 0xff;
 565         ram_table->hybrid_factor[1] = 0xff;
 566         ram_table->hybrid_factor[2] = 0xff;
 567         ram_table->hybrid_factor[3] = 0xc0;
 568
 569         ram_table->contrast_factor[0] = 0x99;
 570         ram_table->contrast_factor[1] = 0x99;
 571         ram_table->contrast_factor[2] = 0x90;
 572         ram_table->contrast_factor[3] = 0x80;
 573
 574         ram_table->iir_curve[0] = 0x65;
 575         ram_table->iir_curve[1] = 0x65;
 576         ram_table->iir_curve[2] = 0x65;
 577         ram_table->iir_curve[3] = 0x65;
 578         ram_table->iir_curve[4] = 0x65;
 579
 580         //Gamma 2.2
 581         ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
 582         ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
 583         ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
 584         ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
 585         ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
 586         ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
 587         ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
 588         ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
 589         ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
 590         ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
 591         ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
 592         ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
 593         ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
 594         ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
 595         ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
 596         ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
 597         ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
 598         ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
 599         ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
 600         ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
 601         ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
 602         ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
 603         ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
 604         ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
 605
 606         fill_backlight_transform_table_v_2_2(
 607                         params, ram_table, true);
 608 }
 609
 610 static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian)
 611 {
 612         unsigned int i, j;
 613         unsigned int set = params.set;
 614
 615         ram_table->flags = 0x0;
 616         ram_table->min_abm_backlight = (big_endian) ?
 617                 cpu_to_be16(params.min_abm_backlight) :
 618                 cpu_to_le16(params.min_abm_backlight);
 619
 620         for (i = 0; i < NUM_AGGR_LEVEL; i++) {
 621                 ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
 622                 ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
 623                 ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
 624                 ram_table->min_knee[i] = abm_settings[set][i].min_knee;
 625                 ram_table->max_knee[i] = abm_settings[set][i].max_knee;
 626
 627                 for (j = 0; j < NUM_AMBI_LEVEL; j++) {
 628                         ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
 629                         ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
 630                         ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
 631                         ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
 632                 }
 633         }
 634
 635         ram_table->iir_curve[0] = 0x65;
 636         ram_table->iir_curve[1] = 0x65;
 637         ram_table->iir_curve[2] = 0x65;
 638         ram_table->iir_curve[3] = 0x65;
 639         ram_table->iir_curve[4] = 0x65;
 640
 641         //Gamma 2.2
 642         ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c);
 643         ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b);
 644         ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5);
 645         ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56);
 646         ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83);
 647         ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72);
 648         ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0);
 649         ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b);
 650         ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999);
 651         ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999);
 652         ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666);
 653         ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999);
 654         ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333);
 655         ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800);
 656         ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00);
 657         ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000);
 658         ram_table->crgb_slope[0]  = bswap16_based_on_endian(big_endian, 0x3609);
 659         ram_table->crgb_slope[1]  = bswap16_based_on_endian(big_endian, 0x2dfa);
 660         ram_table->crgb_slope[2]  = bswap16_based_on_endian(big_endian, 0x27ea);
 661         ram_table->crgb_slope[3]  = bswap16_based_on_endian(big_endian, 0x235d);
 662         ram_table->crgb_slope[4]  = bswap16_based_on_endian(big_endian, 0x2042);
 663         ram_table->crgb_slope[5]  = bswap16_based_on_endian(big_endian, 0x1dc3);
 664         ram_table->crgb_slope[6]  = bswap16_based_on_endian(big_endian, 0x1b1a);
 665         ram_table->crgb_slope[7]  = bswap16_based_on_endian(big_endian, 0x1910);
 666
 667         fill_backlight_transform_table_v_2_2(
 668                         params, ram_table, big_endian);
 669 }
 670
 671 bool dmub_init_abm_config(struct resource_pool *res_pool,
 672         struct dmcu_iram_parameters params,
 673         unsigned int inst)
 674 {
 675         struct iram_table_v_2_2 ram_table;
 676         struct abm_config_table config;
 677         unsigned int set = params.set;
 678         bool result = false;
 679         uint32_t i, j = 0;
 680
 681         if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
 682                 return false;
 683
 684         memset(&ram_table, 0, sizeof(ram_table));
 685         memset(&config, 0, sizeof(config));
 686
 687         fill_iram_v_2_3(&ram_table, params, false);
 688
 689         // We must copy to structure that is aligned to 32-bit
 690         for (i = 0; i < NUM_POWER_FN_SEGS; i++) {
 691                 config.crgb_thresh[i] = ram_table.crgb_thresh[i];
 692                 config.crgb_offset[i] = ram_table.crgb_offset[i];
 693                 config.crgb_slope[i] = ram_table.crgb_slope[i];
 694         }
 695
 696         for (i = 0; i < NUM_BL_CURVE_SEGS; i++) {
 697                 config.backlight_thresholds[i] = ram_table.backlight_thresholds[i];
 698                 config.backlight_offsets[i] = ram_table.backlight_offsets[i];
 699         }
 700
 701         for (i = 0; i < NUM_AMBI_LEVEL; i++)
 702                 config.iir_curve[i] = ram_table.iir_curve[i];
 703
 704         for (i = 0; i < NUM_AMBI_LEVEL; i++) {
 705                 for (j = 0; j < NUM_AGGR_LEVEL; j++) {
 706                         config.min_reduction[i][j] = ram_table.min_reduction[i][j];
 707                         config.max_reduction[i][j] = ram_table.max_reduction[i][j];
 708                         config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j];
 709                         config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j];
 710                 }
 711         }
 712
 713         for (i = 0; i < NUM_AGGR_LEVEL; i++) {
 714                 config.hybrid_factor[i] = ram_table.hybrid_factor[i];
 715                 config.contrast_factor[i] = ram_table.contrast_factor[i];
 716                 config.deviation_gain[i] = ram_table.deviation_gain[i];
 717                 config.min_knee[i] = ram_table.min_knee[i];
 718                 config.max_knee[i] = ram_table.max_knee[i];
 719         }
 720
 721         if (params.backlight_ramping_override) {
 722                 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
 723                         config.blRampReduction[i] = params.backlight_ramping_reduction;
 724                         config.blRampStart[i] = params.backlight_ramping_start;
 725                         }
 726                 } else {
 727                         for (i = 0; i < NUM_AGGR_LEVEL; i++) {
 728                                 config.blRampReduction[i] = abm_settings[set][i].blRampReduction;
 729                                 config.blRampStart[i] = abm_settings[set][i].blRampStart;
 730                                 }
 731                         }
 732
 733         config.min_abm_backlight = ram_table.min_abm_backlight;
 734
 735         if (res_pool->multiple_abms[inst]) {
 736                 result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
 737                         res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
 738         } else
 739                 result = res_pool->abm->funcs->init_abm_config(
 740                         res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
 741
 742         return result;
 743 }
 744
 745 bool dmcu_load_iram(struct dmcu *dmcu,
 746         struct dmcu_iram_parameters params)
 747 {
 748         unsigned char ram_table[IRAM_SIZE];
 749         bool result = false;
 750
 751         if (dmcu == NULL)
 752                 return false;
 753
 754         if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
 755                 return true;
 756
 757         memset(&ram_table, 0, sizeof(ram_table));
 758
 759         if (dmcu->dmcu_version.abm_version == 0x24) {
 760                 fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
 761                 result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
 762                                                 IRAM_RESERVE_AREA_START_V2_2);
 763         } else if (dmcu->dmcu_version.abm_version == 0x23) {
 764                 fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
 765
 766                 result = dmcu->funcs->load_iram(
 767                                 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
 768         } else if (dmcu->dmcu_version.abm_version == 0x22) {
 769                 fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
 770
 771                 result = dmcu->funcs->load_iram(
 772                                 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
 773         } else {
 774                 fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
 775
 776                 result = dmcu->funcs->load_iram(
 777                                 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
 778
 779                 if (result)
 780                         result = dmcu->funcs->load_iram(
 781                                         dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
 782                                         (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
 783                                         sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
 784         }
 785
 786         return result;
 787 }
 788
 789 /*
 790  * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU
 791  * supported eDP device.
 792  *
 793  * @link: dc link pointer
 794  *
 795  * Return: true if AMDGPU vendor specific PSR-SU eDP panel
 796  */
 797 bool is_psr_su_specific_panel(struct dc_link *link)
 798 {
 799         bool isPSRSUSupported = false;
 800         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 801
 802         if (dpcd_caps->edp_rev >= DP_EDP_14) {
 803                 if (dpcd_caps->psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
 804                         isPSRSUSupported = true;
 805                 /*
 806                  * Some panels will report PSR capabilities over additional DPCD bits.
 807                  * Such panels are approved despite reporting only PSR v3, as long as
 808                  * the additional bits are reported.
 809                  */
 810                 if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
 811                         /*
 812                          * This is the temporary workaround to disable PSRSU when system turned on
 813                          * DSC function on the sepcific sink.
 814                          */
 815                         if (dpcd_caps->psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
 816                                 isPSRSUSupported = false;
 817                         else if (dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 818                                 ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) ||
 819                                 (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07)))
 820                                 isPSRSUSupported = false;
 821                         else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1)
 822                                 isPSRSUSupported = true;
 823                 }
 824         }
 825
 826         return isPSRSUSupported;
 827 }
 828
 829 /**
 830  * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields.
 831  * @psr_config: [output], psr configuration structure to be updated
 832  * @link: [input] dc link pointer
 833  * @stream: [input] dc stream state pointer
 834  *
 835  * calculate and update the psr configuration fields that are not DM specific, i.e. such
 836  * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW,
 837  * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr().
 838  *
 839  * PSR config fields to be updated within the helper:
 840  * - psr_rfb_setup_time
 841  * - psr_sdp_transmit_line_num_deadline
 842  * - line_time_in_us
 843  * - su_y_granularity
 844  * - su_granularity_required
 845  * - psr_frame_capture_indication_req
 846  * - psr_exit_link_training_required
 847  *
 848  * PSR config fields that are DM specific and NOT updated within the helper:
 849  * - allow_smu_optimizations
 850  * - allow_multi_disp_optimizations
 851  */
 852 void mod_power_calc_psr_configs(struct psr_config *psr_config,
 853                 struct dc_link *link,
 854                 const struct dc_stream_state *stream)
 855 {
 856         unsigned int num_vblank_lines = 0;
 857         unsigned int vblank_time_in_us = 0;
 858         unsigned int sdp_tx_deadline_in_us = 0;
 859         unsigned int line_time_in_us = 0;
 860         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 861         const int psr_setup_time_step_in_us = 55;       /* refer to eDP spec DPCD 0x071h */
 862
 863         /* timing parameters */
 864         num_vblank_lines = stream->timing.v_total -
 865                          stream->timing.v_addressable -
 866                          stream->timing.v_border_top -
 867                          stream->timing.v_border_bottom;
 868
 869         vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
 870
 871         line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
 872
 873         /**
 874          * psr configuration fields
 875          *
 876          * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below
 877          * 000b <--> 330 us (default)
 878          * 001b <--> 275 us
 879          * 010b <--> 220 us
 880          * 011b <--> 165 us
 881          * 100b <--> 110 us
 882          * 101b <--> 055 us
 883          * 110b <--> 000 us
 884          */
 885         psr_config->psr_rfb_setup_time =
 886                 (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;
 887
 888         if (psr_config->psr_rfb_setup_time > vblank_time_in_us) {
 889                 link->psr_settings.psr_frame_capture_indication_req = true;
 890                 link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines;
 891         } else {
 892                 sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time;
 893
 894                 /* Set the last possible line SDP may be transmitted without violating the RFB setup time */
 895                 link->psr_settings.psr_frame_capture_indication_req = false;
 896                 link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us;
 897         }
 898
 899         psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline;
 900         psr_config->line_time_in_us = line_time_in_us;
 901         psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
 902         psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
 903         psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req;
 904         psr_config->psr_exit_link_training_required =
 905                 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
 906 }
 907
 908 bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
 909 {
 910         return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
 911 }
 912
 913 bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
 914                               struct dc_stream_state *stream,
 915                               struct psr_config *config)
 916 {
 917         uint16_t pic_height;
 918         uint16_t slice_height;
 919
 920         config->dsc_slice_height = 0;
 921         if ((link->connector_signal & SIGNAL_TYPE_EDP) &&
 922             (!dc->caps.edp_dsc_support ||
 923             link->panel_config.dsc.disable_dsc_edp ||
 924             !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
 925             !stream->timing.dsc_cfg.num_slices_v))
 926                 return true;
 927
 928         pic_height = stream->timing.v_addressable +
 929                 stream->timing.v_border_top + stream->timing.v_border_bottom;
 930
 931         if (stream->timing.dsc_cfg.num_slices_v == 0)
 932                 return false;
 933
 934         slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
 935         config->dsc_slice_height = slice_height;
 936
 937         if (slice_height) {
 938                 if (config->su_y_granularity &&
 939                     (slice_height % config->su_y_granularity)) {
 940                         ASSERT(0);
 941                         return false;
 942                 }
 943         }
 944
 945         return true;
 946 }