drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include <drm/drm_vblank.h>
  27 #include <drm/drm_atomic_helper.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm_psr.h"
  32 #include "amdgpu_dm_crtc.h"
  33 #include "amdgpu_dm_plane.h"
  34 #include "amdgpu_dm_trace.h"
  35 #include "amdgpu_dm_debugfs.h"
  36
  37 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
  38 {
  39         struct drm_crtc *crtc = &acrtc->base;
  40         struct drm_device *dev = crtc->dev;
  41         unsigned long flags;
  42
  43         drm_crtc_handle_vblank(crtc);
  44
  45         spin_lock_irqsave(&dev->event_lock, flags);
  46
  47         /* Send completion event for cursor-only commits */
  48         if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  49                 drm_crtc_send_vblank_event(crtc, acrtc->event);
  50                 drm_crtc_vblank_put(crtc);
  51                 acrtc->event = NULL;
  52         }
  53
  54         spin_unlock_irqrestore(&dev->event_lock, flags);
  55 }
  56
  57 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
  58                              struct dc_stream_state *new_stream,
  59                              struct dc_stream_state *old_stream)
  60 {
  61         return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
  62 }
  63
  64 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
  65
  66 {
  67         return acrtc->dm_irq_params.freesync_config.state ==
  68                        VRR_STATE_ACTIVE_VARIABLE ||
  69                acrtc->dm_irq_params.freesync_config.state ==
  70                        VRR_STATE_ACTIVE_FIXED;
  71 }
  72
  73 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
  74 {
  75         enum dc_irq_source irq_source;
  76         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  77         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
  78         int rc;
  79
  80         if (acrtc->otg_inst == -1)
  81                 return 0;
  82
  83         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
  84
  85         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
  86
  87         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
  88                       acrtc->crtc_id, enable ? "en" : "dis", rc);
  89         return rc;
  90 }
  91
  92 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
  93 {
  94         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
  95                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
  96 }
  97
  98 static void vblank_control_worker(struct work_struct *work)
  99 {
 100         struct vblank_control_work *vblank_work =
 101                 container_of(work, struct vblank_control_work, work);
 102         struct amdgpu_display_manager *dm = vblank_work->dm;
 103
 104         mutex_lock(&dm->dc_lock);
 105
 106         if (vblank_work->enable)
 107                 dm->active_vblank_irq_count++;
 108         else if (dm->active_vblank_irq_count)
 109                 dm->active_vblank_irq_count--;
 110
 111         dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
 112
 113         DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 114
 115         /*
 116          * Control PSR based on vblank requirements from OS
 117          *
 118          * If panel supports PSR SU, there's no need to disable PSR when OS is
 119          * submitting fast atomic commits (we infer this by whether the OS
 120          * requests vblank events). Fast atomic commits will simply trigger a
 121          * full-frame-update (FFU); a specific case of selective-update (SU)
 122          * where the SU region is the full hactive*vactive region. See
 123          * fill_dc_dirty_rects().
 124          */
 125         if (vblank_work->stream && vblank_work->stream->link) {
 126                 if (vblank_work->enable) {
 127                         if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
 128                             vblank_work->stream->link->psr_settings.psr_allow_active)
 129                                 amdgpu_dm_psr_disable(vblank_work->stream);
 130                 } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
 131                            !vblank_work->stream->link->psr_settings.psr_allow_active &&
 132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 133                            !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
 134 #endif
 135                            vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
 136                         amdgpu_dm_psr_enable(vblank_work->stream);
 137                 }
 138         }
 139
 140         mutex_unlock(&dm->dc_lock);
 141
 142         dc_stream_release(vblank_work->stream);
 143
 144         kfree(vblank_work);
 145 }
 146
 147 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
 148 {
 149         enum dc_irq_source irq_source;
 150         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 151         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 152         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 153         struct amdgpu_display_manager *dm = &adev->dm;
 154         struct vblank_control_work *work;
 155         int rc = 0;
 156
 157         if (acrtc->otg_inst == -1)
 158                 goto skip;
 159
 160         if (enable) {
 161                 /* vblank irq on -> Only need vupdate irq in vrr mode */
 162                 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
 163                         rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
 164         } else {
 165                 /* vblank irq off -> vupdate irq off */
 166                 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
 167         }
 168
 169         if (rc)
 170                 return rc;
 171
 172         if (amdgpu_in_reset(adev)) {
 173                 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
 174                 /* During gpu-reset we disable and then enable vblank irq, so
 175                  * don't use amdgpu_irq_get/put() to avoid refcount change.
 176                  */
 177                 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
 178                         rc = -EBUSY;
 179         } else {
 180                 rc = (enable)
 181                         ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
 182                         : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
 183         }
 184
 185         if (rc)
 186                 return rc;
 187
 188 skip:
 189         if (amdgpu_in_reset(adev))
 190                 return 0;
 191
 192         if (dm->vblank_control_workqueue) {
 193                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 194                 if (!work)
 195                         return -ENOMEM;
 196
 197                 INIT_WORK(&work->work, vblank_control_worker);
 198                 work->dm = dm;
 199                 work->acrtc = acrtc;
 200                 work->enable = enable;
 201
 202                 if (acrtc_state->stream) {
 203                         dc_stream_retain(acrtc_state->stream);
 204                         work->stream = acrtc_state->stream;
 205                 }
 206
 207                 queue_work(dm->vblank_control_workqueue, &work->work);
 208         }
 209
 210         return 0;
 211 }
 212
 213 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
 214 {
 215         return dm_set_vblank(crtc, true);
 216 }
 217
 218 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
 219 {
 220         dm_set_vblank(crtc, false);
 221 }
 222
 223 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
 224                                   struct drm_crtc_state *state)
 225 {
 226         struct dm_crtc_state *cur = to_dm_crtc_state(state);
 227
 228         /* TODO Destroy dc_stream objects are stream object is flattened */
 229         if (cur->stream)
 230                 dc_stream_release(cur->stream);
 231
 232
 233         __drm_atomic_helper_crtc_destroy_state(state);
 234
 235
 236         kfree(state);
 237 }
 238
 239 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
 240 {
 241         struct dm_crtc_state *state, *cur;
 242
 243         cur = to_dm_crtc_state(crtc->state);
 244
 245         if (WARN_ON(!crtc->state))
 246                 return NULL;
 247
 248         state = kzalloc(sizeof(*state), GFP_KERNEL);
 249         if (!state)
 250                 return NULL;
 251
 252         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 253
 254         if (cur->stream) {
 255                 state->stream = cur->stream;
 256                 dc_stream_retain(state->stream);
 257         }
 258
 259         state->active_planes = cur->active_planes;
 260         state->vrr_infopacket = cur->vrr_infopacket;
 261         state->abm_level = cur->abm_level;
 262         state->vrr_supported = cur->vrr_supported;
 263         state->freesync_config = cur->freesync_config;
 264         state->cm_has_degamma = cur->cm_has_degamma;
 265         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 266         state->crc_skip_count = cur->crc_skip_count;
 267         state->mpo_requested = cur->mpo_requested;
 268         /* TODO Duplicate dc_stream after objects are stream object is flattened */
 269
 270         return &state->base;
 271 }
 272
 273 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
 274 {
 275         drm_crtc_cleanup(crtc);
 276         kfree(crtc);
 277 }
 278
 279 static void dm_crtc_reset_state(struct drm_crtc *crtc)
 280 {
 281         struct dm_crtc_state *state;
 282
 283         if (crtc->state)
 284                 dm_crtc_destroy_state(crtc, crtc->state);
 285
 286         state = kzalloc(sizeof(*state), GFP_KERNEL);
 287         if (WARN_ON(!state))
 288                 return;
 289
 290         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 291 }
 292
 293 #ifdef CONFIG_DEBUG_FS
 294 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 295 {
 296         crtc_debugfs_init(crtc);
 297
 298         return 0;
 299 }
 300 #endif
 301
 302 /* Implemented only the options currently available for the driver */
 303 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 304         .reset = dm_crtc_reset_state,
 305         .destroy = amdgpu_dm_crtc_destroy,
 306         .set_config = drm_atomic_helper_set_config,
 307         .page_flip = drm_atomic_helper_page_flip,
 308         .atomic_duplicate_state = dm_crtc_duplicate_state,
 309         .atomic_destroy_state = dm_crtc_destroy_state,
 310         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
 311         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
 312         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
 313         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 314         .enable_vblank = amdgpu_dm_crtc_enable_vblank,
 315         .disable_vblank = amdgpu_dm_crtc_disable_vblank,
 316         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 317 #if defined(CONFIG_DEBUG_FS)
 318         .late_register = amdgpu_dm_crtc_late_register,
 319 #endif
 320 };
 321
 322 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
 323 {
 324 }
 325
 326 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
 327 {
 328         struct drm_atomic_state *state = new_crtc_state->state;
 329         struct drm_plane *plane;
 330         int num_active = 0;
 331
 332         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
 333                 struct drm_plane_state *new_plane_state;
 334
 335                 /* Cursor planes are "fake". */
 336                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 337                         continue;
 338
 339                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
 340
 341                 if (!new_plane_state) {
 342                         /*
 343                          * The plane is enable on the CRTC and hasn't changed
 344                          * state. This means that it previously passed
 345                          * validation and is therefore enabled.
 346                          */
 347                         num_active += 1;
 348                         continue;
 349                 }
 350
 351                 /* We need a framebuffer to be considered enabled. */
 352                 num_active += (new_plane_state->fb != NULL);
 353         }
 354
 355         return num_active;
 356 }
 357
 358 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
 359                                          struct drm_crtc_state *new_crtc_state)
 360 {
 361         struct dm_crtc_state *dm_new_crtc_state =
 362                 to_dm_crtc_state(new_crtc_state);
 363
 364         dm_new_crtc_state->active_planes = 0;
 365
 366         if (!dm_new_crtc_state->stream)
 367                 return;
 368
 369         dm_new_crtc_state->active_planes =
 370                 count_crtc_active_planes(new_crtc_state);
 371 }
 372
 373 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
 374                                       const struct drm_display_mode *mode,
 375                                       struct drm_display_mode *adjusted_mode)
 376 {
 377         return true;
 378 }
 379
 380 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 381                                       struct drm_atomic_state *state)
 382 {
 383         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 384                                                                                 crtc);
 385         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 386         struct dc *dc = adev->dm.dc;
 387         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 388         int ret = -EINVAL;
 389
 390         trace_amdgpu_dm_crtc_atomic_check(crtc_state);
 391
 392         dm_update_crtc_active_planes(crtc, crtc_state);
 393
 394         if (WARN_ON(unlikely(!dm_crtc_state->stream &&
 395                         amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
 396                 return ret;
 397         }
 398
 399         /*
 400          * We require the primary plane to be enabled whenever the CRTC is, otherwise
 401          * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
 402          * planes are disabled, which is not supported by the hardware. And there is legacy
 403          * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
 404          */
 405         if (crtc_state->enable &&
 406                 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
 407                 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
 408                 return -EINVAL;
 409         }
 410
 411         /* In some use cases, like reset, no stream is attached */
 412         if (!dm_crtc_state->stream)
 413                 return 0;
 414
 415         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
 416                 return 0;
 417
 418         DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
 419         return ret;
 420 }
 421
 422 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
 423         .disable = dm_crtc_helper_disable,
 424         .atomic_check = dm_crtc_helper_atomic_check,
 425         .mode_fixup = dm_crtc_helper_mode_fixup,
 426         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 427 };
 428
 429 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 430                                struct drm_plane *plane,
 431                                uint32_t crtc_index)
 432 {
 433         struct amdgpu_crtc *acrtc = NULL;
 434         struct drm_plane *cursor_plane;
 435         bool is_dcn;
 436         int res = -ENOMEM;
 437
 438         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
 439         if (!cursor_plane)
 440                 goto fail;
 441
 442         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
 443         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
 444
 445         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 446         if (!acrtc)
 447                 goto fail;
 448
 449         res = drm_crtc_init_with_planes(
 450                         dm->ddev,
 451                         &acrtc->base,
 452                         plane,
 453                         cursor_plane,
 454                         &amdgpu_dm_crtc_funcs, NULL);
 455
 456         if (res)
 457                 goto fail;
 458
 459         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
 460
 461         /* Create (reset) the plane state */
 462         if (acrtc->base.funcs->reset)
 463                 acrtc->base.funcs->reset(&acrtc->base);
 464
 465         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
 466         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
 467
 468         acrtc->crtc_id = crtc_index;
 469         acrtc->base.enabled = false;
 470         acrtc->otg_inst = -1;
 471
 472         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
 473
 474         /* Don't enable DRM CRTC degamma property for DCE since it doesn't
 475          * support programmable degamma anywhere.
 476          */
 477         is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
 478         drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
 479                                    true, MAX_COLOR_LUT_ENTRIES);
 480
 481         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
 482
 483         return 0;
 484
 485 fail:
 486         kfree(acrtc);
 487         kfree(cursor_plane);
 488         return res;
 489 }
 490