drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *    Daniel Vetter <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 401         (POWER_DOMAIN_MASK & ~(                         \
 402         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 403         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 404         BIT(POWER_DOMAIN_INIT))
 405
 406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 407         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 408         BIT(POWER_DOMAIN_PIPE_B) |                      \
 409         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 410         BIT(POWER_DOMAIN_PIPE_C) |                      \
 411         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 412         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 413         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 414         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 415         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 416         BIT(POWER_DOMAIN_AUX_B) |                       \
 417         BIT(POWER_DOMAIN_AUX_C) |                       \
 418         BIT(POWER_DOMAIN_AUDIO) |                       \
 419         BIT(POWER_DOMAIN_VGA) |                         \
 420         BIT(POWER_DOMAIN_GMBUS) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 423         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 424         BIT(POWER_DOMAIN_PIPE_A) |                      \
 425         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 426         BIT(POWER_DOMAIN_TRANSCODER_DSI_A) |            \
 427         BIT(POWER_DOMAIN_TRANSCODER_DSI_C) |            \
 428         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 429         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 430         BIT(POWER_DOMAIN_PORT_DSI) |                    \
 431         BIT(POWER_DOMAIN_AUX_A) |                       \
 432         BIT(POWER_DOMAIN_PLLS) |                        \
 433         BIT(POWER_DOMAIN_INIT))
 434 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 435         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 436         BIT(POWER_DOMAIN_MODESET) |                     \
 437         BIT(POWER_DOMAIN_AUX_A) |                       \
 438         BIT(POWER_DOMAIN_INIT))
 439 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 440         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 441         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 442         BIT(POWER_DOMAIN_INIT))
 443
 444 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 445 {
 446         struct drm_device *dev = dev_priv->dev;
 447
 448         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 449         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 450                 "DC9 already programmed to be enabled.\n");
 451         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 452                 "DC5 still not disabled to enable DC9.\n");
 453         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 454         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 455
 456          /*
 457           * TODO: check for the following to verify the conditions to enter DC9
 458           * state are satisfied:
 459           * 1] Check relevant display engine registers to verify if mode set
 460           * disable sequence was followed.
 461           * 2] Check if display uninitialize sequence is initialized.
 462           */
 463 }
 464
 465 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 466 {
 467         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 468         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 469                 "DC5 still not disabled.\n");
 470
 471          /*
 472           * TODO: check for the following to verify DC9 state was indeed
 473           * entered before programming to disable it:
 474           * 1] Check relevant display engine registers to verify if mode
 475           *  set disable sequence was followed.
 476           * 2] Check if display uninitialize sequence is initialized.
 477           */
 478 }
 479
 480 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 481                                 u32 state)
 482 {
 483         int rewrites = 0;
 484         int rereads = 0;
 485         u32 v;
 486
 487         I915_WRITE(DC_STATE_EN, state);
 488
 489         /* It has been observed that disabling the dc6 state sometimes
 490          * doesn't stick and dmc keeps returning old value. Make sure
 491          * the write really sticks enough times and also force rewrite until
 492          * we are confident that state is exactly what we want.
 493          */
 494         do  {
 495                 v = I915_READ(DC_STATE_EN);
 496
 497                 if (v != state) {
 498                         I915_WRITE(DC_STATE_EN, state);
 499                         rewrites++;
 500                         rereads = 0;
 501                 } else if (rereads++ > 5) {
 502                         break;
 503                 }
 504
 505         } while (rewrites < 100);
 506
 507         if (v != state)
 508                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 509                           state, v);
 510
 511         /* Most of the times we need one retry, avoid spam */
 512         if (rewrites > 1)
 513                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 514                               state, rewrites);
 515 }
 516
 517 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 518 {
 519         uint32_t val;
 520         uint32_t mask;
 521
 522         mask = DC_STATE_EN_UPTO_DC5;
 523         if (IS_BROXTON(dev_priv))
 524                 mask |= DC_STATE_EN_DC9;
 525         else
 526                 mask |= DC_STATE_EN_UPTO_DC6;
 527
 528         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 529                 state &= dev_priv->csr.allowed_dc_mask;
 530
 531         val = I915_READ(DC_STATE_EN);
 532         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 533                       val & mask, state);
 534
 535         /* Check if DMC is ignoring our DC state requests */
 536         if ((val & mask) != dev_priv->csr.dc_state)
 537                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 538                           dev_priv->csr.dc_state, val & mask);
 539
 540         val &= ~mask;
 541         val |= state;
 542
 543         gen9_write_dc_state(dev_priv, val);
 544
 545         dev_priv->csr.dc_state = val & mask;
 546 }
 547
 548 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 549 {
 550         assert_can_enable_dc9(dev_priv);
 551
 552         DRM_DEBUG_KMS("Enabling DC9\n");
 553
 554         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 555 }
 556
 557 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 558 {
 559         assert_can_disable_dc9(dev_priv);
 560
 561         DRM_DEBUG_KMS("Disabling DC9\n");
 562
 563         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 564 }
 565
 566 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 567 {
 568         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 569                   "CSR program storage start is NULL\n");
 570         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 571         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 572 }
 573
 574 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 575 {
 576         struct drm_device *dev = dev_priv->dev;
 577         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 578                                         SKL_DISP_PW_2);
 579
 580         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 581                   "Platform doesn't support DC5.\n");
 582         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 583         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 584
 585         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 586                   "DC5 already programmed to be enabled.\n");
 587         assert_rpm_wakelock_held(dev_priv);
 588
 589         assert_csr_loaded(dev_priv);
 590 }
 591
 592 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 593 {
 594         assert_can_enable_dc5(dev_priv);
 595
 596         DRM_DEBUG_KMS("Enabling DC5\n");
 597
 598         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 599 }
 600
 601 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 602 {
 603         struct drm_device *dev = dev_priv->dev;
 604
 605         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 606                   "Platform doesn't support DC6.\n");
 607         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 608         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 609                   "Backlight is not disabled.\n");
 610         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 611                   "DC6 already programmed to be enabled.\n");
 612
 613         assert_csr_loaded(dev_priv);
 614 }
 615
 616 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 617 {
 618         assert_can_enable_dc6(dev_priv);
 619
 620         DRM_DEBUG_KMS("Enabling DC6\n");
 621
 622         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 623
 624 }
 625
 626 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 627 {
 628         DRM_DEBUG_KMS("Disabling DC6\n");
 629
 630         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 631 }
 632
 633 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 634                         struct i915_power_well *power_well, bool enable)
 635 {
 636         uint32_t tmp, fuse_status;
 637         uint32_t req_mask, state_mask;
 638         bool is_enabled, enable_requested, check_fuse_status = false;
 639
 640         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 641         fuse_status = I915_READ(SKL_FUSE_STATUS);
 642
 643         switch (power_well->data) {
 644         case SKL_DISP_PW_1:
 645                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 646                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 647                         DRM_ERROR("PG0 not enabled\n");
 648                         return;
 649                 }
 650                 break;
 651         case SKL_DISP_PW_2:
 652                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 653                         DRM_ERROR("PG1 in disabled state\n");
 654                         return;
 655                 }
 656                 break;
 657         case SKL_DISP_PW_DDI_A_E:
 658         case SKL_DISP_PW_DDI_B:
 659         case SKL_DISP_PW_DDI_C:
 660         case SKL_DISP_PW_DDI_D:
 661         case SKL_DISP_PW_MISC_IO:
 662                 break;
 663         default:
 664                 WARN(1, "Unknown power well %lu\n", power_well->data);
 665                 return;
 666         }
 667
 668         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 669         enable_requested = tmp & req_mask;
 670         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 671         is_enabled = tmp & state_mask;
 672
 673         if (!enable && enable_requested)
 674                 skl_power_well_pre_disable(dev_priv, power_well);
 675
 676         if (enable) {
 677                 if (!enable_requested) {
 678                         WARN((tmp & state_mask) &&
 679                                 !I915_READ(HSW_PWR_WELL_BIOS),
 680                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 681                                 when request is to disable!\n");
 682                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 683                 }
 684
 685                 if (!is_enabled) {
 686                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 687                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 688                                 state_mask), 1))
 689                                 DRM_ERROR("%s enable timeout\n",
 690                                         power_well->name);
 691                         check_fuse_status = true;
 692                 }
 693         } else {
 694                 if (enable_requested) {
 695                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 696                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 697                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 698                 }
 699         }
 700
 701         if (check_fuse_status) {
 702                 if (power_well->data == SKL_DISP_PW_1) {
 703                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 704                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 705                                 DRM_ERROR("PG1 distributing status timeout\n");
 706                 } else if (power_well->data == SKL_DISP_PW_2) {
 707                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 708                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 709                                 DRM_ERROR("PG2 distributing status timeout\n");
 710                 }
 711         }
 712
 713         if (enable && !is_enabled)
 714                 skl_power_well_post_enable(dev_priv, power_well);
 715 }
 716
 717 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 718                                    struct i915_power_well *power_well)
 719 {
 720         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 721
 722         /*
 723          * We're taking over the BIOS, so clear any requests made by it since
 724          * the driver is in charge now.
 725          */
 726         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 727                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 728 }
 729
 730 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 731                                   struct i915_power_well *power_well)
 732 {
 733         hsw_set_power_well(dev_priv, power_well, true);
 734 }
 735
 736 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 737                                    struct i915_power_well *power_well)
 738 {
 739         hsw_set_power_well(dev_priv, power_well, false);
 740 }
 741
 742 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 743                                         struct i915_power_well *power_well)
 744 {
 745         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 746                 SKL_POWER_WELL_STATE(power_well->data);
 747
 748         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 749 }
 750
 751 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 752                                 struct i915_power_well *power_well)
 753 {
 754         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 755
 756         /* Clear any request made by BIOS as driver is taking over */
 757         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 758 }
 759
 760 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 761                                 struct i915_power_well *power_well)
 762 {
 763         skl_set_power_well(dev_priv, power_well, true);
 764 }
 765
 766 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 767                                 struct i915_power_well *power_well)
 768 {
 769         skl_set_power_well(dev_priv, power_well, false);
 770 }
 771
 772 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 773                                            struct i915_power_well *power_well)
 774 {
 775         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 776 }
 777
 778 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 779                                           struct i915_power_well *power_well)
 780 {
 781         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 782 }
 783
 784 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 785                                            struct i915_power_well *power_well)
 786 {
 787         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 788                 skl_enable_dc6(dev_priv);
 789         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 790                 gen9_enable_dc5(dev_priv);
 791 }
 792
 793 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 794                                            struct i915_power_well *power_well)
 795 {
 796         if (power_well->count > 0)
 797                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 798         else
 799                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 800 }
 801
 802 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 803                                            struct i915_power_well *power_well)
 804 {
 805 }
 806
 807 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 808                                              struct i915_power_well *power_well)
 809 {
 810         return true;
 811 }
 812
 813 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 814                                struct i915_power_well *power_well, bool enable)
 815 {
 816         enum punit_power_well power_well_id = power_well->data;
 817         u32 mask;
 818         u32 state;
 819         u32 ctrl;
 820
 821         mask = PUNIT_PWRGT_MASK(power_well_id);
 822         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 823                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 824
 825         mutex_lock(&dev_priv->rps.hw_lock);
 826
 827 #define COND \
 828         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 829
 830         if (COND)
 831                 goto out;
 832
 833         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 834         ctrl &= ~mask;
 835         ctrl |= state;
 836         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 837
 838         if (wait_for(COND, 100))
 839                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 840                           state,
 841                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 842
 843 #undef COND
 844
 845 out:
 846         mutex_unlock(&dev_priv->rps.hw_lock);
 847 }
 848
 849 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 850                                    struct i915_power_well *power_well)
 851 {
 852         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 853 }
 854
 855 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 856                                   struct i915_power_well *power_well)
 857 {
 858         vlv_set_power_well(dev_priv, power_well, true);
 859 }
 860
 861 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 862                                    struct i915_power_well *power_well)
 863 {
 864         vlv_set_power_well(dev_priv, power_well, false);
 865 }
 866
 867 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 868                                    struct i915_power_well *power_well)
 869 {
 870         int power_well_id = power_well->data;
 871         bool enabled = false;
 872         u32 mask;
 873         u32 state;
 874         u32 ctrl;
 875
 876         mask = PUNIT_PWRGT_MASK(power_well_id);
 877         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 878
 879         mutex_lock(&dev_priv->rps.hw_lock);
 880
 881         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 882         /*
 883          * We only ever set the power-on and power-gate states, anything
 884          * else is unexpected.
 885          */
 886         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 887                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 888         if (state == ctrl)
 889                 enabled = true;
 890
 891         /*
 892          * A transient state at this point would mean some unexpected party
 893          * is poking at the power controls too.
 894          */
 895         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 896         WARN_ON(ctrl != state);
 897
 898         mutex_unlock(&dev_priv->rps.hw_lock);
 899
 900         return enabled;
 901 }
 902
 903 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 904 {
 905         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 906
 907         /*
 908          * Disable trickle feed and enable pnd deadline calculation
 909          */
 910         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 911         I915_WRITE(CBR1_VLV, 0);
 912 }
 913
 914 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 915 {
 916         enum pipe pipe;
 917
 918         /*
 919          * Enable the CRI clock source so we can get at the
 920          * display and the reference clock for VGA
 921          * hotplug / manual detection. Supposedly DSI also
 922          * needs the ref clock up and running.
 923          *
 924          * CHV DPLL B/C have some issues if VGA mode is enabled.
 925          */
 926         for_each_pipe(dev_priv->dev, pipe) {
 927                 u32 val = I915_READ(DPLL(pipe));
 928
 929                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 930                 if (pipe != PIPE_A)
 931                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 932
 933                 I915_WRITE(DPLL(pipe), val);
 934         }
 935
 936         vlv_init_display_clock_gating(dev_priv);
 937
 938         spin_lock_irq(&dev_priv->irq_lock);
 939         valleyview_enable_display_irqs(dev_priv);
 940         spin_unlock_irq(&dev_priv->irq_lock);
 941
 942         /*
 943          * During driver initialization/resume we can avoid restoring the
 944          * part of the HW/SW state that will be inited anyway explicitly.
 945          */
 946         if (dev_priv->power_domains.initializing)
 947                 return;
 948
 949         intel_hpd_init(dev_priv);
 950
 951         i915_redisable_vga_power_on(dev_priv->dev);
 952 }
 953
 954 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 955 {
 956         spin_lock_irq(&dev_priv->irq_lock);
 957         valleyview_disable_display_irqs(dev_priv);
 958         spin_unlock_irq(&dev_priv->irq_lock);
 959
 960         /* make sure we're done processing display irqs */
 961         synchronize_irq(dev_priv->dev->irq);
 962
 963         vlv_power_sequencer_reset(dev_priv);
 964 }
 965
 966 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 967                                           struct i915_power_well *power_well)
 968 {
 969         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 970
 971         vlv_set_power_well(dev_priv, power_well, true);
 972
 973         vlv_display_power_well_init(dev_priv);
 974 }
 975
 976 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 977                                            struct i915_power_well *power_well)
 978 {
 979         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 980
 981         vlv_display_power_well_deinit(dev_priv);
 982
 983         vlv_set_power_well(dev_priv, power_well, false);
 984 }
 985
 986 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 987                                            struct i915_power_well *power_well)
 988 {
 989         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 990
 991         /* since ref/cri clock was enabled */
 992         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 993
 994         vlv_set_power_well(dev_priv, power_well, true);
 995
 996         /*
 997          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 998          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 999          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1000          *   b. The other bits such as sfr settings / modesel may all
1001          *      be set to 0.
1002          *
1003          * This should only be done on init and resume from S3 with
1004          * both PLLs disabled, or we risk losing DPIO and PLL
1005          * synchronization.
1006          */
1007         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1008 }
1009
1010 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1011                                             struct i915_power_well *power_well)
1012 {
1013         enum pipe pipe;
1014
1015         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1016
1017         for_each_pipe(dev_priv, pipe)
1018                 assert_pll_disabled(dev_priv, pipe);
1019
1020         /* Assert common reset */
1021         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1022
1023         vlv_set_power_well(dev_priv, power_well, false);
1024 }
1025
1026 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1027
1028 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1029                                                  int power_well_id)
1030 {
1031         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1032         int i;
1033
1034         for (i = 0; i < power_domains->power_well_count; i++) {
1035                 struct i915_power_well *power_well;
1036
1037                 power_well = &power_domains->power_wells[i];
1038                 if (power_well->data == power_well_id)
1039                         return power_well;
1040         }
1041
1042         return NULL;
1043 }
1044
1045 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1046
1047 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1048 {
1049         struct i915_power_well *cmn_bc =
1050                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1051         struct i915_power_well *cmn_d =
1052                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1053         u32 phy_control = dev_priv->chv_phy_control;
1054         u32 phy_status = 0;
1055         u32 phy_status_mask = 0xffffffff;
1056         u32 tmp;
1057
1058         /*
1059          * The BIOS can leave the PHY is some weird state
1060          * where it doesn't fully power down some parts.
1061          * Disable the asserts until the PHY has been fully
1062          * reset (ie. the power well has been disabled at
1063          * least once).
1064          */
1065         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1066                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1067                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1068                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1069                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1070                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1071                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1072
1073         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1074                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1075                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1076                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1077
1078         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1079                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1080
1081                 /* this assumes override is only used to enable lanes */
1082                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1083                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1084
1085                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1086                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1087
1088                 /* CL1 is on whenever anything is on in either channel */
1089                 if (BITS_SET(phy_control,
1090                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1091                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1092                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1093
1094                 /*
1095                  * The DPLLB check accounts for the pipe B + port A usage
1096                  * with CL2 powered up but all the lanes in the second channel
1097                  * powered down.
1098                  */
1099                 if (BITS_SET(phy_control,
1100                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1101                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1102                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1103
1104                 if (BITS_SET(phy_control,
1105                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1106                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1107                 if (BITS_SET(phy_control,
1108                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1109                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1110
1111                 if (BITS_SET(phy_control,
1112                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1113                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1114                 if (BITS_SET(phy_control,
1115                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1116                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1117         }
1118
1119         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1120                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1121
1122                 /* this assumes override is only used to enable lanes */
1123                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1124                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1125
1126                 if (BITS_SET(phy_control,
1127                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1128                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1129
1130                 if (BITS_SET(phy_control,
1131                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1132                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1133                 if (BITS_SET(phy_control,
1134                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1135                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1136         }
1137
1138         phy_status &= phy_status_mask;
1139
1140         /*
1141          * The PHY may be busy with some initial calibration and whatnot,
1142          * so the power state can take a while to actually change.
1143          */
1144         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1145                 WARN(phy_status != tmp,
1146                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1147                      tmp, phy_status, dev_priv->chv_phy_control);
1148 }
1149
1150 #undef BITS_SET
1151
1152 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1153                                            struct i915_power_well *power_well)
1154 {
1155         enum dpio_phy phy;
1156         enum pipe pipe;
1157         uint32_t tmp;
1158
1159         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1160                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1161
1162         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1163                 pipe = PIPE_A;
1164                 phy = DPIO_PHY0;
1165         } else {
1166                 pipe = PIPE_C;
1167                 phy = DPIO_PHY1;
1168         }
1169
1170         /* since ref/cri clock was enabled */
1171         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1172         vlv_set_power_well(dev_priv, power_well, true);
1173
1174         /* Poll for phypwrgood signal */
1175         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1176                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179
1180         /* Enable dynamic power down */
1181         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1182         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1183                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1184         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1185
1186         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1187                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1188                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1189                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1190         } else {
1191                 /*
1192                  * Force the non-existing CL2 off. BXT does this
1193                  * too, so maybe it saves some power even though
1194                  * CL2 doesn't exist?
1195                  */
1196                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1197                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1198                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1199         }
1200
1201         mutex_unlock(&dev_priv->sb_lock);
1202
1203         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1204         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1205
1206         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1207                       phy, dev_priv->chv_phy_control);
1208
1209         assert_chv_phy_status(dev_priv);
1210 }
1211
1212 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1213                                             struct i915_power_well *power_well)
1214 {
1215         enum dpio_phy phy;
1216
1217         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1218                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1219
1220         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1221                 phy = DPIO_PHY0;
1222                 assert_pll_disabled(dev_priv, PIPE_A);
1223                 assert_pll_disabled(dev_priv, PIPE_B);
1224         } else {
1225                 phy = DPIO_PHY1;
1226                 assert_pll_disabled(dev_priv, PIPE_C);
1227         }
1228
1229         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1230         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1231
1232         vlv_set_power_well(dev_priv, power_well, false);
1233
1234         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1235                       phy, dev_priv->chv_phy_control);
1236
1237         /* PHY is fully reset now, so we can enable the PHY state asserts */
1238         dev_priv->chv_phy_assert[phy] = true;
1239
1240         assert_chv_phy_status(dev_priv);
1241 }
1242
1243 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1244                                      enum dpio_channel ch, bool override, unsigned int mask)
1245 {
1246         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1247         u32 reg, val, expected, actual;
1248
1249         /*
1250          * The BIOS can leave the PHY is some weird state
1251          * where it doesn't fully power down some parts.
1252          * Disable the asserts until the PHY has been fully
1253          * reset (ie. the power well has been disabled at
1254          * least once).
1255          */
1256         if (!dev_priv->chv_phy_assert[phy])
1257                 return;
1258
1259         if (ch == DPIO_CH0)
1260                 reg = _CHV_CMN_DW0_CH0;
1261         else
1262                 reg = _CHV_CMN_DW6_CH1;
1263
1264         mutex_lock(&dev_priv->sb_lock);
1265         val = vlv_dpio_read(dev_priv, pipe, reg);
1266         mutex_unlock(&dev_priv->sb_lock);
1267
1268         /*
1269          * This assumes !override is only used when the port is disabled.
1270          * All lanes should power down even without the override when
1271          * the port is disabled.
1272          */
1273         if (!override || mask == 0xf) {
1274                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1275                 /*
1276                  * If CH1 common lane is not active anymore
1277                  * (eg. for pipe B DPLL) the entire channel will
1278                  * shut down, which causes the common lane registers
1279                  * to read as 0. That means we can't actually check
1280                  * the lane power down status bits, but as the entire
1281                  * register reads as 0 it's a good indication that the
1282                  * channel is indeed entirely powered down.
1283                  */
1284                 if (ch == DPIO_CH1 && val == 0)
1285                         expected = 0;
1286         } else if (mask != 0x0) {
1287                 expected = DPIO_ANYDL_POWERDOWN;
1288         } else {
1289                 expected = 0;
1290         }
1291
1292         if (ch == DPIO_CH0)
1293                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1294         else
1295                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1296         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1297
1298         WARN(actual != expected,
1299              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1300              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1301              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1302              reg, val);
1303 }
1304
1305 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1306                           enum dpio_channel ch, bool override)
1307 {
1308         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1309         bool was_override;
1310
1311         mutex_lock(&power_domains->lock);
1312
1313         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1314
1315         if (override == was_override)
1316                 goto out;
1317
1318         if (override)
1319                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1320         else
1321                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1322
1323         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1324
1325         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1326                       phy, ch, dev_priv->chv_phy_control);
1327
1328         assert_chv_phy_status(dev_priv);
1329
1330 out:
1331         mutex_unlock(&power_domains->lock);
1332
1333         return was_override;
1334 }
1335
1336 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1337                              bool override, unsigned int mask)
1338 {
1339         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1340         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1341         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1342         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1343
1344         mutex_lock(&power_domains->lock);
1345
1346         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1347         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1348
1349         if (override)
1350                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1351         else
1352                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1353
1354         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1355
1356         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1357                       phy, ch, mask, dev_priv->chv_phy_control);
1358
1359         assert_chv_phy_status(dev_priv);
1360
1361         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1362
1363         mutex_unlock(&power_domains->lock);
1364 }
1365
1366 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1367                                         struct i915_power_well *power_well)
1368 {
1369         enum pipe pipe = power_well->data;
1370         bool enabled;
1371         u32 state, ctrl;
1372
1373         mutex_lock(&dev_priv->rps.hw_lock);
1374
1375         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1376         /*
1377          * We only ever set the power-on and power-gate states, anything
1378          * else is unexpected.
1379          */
1380         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1381         enabled = state == DP_SSS_PWR_ON(pipe);
1382
1383         /*
1384          * A transient state at this point would mean some unexpected party
1385          * is poking at the power controls too.
1386          */
1387         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1388         WARN_ON(ctrl << 16 != state);
1389
1390         mutex_unlock(&dev_priv->rps.hw_lock);
1391
1392         return enabled;
1393 }
1394
1395 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1396                                     struct i915_power_well *power_well,
1397                                     bool enable)
1398 {
1399         enum pipe pipe = power_well->data;
1400         u32 state;
1401         u32 ctrl;
1402
1403         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1404
1405         mutex_lock(&dev_priv->rps.hw_lock);
1406
1407 #define COND \
1408         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1409
1410         if (COND)
1411                 goto out;
1412
1413         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1414         ctrl &= ~DP_SSC_MASK(pipe);
1415         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1416         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1417
1418         if (wait_for(COND, 100))
1419                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1420                           state,
1421                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1422
1423 #undef COND
1424
1425 out:
1426         mutex_unlock(&dev_priv->rps.hw_lock);
1427 }
1428
1429 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1430                                         struct i915_power_well *power_well)
1431 {
1432         WARN_ON_ONCE(power_well->data != PIPE_A);
1433
1434         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1435 }
1436
1437 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1438                                        struct i915_power_well *power_well)
1439 {
1440         WARN_ON_ONCE(power_well->data != PIPE_A);
1441
1442         chv_set_pipe_power_well(dev_priv, power_well, true);
1443
1444         vlv_display_power_well_init(dev_priv);
1445 }
1446
1447 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1448                                         struct i915_power_well *power_well)
1449 {
1450         WARN_ON_ONCE(power_well->data != PIPE_A);
1451
1452         vlv_display_power_well_deinit(dev_priv);
1453
1454         chv_set_pipe_power_well(dev_priv, power_well, false);
1455 }
1456
1457 static void
1458 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1459                                  enum intel_display_power_domain domain)
1460 {
1461         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1462         struct i915_power_well *power_well;
1463         int i;
1464
1465         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1466                 if (!power_well->count++)
1467                         intel_power_well_enable(dev_priv, power_well);
1468         }
1469
1470         power_domains->domain_use_count[domain]++;
1471 }
1472
1473 /**
1474  * intel_display_power_get - grab a power domain reference
1475  * @dev_priv: i915 device instance
1476  * @domain: power domain to reference
1477  *
1478  * This function grabs a power domain reference for @domain and ensures that the
1479  * power domain and all its parents are powered up. Therefore users should only
1480  * grab a reference to the innermost power domain they need.
1481  *
1482  * Any power domain reference obtained by this function must have a symmetric
1483  * call to intel_display_power_put() to release the reference again.
1484  */
1485 void intel_display_power_get(struct drm_i915_private *dev_priv,
1486                              enum intel_display_power_domain domain)
1487 {
1488         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1489
1490         intel_runtime_pm_get(dev_priv);
1491
1492         mutex_lock(&power_domains->lock);
1493
1494         __intel_display_power_get_domain(dev_priv, domain);
1495
1496         mutex_unlock(&power_domains->lock);
1497 }
1498
1499 /**
1500  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1501  * @dev_priv: i915 device instance
1502  * @domain: power domain to reference
1503  *
1504  * This function grabs a power domain reference for @domain and ensures that the
1505  * power domain and all its parents are powered up. Therefore users should only
1506  * grab a reference to the innermost power domain they need.
1507  *
1508  * Any power domain reference obtained by this function must have a symmetric
1509  * call to intel_display_power_put() to release the reference again.
1510  */
1511 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1512                                         enum intel_display_power_domain domain)
1513 {
1514         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1515         bool is_enabled;
1516
1517         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1518                 return false;
1519
1520         mutex_lock(&power_domains->lock);
1521
1522         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1523                 __intel_display_power_get_domain(dev_priv, domain);
1524                 is_enabled = true;
1525         } else {
1526                 is_enabled = false;
1527         }
1528
1529         mutex_unlock(&power_domains->lock);
1530
1531         if (!is_enabled)
1532                 intel_runtime_pm_put(dev_priv);
1533
1534         return is_enabled;
1535 }
1536
1537 /**
1538  * intel_display_power_put - release a power domain reference
1539  * @dev_priv: i915 device instance
1540  * @domain: power domain to reference
1541  *
1542  * This function drops the power domain reference obtained by
1543  * intel_display_power_get() and might power down the corresponding hardware
1544  * block right away if this is the last reference.
1545  */
1546 void intel_display_power_put(struct drm_i915_private *dev_priv,
1547                              enum intel_display_power_domain domain)
1548 {
1549         struct i915_power_domains *power_domains;
1550         struct i915_power_well *power_well;
1551         int i;
1552
1553         power_domains = &dev_priv->power_domains;
1554
1555         mutex_lock(&power_domains->lock);
1556
1557         WARN(!power_domains->domain_use_count[domain],
1558              "Use count on domain %s is already zero\n",
1559              intel_display_power_domain_str(domain));
1560         power_domains->domain_use_count[domain]--;
1561
1562         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1563                 WARN(!power_well->count,
1564                      "Use count on power well %s is already zero",
1565                      power_well->name);
1566
1567                 if (!--power_well->count)
1568                         intel_power_well_disable(dev_priv, power_well);
1569         }
1570
1571         mutex_unlock(&power_domains->lock);
1572
1573         intel_runtime_pm_put(dev_priv);
1574 }
1575
1576 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1577         BIT(POWER_DOMAIN_PIPE_A) |                      \
1578         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1579         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1580         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1581         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1582         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1583         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1584         BIT(POWER_DOMAIN_PLLS) |                        \
1585         BIT(POWER_DOMAIN_AUX_A) |                       \
1586         BIT(POWER_DOMAIN_AUX_B) |                       \
1587         BIT(POWER_DOMAIN_AUX_C) |                       \
1588         BIT(POWER_DOMAIN_AUX_D) |                       \
1589         BIT(POWER_DOMAIN_GMBUS) |                       \
1590         BIT(POWER_DOMAIN_INIT))
1591 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1592         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1593         BIT(POWER_DOMAIN_INIT))
1594
1595 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1596         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1597         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1598 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1599         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1600         BIT(POWER_DOMAIN_INIT))
1601
1602 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1603 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1604
1605 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1606         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1607         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1608         BIT(POWER_DOMAIN_PORT_CRT) |            \
1609         BIT(POWER_DOMAIN_AUX_B) |               \
1610         BIT(POWER_DOMAIN_AUX_C) |               \
1611         BIT(POWER_DOMAIN_INIT))
1612
1613 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1614         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1615         BIT(POWER_DOMAIN_AUX_B) |               \
1616         BIT(POWER_DOMAIN_INIT))
1617
1618 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1619         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1620         BIT(POWER_DOMAIN_AUX_B) |               \
1621         BIT(POWER_DOMAIN_INIT))
1622
1623 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1624         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1625         BIT(POWER_DOMAIN_AUX_C) |               \
1626         BIT(POWER_DOMAIN_INIT))
1627
1628 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1629         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1630         BIT(POWER_DOMAIN_AUX_C) |               \
1631         BIT(POWER_DOMAIN_INIT))
1632
1633 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1634         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1635         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1636         BIT(POWER_DOMAIN_AUX_B) |               \
1637         BIT(POWER_DOMAIN_AUX_C) |               \
1638         BIT(POWER_DOMAIN_INIT))
1639
1640 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1641         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1642         BIT(POWER_DOMAIN_AUX_D) |               \
1643         BIT(POWER_DOMAIN_INIT))
1644
1645 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1646         .sync_hw = i9xx_always_on_power_well_noop,
1647         .enable = i9xx_always_on_power_well_noop,
1648         .disable = i9xx_always_on_power_well_noop,
1649         .is_enabled = i9xx_always_on_power_well_enabled,
1650 };
1651
1652 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1653         .sync_hw = chv_pipe_power_well_sync_hw,
1654         .enable = chv_pipe_power_well_enable,
1655         .disable = chv_pipe_power_well_disable,
1656         .is_enabled = chv_pipe_power_well_enabled,
1657 };
1658
1659 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1660         .sync_hw = vlv_power_well_sync_hw,
1661         .enable = chv_dpio_cmn_power_well_enable,
1662         .disable = chv_dpio_cmn_power_well_disable,
1663         .is_enabled = vlv_power_well_enabled,
1664 };
1665
1666 static struct i915_power_well i9xx_always_on_power_well[] = {
1667         {
1668                 .name = "always-on",
1669                 .always_on = 1,
1670                 .domains = POWER_DOMAIN_MASK,
1671                 .ops = &i9xx_always_on_power_well_ops,
1672         },
1673 };
1674
1675 static const struct i915_power_well_ops hsw_power_well_ops = {
1676         .sync_hw = hsw_power_well_sync_hw,
1677         .enable = hsw_power_well_enable,
1678         .disable = hsw_power_well_disable,
1679         .is_enabled = hsw_power_well_enabled,
1680 };
1681
1682 static const struct i915_power_well_ops skl_power_well_ops = {
1683         .sync_hw = skl_power_well_sync_hw,
1684         .enable = skl_power_well_enable,
1685         .disable = skl_power_well_disable,
1686         .is_enabled = skl_power_well_enabled,
1687 };
1688
1689 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1690         .sync_hw = gen9_dc_off_power_well_sync_hw,
1691         .enable = gen9_dc_off_power_well_enable,
1692         .disable = gen9_dc_off_power_well_disable,
1693         .is_enabled = gen9_dc_off_power_well_enabled,
1694 };
1695
1696 static struct i915_power_well hsw_power_wells[] = {
1697         {
1698                 .name = "always-on",
1699                 .always_on = 1,
1700                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1701                 .ops = &i9xx_always_on_power_well_ops,
1702         },
1703         {
1704                 .name = "display",
1705                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1706                 .ops = &hsw_power_well_ops,
1707         },
1708 };
1709
1710 static struct i915_power_well bdw_power_wells[] = {
1711         {
1712                 .name = "always-on",
1713                 .always_on = 1,
1714                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1715                 .ops = &i9xx_always_on_power_well_ops,
1716         },
1717         {
1718                 .name = "display",
1719                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1720                 .ops = &hsw_power_well_ops,
1721         },
1722 };
1723
1724 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1725         .sync_hw = vlv_power_well_sync_hw,
1726         .enable = vlv_display_power_well_enable,
1727         .disable = vlv_display_power_well_disable,
1728         .is_enabled = vlv_power_well_enabled,
1729 };
1730
1731 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1732         .sync_hw = vlv_power_well_sync_hw,
1733         .enable = vlv_dpio_cmn_power_well_enable,
1734         .disable = vlv_dpio_cmn_power_well_disable,
1735         .is_enabled = vlv_power_well_enabled,
1736 };
1737
1738 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1739         .sync_hw = vlv_power_well_sync_hw,
1740         .enable = vlv_power_well_enable,
1741         .disable = vlv_power_well_disable,
1742         .is_enabled = vlv_power_well_enabled,
1743 };
1744
1745 static struct i915_power_well vlv_power_wells[] = {
1746         {
1747                 .name = "always-on",
1748                 .always_on = 1,
1749                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1750                 .ops = &i9xx_always_on_power_well_ops,
1751                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1752         },
1753         {
1754                 .name = "display",
1755                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1756                 .data = PUNIT_POWER_WELL_DISP2D,
1757                 .ops = &vlv_display_power_well_ops,
1758         },
1759         {
1760                 .name = "dpio-tx-b-01",
1761                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1762                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1763                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1764                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1765                 .ops = &vlv_dpio_power_well_ops,
1766                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1767         },
1768         {
1769                 .name = "dpio-tx-b-23",
1770                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1771                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1772                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1773                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1774                 .ops = &vlv_dpio_power_well_ops,
1775                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1776         },
1777         {
1778                 .name = "dpio-tx-c-01",
1779                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1780                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1781                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1782                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1783                 .ops = &vlv_dpio_power_well_ops,
1784                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1785         },
1786         {
1787                 .name = "dpio-tx-c-23",
1788                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1789                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1790                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1791                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1792                 .ops = &vlv_dpio_power_well_ops,
1793                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1794         },
1795         {
1796                 .name = "dpio-common",
1797                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1798                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1799                 .ops = &vlv_dpio_cmn_power_well_ops,
1800         },
1801 };
1802
1803 static struct i915_power_well chv_power_wells[] = {
1804         {
1805                 .name = "always-on",
1806                 .always_on = 1,
1807                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1808                 .ops = &i9xx_always_on_power_well_ops,
1809         },
1810         {
1811                 .name = "display",
1812                 /*
1813                  * Pipe A power well is the new disp2d well. Pipe B and C
1814                  * power wells don't actually exist. Pipe A power well is
1815                  * required for any pipe to work.
1816                  */
1817                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1818                 .data = PIPE_A,
1819                 .ops = &chv_pipe_power_well_ops,
1820         },
1821         {
1822                 .name = "dpio-common-bc",
1823                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1824                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1825                 .ops = &chv_dpio_cmn_power_well_ops,
1826         },
1827         {
1828                 .name = "dpio-common-d",
1829                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1830                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1831                 .ops = &chv_dpio_cmn_power_well_ops,
1832         },
1833 };
1834
1835 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1836                                     int power_well_id)
1837 {
1838         struct i915_power_well *power_well;
1839         bool ret;
1840
1841         power_well = lookup_power_well(dev_priv, power_well_id);
1842         ret = power_well->ops->is_enabled(dev_priv, power_well);
1843
1844         return ret;
1845 }
1846
1847 static struct i915_power_well skl_power_wells[] = {
1848         {
1849                 .name = "always-on",
1850                 .always_on = 1,
1851                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1852                 .ops = &i9xx_always_on_power_well_ops,
1853                 .data = SKL_DISP_PW_ALWAYS_ON,
1854         },
1855         {
1856                 .name = "power well 1",
1857                 /* Handled by the DMC firmware */
1858                 .domains = 0,
1859                 .ops = &skl_power_well_ops,
1860                 .data = SKL_DISP_PW_1,
1861         },
1862         {
1863                 .name = "MISC IO power well",
1864                 /* Handled by the DMC firmware */
1865                 .domains = 0,
1866                 .ops = &skl_power_well_ops,
1867                 .data = SKL_DISP_PW_MISC_IO,
1868         },
1869         {
1870                 .name = "DC off",
1871                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1872                 .ops = &gen9_dc_off_power_well_ops,
1873                 .data = SKL_DISP_PW_DC_OFF,
1874         },
1875         {
1876                 .name = "power well 2",
1877                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1878                 .ops = &skl_power_well_ops,
1879                 .data = SKL_DISP_PW_2,
1880         },
1881         {
1882                 .name = "DDI A/E power well",
1883                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1884                 .ops = &skl_power_well_ops,
1885                 .data = SKL_DISP_PW_DDI_A_E,
1886         },
1887         {
1888                 .name = "DDI B power well",
1889                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1890                 .ops = &skl_power_well_ops,
1891                 .data = SKL_DISP_PW_DDI_B,
1892         },
1893         {
1894                 .name = "DDI C power well",
1895                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1896                 .ops = &skl_power_well_ops,
1897                 .data = SKL_DISP_PW_DDI_C,
1898         },
1899         {
1900                 .name = "DDI D power well",
1901                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1902                 .ops = &skl_power_well_ops,
1903                 .data = SKL_DISP_PW_DDI_D,
1904         },
1905 };
1906
1907 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1908 {
1909         struct i915_power_well *well;
1910
1911         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1912                 return;
1913
1914         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1915         intel_power_well_enable(dev_priv, well);
1916
1917         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1918         intel_power_well_enable(dev_priv, well);
1919 }
1920
1921 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1922 {
1923         struct i915_power_well *well;
1924
1925         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1926                 return;
1927
1928         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1929         intel_power_well_disable(dev_priv, well);
1930
1931         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1932         intel_power_well_disable(dev_priv, well);
1933 }
1934
1935 static struct i915_power_well bxt_power_wells[] = {
1936         {
1937                 .name = "always-on",
1938                 .always_on = 1,
1939                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1940                 .ops = &i9xx_always_on_power_well_ops,
1941         },
1942         {
1943                 .name = "power well 1",
1944                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1945                 .ops = &skl_power_well_ops,
1946                 .data = SKL_DISP_PW_1,
1947         },
1948         {
1949                 .name = "DC off",
1950                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1951                 .ops = &gen9_dc_off_power_well_ops,
1952                 .data = SKL_DISP_PW_DC_OFF,
1953         },
1954         {
1955                 .name = "power well 2",
1956                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1957                 .ops = &skl_power_well_ops,
1958                 .data = SKL_DISP_PW_2,
1959         },
1960 };
1961
1962 static int
1963 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1964                                    int disable_power_well)
1965 {
1966         if (disable_power_well >= 0)
1967                 return !!disable_power_well;
1968
1969         if (IS_BROXTON(dev_priv)) {
1970                 DRM_DEBUG_KMS("Disabling display power well support\n");
1971                 return 0;
1972         }
1973
1974         return 1;
1975 }
1976
1977 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
1978                                     int enable_dc)
1979 {
1980         uint32_t mask;
1981         int requested_dc;
1982         int max_dc;
1983
1984         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1985                 max_dc = 2;
1986                 mask = 0;
1987         } else if (IS_BROXTON(dev_priv)) {
1988                 max_dc = 1;
1989                 /*
1990                  * DC9 has a separate HW flow from the rest of the DC states,
1991                  * not depending on the DMC firmware. It's needed by system
1992                  * suspend/resume, so allow it unconditionally.
1993                  */
1994                 mask = DC_STATE_EN_DC9;
1995         } else {
1996                 max_dc = 0;
1997                 mask = 0;
1998         }
1999
2000         if (!i915.disable_power_well)
2001                 max_dc = 0;
2002
2003         if (enable_dc >= 0 && enable_dc <= max_dc) {
2004                 requested_dc = enable_dc;
2005         } else if (enable_dc == -1) {
2006                 requested_dc = max_dc;
2007         } else if (enable_dc > max_dc && enable_dc <= 2) {
2008                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2009                               enable_dc, max_dc);
2010                 requested_dc = max_dc;
2011         } else {
2012                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2013                 requested_dc = max_dc;
2014         }
2015
2016         if (requested_dc > 1)
2017                 mask |= DC_STATE_EN_UPTO_DC6;
2018         if (requested_dc > 0)
2019                 mask |= DC_STATE_EN_UPTO_DC5;
2020
2021         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2022
2023         return mask;
2024 }
2025
2026 #define set_power_wells(power_domains, __power_wells) ({                \
2027         (power_domains)->power_wells = (__power_wells);                 \
2028         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2029 })
2030
2031 /**
2032  * intel_power_domains_init - initializes the power domain structures
2033  * @dev_priv: i915 device instance
2034  *
2035  * Initializes the power domain structures for @dev_priv depending upon the
2036  * supported platform.
2037  */
2038 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2039 {
2040         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2041
2042         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2043                                                      i915.disable_power_well);
2044         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2045                                                             i915.enable_dc);
2046
2047         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2048
2049         mutex_init(&power_domains->lock);
2050
2051         /*
2052          * The enabling order will be from lower to higher indexed wells,
2053          * the disabling order is reversed.
2054          */
2055         if (IS_HASWELL(dev_priv)) {
2056                 set_power_wells(power_domains, hsw_power_wells);
2057         } else if (IS_BROADWELL(dev_priv)) {
2058                 set_power_wells(power_domains, bdw_power_wells);
2059         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2060                 set_power_wells(power_domains, skl_power_wells);
2061         } else if (IS_BROXTON(dev_priv)) {
2062                 set_power_wells(power_domains, bxt_power_wells);
2063         } else if (IS_CHERRYVIEW(dev_priv)) {
2064                 set_power_wells(power_domains, chv_power_wells);
2065         } else if (IS_VALLEYVIEW(dev_priv)) {
2066                 set_power_wells(power_domains, vlv_power_wells);
2067         } else {
2068                 set_power_wells(power_domains, i9xx_always_on_power_well);
2069         }
2070
2071         return 0;
2072 }
2073
2074 /**
2075  * intel_power_domains_fini - finalizes the power domain structures
2076  * @dev_priv: i915 device instance
2077  *
2078  * Finalizes the power domain structures for @dev_priv depending upon the
2079  * supported platform. This function also disables runtime pm and ensures that
2080  * the device stays powered up so that the driver can be reloaded.
2081  */
2082 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2083 {
2084         struct device *device = &dev_priv->dev->pdev->dev;
2085
2086         /*
2087          * The i915.ko module is still not prepared to be loaded when
2088          * the power well is not enabled, so just enable it in case
2089          * we're going to unload/reload.
2090          * The following also reacquires the RPM reference the core passed
2091          * to the driver during loading, which is dropped in
2092          * intel_runtime_pm_enable(). We have to hand back the control of the
2093          * device to the core with this reference held.
2094          */
2095         intel_display_set_init_power(dev_priv, true);
2096
2097         /* Remove the refcount we took to keep power well support disabled. */
2098         if (!i915.disable_power_well)
2099                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2100
2101         /*
2102          * Remove the refcount we took in intel_runtime_pm_enable() in case
2103          * the platform doesn't support runtime PM.
2104          */
2105         if (!HAS_RUNTIME_PM(dev_priv))
2106                 pm_runtime_put(device);
2107 }
2108
2109 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2110 {
2111         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2112         struct i915_power_well *power_well;
2113         int i;
2114
2115         mutex_lock(&power_domains->lock);
2116         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2117                 power_well->ops->sync_hw(dev_priv, power_well);
2118                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2119                                                                      power_well);
2120         }
2121         mutex_unlock(&power_domains->lock);
2122 }
2123
2124 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2125                                   bool resume)
2126 {
2127         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2128         uint32_t val;
2129
2130         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2131
2132         /* enable PCH reset handshake */
2133         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2134         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2135
2136         /* enable PG1 and Misc I/O */
2137         mutex_lock(&power_domains->lock);
2138         skl_pw1_misc_io_init(dev_priv);
2139         mutex_unlock(&power_domains->lock);
2140
2141         if (!resume)
2142                 return;
2143
2144         skl_init_cdclk(dev_priv);
2145
2146         if (dev_priv->csr.dmc_payload)
2147                 intel_csr_load_program(dev_priv);
2148 }
2149
2150 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2151 {
2152         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2153
2154         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2155
2156         skl_uninit_cdclk(dev_priv);
2157
2158         /* The spec doesn't call for removing the reset handshake flag */
2159         /* disable PG1 and Misc I/O */
2160         mutex_lock(&power_domains->lock);
2161         skl_pw1_misc_io_fini(dev_priv);
2162         mutex_unlock(&power_domains->lock);
2163 }
2164
2165 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2166 {
2167         struct i915_power_well *cmn_bc =
2168                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2169         struct i915_power_well *cmn_d =
2170                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2171
2172         /*
2173          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2174          * workaround never ever read DISPLAY_PHY_CONTROL, and
2175          * instead maintain a shadow copy ourselves. Use the actual
2176          * power well state and lane status to reconstruct the
2177          * expected initial value.
2178          */
2179         dev_priv->chv_phy_control =
2180                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2181                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2182                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2183                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2184                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2185
2186         /*
2187          * If all lanes are disabled we leave the override disabled
2188          * with all power down bits cleared to match the state we
2189          * would use after disabling the port. Otherwise enable the
2190          * override and set the lane powerdown bits accding to the
2191          * current lane status.
2192          */
2193         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2194                 uint32_t status = I915_READ(DPLL(PIPE_A));
2195                 unsigned int mask;
2196
2197                 mask = status & DPLL_PORTB_READY_MASK;
2198                 if (mask == 0xf)
2199                         mask = 0x0;
2200                 else
2201                         dev_priv->chv_phy_control |=
2202                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2203
2204                 dev_priv->chv_phy_control |=
2205                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2206
2207                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2208                 if (mask == 0xf)
2209                         mask = 0x0;
2210                 else
2211                         dev_priv->chv_phy_control |=
2212                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2213
2214                 dev_priv->chv_phy_control |=
2215                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2216
2217                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2218
2219                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2220         } else {
2221                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2222         }
2223
2224         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2225                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2226                 unsigned int mask;
2227
2228                 mask = status & DPLL_PORTD_READY_MASK;
2229
2230                 if (mask == 0xf)
2231                         mask = 0x0;
2232                 else
2233                         dev_priv->chv_phy_control |=
2234                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2235
2236                 dev_priv->chv_phy_control |=
2237                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2238
2239                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2240
2241                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2242         } else {
2243                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2244         }
2245
2246         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2247
2248         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2249                       dev_priv->chv_phy_control);
2250 }
2251
2252 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2253 {
2254         struct i915_power_well *cmn =
2255                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2256         struct i915_power_well *disp2d =
2257                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2258
2259         /* If the display might be already active skip this */
2260         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2261             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2262             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2263                 return;
2264
2265         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2266
2267         /* cmnlane needs DPLL registers */
2268         disp2d->ops->enable(dev_priv, disp2d);
2269
2270         /*
2271          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2272          * Need to assert and de-assert PHY SB reset by gating the
2273          * common lane power, then un-gating it.
2274          * Simply ungating isn't enough to reset the PHY enough to get
2275          * ports and lanes running.
2276          */
2277         cmn->ops->disable(dev_priv, cmn);
2278 }
2279
2280 /**
2281  * intel_power_domains_init_hw - initialize hardware power domain state
2282  * @dev_priv: i915 device instance
2283  *
2284  * This function initializes the hardware power domain state and enables all
2285  * power domains using intel_display_set_init_power().
2286  */
2287 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2288 {
2289         struct drm_device *dev = dev_priv->dev;
2290         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2291
2292         power_domains->initializing = true;
2293
2294         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2295                 skl_display_core_init(dev_priv, resume);
2296         } else if (IS_CHERRYVIEW(dev)) {
2297                 mutex_lock(&power_domains->lock);
2298                 chv_phy_control_init(dev_priv);
2299                 mutex_unlock(&power_domains->lock);
2300         } else if (IS_VALLEYVIEW(dev)) {
2301                 mutex_lock(&power_domains->lock);
2302                 vlv_cmnlane_wa(dev_priv);
2303                 mutex_unlock(&power_domains->lock);
2304         }
2305
2306         /* For now, we need the power well to be always enabled. */
2307         intel_display_set_init_power(dev_priv, true);
2308         /* Disable power support if the user asked so. */
2309         if (!i915.disable_power_well)
2310                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2311         intel_power_domains_sync_hw(dev_priv);
2312         power_domains->initializing = false;
2313 }
2314
2315 /**
2316  * intel_power_domains_suspend - suspend power domain state
2317  * @dev_priv: i915 device instance
2318  *
2319  * This function prepares the hardware power domain state before entering
2320  * system suspend. It must be paired with intel_power_domains_init_hw().
2321  */
2322 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2323 {
2324         /*
2325          * Even if power well support was disabled we still want to disable
2326          * power wells while we are system suspended.
2327          */
2328         if (!i915.disable_power_well)
2329                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2330
2331         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2332                 skl_display_core_uninit(dev_priv);
2333 }
2334
2335 /**
2336  * intel_runtime_pm_get - grab a runtime pm reference
2337  * @dev_priv: i915 device instance
2338  *
2339  * This function grabs a device-level runtime pm reference (mostly used for GEM
2340  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2341  *
2342  * Any runtime pm reference obtained by this function must have a symmetric
2343  * call to intel_runtime_pm_put() to release the reference again.
2344  */
2345 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2346 {
2347         struct drm_device *dev = dev_priv->dev;
2348         struct device *device = &dev->pdev->dev;
2349
2350         pm_runtime_get_sync(device);
2351
2352         atomic_inc(&dev_priv->pm.wakeref_count);
2353         assert_rpm_wakelock_held(dev_priv);
2354 }
2355
2356 /**
2357  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2358  * @dev_priv: i915 device instance
2359  *
2360  * This function grabs a device-level runtime pm reference if the device is
2361  * already in use and ensures that it is powered up.
2362  *
2363  * Any runtime pm reference obtained by this function must have a symmetric
2364  * call to intel_runtime_pm_put() to release the reference again.
2365  */
2366 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2367 {
2368         struct drm_device *dev = dev_priv->dev;
2369         struct device *device = &dev->pdev->dev;
2370
2371         if (IS_ENABLED(CONFIG_PM)) {
2372                 int ret = pm_runtime_get_if_in_use(device);
2373
2374                 /*
2375                  * In cases runtime PM is disabled by the RPM core and we get
2376                  * an -EINVAL return value we are not supposed to call this
2377                  * function, since the power state is undefined. This applies
2378                  * atm to the late/early system suspend/resume handlers.
2379                  */
2380                 WARN_ON_ONCE(ret < 0);
2381                 if (ret <= 0)
2382                         return false;
2383         }
2384
2385         atomic_inc(&dev_priv->pm.wakeref_count);
2386         assert_rpm_wakelock_held(dev_priv);
2387
2388         return true;
2389 }
2390
2391 /**
2392  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2393  * @dev_priv: i915 device instance
2394  *
2395  * This function grabs a device-level runtime pm reference (mostly used for GEM
2396  * code to ensure the GTT or GT is on).
2397  *
2398  * It will _not_ power up the device but instead only check that it's powered
2399  * on.  Therefore it is only valid to call this functions from contexts where
2400  * the device is known to be powered up and where trying to power it up would
2401  * result in hilarity and deadlocks. That pretty much means only the system
2402  * suspend/resume code where this is used to grab runtime pm references for
2403  * delayed setup down in work items.
2404  *
2405  * Any runtime pm reference obtained by this function must have a symmetric
2406  * call to intel_runtime_pm_put() to release the reference again.
2407  */
2408 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2409 {
2410         struct drm_device *dev = dev_priv->dev;
2411         struct device *device = &dev->pdev->dev;
2412
2413         assert_rpm_wakelock_held(dev_priv);
2414         pm_runtime_get_noresume(device);
2415
2416         atomic_inc(&dev_priv->pm.wakeref_count);
2417 }
2418
2419 /**
2420  * intel_runtime_pm_put - release a runtime pm reference
2421  * @dev_priv: i915 device instance
2422  *
2423  * This function drops the device-level runtime pm reference obtained by
2424  * intel_runtime_pm_get() and might power down the corresponding
2425  * hardware block right away if this is the last reference.
2426  */
2427 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2428 {
2429         struct drm_device *dev = dev_priv->dev;
2430         struct device *device = &dev->pdev->dev;
2431
2432         assert_rpm_wakelock_held(dev_priv);
2433         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2434                 atomic_inc(&dev_priv->pm.atomic_seq);
2435
2436         pm_runtime_mark_last_busy(device);
2437         pm_runtime_put_autosuspend(device);
2438 }
2439
2440 /**
2441  * intel_runtime_pm_enable - enable runtime pm
2442  * @dev_priv: i915 device instance
2443  *
2444  * This function enables runtime pm at the end of the driver load sequence.
2445  *
2446  * Note that this function does currently not enable runtime pm for the
2447  * subordinate display power domains. That is only done on the first modeset
2448  * using intel_display_set_init_power().
2449  */
2450 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2451 {
2452         struct drm_device *dev = dev_priv->dev;
2453         struct device *device = &dev->pdev->dev;
2454
2455         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2456         pm_runtime_mark_last_busy(device);
2457
2458         /*
2459          * Take a permanent reference to disable the RPM functionality and drop
2460          * it only when unloading the driver. Use the low level get/put helpers,
2461          * so the driver's own RPM reference tracking asserts also work on
2462          * platforms without RPM support.
2463          */
2464         if (!HAS_RUNTIME_PM(dev)) {
2465                 pm_runtime_dont_use_autosuspend(device);
2466                 pm_runtime_get_sync(device);
2467         } else {
2468                 pm_runtime_use_autosuspend(device);
2469         }
2470
2471         /*
2472          * The core calls the driver load handler with an RPM reference held.
2473          * We drop that here and will reacquire it during unloading in
2474          * intel_power_domains_fini().
2475          */
2476         pm_runtime_put_autosuspend(device);
2477 }
2478