drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <[email protected]>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <trace/events/power.h>
  28
  29 #include <asm/div64.h>
  30 #include <asm/msr.h>
  31 #include <asm/cpu_device_id.h>
  32 #include <asm/cpufeature.h>
  33 #include <asm/intel-family.h>
  34
  35 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  36
  37 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  38 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  39
  40 #ifdef CONFIG_ACPI
  41 #include <acpi/processor.h>
  42 #include <acpi/cppc_acpi.h>
  43 #endif
  44
  45 #define FRAC_BITS 8
  46 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  47 #define fp_toint(X) ((X) >> FRAC_BITS)
  48
  49 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  50
  51 #define EXT_BITS 6
  52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline int32_t percent_fp(int percent)
  78 {
  79         return div_fp(percent, 100);
  80 }
  81
  82 static inline u64 mul_ext_fp(u64 x, u64 y)
  83 {
  84         return (x * y) >> EXT_FRAC_BITS;
  85 }
  86
  87 static inline u64 div_ext_fp(u64 x, u64 y)
  88 {
  89         return div64_u64(x << EXT_FRAC_BITS, y);
  90 }
  91
  92 static inline int32_t percent_ext_fp(int percent)
  93 {
  94         return div_ext_fp(percent, 100);
  95 }
  96
  97 /**
  98  * struct sample -      Store performance sample
  99  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 100  *                      performance during last sample period
 101  * @busy_scaled:        Scaled busy value which is used to calculate next
 102  *                      P state. This can be different than core_avg_perf
 103  *                      to account for cpu idle period
 104  * @aperf:              Difference of actual performance frequency clock count
 105  *                      read from APERF MSR between last and current sample
 106  * @mperf:              Difference of maximum performance frequency clock count
 107  *                      read from MPERF MSR between last and current sample
 108  * @tsc:                Difference of time stamp counter between last and
 109  *                      current sample
 110  * @time:               Current time from scheduler
 111  *
 112  * This structure is used in the cpudata structure to store performance sample
 113  * data for choosing next P State.
 114  */
 115 struct sample {
 116         int32_t core_avg_perf;
 117         int32_t busy_scaled;
 118         u64 aperf;
 119         u64 mperf;
 120         u64 tsc;
 121         u64 time;
 122 };
 123
 124 /**
 125  * struct pstate_data - Store P state data
 126  * @current_pstate:     Current requested P state
 127  * @min_pstate:         Min P state possible for this platform
 128  * @max_pstate:         Max P state possible for this platform
 129  * @max_pstate_physical:This is physical Max P state for a processor
 130  *                      This can be higher than the max_pstate which can
 131  *                      be limited by platform thermal design power limits
 132  * @scaling:            Scaling factor to  convert frequency to cpufreq
 133  *                      frequency units
 134  * @turbo_pstate:       Max Turbo P state possible for this platform
 135  * @max_freq:           @max_pstate frequency in cpufreq units
 136  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 137  *
 138  * Stores the per cpu model P state limits and current P state.
 139  */
 140 struct pstate_data {
 141         int     current_pstate;
 142         int     min_pstate;
 143         int     max_pstate;
 144         int     max_pstate_physical;
 145         int     scaling;
 146         int     turbo_pstate;
 147         unsigned int max_freq;
 148         unsigned int turbo_freq;
 149 };
 150
 151 /**
 152  * struct vid_data -    Stores voltage information data
 153  * @min:                VID data for this platform corresponding to
 154  *                      the lowest P state
 155  * @max:                VID data corresponding to the highest P State.
 156  * @turbo:              VID data for turbo P state
 157  * @ratio:              Ratio of (vid max - vid min) /
 158  *                      (max P state - Min P State)
 159  *
 160  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 161  * This data is used in Atom platforms, where in addition to target P state,
 162  * the voltage data needs to be specified to select next P State.
 163  */
 164 struct vid_data {
 165         int min;
 166         int max;
 167         int turbo;
 168         int32_t ratio;
 169 };
 170
 171 /**
 172  * struct global_params - Global parameters, mostly tunable via sysfs.
 173  * @no_turbo:           Whether or not to use turbo P-states.
 174  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
 175  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 176  *                      not the maximum reported turbo P-state is different from
 177  *                      the maximum reported non-turbo one.
 178  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 179  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 180  *                      P-state capacity.
 181  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 182  *                      P-state capacity.
 183  */
 184 struct global_params {
 185         bool no_turbo;
 186         bool turbo_disabled;
 187         bool turbo_disabled_mf;
 188         int max_perf_pct;
 189         int min_perf_pct;
 190 };
 191
 192 /**
 193  * struct cpudata -     Per CPU instance data storage
 194  * @cpu:                CPU number for this instance data
 195  * @policy:             CPUFreq policy value
 196  * @update_util:        CPUFreq utility callback information
 197  * @update_util_set:    CPUFreq utility callback is set
 198  * @iowait_boost:       iowait-related boost fraction
 199  * @last_update:        Time of the last update.
 200  * @pstate:             Stores P state limits for this CPU
 201  * @vid:                Stores VID limits for this CPU
 202  * @last_sample_time:   Last Sample time
 203  * @aperf_mperf_shift:  Number of clock cycles after aperf, merf is incremented
 204  *                      This shift is a multiplier to mperf delta to
 205  *                      calculate CPU busy.
 206  * @prev_aperf:         Last APERF value read from APERF MSR
 207  * @prev_mperf:         Last MPERF value read from MPERF MSR
 208  * @prev_tsc:           Last timestamp counter (TSC) value
 209  * @prev_cummulative_iowait: IO Wait time difference from last and
 210  *                      current sample
 211  * @sample:             Storage for storing last Sample data
 212  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 213  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 214  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 215  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 216  * @epp_powersave:      Last saved HWP energy performance preference
 217  *                      (EPP) or energy performance bias (EPB),
 218  *                      when policy switched to performance
 219  * @epp_policy:         Last saved policy used to set EPP/EPB
 220  * @epp_default:        Power on default HWP energy performance
 221  *                      preference/bias
 222  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 223  *                      operation
 224  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 225  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 226  * @last_io_update:     Last time when IO wake flag was set
 227  * @sched_flags:        Store scheduler flags for possible cross CPU update
 228  * @hwp_boost_min:      Last HWP boosted min performance
 229  *
 230  * This structure stores per CPU instance data for all CPUs.
 231  */
 232 struct cpudata {
 233         int cpu;
 234
 235         unsigned int policy;
 236         struct update_util_data update_util;
 237         bool   update_util_set;
 238
 239         struct pstate_data pstate;
 240         struct vid_data vid;
 241
 242         u64     last_update;
 243         u64     last_sample_time;
 244         u64     aperf_mperf_shift;
 245         u64     prev_aperf;
 246         u64     prev_mperf;
 247         u64     prev_tsc;
 248         u64     prev_cummulative_iowait;
 249         struct sample sample;
 250         int32_t min_perf_ratio;
 251         int32_t max_perf_ratio;
 252 #ifdef CONFIG_ACPI
 253         struct acpi_processor_performance acpi_perf_data;
 254         bool valid_pss_table;
 255 #endif
 256         unsigned int iowait_boost;
 257         s16 epp_powersave;
 258         s16 epp_policy;
 259         s16 epp_default;
 260         s16 epp_saved;
 261         u64 hwp_req_cached;
 262         u64 hwp_cap_cached;
 263         u64 last_io_update;
 264         unsigned int sched_flags;
 265         u32 hwp_boost_min;
 266 };
 267
 268 static struct cpudata **all_cpu_data;
 269
 270 /**
 271  * struct pstate_funcs - Per CPU model specific callbacks
 272  * @get_max:            Callback to get maximum non turbo effective P state
 273  * @get_max_physical:   Callback to get maximum non turbo physical P state
 274  * @get_min:            Callback to get minimum P state
 275  * @get_turbo:          Callback to get turbo P state
 276  * @get_scaling:        Callback to get frequency scaling factor
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(void);
 285         int (*get_max_physical)(void);
 286         int (*get_min)(void);
 287         int (*get_turbo)(void);
 288         int (*get_scaling)(void);
 289         int (*get_aperf_mperf_shift)(void);
 290         u64 (*get_val)(struct cpudata*, int pstate);
 291         void (*get_vid)(struct cpudata *);
 292 };
 293
 294 static struct pstate_funcs pstate_funcs __read_mostly;
 295
 296 static int hwp_active __read_mostly;
 297 static int hwp_mode_bdw __read_mostly;
 298 static bool per_cpu_limits __read_mostly;
 299 static bool hwp_boost __read_mostly;
 300
 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 302
 303 #ifdef CONFIG_ACPI
 304 static bool acpi_ppc;
 305 #endif
 306
 307 static struct global_params global;
 308
 309 static DEFINE_MUTEX(intel_pstate_driver_lock);
 310 static DEFINE_MUTEX(intel_pstate_limits_lock);
 311
 312 #ifdef CONFIG_ACPI
 313
 314 static bool intel_pstate_acpi_pm_profile_server(void)
 315 {
 316         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 317             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 318                 return true;
 319
 320         return false;
 321 }
 322
 323 static bool intel_pstate_get_ppc_enable_status(void)
 324 {
 325         if (intel_pstate_acpi_pm_profile_server())
 326                 return true;
 327
 328         return acpi_ppc;
 329 }
 330
 331 #ifdef CONFIG_ACPI_CPPC_LIB
 332
 333 /* The work item is needed to avoid CPU hotplug locking issues */
 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 335 {
 336         sched_set_itmt_support();
 337 }
 338
 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 340
 341 static void intel_pstate_set_itmt_prio(int cpu)
 342 {
 343         struct cppc_perf_caps cppc_perf;
 344         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 345         int ret;
 346
 347         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 348         if (ret)
 349                 return;
 350
 351         /*
 352          * The priorities can be set regardless of whether or not
 353          * sched_set_itmt_support(true) has been called and it is valid to
 354          * update them at any time after it has been called.
 355          */
 356         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 357
 358         if (max_highest_perf <= min_highest_perf) {
 359                 if (cppc_perf.highest_perf > max_highest_perf)
 360                         max_highest_perf = cppc_perf.highest_perf;
 361
 362                 if (cppc_perf.highest_perf < min_highest_perf)
 363                         min_highest_perf = cppc_perf.highest_perf;
 364
 365                 if (max_highest_perf > min_highest_perf) {
 366                         /*
 367                          * This code can be run during CPU online under the
 368                          * CPU hotplug locks, so sched_set_itmt_support()
 369                          * cannot be called from here.  Queue up a work item
 370                          * to invoke it.
 371                          */
 372                         schedule_work(&sched_itmt_work);
 373                 }
 374         }
 375 }
 376
 377 static int intel_pstate_get_cppc_guranteed(int cpu)
 378 {
 379         struct cppc_perf_caps cppc_perf;
 380         int ret;
 381
 382         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 383         if (ret)
 384                 return ret;
 385
 386         if (cppc_perf.guaranteed_perf)
 387                 return cppc_perf.guaranteed_perf;
 388
 389         return cppc_perf.nominal_perf;
 390 }
 391
 392 #else /* CONFIG_ACPI_CPPC_LIB */
 393 static void intel_pstate_set_itmt_prio(int cpu)
 394 {
 395 }
 396 #endif /* CONFIG_ACPI_CPPC_LIB */
 397
 398 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 399 {
 400         struct cpudata *cpu;
 401         int ret;
 402         int i;
 403
 404         if (hwp_active) {
 405                 intel_pstate_set_itmt_prio(policy->cpu);
 406                 return;
 407         }
 408
 409         if (!intel_pstate_get_ppc_enable_status())
 410                 return;
 411
 412         cpu = all_cpu_data[policy->cpu];
 413
 414         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 415                                                   policy->cpu);
 416         if (ret)
 417                 return;
 418
 419         /*
 420          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 421          * guarantee that the states returned by it map to the states in our
 422          * list directly.
 423          */
 424         if (cpu->acpi_perf_data.control_register.space_id !=
 425                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 426                 goto err;
 427
 428         /*
 429          * If there is only one entry _PSS, simply ignore _PSS and continue as
 430          * usual without taking _PSS into account
 431          */
 432         if (cpu->acpi_perf_data.state_count < 2)
 433                 goto err;
 434
 435         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 436         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 437                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 438                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 439                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 440                          (u32) cpu->acpi_perf_data.states[i].power,
 441                          (u32) cpu->acpi_perf_data.states[i].control);
 442         }
 443
 444         /*
 445          * The _PSS table doesn't contain whole turbo frequency range.
 446          * This just contains +1 MHZ above the max non turbo frequency,
 447          * with control value corresponding to max turbo ratio. But
 448          * when cpufreq set policy is called, it will call with this
 449          * max frequency, which will cause a reduced performance as
 450          * this driver uses real max turbo frequency as the max
 451          * frequency. So correct this frequency in _PSS table to
 452          * correct max turbo frequency based on the turbo state.
 453          * Also need to convert to MHz as _PSS freq is in MHz.
 454          */
 455         if (!global.turbo_disabled)
 456                 cpu->acpi_perf_data.states[0].core_frequency =
 457                                         policy->cpuinfo.max_freq / 1000;
 458         cpu->valid_pss_table = true;
 459         pr_debug("_PPC limits will be enforced\n");
 460
 461         return;
 462
 463  err:
 464         cpu->valid_pss_table = false;
 465         acpi_processor_unregister_performance(policy->cpu);
 466 }
 467
 468 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 469 {
 470         struct cpudata *cpu;
 471
 472         cpu = all_cpu_data[policy->cpu];
 473         if (!cpu->valid_pss_table)
 474                 return;
 475
 476         acpi_processor_unregister_performance(policy->cpu);
 477 }
 478 #else /* CONFIG_ACPI */
 479 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 480 {
 481 }
 482
 483 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 484 {
 485 }
 486
 487 static inline bool intel_pstate_acpi_pm_profile_server(void)
 488 {
 489         return false;
 490 }
 491 #endif /* CONFIG_ACPI */
 492
 493 #ifndef CONFIG_ACPI_CPPC_LIB
 494 static int intel_pstate_get_cppc_guranteed(int cpu)
 495 {
 496         return -ENOTSUPP;
 497 }
 498 #endif /* CONFIG_ACPI_CPPC_LIB */
 499
 500 static inline void update_turbo_state(void)
 501 {
 502         u64 misc_en;
 503         struct cpudata *cpu;
 504
 505         cpu = all_cpu_data[0];
 506         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 507         global.turbo_disabled =
 508                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 509                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 510 }
 511
 512 static int min_perf_pct_min(void)
 513 {
 514         struct cpudata *cpu = all_cpu_data[0];
 515         int turbo_pstate = cpu->pstate.turbo_pstate;
 516
 517         return turbo_pstate ?
 518                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 519 }
 520
 521 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 522 {
 523         u64 epb;
 524         int ret;
 525
 526         if (!boot_cpu_has(X86_FEATURE_EPB))
 527                 return -ENXIO;
 528
 529         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 530         if (ret)
 531                 return (s16)ret;
 532
 533         return (s16)(epb & 0x0f);
 534 }
 535
 536 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 537 {
 538         s16 epp;
 539
 540         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 541                 /*
 542                  * When hwp_req_data is 0, means that caller didn't read
 543                  * MSR_HWP_REQUEST, so need to read and get EPP.
 544                  */
 545                 if (!hwp_req_data) {
 546                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 547                                             &hwp_req_data);
 548                         if (epp)
 549                                 return epp;
 550                 }
 551                 epp = (hwp_req_data >> 24) & 0xff;
 552         } else {
 553                 /* When there is no EPP present, HWP uses EPB settings */
 554                 epp = intel_pstate_get_epb(cpu_data);
 555         }
 556
 557         return epp;
 558 }
 559
 560 static int intel_pstate_set_epb(int cpu, s16 pref)
 561 {
 562         u64 epb;
 563         int ret;
 564
 565         if (!boot_cpu_has(X86_FEATURE_EPB))
 566                 return -ENXIO;
 567
 568         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 569         if (ret)
 570                 return ret;
 571
 572         epb = (epb & ~0x0f) | pref;
 573         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * EPP/EPB display strings corresponding to EPP index in the
 580  * energy_perf_strings[]
 581  *      index           String
 582  *-------------------------------------
 583  *      0               default
 584  *      1               performance
 585  *      2               balance_performance
 586  *      3               balance_power
 587  *      4               power
 588  */
 589 static const char * const energy_perf_strings[] = {
 590         "default",
 591         "performance",
 592         "balance_performance",
 593         "balance_power",
 594         "power",
 595         NULL
 596 };
 597 static const unsigned int epp_values[] = {
 598         HWP_EPP_PERFORMANCE,
 599         HWP_EPP_BALANCE_PERFORMANCE,
 600         HWP_EPP_BALANCE_POWERSAVE,
 601         HWP_EPP_POWERSAVE
 602 };
 603
 604 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 605 {
 606         s16 epp;
 607         int index = -EINVAL;
 608
 609         epp = intel_pstate_get_epp(cpu_data, 0);
 610         if (epp < 0)
 611                 return epp;
 612
 613         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 614                 if (epp == HWP_EPP_PERFORMANCE)
 615                         return 1;
 616                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
 617                         return 2;
 618                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
 619                         return 3;
 620                 else
 621                         return 4;
 622         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 623                 /*
 624                  * Range:
 625                  *      0x00-0x03       :       Performance
 626                  *      0x04-0x07       :       Balance performance
 627                  *      0x08-0x0B       :       Balance power
 628                  *      0x0C-0x0F       :       Power
 629                  * The EPB is a 4 bit value, but our ranges restrict the
 630                  * value which can be set. Here only using top two bits
 631                  * effectively.
 632                  */
 633                 index = (epp >> 2) + 1;
 634         }
 635
 636         return index;
 637 }
 638
 639 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 640                                               int pref_index)
 641 {
 642         int epp = -EINVAL;
 643         int ret;
 644
 645         if (!pref_index)
 646                 epp = cpu_data->epp_default;
 647
 648         mutex_lock(&intel_pstate_limits_lock);
 649
 650         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 651                 u64 value;
 652
 653                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 654                 if (ret)
 655                         goto return_pref;
 656
 657                 value &= ~GENMASK_ULL(31, 24);
 658
 659                 if (epp == -EINVAL)
 660                         epp = epp_values[pref_index - 1];
 661
 662                 value |= (u64)epp << 24;
 663                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 664         } else {
 665                 if (epp == -EINVAL)
 666                         epp = (pref_index - 1) << 2;
 667                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 668         }
 669 return_pref:
 670         mutex_unlock(&intel_pstate_limits_lock);
 671
 672         return ret;
 673 }
 674
 675 static ssize_t show_energy_performance_available_preferences(
 676                                 struct cpufreq_policy *policy, char *buf)
 677 {
 678         int i = 0;
 679         int ret = 0;
 680
 681         while (energy_perf_strings[i] != NULL)
 682                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 683
 684         ret += sprintf(&buf[ret], "\n");
 685
 686         return ret;
 687 }
 688
 689 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 690
 691 static ssize_t store_energy_performance_preference(
 692                 struct cpufreq_policy *policy, const char *buf, size_t count)
 693 {
 694         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 695         char str_preference[21];
 696         int ret;
 697
 698         ret = sscanf(buf, "%20s", str_preference);
 699         if (ret != 1)
 700                 return -EINVAL;
 701
 702         ret = match_string(energy_perf_strings, -1, str_preference);
 703         if (ret < 0)
 704                 return ret;
 705
 706         intel_pstate_set_energy_pref_index(cpu_data, ret);
 707         return count;
 708 }
 709
 710 static ssize_t show_energy_performance_preference(
 711                                 struct cpufreq_policy *policy, char *buf)
 712 {
 713         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 714         int preference;
 715
 716         preference = intel_pstate_get_energy_pref_index(cpu_data);
 717         if (preference < 0)
 718                 return preference;
 719
 720         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 721 }
 722
 723 cpufreq_freq_attr_rw(energy_performance_preference);
 724
 725 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 726 {
 727         struct cpudata *cpu;
 728         u64 cap;
 729         int ratio;
 730
 731         ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
 732         if (ratio <= 0) {
 733                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 734                 ratio = HWP_GUARANTEED_PERF(cap);
 735         }
 736
 737         cpu = all_cpu_data[policy->cpu];
 738
 739         return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
 740 }
 741
 742 cpufreq_freq_attr_ro(base_frequency);
 743
 744 static struct freq_attr *hwp_cpufreq_attrs[] = {
 745         &energy_performance_preference,
 746         &energy_performance_available_preferences,
 747         &base_frequency,
 748         NULL,
 749 };
 750
 751 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
 752                                      int *current_max)
 753 {
 754         u64 cap;
 755
 756         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 757         WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
 758         if (global.no_turbo)
 759                 *current_max = HWP_GUARANTEED_PERF(cap);
 760         else
 761                 *current_max = HWP_HIGHEST_PERF(cap);
 762
 763         *phy_max = HWP_HIGHEST_PERF(cap);
 764 }
 765
 766 static void intel_pstate_hwp_set(unsigned int cpu)
 767 {
 768         struct cpudata *cpu_data = all_cpu_data[cpu];
 769         int max, min;
 770         u64 value;
 771         s16 epp;
 772
 773         max = cpu_data->max_perf_ratio;
 774         min = cpu_data->min_perf_ratio;
 775
 776         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 777                 min = max;
 778
 779         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 780
 781         value &= ~HWP_MIN_PERF(~0L);
 782         value |= HWP_MIN_PERF(min);
 783
 784         value &= ~HWP_MAX_PERF(~0L);
 785         value |= HWP_MAX_PERF(max);
 786
 787         if (cpu_data->epp_policy == cpu_data->policy)
 788                 goto skip_epp;
 789
 790         cpu_data->epp_policy = cpu_data->policy;
 791
 792         if (cpu_data->epp_saved >= 0) {
 793                 epp = cpu_data->epp_saved;
 794                 cpu_data->epp_saved = -EINVAL;
 795                 goto update_epp;
 796         }
 797
 798         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 799                 epp = intel_pstate_get_epp(cpu_data, value);
 800                 cpu_data->epp_powersave = epp;
 801                 /* If EPP read was failed, then don't try to write */
 802                 if (epp < 0)
 803                         goto skip_epp;
 804
 805                 epp = 0;
 806         } else {
 807                 /* skip setting EPP, when saved value is invalid */
 808                 if (cpu_data->epp_powersave < 0)
 809                         goto skip_epp;
 810
 811                 /*
 812                  * No need to restore EPP when it is not zero. This
 813                  * means:
 814                  *  - Policy is not changed
 815                  *  - user has manually changed
 816                  *  - Error reading EPB
 817                  */
 818                 epp = intel_pstate_get_epp(cpu_data, value);
 819                 if (epp)
 820                         goto skip_epp;
 821
 822                 epp = cpu_data->epp_powersave;
 823         }
 824 update_epp:
 825         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 826                 value &= ~GENMASK_ULL(31, 24);
 827                 value |= (u64)epp << 24;
 828         } else {
 829                 intel_pstate_set_epb(cpu, epp);
 830         }
 831 skip_epp:
 832         WRITE_ONCE(cpu_data->hwp_req_cached, value);
 833         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 834 }
 835
 836 static void intel_pstate_hwp_force_min_perf(int cpu)
 837 {
 838         u64 value;
 839         int min_perf;
 840
 841         value = all_cpu_data[cpu]->hwp_req_cached;
 842         value &= ~GENMASK_ULL(31, 0);
 843         min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
 844
 845         /* Set hwp_max = hwp_min */
 846         value |= HWP_MAX_PERF(min_perf);
 847         value |= HWP_MIN_PERF(min_perf);
 848
 849         /* Set EPP/EPB to min */
 850         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
 851                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
 852         else
 853                 intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
 854
 855         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 856 }
 857
 858 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 859 {
 860         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 861
 862         if (!hwp_active)
 863                 return 0;
 864
 865         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 866
 867         return 0;
 868 }
 869
 870 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
 871
 872 static int intel_pstate_resume(struct cpufreq_policy *policy)
 873 {
 874         if (!hwp_active)
 875                 return 0;
 876
 877         mutex_lock(&intel_pstate_limits_lock);
 878
 879         if (policy->cpu == 0)
 880                 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
 881
 882         all_cpu_data[policy->cpu]->epp_policy = 0;
 883         intel_pstate_hwp_set(policy->cpu);
 884
 885         mutex_unlock(&intel_pstate_limits_lock);
 886
 887         return 0;
 888 }
 889
 890 static void intel_pstate_update_policies(void)
 891 {
 892         int cpu;
 893
 894         for_each_possible_cpu(cpu)
 895                 cpufreq_update_policy(cpu);
 896 }
 897
 898 static void intel_pstate_update_max_freq(unsigned int cpu)
 899 {
 900         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
 901         struct cpufreq_policy new_policy;
 902         struct cpudata *cpudata;
 903
 904         if (!policy)
 905                 return;
 906
 907         cpudata = all_cpu_data[cpu];
 908         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
 909                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
 910
 911         memcpy(&new_policy, policy, sizeof(*policy));
 912         new_policy.max = min(policy->user_policy.max, policy->cpuinfo.max_freq);
 913         new_policy.min = min(policy->user_policy.min, new_policy.max);
 914
 915         cpufreq_set_policy(policy, &new_policy);
 916
 917         cpufreq_cpu_release(policy);
 918 }
 919
 920 static void intel_pstate_update_limits(unsigned int cpu)
 921 {
 922         mutex_lock(&intel_pstate_driver_lock);
 923
 924         update_turbo_state();
 925         /*
 926          * If turbo has been turned on or off globally, policy limits for
 927          * all CPUs need to be updated to reflect that.
 928          */
 929         if (global.turbo_disabled_mf != global.turbo_disabled) {
 930                 global.turbo_disabled_mf = global.turbo_disabled;
 931                 for_each_possible_cpu(cpu)
 932                         intel_pstate_update_max_freq(cpu);
 933         } else {
 934                 cpufreq_update_policy(cpu);
 935         }
 936
 937         mutex_unlock(&intel_pstate_driver_lock);
 938 }
 939
 940 /************************** sysfs begin ************************/
 941 #define show_one(file_name, object)                                     \
 942         static ssize_t show_##file_name                                 \
 943         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
 944         {                                                               \
 945                 return sprintf(buf, "%u\n", global.object);             \
 946         }
 947
 948 static ssize_t intel_pstate_show_status(char *buf);
 949 static int intel_pstate_update_status(const char *buf, size_t size);
 950
 951 static ssize_t show_status(struct kobject *kobj,
 952                            struct kobj_attribute *attr, char *buf)
 953 {
 954         ssize_t ret;
 955
 956         mutex_lock(&intel_pstate_driver_lock);
 957         ret = intel_pstate_show_status(buf);
 958         mutex_unlock(&intel_pstate_driver_lock);
 959
 960         return ret;
 961 }
 962
 963 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
 964                             const char *buf, size_t count)
 965 {
 966         char *p = memchr(buf, '\n', count);
 967         int ret;
 968
 969         mutex_lock(&intel_pstate_driver_lock);
 970         ret = intel_pstate_update_status(buf, p ? p - buf : count);
 971         mutex_unlock(&intel_pstate_driver_lock);
 972
 973         return ret < 0 ? ret : count;
 974 }
 975
 976 static ssize_t show_turbo_pct(struct kobject *kobj,
 977                                 struct kobj_attribute *attr, char *buf)
 978 {
 979         struct cpudata *cpu;
 980         int total, no_turbo, turbo_pct;
 981         uint32_t turbo_fp;
 982
 983         mutex_lock(&intel_pstate_driver_lock);
 984
 985         if (!intel_pstate_driver) {
 986                 mutex_unlock(&intel_pstate_driver_lock);
 987                 return -EAGAIN;
 988         }
 989
 990         cpu = all_cpu_data[0];
 991
 992         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 993         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 994         turbo_fp = div_fp(no_turbo, total);
 995         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 996
 997         mutex_unlock(&intel_pstate_driver_lock);
 998
 999         return sprintf(buf, "%u\n", turbo_pct);
1000 }
1001
1002 static ssize_t show_num_pstates(struct kobject *kobj,
1003                                 struct kobj_attribute *attr, char *buf)
1004 {
1005         struct cpudata *cpu;
1006         int total;
1007
1008         mutex_lock(&intel_pstate_driver_lock);
1009
1010         if (!intel_pstate_driver) {
1011                 mutex_unlock(&intel_pstate_driver_lock);
1012                 return -EAGAIN;
1013         }
1014
1015         cpu = all_cpu_data[0];
1016         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1017
1018         mutex_unlock(&intel_pstate_driver_lock);
1019
1020         return sprintf(buf, "%u\n", total);
1021 }
1022
1023 static ssize_t show_no_turbo(struct kobject *kobj,
1024                              struct kobj_attribute *attr, char *buf)
1025 {
1026         ssize_t ret;
1027
1028         mutex_lock(&intel_pstate_driver_lock);
1029
1030         if (!intel_pstate_driver) {
1031                 mutex_unlock(&intel_pstate_driver_lock);
1032                 return -EAGAIN;
1033         }
1034
1035         update_turbo_state();
1036         if (global.turbo_disabled)
1037                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1038         else
1039                 ret = sprintf(buf, "%u\n", global.no_turbo);
1040
1041         mutex_unlock(&intel_pstate_driver_lock);
1042
1043         return ret;
1044 }
1045
1046 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1047                               const char *buf, size_t count)
1048 {
1049         unsigned int input;
1050         int ret;
1051
1052         ret = sscanf(buf, "%u", &input);
1053         if (ret != 1)
1054                 return -EINVAL;
1055
1056         mutex_lock(&intel_pstate_driver_lock);
1057
1058         if (!intel_pstate_driver) {
1059                 mutex_unlock(&intel_pstate_driver_lock);
1060                 return -EAGAIN;
1061         }
1062
1063         mutex_lock(&intel_pstate_limits_lock);
1064
1065         update_turbo_state();
1066         if (global.turbo_disabled) {
1067                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1068                 mutex_unlock(&intel_pstate_limits_lock);
1069                 mutex_unlock(&intel_pstate_driver_lock);
1070                 return -EPERM;
1071         }
1072
1073         global.no_turbo = clamp_t(int, input, 0, 1);
1074
1075         if (global.no_turbo) {
1076                 struct cpudata *cpu = all_cpu_data[0];
1077                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1078
1079                 /* Squash the global minimum into the permitted range. */
1080                 if (global.min_perf_pct > pct)
1081                         global.min_perf_pct = pct;
1082         }
1083
1084         mutex_unlock(&intel_pstate_limits_lock);
1085
1086         intel_pstate_update_policies();
1087
1088         mutex_unlock(&intel_pstate_driver_lock);
1089
1090         return count;
1091 }
1092
1093 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1094                                   const char *buf, size_t count)
1095 {
1096         unsigned int input;
1097         int ret;
1098
1099         ret = sscanf(buf, "%u", &input);
1100         if (ret != 1)
1101                 return -EINVAL;
1102
1103         mutex_lock(&intel_pstate_driver_lock);
1104
1105         if (!intel_pstate_driver) {
1106                 mutex_unlock(&intel_pstate_driver_lock);
1107                 return -EAGAIN;
1108         }
1109
1110         mutex_lock(&intel_pstate_limits_lock);
1111
1112         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1113
1114         mutex_unlock(&intel_pstate_limits_lock);
1115
1116         intel_pstate_update_policies();
1117
1118         mutex_unlock(&intel_pstate_driver_lock);
1119
1120         return count;
1121 }
1122
1123 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1124                                   const char *buf, size_t count)
1125 {
1126         unsigned int input;
1127         int ret;
1128
1129         ret = sscanf(buf, "%u", &input);
1130         if (ret != 1)
1131                 return -EINVAL;
1132
1133         mutex_lock(&intel_pstate_driver_lock);
1134
1135         if (!intel_pstate_driver) {
1136                 mutex_unlock(&intel_pstate_driver_lock);
1137                 return -EAGAIN;
1138         }
1139
1140         mutex_lock(&intel_pstate_limits_lock);
1141
1142         global.min_perf_pct = clamp_t(int, input,
1143                                       min_perf_pct_min(), global.max_perf_pct);
1144
1145         mutex_unlock(&intel_pstate_limits_lock);
1146
1147         intel_pstate_update_policies();
1148
1149         mutex_unlock(&intel_pstate_driver_lock);
1150
1151         return count;
1152 }
1153
1154 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1155                                 struct kobj_attribute *attr, char *buf)
1156 {
1157         return sprintf(buf, "%u\n", hwp_boost);
1158 }
1159
1160 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1161                                        struct kobj_attribute *b,
1162                                        const char *buf, size_t count)
1163 {
1164         unsigned int input;
1165         int ret;
1166
1167         ret = kstrtouint(buf, 10, &input);
1168         if (ret)
1169                 return ret;
1170
1171         mutex_lock(&intel_pstate_driver_lock);
1172         hwp_boost = !!input;
1173         intel_pstate_update_policies();
1174         mutex_unlock(&intel_pstate_driver_lock);
1175
1176         return count;
1177 }
1178
1179 show_one(max_perf_pct, max_perf_pct);
1180 show_one(min_perf_pct, min_perf_pct);
1181
1182 define_one_global_rw(status);
1183 define_one_global_rw(no_turbo);
1184 define_one_global_rw(max_perf_pct);
1185 define_one_global_rw(min_perf_pct);
1186 define_one_global_ro(turbo_pct);
1187 define_one_global_ro(num_pstates);
1188 define_one_global_rw(hwp_dynamic_boost);
1189
1190 static struct attribute *intel_pstate_attributes[] = {
1191         &status.attr,
1192         &no_turbo.attr,
1193         &turbo_pct.attr,
1194         &num_pstates.attr,
1195         NULL
1196 };
1197
1198 static const struct attribute_group intel_pstate_attr_group = {
1199         .attrs = intel_pstate_attributes,
1200 };
1201
1202 static void __init intel_pstate_sysfs_expose_params(void)
1203 {
1204         struct kobject *intel_pstate_kobject;
1205         int rc;
1206
1207         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1208                                                 &cpu_subsys.dev_root->kobj);
1209         if (WARN_ON(!intel_pstate_kobject))
1210                 return;
1211
1212         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1213         if (WARN_ON(rc))
1214                 return;
1215
1216         /*
1217          * If per cpu limits are enforced there are no global limits, so
1218          * return without creating max/min_perf_pct attributes
1219          */
1220         if (per_cpu_limits)
1221                 return;
1222
1223         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1224         WARN_ON(rc);
1225
1226         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1227         WARN_ON(rc);
1228
1229         if (hwp_active) {
1230                 rc = sysfs_create_file(intel_pstate_kobject,
1231                                        &hwp_dynamic_boost.attr);
1232                 WARN_ON(rc);
1233         }
1234 }
1235 /************************** sysfs end ************************/
1236
1237 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1238 {
1239         /* First disable HWP notification interrupt as we don't process them */
1240         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1241                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1242
1243         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1244         cpudata->epp_policy = 0;
1245         if (cpudata->epp_default == -EINVAL)
1246                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1247 }
1248
1249 #define MSR_IA32_POWER_CTL_BIT_EE       19
1250
1251 /* Disable energy efficiency optimization */
1252 static void intel_pstate_disable_ee(int cpu)
1253 {
1254         u64 power_ctl;
1255         int ret;
1256
1257         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1258         if (ret)
1259                 return;
1260
1261         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1262                 pr_info("Disabling energy efficiency optimization\n");
1263                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1264                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1265         }
1266 }
1267
1268 static int atom_get_min_pstate(void)
1269 {
1270         u64 value;
1271
1272         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1273         return (value >> 8) & 0x7F;
1274 }
1275
1276 static int atom_get_max_pstate(void)
1277 {
1278         u64 value;
1279
1280         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1281         return (value >> 16) & 0x7F;
1282 }
1283
1284 static int atom_get_turbo_pstate(void)
1285 {
1286         u64 value;
1287
1288         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1289         return value & 0x7F;
1290 }
1291
1292 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1293 {
1294         u64 val;
1295         int32_t vid_fp;
1296         u32 vid;
1297
1298         val = (u64)pstate << 8;
1299         if (global.no_turbo && !global.turbo_disabled)
1300                 val |= (u64)1 << 32;
1301
1302         vid_fp = cpudata->vid.min + mul_fp(
1303                 int_tofp(pstate - cpudata->pstate.min_pstate),
1304                 cpudata->vid.ratio);
1305
1306         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1307         vid = ceiling_fp(vid_fp);
1308
1309         if (pstate > cpudata->pstate.max_pstate)
1310                 vid = cpudata->vid.turbo;
1311
1312         return val | vid;
1313 }
1314
1315 static int silvermont_get_scaling(void)
1316 {
1317         u64 value;
1318         int i;
1319         /* Defined in Table 35-6 from SDM (Sept 2015) */
1320         static int silvermont_freq_table[] = {
1321                 83300, 100000, 133300, 116700, 80000};
1322
1323         rdmsrl(MSR_FSB_FREQ, value);
1324         i = value & 0x7;
1325         WARN_ON(i > 4);
1326
1327         return silvermont_freq_table[i];
1328 }
1329
1330 static int airmont_get_scaling(void)
1331 {
1332         u64 value;
1333         int i;
1334         /* Defined in Table 35-10 from SDM (Sept 2015) */
1335         static int airmont_freq_table[] = {
1336                 83300, 100000, 133300, 116700, 80000,
1337                 93300, 90000, 88900, 87500};
1338
1339         rdmsrl(MSR_FSB_FREQ, value);
1340         i = value & 0xF;
1341         WARN_ON(i > 8);
1342
1343         return airmont_freq_table[i];
1344 }
1345
1346 static void atom_get_vid(struct cpudata *cpudata)
1347 {
1348         u64 value;
1349
1350         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1351         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1352         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1353         cpudata->vid.ratio = div_fp(
1354                 cpudata->vid.max - cpudata->vid.min,
1355                 int_tofp(cpudata->pstate.max_pstate -
1356                         cpudata->pstate.min_pstate));
1357
1358         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1359         cpudata->vid.turbo = value & 0x7f;
1360 }
1361
1362 static int core_get_min_pstate(void)
1363 {
1364         u64 value;
1365
1366         rdmsrl(MSR_PLATFORM_INFO, value);
1367         return (value >> 40) & 0xFF;
1368 }
1369
1370 static int core_get_max_pstate_physical(void)
1371 {
1372         u64 value;
1373
1374         rdmsrl(MSR_PLATFORM_INFO, value);
1375         return (value >> 8) & 0xFF;
1376 }
1377
1378 static int core_get_tdp_ratio(u64 plat_info)
1379 {
1380         /* Check how many TDP levels present */
1381         if (plat_info & 0x600000000) {
1382                 u64 tdp_ctrl;
1383                 u64 tdp_ratio;
1384                 int tdp_msr;
1385                 int err;
1386
1387                 /* Get the TDP level (0, 1, 2) to get ratios */
1388                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1389                 if (err)
1390                         return err;
1391
1392                 /* TDP MSR are continuous starting at 0x648 */
1393                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1394                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1395                 if (err)
1396                         return err;
1397
1398                 /* For level 1 and 2, bits[23:16] contain the ratio */
1399                 if (tdp_ctrl & 0x03)
1400                         tdp_ratio >>= 16;
1401
1402                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1403                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1404
1405                 return (int)tdp_ratio;
1406         }
1407
1408         return -ENXIO;
1409 }
1410
1411 static int core_get_max_pstate(void)
1412 {
1413         u64 tar;
1414         u64 plat_info;
1415         int max_pstate;
1416         int tdp_ratio;
1417         int err;
1418
1419         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1420         max_pstate = (plat_info >> 8) & 0xFF;
1421
1422         tdp_ratio = core_get_tdp_ratio(plat_info);
1423         if (tdp_ratio <= 0)
1424                 return max_pstate;
1425
1426         if (hwp_active) {
1427                 /* Turbo activation ratio is not used on HWP platforms */
1428                 return tdp_ratio;
1429         }
1430
1431         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1432         if (!err) {
1433                 int tar_levels;
1434
1435                 /* Do some sanity checking for safety */
1436                 tar_levels = tar & 0xff;
1437                 if (tdp_ratio - 1 == tar_levels) {
1438                         max_pstate = tar_levels;
1439                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1440                 }
1441         }
1442
1443         return max_pstate;
1444 }
1445
1446 static int core_get_turbo_pstate(void)
1447 {
1448         u64 value;
1449         int nont, ret;
1450
1451         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1452         nont = core_get_max_pstate();
1453         ret = (value) & 255;
1454         if (ret <= nont)
1455                 ret = nont;
1456         return ret;
1457 }
1458
1459 static inline int core_get_scaling(void)
1460 {
1461         return 100000;
1462 }
1463
1464 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1465 {
1466         u64 val;
1467
1468         val = (u64)pstate << 8;
1469         if (global.no_turbo && !global.turbo_disabled)
1470                 val |= (u64)1 << 32;
1471
1472         return val;
1473 }
1474
1475 static int knl_get_aperf_mperf_shift(void)
1476 {
1477         return 10;
1478 }
1479
1480 static int knl_get_turbo_pstate(void)
1481 {
1482         u64 value;
1483         int nont, ret;
1484
1485         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1486         nont = core_get_max_pstate();
1487         ret = (((value) >> 8) & 0xFF);
1488         if (ret <= nont)
1489                 ret = nont;
1490         return ret;
1491 }
1492
1493 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1494 {
1495         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1496         cpu->pstate.current_pstate = pstate;
1497         /*
1498          * Generally, there is no guarantee that this code will always run on
1499          * the CPU being updated, so force the register update to run on the
1500          * right CPU.
1501          */
1502         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1503                       pstate_funcs.get_val(cpu, pstate));
1504 }
1505
1506 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1507 {
1508         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1509 }
1510
1511 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1512 {
1513         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1514
1515         update_turbo_state();
1516         intel_pstate_set_pstate(cpu, pstate);
1517 }
1518
1519 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1520 {
1521         cpu->pstate.min_pstate = pstate_funcs.get_min();
1522         cpu->pstate.max_pstate = pstate_funcs.get_max();
1523         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1524         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1525         cpu->pstate.scaling = pstate_funcs.get_scaling();
1526         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1527
1528         if (hwp_active && !hwp_mode_bdw) {
1529                 unsigned int phy_max, current_max;
1530
1531                 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1532                 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1533         } else {
1534                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1535         }
1536
1537         if (pstate_funcs.get_aperf_mperf_shift)
1538                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1539
1540         if (pstate_funcs.get_vid)
1541                 pstate_funcs.get_vid(cpu);
1542
1543         intel_pstate_set_min_pstate(cpu);
1544 }
1545
1546 /*
1547  * Long hold time will keep high perf limits for long time,
1548  * which negatively impacts perf/watt for some workloads,
1549  * like specpower. 3ms is based on experiements on some
1550  * workoads.
1551  */
1552 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1553
1554 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1555 {
1556         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1557         u32 max_limit = (hwp_req & 0xff00) >> 8;
1558         u32 min_limit = (hwp_req & 0xff);
1559         u32 boost_level1;
1560
1561         /*
1562          * Cases to consider (User changes via sysfs or boot time):
1563          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1564          *      No boost, return.
1565          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1566          *     Should result in one level boost only for P0.
1567          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1568          *     Should result in two level boost:
1569          *         (min + p1)/2 and P1.
1570          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1571          *     Should result in three level boost:
1572          *        (min + p1)/2, P1 and P0.
1573          */
1574
1575         /* If max and min are equal or already at max, nothing to boost */
1576         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1577                 return;
1578
1579         if (!cpu->hwp_boost_min)
1580                 cpu->hwp_boost_min = min_limit;
1581
1582         /* level at half way mark between min and guranteed */
1583         boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1584
1585         if (cpu->hwp_boost_min < boost_level1)
1586                 cpu->hwp_boost_min = boost_level1;
1587         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1588                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1589         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1590                  max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1591                 cpu->hwp_boost_min = max_limit;
1592         else
1593                 return;
1594
1595         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1596         wrmsrl(MSR_HWP_REQUEST, hwp_req);
1597         cpu->last_update = cpu->sample.time;
1598 }
1599
1600 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1601 {
1602         if (cpu->hwp_boost_min) {
1603                 bool expired;
1604
1605                 /* Check if we are idle for hold time to boost down */
1606                 expired = time_after64(cpu->sample.time, cpu->last_update +
1607                                        hwp_boost_hold_time_ns);
1608                 if (expired) {
1609                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1610                         cpu->hwp_boost_min = 0;
1611                 }
1612         }
1613         cpu->last_update = cpu->sample.time;
1614 }
1615
1616 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1617                                                       u64 time)
1618 {
1619         cpu->sample.time = time;
1620
1621         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1622                 bool do_io = false;
1623
1624                 cpu->sched_flags = 0;
1625                 /*
1626                  * Set iowait_boost flag and update time. Since IO WAIT flag
1627                  * is set all the time, we can't just conclude that there is
1628                  * some IO bound activity is scheduled on this CPU with just
1629                  * one occurrence. If we receive at least two in two
1630                  * consecutive ticks, then we treat as boost candidate.
1631                  */
1632                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1633                         do_io = true;
1634
1635                 cpu->last_io_update = time;
1636
1637                 if (do_io)
1638                         intel_pstate_hwp_boost_up(cpu);
1639
1640         } else {
1641                 intel_pstate_hwp_boost_down(cpu);
1642         }
1643 }
1644
1645 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1646                                                 u64 time, unsigned int flags)
1647 {
1648         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1649
1650         cpu->sched_flags |= flags;
1651
1652         if (smp_processor_id() == cpu->cpu)
1653                 intel_pstate_update_util_hwp_local(cpu, time);
1654 }
1655
1656 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1657 {
1658         struct sample *sample = &cpu->sample;
1659
1660         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1661 }
1662
1663 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1664 {
1665         u64 aperf, mperf;
1666         unsigned long flags;
1667         u64 tsc;
1668
1669         local_irq_save(flags);
1670         rdmsrl(MSR_IA32_APERF, aperf);
1671         rdmsrl(MSR_IA32_MPERF, mperf);
1672         tsc = rdtsc();
1673         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1674                 local_irq_restore(flags);
1675                 return false;
1676         }
1677         local_irq_restore(flags);
1678
1679         cpu->last_sample_time = cpu->sample.time;
1680         cpu->sample.time = time;
1681         cpu->sample.aperf = aperf;
1682         cpu->sample.mperf = mperf;
1683         cpu->sample.tsc =  tsc;
1684         cpu->sample.aperf -= cpu->prev_aperf;
1685         cpu->sample.mperf -= cpu->prev_mperf;
1686         cpu->sample.tsc -= cpu->prev_tsc;
1687
1688         cpu->prev_aperf = aperf;
1689         cpu->prev_mperf = mperf;
1690         cpu->prev_tsc = tsc;
1691         /*
1692          * First time this function is invoked in a given cycle, all of the
1693          * previous sample data fields are equal to zero or stale and they must
1694          * be populated with meaningful numbers for things to work, so assume
1695          * that sample.time will always be reset before setting the utilization
1696          * update hook and make the caller skip the sample then.
1697          */
1698         if (cpu->last_sample_time) {
1699                 intel_pstate_calc_avg_perf(cpu);
1700                 return true;
1701         }
1702         return false;
1703 }
1704
1705 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1706 {
1707         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1708 }
1709
1710 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1711 {
1712         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1713                           cpu->sample.core_avg_perf);
1714 }
1715
1716 static inline int32_t get_target_pstate(struct cpudata *cpu)
1717 {
1718         struct sample *sample = &cpu->sample;
1719         int32_t busy_frac;
1720         int target, avg_pstate;
1721
1722         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1723                            sample->tsc);
1724
1725         if (busy_frac < cpu->iowait_boost)
1726                 busy_frac = cpu->iowait_boost;
1727
1728         sample->busy_scaled = busy_frac * 100;
1729
1730         target = global.no_turbo || global.turbo_disabled ?
1731                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1732         target += target >> 2;
1733         target = mul_fp(target, busy_frac);
1734         if (target < cpu->pstate.min_pstate)
1735                 target = cpu->pstate.min_pstate;
1736
1737         /*
1738          * If the average P-state during the previous cycle was higher than the
1739          * current target, add 50% of the difference to the target to reduce
1740          * possible performance oscillations and offset possible performance
1741          * loss related to moving the workload from one CPU to another within
1742          * a package/module.
1743          */
1744         avg_pstate = get_avg_pstate(cpu);
1745         if (avg_pstate > target)
1746                 target += (avg_pstate - target) >> 1;
1747
1748         return target;
1749 }
1750
1751 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1752 {
1753         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1754         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1755
1756         return clamp_t(int, pstate, min_pstate, max_pstate);
1757 }
1758
1759 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1760 {
1761         if (pstate == cpu->pstate.current_pstate)
1762                 return;
1763
1764         cpu->pstate.current_pstate = pstate;
1765         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1766 }
1767
1768 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1769 {
1770         int from = cpu->pstate.current_pstate;
1771         struct sample *sample;
1772         int target_pstate;
1773
1774         update_turbo_state();
1775
1776         target_pstate = get_target_pstate(cpu);
1777         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1778         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1779         intel_pstate_update_pstate(cpu, target_pstate);
1780
1781         sample = &cpu->sample;
1782         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1783                 fp_toint(sample->busy_scaled),
1784                 from,
1785                 cpu->pstate.current_pstate,
1786                 sample->mperf,
1787                 sample->aperf,
1788                 sample->tsc,
1789                 get_avg_frequency(cpu),
1790                 fp_toint(cpu->iowait_boost * 100));
1791 }
1792
1793 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1794                                      unsigned int flags)
1795 {
1796         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1797         u64 delta_ns;
1798
1799         /* Don't allow remote callbacks */
1800         if (smp_processor_id() != cpu->cpu)
1801                 return;
1802
1803         delta_ns = time - cpu->last_update;
1804         if (flags & SCHED_CPUFREQ_IOWAIT) {
1805                 /* Start over if the CPU may have been idle. */
1806                 if (delta_ns > TICK_NSEC) {
1807                         cpu->iowait_boost = ONE_EIGHTH_FP;
1808                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
1809                         cpu->iowait_boost <<= 1;
1810                         if (cpu->iowait_boost > int_tofp(1))
1811                                 cpu->iowait_boost = int_tofp(1);
1812                 } else {
1813                         cpu->iowait_boost = ONE_EIGHTH_FP;
1814                 }
1815         } else if (cpu->iowait_boost) {
1816                 /* Clear iowait_boost if the CPU may have been idle. */
1817                 if (delta_ns > TICK_NSEC)
1818                         cpu->iowait_boost = 0;
1819                 else
1820                         cpu->iowait_boost >>= 1;
1821         }
1822         cpu->last_update = time;
1823         delta_ns = time - cpu->sample.time;
1824         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1825                 return;
1826
1827         if (intel_pstate_sample(cpu, time))
1828                 intel_pstate_adjust_pstate(cpu);
1829 }
1830
1831 static struct pstate_funcs core_funcs = {
1832         .get_max = core_get_max_pstate,
1833         .get_max_physical = core_get_max_pstate_physical,
1834         .get_min = core_get_min_pstate,
1835         .get_turbo = core_get_turbo_pstate,
1836         .get_scaling = core_get_scaling,
1837         .get_val = core_get_val,
1838 };
1839
1840 static const struct pstate_funcs silvermont_funcs = {
1841         .get_max = atom_get_max_pstate,
1842         .get_max_physical = atom_get_max_pstate,
1843         .get_min = atom_get_min_pstate,
1844         .get_turbo = atom_get_turbo_pstate,
1845         .get_val = atom_get_val,
1846         .get_scaling = silvermont_get_scaling,
1847         .get_vid = atom_get_vid,
1848 };
1849
1850 static const struct pstate_funcs airmont_funcs = {
1851         .get_max = atom_get_max_pstate,
1852         .get_max_physical = atom_get_max_pstate,
1853         .get_min = atom_get_min_pstate,
1854         .get_turbo = atom_get_turbo_pstate,
1855         .get_val = atom_get_val,
1856         .get_scaling = airmont_get_scaling,
1857         .get_vid = atom_get_vid,
1858 };
1859
1860 static const struct pstate_funcs knl_funcs = {
1861         .get_max = core_get_max_pstate,
1862         .get_max_physical = core_get_max_pstate_physical,
1863         .get_min = core_get_min_pstate,
1864         .get_turbo = knl_get_turbo_pstate,
1865         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1866         .get_scaling = core_get_scaling,
1867         .get_val = core_get_val,
1868 };
1869
1870 #define ICPU(model, policy) \
1871         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1872                         (unsigned long)&policy }
1873
1874 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1875         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1876         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1877         ICPU(INTEL_FAM6_ATOM_SILVERMONT,        silvermont_funcs),
1878         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1879         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1880         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1881         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1882         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1883         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1884         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1885         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1886         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1887         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1888         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1889         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1890         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1891         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1892         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1893         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          core_funcs),
1894         ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS,     core_funcs),
1895         ICPU(INTEL_FAM6_SKYLAKE_X,              core_funcs),
1896         {}
1897 };
1898 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1899
1900 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1901         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1902         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1903         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1904         {}
1905 };
1906
1907 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1908         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1909         {}
1910 };
1911
1912 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1913         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1914         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1915         {}
1916 };
1917
1918 static int intel_pstate_init_cpu(unsigned int cpunum)
1919 {
1920         struct cpudata *cpu;
1921
1922         cpu = all_cpu_data[cpunum];
1923
1924         if (!cpu) {
1925                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1926                 if (!cpu)
1927                         return -ENOMEM;
1928
1929                 all_cpu_data[cpunum] = cpu;
1930
1931                 cpu->epp_default = -EINVAL;
1932                 cpu->epp_powersave = -EINVAL;
1933                 cpu->epp_saved = -EINVAL;
1934         }
1935
1936         cpu = all_cpu_data[cpunum];
1937
1938         cpu->cpu = cpunum;
1939
1940         if (hwp_active) {
1941                 const struct x86_cpu_id *id;
1942
1943                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1944                 if (id)
1945                         intel_pstate_disable_ee(cpunum);
1946
1947                 intel_pstate_hwp_enable(cpu);
1948
1949                 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1950                 if (id && intel_pstate_acpi_pm_profile_server())
1951                         hwp_boost = true;
1952         }
1953
1954         intel_pstate_get_cpu_pstates(cpu);
1955
1956         pr_debug("controlling: cpu %d\n", cpunum);
1957
1958         return 0;
1959 }
1960
1961 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1962 {
1963         struct cpudata *cpu = all_cpu_data[cpu_num];
1964
1965         if (hwp_active && !hwp_boost)
1966                 return;
1967
1968         if (cpu->update_util_set)
1969                 return;
1970
1971         /* Prevent intel_pstate_update_util() from using stale data. */
1972         cpu->sample.time = 0;
1973         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1974                                      (hwp_active ?
1975                                       intel_pstate_update_util_hwp :
1976                                       intel_pstate_update_util));
1977         cpu->update_util_set = true;
1978 }
1979
1980 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1981 {
1982         struct cpudata *cpu_data = all_cpu_data[cpu];
1983
1984         if (!cpu_data->update_util_set)
1985                 return;
1986
1987         cpufreq_remove_update_util_hook(cpu);
1988         cpu_data->update_util_set = false;
1989         synchronize_rcu();
1990 }
1991
1992 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1993 {
1994         return global.turbo_disabled || global.no_turbo ?
1995                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1996 }
1997
1998 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1999                                             struct cpudata *cpu)
2000 {
2001         int max_freq = intel_pstate_get_max_freq(cpu);
2002         int32_t max_policy_perf, min_policy_perf;
2003         int max_state, turbo_max;
2004
2005         /*
2006          * HWP needs some special consideration, because on BDX the
2007          * HWP_REQUEST uses abstract value to represent performance
2008          * rather than pure ratios.
2009          */
2010         if (hwp_active) {
2011                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2012         } else {
2013                 max_state = global.no_turbo || global.turbo_disabled ?
2014                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2015                 turbo_max = cpu->pstate.turbo_pstate;
2016         }
2017
2018         max_policy_perf = max_state * policy->max / max_freq;
2019         if (policy->max == policy->min) {
2020                 min_policy_perf = max_policy_perf;
2021         } else {
2022                 min_policy_perf = max_state * policy->min / max_freq;
2023                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2024                                           0, max_policy_perf);
2025         }
2026
2027         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2028                  policy->cpu, max_state,
2029                  min_policy_perf, max_policy_perf);
2030
2031         /* Normalize user input to [min_perf, max_perf] */
2032         if (per_cpu_limits) {
2033                 cpu->min_perf_ratio = min_policy_perf;
2034                 cpu->max_perf_ratio = max_policy_perf;
2035         } else {
2036                 int32_t global_min, global_max;
2037
2038                 /* Global limits are in percent of the maximum turbo P-state. */
2039                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2040                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2041                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2042
2043                 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2044                          global_min, global_max);
2045
2046                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2047                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2048                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2049                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2050
2051                 /* Make sure min_perf <= max_perf */
2052                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2053                                           cpu->max_perf_ratio);
2054
2055         }
2056         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2057                  cpu->max_perf_ratio,
2058                  cpu->min_perf_ratio);
2059 }
2060
2061 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2062 {
2063         struct cpudata *cpu;
2064
2065         if (!policy->cpuinfo.max_freq)
2066                 return -ENODEV;
2067
2068         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2069                  policy->cpuinfo.max_freq, policy->max);
2070
2071         cpu = all_cpu_data[policy->cpu];
2072         cpu->policy = policy->policy;
2073
2074         mutex_lock(&intel_pstate_limits_lock);
2075
2076         intel_pstate_update_perf_limits(policy, cpu);
2077
2078         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2079                 /*
2080                  * NOHZ_FULL CPUs need this as the governor callback may not
2081                  * be invoked on them.
2082                  */
2083                 intel_pstate_clear_update_util_hook(policy->cpu);
2084                 intel_pstate_max_within_limits(cpu);
2085         } else {
2086                 intel_pstate_set_update_util_hook(policy->cpu);
2087         }
2088
2089         if (hwp_active) {
2090                 /*
2091                  * When hwp_boost was active before and dynamically it
2092                  * was turned off, in that case we need to clear the
2093                  * update util hook.
2094                  */
2095                 if (!hwp_boost)
2096                         intel_pstate_clear_update_util_hook(policy->cpu);
2097                 intel_pstate_hwp_set(policy->cpu);
2098         }
2099
2100         mutex_unlock(&intel_pstate_limits_lock);
2101
2102         return 0;
2103 }
2104
2105 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2106                                          struct cpudata *cpu)
2107 {
2108         if (!hwp_active &&
2109             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2110             policy->max < policy->cpuinfo.max_freq &&
2111             policy->max > cpu->pstate.max_freq) {
2112                 pr_debug("policy->max > max non turbo frequency\n");
2113                 policy->max = policy->cpuinfo.max_freq;
2114         }
2115 }
2116
2117 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2118 {
2119         struct cpudata *cpu = all_cpu_data[policy->cpu];
2120
2121         update_turbo_state();
2122         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2123                                      intel_pstate_get_max_freq(cpu));
2124
2125         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2126             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2127                 return -EINVAL;
2128
2129         intel_pstate_adjust_policy_max(policy, cpu);
2130
2131         return 0;
2132 }
2133
2134 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2135 {
2136         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2137 }
2138
2139 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2140 {
2141         pr_debug("CPU %d exiting\n", policy->cpu);
2142
2143         intel_pstate_clear_update_util_hook(policy->cpu);
2144         if (hwp_active) {
2145                 intel_pstate_hwp_save_state(policy);
2146                 intel_pstate_hwp_force_min_perf(policy->cpu);
2147         } else {
2148                 intel_cpufreq_stop_cpu(policy);
2149         }
2150 }
2151
2152 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2153 {
2154         intel_pstate_exit_perf_limits(policy);
2155
2156         policy->fast_switch_possible = false;
2157
2158         return 0;
2159 }
2160
2161 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2162 {
2163         struct cpudata *cpu;
2164         int rc;
2165
2166         rc = intel_pstate_init_cpu(policy->cpu);
2167         if (rc)
2168                 return rc;
2169
2170         cpu = all_cpu_data[policy->cpu];
2171
2172         cpu->max_perf_ratio = 0xFF;
2173         cpu->min_perf_ratio = 0;
2174
2175         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2176         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2177
2178         /* cpuinfo and default policy values */
2179         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2180         update_turbo_state();
2181         global.turbo_disabled_mf = global.turbo_disabled;
2182         policy->cpuinfo.max_freq = global.turbo_disabled ?
2183                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2184         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2185
2186         if (hwp_active) {
2187                 unsigned int max_freq;
2188
2189                 max_freq = global.turbo_disabled ?
2190                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2191                 if (max_freq < policy->cpuinfo.max_freq)
2192                         policy->cpuinfo.max_freq = max_freq;
2193         }
2194
2195         intel_pstate_init_acpi_perf_limits(policy);
2196
2197         policy->fast_switch_possible = true;
2198
2199         return 0;
2200 }
2201
2202 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2203 {
2204         int ret = __intel_pstate_cpu_init(policy);
2205
2206         if (ret)
2207                 return ret;
2208
2209         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2210                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2211         else
2212                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2213
2214         return 0;
2215 }
2216
2217 static struct cpufreq_driver intel_pstate = {
2218         .flags          = CPUFREQ_CONST_LOOPS,
2219         .verify         = intel_pstate_verify_policy,
2220         .setpolicy      = intel_pstate_set_policy,
2221         .suspend        = intel_pstate_hwp_save_state,
2222         .resume         = intel_pstate_resume,
2223         .init           = intel_pstate_cpu_init,
2224         .exit           = intel_pstate_cpu_exit,
2225         .stop_cpu       = intel_pstate_stop_cpu,
2226         .update_limits  = intel_pstate_update_limits,
2227         .name           = "intel_pstate",
2228 };
2229
2230 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2231 {
2232         struct cpudata *cpu = all_cpu_data[policy->cpu];
2233
2234         update_turbo_state();
2235         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2236                                      intel_pstate_get_max_freq(cpu));
2237
2238         intel_pstate_adjust_policy_max(policy, cpu);
2239
2240         intel_pstate_update_perf_limits(policy, cpu);
2241
2242         return 0;
2243 }
2244
2245 /* Use of trace in passive mode:
2246  *
2247  * In passive mode the trace core_busy field (also known as the
2248  * performance field, and lablelled as such on the graphs; also known as
2249  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2250  * driver call was via the normal or fast switch path. Various graphs
2251  * output from the intel_pstate_tracer.py utility that include core_busy
2252  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2253  * so we use 10 to indicate the the normal path through the driver, and
2254  * 90 to indicate the fast switch path through the driver.
2255  * The scaled_busy field is not used, and is set to 0.
2256  */
2257
2258 #define INTEL_PSTATE_TRACE_TARGET 10
2259 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2260
2261 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2262 {
2263         struct sample *sample;
2264
2265         if (!trace_pstate_sample_enabled())
2266                 return;
2267
2268         if (!intel_pstate_sample(cpu, ktime_get()))
2269                 return;
2270
2271         sample = &cpu->sample;
2272         trace_pstate_sample(trace_type,
2273                 0,
2274                 old_pstate,
2275                 cpu->pstate.current_pstate,
2276                 sample->mperf,
2277                 sample->aperf,
2278                 sample->tsc,
2279                 get_avg_frequency(cpu),
2280                 fp_toint(cpu->iowait_boost * 100));
2281 }
2282
2283 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2284                                 unsigned int target_freq,
2285                                 unsigned int relation)
2286 {
2287         struct cpudata *cpu = all_cpu_data[policy->cpu];
2288         struct cpufreq_freqs freqs;
2289         int target_pstate, old_pstate;
2290
2291         update_turbo_state();
2292
2293         freqs.old = policy->cur;
2294         freqs.new = target_freq;
2295
2296         cpufreq_freq_transition_begin(policy, &freqs);
2297         switch (relation) {
2298         case CPUFREQ_RELATION_L:
2299                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2300                 break;
2301         case CPUFREQ_RELATION_H:
2302                 target_pstate = freqs.new / cpu->pstate.scaling;
2303                 break;
2304         default:
2305                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2306                 break;
2307         }
2308         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2309         old_pstate = cpu->pstate.current_pstate;
2310         if (target_pstate != cpu->pstate.current_pstate) {
2311                 cpu->pstate.current_pstate = target_pstate;
2312                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2313                               pstate_funcs.get_val(cpu, target_pstate));
2314         }
2315         freqs.new = target_pstate * cpu->pstate.scaling;
2316         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2317         cpufreq_freq_transition_end(policy, &freqs, false);
2318
2319         return 0;
2320 }
2321
2322 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2323                                               unsigned int target_freq)
2324 {
2325         struct cpudata *cpu = all_cpu_data[policy->cpu];
2326         int target_pstate, old_pstate;
2327
2328         update_turbo_state();
2329
2330         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2331         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2332         old_pstate = cpu->pstate.current_pstate;
2333         intel_pstate_update_pstate(cpu, target_pstate);
2334         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2335         return target_pstate * cpu->pstate.scaling;
2336 }
2337
2338 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2339 {
2340         int ret = __intel_pstate_cpu_init(policy);
2341
2342         if (ret)
2343                 return ret;
2344
2345         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2346         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2347         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2348         policy->cur = policy->cpuinfo.min_freq;
2349
2350         return 0;
2351 }
2352
2353 static struct cpufreq_driver intel_cpufreq = {
2354         .flags          = CPUFREQ_CONST_LOOPS,
2355         .verify         = intel_cpufreq_verify_policy,
2356         .target         = intel_cpufreq_target,
2357         .fast_switch    = intel_cpufreq_fast_switch,
2358         .init           = intel_cpufreq_cpu_init,
2359         .exit           = intel_pstate_cpu_exit,
2360         .stop_cpu       = intel_cpufreq_stop_cpu,
2361         .update_limits  = intel_pstate_update_limits,
2362         .name           = "intel_cpufreq",
2363 };
2364
2365 static struct cpufreq_driver *default_driver = &intel_pstate;
2366
2367 static void intel_pstate_driver_cleanup(void)
2368 {
2369         unsigned int cpu;
2370
2371         get_online_cpus();
2372         for_each_online_cpu(cpu) {
2373                 if (all_cpu_data[cpu]) {
2374                         if (intel_pstate_driver == &intel_pstate)
2375                                 intel_pstate_clear_update_util_hook(cpu);
2376
2377                         kfree(all_cpu_data[cpu]);
2378                         all_cpu_data[cpu] = NULL;
2379                 }
2380         }
2381         put_online_cpus();
2382         intel_pstate_driver = NULL;
2383 }
2384
2385 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2386 {
2387         int ret;
2388
2389         memset(&global, 0, sizeof(global));
2390         global.max_perf_pct = 100;
2391
2392         intel_pstate_driver = driver;
2393         ret = cpufreq_register_driver(intel_pstate_driver);
2394         if (ret) {
2395                 intel_pstate_driver_cleanup();
2396                 return ret;
2397         }
2398
2399         global.min_perf_pct = min_perf_pct_min();
2400
2401         return 0;
2402 }
2403
2404 static int intel_pstate_unregister_driver(void)
2405 {
2406         if (hwp_active)
2407                 return -EBUSY;
2408
2409         cpufreq_unregister_driver(intel_pstate_driver);
2410         intel_pstate_driver_cleanup();
2411
2412         return 0;
2413 }
2414
2415 static ssize_t intel_pstate_show_status(char *buf)
2416 {
2417         if (!intel_pstate_driver)
2418                 return sprintf(buf, "off\n");
2419
2420         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2421                                         "active" : "passive");
2422 }
2423
2424 static int intel_pstate_update_status(const char *buf, size_t size)
2425 {
2426         int ret;
2427
2428         if (size == 3 && !strncmp(buf, "off", size))
2429                 return intel_pstate_driver ?
2430                         intel_pstate_unregister_driver() : -EINVAL;
2431
2432         if (size == 6 && !strncmp(buf, "active", size)) {
2433                 if (intel_pstate_driver) {
2434                         if (intel_pstate_driver == &intel_pstate)
2435                                 return 0;
2436
2437                         ret = intel_pstate_unregister_driver();
2438                         if (ret)
2439                                 return ret;
2440                 }
2441
2442                 return intel_pstate_register_driver(&intel_pstate);
2443         }
2444
2445         if (size == 7 && !strncmp(buf, "passive", size)) {
2446                 if (intel_pstate_driver) {
2447                         if (intel_pstate_driver == &intel_cpufreq)
2448                                 return 0;
2449
2450                         ret = intel_pstate_unregister_driver();
2451                         if (ret)
2452                                 return ret;
2453                 }
2454
2455                 return intel_pstate_register_driver(&intel_cpufreq);
2456         }
2457
2458         return -EINVAL;
2459 }
2460
2461 static int no_load __initdata;
2462 static int no_hwp __initdata;
2463 static int hwp_only __initdata;
2464 static unsigned int force_load __initdata;
2465
2466 static int __init intel_pstate_msrs_not_valid(void)
2467 {
2468         if (!pstate_funcs.get_max() ||
2469             !pstate_funcs.get_min() ||
2470             !pstate_funcs.get_turbo())
2471                 return -ENODEV;
2472
2473         return 0;
2474 }
2475
2476 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2477 {
2478         pstate_funcs.get_max   = funcs->get_max;
2479         pstate_funcs.get_max_physical = funcs->get_max_physical;
2480         pstate_funcs.get_min   = funcs->get_min;
2481         pstate_funcs.get_turbo = funcs->get_turbo;
2482         pstate_funcs.get_scaling = funcs->get_scaling;
2483         pstate_funcs.get_val   = funcs->get_val;
2484         pstate_funcs.get_vid   = funcs->get_vid;
2485         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2486 }
2487
2488 #ifdef CONFIG_ACPI
2489
2490 static bool __init intel_pstate_no_acpi_pss(void)
2491 {
2492         int i;
2493
2494         for_each_possible_cpu(i) {
2495                 acpi_status status;
2496                 union acpi_object *pss;
2497                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2498                 struct acpi_processor *pr = per_cpu(processors, i);
2499
2500                 if (!pr)
2501                         continue;
2502
2503                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2504                 if (ACPI_FAILURE(status))
2505                         continue;
2506
2507                 pss = buffer.pointer;
2508                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2509                         kfree(pss);
2510                         return false;
2511                 }
2512
2513                 kfree(pss);
2514         }
2515
2516         pr_debug("ACPI _PSS not found\n");
2517         return true;
2518 }
2519
2520 static bool __init intel_pstate_no_acpi_pcch(void)
2521 {
2522         acpi_status status;
2523         acpi_handle handle;
2524
2525         status = acpi_get_handle(NULL, "\\_SB", &handle);
2526         if (ACPI_FAILURE(status))
2527                 goto not_found;
2528
2529         if (acpi_has_method(handle, "PCCH"))
2530                 return false;
2531
2532 not_found:
2533         pr_debug("ACPI PCCH not found\n");
2534         return true;
2535 }
2536
2537 static bool __init intel_pstate_has_acpi_ppc(void)
2538 {
2539         int i;
2540
2541         for_each_possible_cpu(i) {
2542                 struct acpi_processor *pr = per_cpu(processors, i);
2543
2544                 if (!pr)
2545                         continue;
2546                 if (acpi_has_method(pr->handle, "_PPC"))
2547                         return true;
2548         }
2549         pr_debug("ACPI _PPC not found\n");
2550         return false;
2551 }
2552
2553 enum {
2554         PSS,
2555         PPC,
2556 };
2557
2558 /* Hardware vendor-specific info that has its own power management modes */
2559 static struct acpi_platform_list plat_info[] __initdata = {
2560         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2561         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2562         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2563         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2564         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2565         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2566         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2567         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2568         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2569         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2570         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2571         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2572         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2573         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2574         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2575         { } /* End */
2576 };
2577
2578 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2579 {
2580         const struct x86_cpu_id *id;
2581         u64 misc_pwr;
2582         int idx;
2583
2584         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2585         if (id) {
2586                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2587                 if (misc_pwr & (1 << 8)) {
2588                         pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
2589                         return true;
2590                 }
2591         }
2592
2593         idx = acpi_match_platform_list(plat_info);
2594         if (idx < 0)
2595                 return false;
2596
2597         switch (plat_info[idx].data) {
2598         case PSS:
2599                 if (!intel_pstate_no_acpi_pss())
2600                         return false;
2601
2602                 return intel_pstate_no_acpi_pcch();
2603         case PPC:
2604                 return intel_pstate_has_acpi_ppc() && !force_load;
2605         }
2606
2607         return false;
2608 }
2609
2610 static void intel_pstate_request_control_from_smm(void)
2611 {
2612         /*
2613          * It may be unsafe to request P-states control from SMM if _PPC support
2614          * has not been enabled.
2615          */
2616         if (acpi_ppc)
2617                 acpi_processor_pstate_control();
2618 }
2619 #else /* CONFIG_ACPI not enabled */
2620 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2621 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2622 static inline void intel_pstate_request_control_from_smm(void) {}
2623 #endif /* CONFIG_ACPI */
2624
2625 #define INTEL_PSTATE_HWP_BROADWELL      0x01
2626
2627 #define ICPU_HWP(model, hwp_mode) \
2628         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2629
2630 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2631         ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2632         ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2633         ICPU_HWP(X86_MODEL_ANY, 0),
2634         {}
2635 };
2636
2637 static int __init intel_pstate_init(void)
2638 {
2639         const struct x86_cpu_id *id;
2640         int rc;
2641
2642         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2643                 return -ENODEV;
2644
2645         if (no_load)
2646                 return -ENODEV;
2647
2648         id = x86_match_cpu(hwp_support_ids);
2649         if (id) {
2650                 copy_cpu_funcs(&core_funcs);
2651                 if (!no_hwp) {
2652                         hwp_active++;
2653                         hwp_mode_bdw = id->driver_data;
2654                         intel_pstate.attr = hwp_cpufreq_attrs;
2655                         goto hwp_cpu_matched;
2656                 }
2657         } else {
2658                 id = x86_match_cpu(intel_pstate_cpu_ids);
2659                 if (!id) {
2660                         pr_info("CPU model not supported\n");
2661                         return -ENODEV;
2662                 }
2663
2664                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2665         }
2666
2667         if (intel_pstate_msrs_not_valid()) {
2668                 pr_info("Invalid MSRs\n");
2669                 return -ENODEV;
2670         }
2671
2672 hwp_cpu_matched:
2673         /*
2674          * The Intel pstate driver will be ignored if the platform
2675          * firmware has its own power management modes.
2676          */
2677         if (intel_pstate_platform_pwr_mgmt_exists()) {
2678                 pr_info("P-states controlled by the platform\n");
2679                 return -ENODEV;
2680         }
2681
2682         if (!hwp_active && hwp_only)
2683                 return -ENOTSUPP;
2684
2685         pr_info("Intel P-state driver initializing\n");
2686
2687         all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2688         if (!all_cpu_data)
2689                 return -ENOMEM;
2690
2691         intel_pstate_request_control_from_smm();
2692
2693         intel_pstate_sysfs_expose_params();
2694
2695         mutex_lock(&intel_pstate_driver_lock);
2696         rc = intel_pstate_register_driver(default_driver);
2697         mutex_unlock(&intel_pstate_driver_lock);
2698         if (rc)
2699                 return rc;
2700
2701         if (hwp_active)
2702                 pr_info("HWP enabled\n");
2703
2704         return 0;
2705 }
2706 device_initcall(intel_pstate_init);
2707
2708 static int __init intel_pstate_setup(char *str)
2709 {
2710         if (!str)
2711                 return -EINVAL;
2712
2713         if (!strcmp(str, "disable")) {
2714                 no_load = 1;
2715         } else if (!strcmp(str, "passive")) {
2716                 pr_info("Passive mode enabled\n");
2717                 default_driver = &intel_cpufreq;
2718                 no_hwp = 1;
2719         }
2720         if (!strcmp(str, "no_hwp")) {
2721                 pr_info("HWP disabled\n");
2722                 no_hwp = 1;
2723         }
2724         if (!strcmp(str, "force"))
2725                 force_load = 1;
2726         if (!strcmp(str, "hwp_only"))
2727                 hwp_only = 1;
2728         if (!strcmp(str, "per_cpu_perf_limits"))
2729                 per_cpu_limits = true;
2730
2731 #ifdef CONFIG_ACPI
2732         if (!strcmp(str, "support_acpi_ppc"))
2733                 acpi_ppc = true;
2734 #endif
2735
2736         return 0;
2737 }
2738 early_param("intel_pstate", intel_pstate_setup);
2739
2740 MODULE_AUTHOR("Dirk Brandewie <[email protected]>");
2741 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2742 MODULE_LICENSE("GPL");