drivers/cpufreq/imx6q-cpufreq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/cpu.h>
   8 #include <linux/cpufreq.h>
   9 #include <linux/err.h>
  10 #include <linux/module.h>
  11 #include <linux/nvmem-consumer.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regulator/consumer.h>
  17
  18 #define PU_SOC_VOLTAGE_NORMAL   1250000
  19 #define PU_SOC_VOLTAGE_HIGH     1275000
  20 #define FREQ_1P2_GHZ            1200000000
  21
  22 static struct regulator *arm_reg;
  23 static struct regulator *pu_reg;
  24 static struct regulator *soc_reg;
  25
  26 enum IMX6_CPUFREQ_CLKS {
  27         ARM,
  28         PLL1_SYS,
  29         STEP,
  30         PLL1_SW,
  31         PLL2_PFD2_396M,
  32         /* MX6UL requires two more clks */
  33         PLL2_BUS,
  34         SECONDARY_SEL,
  35 };
  36 #define IMX6Q_CPUFREQ_CLK_NUM           5
  37 #define IMX6UL_CPUFREQ_CLK_NUM          7
  38
  39 static int num_clks;
  40 static struct clk_bulk_data clks[] = {
  41         { .id = "arm" },
  42         { .id = "pll1_sys" },
  43         { .id = "step" },
  44         { .id = "pll1_sw" },
  45         { .id = "pll2_pfd2_396m" },
  46         { .id = "pll2_bus" },
  47         { .id = "secondary_sel" },
  48 };
  49
  50 static struct device *cpu_dev;
  51 static bool free_opp;
  52 static struct cpufreq_frequency_table *freq_table;
  53 static unsigned int max_freq;
  54 static unsigned int transition_latency;
  55
  56 static u32 *imx6_soc_volt;
  57 static u32 soc_opp_count;
  58
  59 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  60 {
  61         struct dev_pm_opp *opp;
  62         unsigned long freq_hz, volt, volt_old;
  63         unsigned int old_freq, new_freq;
  64         bool pll1_sys_temp_enabled = false;
  65         int ret;
  66
  67         new_freq = freq_table[index].frequency;
  68         freq_hz = new_freq * 1000;
  69         old_freq = clk_get_rate(clks[ARM].clk) / 1000;
  70
  71         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  72         if (IS_ERR(opp)) {
  73                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  74                 return PTR_ERR(opp);
  75         }
  76
  77         volt = dev_pm_opp_get_voltage(opp);
  78         dev_pm_opp_put(opp);
  79
  80         volt_old = regulator_get_voltage(arm_reg);
  81
  82         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  83                 old_freq / 1000, volt_old / 1000,
  84                 new_freq / 1000, volt / 1000);
  85
  86         /* scaling up?  scale voltage before frequency */
  87         if (new_freq > old_freq) {
  88                 if (!IS_ERR(pu_reg)) {
  89                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  90                         if (ret) {
  91                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  92                                 return ret;
  93                         }
  94                 }
  95                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  96                 if (ret) {
  97                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  98                         return ret;
  99                 }
 100                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 101                 if (ret) {
 102                         dev_err(cpu_dev,
 103                                 "failed to scale vddarm up: %d\n", ret);
 104                         return ret;
 105                 }
 106         }
 107
 108         /*
 109          * The setpoints are selected per PLL/PDF frequencies, so we need to
 110          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 111          * PLL1 is as below.
 112          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
 113          * flow is slightly different from other i.MX6 OSC.
 114          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
 115          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 116          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 117          *  - Disable pll2_pfd2_396m_clk
 118          */
 119         if (of_machine_is_compatible("fsl,imx6ul") ||
 120             of_machine_is_compatible("fsl,imx6ull")) {
 121                 /*
 122                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
 123                  * CPU may run at higher than 528MHz, this will lead to
 124                  * the system unstable if the voltage is lower than the
 125                  * voltage of 528MHz, so lower the CPU frequency to one
 126                  * half before changing CPU frequency.
 127                  */
 128                 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
 129                 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 130                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
 131                         clk_set_parent(clks[SECONDARY_SEL].clk,
 132                                        clks[PLL2_BUS].clk);
 133                 else
 134                         clk_set_parent(clks[SECONDARY_SEL].clk,
 135                                        clks[PLL2_PFD2_396M].clk);
 136                 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
 137                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 138                 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
 139                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 140                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 141                 }
 142         } else {
 143                 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
 144                 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
 145                 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
 146                         clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
 147                         clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
 148                 } else {
 149                         /* pll1_sys needs to be enabled for divider rate change to work. */
 150                         pll1_sys_temp_enabled = true;
 151                         clk_prepare_enable(clks[PLL1_SYS].clk);
 152                 }
 153         }
 154
 155         /* Ensure the arm clock divider is what we expect */
 156         ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
 157         if (ret) {
 158                 int ret1;
 159
 160                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 161                 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
 162                 if (ret1)
 163                         dev_warn(cpu_dev,
 164                                  "failed to restore vddarm voltage: %d\n", ret1);
 165                 return ret;
 166         }
 167
 168         /* PLL1 is only needed until after ARM-PODF is set. */
 169         if (pll1_sys_temp_enabled)
 170                 clk_disable_unprepare(clks[PLL1_SYS].clk);
 171
 172         /* scaling down?  scale voltage after frequency */
 173         if (new_freq < old_freq) {
 174                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 175                 if (ret)
 176                         dev_warn(cpu_dev,
 177                                  "failed to scale vddarm down: %d\n", ret);
 178                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 179                 if (ret)
 180                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 181                 if (!IS_ERR(pu_reg)) {
 182                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 183                         if (ret)
 184                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 185                 }
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 192 {
 193         int ret;
 194
 195         policy->clk = clks[ARM].clk;
 196         ret = cpufreq_generic_init(policy, freq_table, transition_latency);
 197         policy->suspend_freq = max_freq;
 198         dev_pm_opp_of_register_em(policy->cpus);
 199
 200         return ret;
 201 }
 202
 203 static struct cpufreq_driver imx6q_cpufreq_driver = {
 204         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 205                  CPUFREQ_IS_COOLING_DEV,
 206         .verify = cpufreq_generic_frequency_table_verify,
 207         .target_index = imx6q_set_target,
 208         .get = cpufreq_generic_get,
 209         .init = imx6q_cpufreq_init,
 210         .name = "imx6q-cpufreq",
 211         .attr = cpufreq_generic_attr,
 212         .suspend = cpufreq_generic_suspend,
 213 };
 214
 215 #define OCOTP_CFG3                      0x440
 216 #define OCOTP_CFG3_SPEED_SHIFT          16
 217 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 218 #define OCOTP_CFG3_SPEED_996MHZ         0x2
 219 #define OCOTP_CFG3_SPEED_852MHZ         0x1
 220
 221 static void imx6q_opp_check_speed_grading(struct device *dev)
 222 {
 223         struct device_node *np;
 224         void __iomem *base;
 225         u32 val;
 226
 227         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 228         if (!np)
 229                 return;
 230
 231         base = of_iomap(np, 0);
 232         if (!base) {
 233                 dev_err(dev, "failed to map ocotp\n");
 234                 goto put_node;
 235         }
 236
 237         /*
 238          * SPEED_GRADING[1:0] defines the max speed of ARM:
 239          * 2b'11: 1200000000Hz;
 240          * 2b'10: 996000000Hz;
 241          * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
 242          * 2b'00: 792000000Hz;
 243          * We need to set the max speed of ARM according to fuse map.
 244          */
 245         val = readl_relaxed(base + OCOTP_CFG3);
 246         val >>= OCOTP_CFG3_SPEED_SHIFT;
 247         val &= 0x3;
 248
 249         if (val < OCOTP_CFG3_SPEED_996MHZ)
 250                 if (dev_pm_opp_disable(dev, 996000000))
 251                         dev_warn(dev, "failed to disable 996MHz OPP\n");
 252
 253         if (of_machine_is_compatible("fsl,imx6q") ||
 254             of_machine_is_compatible("fsl,imx6qp")) {
 255                 if (val != OCOTP_CFG3_SPEED_852MHZ)
 256                         if (dev_pm_opp_disable(dev, 852000000))
 257                                 dev_warn(dev, "failed to disable 852MHz OPP\n");
 258                 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
 259                         if (dev_pm_opp_disable(dev, 1200000000))
 260                                 dev_warn(dev, "failed to disable 1.2GHz OPP\n");
 261         }
 262         iounmap(base);
 263 put_node:
 264         of_node_put(np);
 265 }
 266
 267 #define OCOTP_CFG3_6UL_SPEED_696MHZ     0x2
 268 #define OCOTP_CFG3_6ULL_SPEED_792MHZ    0x2
 269 #define OCOTP_CFG3_6ULL_SPEED_900MHZ    0x3
 270
 271 static int imx6ul_opp_check_speed_grading(struct device *dev)
 272 {
 273         u32 val;
 274         int ret = 0;
 275
 276         if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
 277                 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
 278                 if (ret)
 279                         return ret;
 280         } else {
 281                 struct device_node *np;
 282                 void __iomem *base;
 283
 284                 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
 285                 if (!np)
 286                         return -ENOENT;
 287
 288                 base = of_iomap(np, 0);
 289                 of_node_put(np);
 290                 if (!base) {
 291                         dev_err(dev, "failed to map ocotp\n");
 292                         return -EFAULT;
 293                 }
 294
 295                 val = readl_relaxed(base + OCOTP_CFG3);
 296                 iounmap(base);
 297         }
 298
 299         /*
 300          * Speed GRADING[1:0] defines the max speed of ARM:
 301          * 2b'00: Reserved;
 302          * 2b'01: 528000000Hz;
 303          * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
 304          * 2b'11: 900000000Hz on i.MX6ULL only;
 305          * We need to set the max speed of ARM according to fuse map.
 306          */
 307         val >>= OCOTP_CFG3_SPEED_SHIFT;
 308         val &= 0x3;
 309
 310         if (of_machine_is_compatible("fsl,imx6ul")) {
 311                 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
 312                         if (dev_pm_opp_disable(dev, 696000000))
 313                                 dev_warn(dev, "failed to disable 696MHz OPP\n");
 314         }
 315
 316         if (of_machine_is_compatible("fsl,imx6ull")) {
 317                 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
 318                         if (dev_pm_opp_disable(dev, 792000000))
 319                                 dev_warn(dev, "failed to disable 792MHz OPP\n");
 320
 321                 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
 322                         if (dev_pm_opp_disable(dev, 900000000))
 323                                 dev_warn(dev, "failed to disable 900MHz OPP\n");
 324         }
 325
 326         return ret;
 327 }
 328
 329 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 330 {
 331         struct device_node *np;
 332         struct dev_pm_opp *opp;
 333         unsigned long min_volt, max_volt;
 334         int num, ret;
 335         const struct property *prop;
 336         const __be32 *val;
 337         u32 nr, i, j;
 338
 339         cpu_dev = get_cpu_device(0);
 340         if (!cpu_dev) {
 341                 pr_err("failed to get cpu0 device\n");
 342                 return -ENODEV;
 343         }
 344
 345         np = of_node_get(cpu_dev->of_node);
 346         if (!np) {
 347                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 348                 return -ENOENT;
 349         }
 350
 351         if (of_machine_is_compatible("fsl,imx6ul") ||
 352             of_machine_is_compatible("fsl,imx6ull"))
 353                 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
 354         else
 355                 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
 356
 357         ret = clk_bulk_get(cpu_dev, num_clks, clks);
 358         if (ret)
 359                 goto put_node;
 360
 361         arm_reg = regulator_get(cpu_dev, "arm");
 362         pu_reg = regulator_get_optional(cpu_dev, "pu");
 363         soc_reg = regulator_get(cpu_dev, "soc");
 364         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
 365                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
 366                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
 367                 ret = -EPROBE_DEFER;
 368                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
 369                 goto put_reg;
 370         }
 371         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
 372                 dev_err(cpu_dev, "failed to get regulators\n");
 373                 ret = -ENOENT;
 374                 goto put_reg;
 375         }
 376
 377         ret = dev_pm_opp_of_add_table(cpu_dev);
 378         if (ret < 0) {
 379                 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 380                 goto put_reg;
 381         }
 382
 383         if (of_machine_is_compatible("fsl,imx6ul") ||
 384             of_machine_is_compatible("fsl,imx6ull")) {
 385                 ret = imx6ul_opp_check_speed_grading(cpu_dev);
 386                 if (ret) {
 387                         if (ret == -EPROBE_DEFER)
 388                                 goto put_node;
 389
 390                         dev_err(cpu_dev, "failed to read ocotp: %d\n",
 391                                 ret);
 392                         goto put_node;
 393                 }
 394         } else {
 395                 imx6q_opp_check_speed_grading(cpu_dev);
 396         }
 397
 398         /* Because we have added the OPPs here, we must free them */
 399         free_opp = true;
 400         num = dev_pm_opp_get_opp_count(cpu_dev);
 401         if (num < 0) {
 402                 ret = num;
 403                 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 404                 goto out_free_opp;
 405         }
 406
 407         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 408         if (ret) {
 409                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 410                 goto out_free_opp;
 411         }
 412
 413         /* Make imx6_soc_volt array's size same as arm opp number */
 414         imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
 415                                      GFP_KERNEL);
 416         if (imx6_soc_volt == NULL) {
 417                 ret = -ENOMEM;
 418                 goto free_freq_table;
 419         }
 420
 421         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 422         if (!prop || !prop->value)
 423                 goto soc_opp_out;
 424
 425         /*
 426          * Each OPP is a set of tuples consisting of frequency and
 427          * voltage like <freq-kHz vol-uV>.
 428          */
 429         nr = prop->length / sizeof(u32);
 430         if (nr % 2 || (nr / 2) < num)
 431                 goto soc_opp_out;
 432
 433         for (j = 0; j < num; j++) {
 434                 val = prop->value;
 435                 for (i = 0; i < nr / 2; i++) {
 436                         unsigned long freq = be32_to_cpup(val++);
 437                         unsigned long volt = be32_to_cpup(val++);
 438                         if (freq_table[j].frequency == freq) {
 439                                 imx6_soc_volt[soc_opp_count++] = volt;
 440                                 break;
 441                         }
 442                 }
 443         }
 444
 445 soc_opp_out:
 446         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 447         if (soc_opp_count != num) {
 448                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 449                 for (j = 0; j < num; j++)
 450                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 451                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 452                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 453         }
 454
 455         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 456                 transition_latency = CPUFREQ_ETERNAL;
 457
 458         /*
 459          * Calculate the ramp time for max voltage change in the
 460          * VDDSOC and VDDPU regulators.
 461          */
 462         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 463         if (ret > 0)
 464                 transition_latency += ret * 1000;
 465         if (!IS_ERR(pu_reg)) {
 466                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 467                 if (ret > 0)
 468                         transition_latency += ret * 1000;
 469         }
 470
 471         /*
 472          * OPP is maintained in order of increasing frequency, and
 473          * freq_table initialised from OPP is therefore sorted in the
 474          * same order.
 475          */
 476         max_freq = freq_table[--num].frequency;
 477         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 478                                   freq_table[0].frequency * 1000, true);
 479         min_volt = dev_pm_opp_get_voltage(opp);
 480         dev_pm_opp_put(opp);
 481         opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
 482         max_volt = dev_pm_opp_get_voltage(opp);
 483         dev_pm_opp_put(opp);
 484
 485         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 486         if (ret > 0)
 487                 transition_latency += ret * 1000;
 488
 489         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 490         if (ret) {
 491                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 492                 goto free_freq_table;
 493         }
 494
 495         of_node_put(np);
 496         return 0;
 497
 498 free_freq_table:
 499         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 500 out_free_opp:
 501         if (free_opp)
 502                 dev_pm_opp_of_remove_table(cpu_dev);
 503 put_reg:
 504         if (!IS_ERR(arm_reg))
 505                 regulator_put(arm_reg);
 506         if (!IS_ERR(pu_reg))
 507                 regulator_put(pu_reg);
 508         if (!IS_ERR(soc_reg))
 509                 regulator_put(soc_reg);
 510
 511         clk_bulk_put(num_clks, clks);
 512 put_node:
 513         of_node_put(np);
 514
 515         return ret;
 516 }
 517
 518 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 519 {
 520         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 521         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 522         if (free_opp)
 523                 dev_pm_opp_of_remove_table(cpu_dev);
 524         regulator_put(arm_reg);
 525         if (!IS_ERR(pu_reg))
 526                 regulator_put(pu_reg);
 527         regulator_put(soc_reg);
 528
 529         clk_bulk_put(num_clks, clks);
 530
 531         return 0;
 532 }
 533
 534 static struct platform_driver imx6q_cpufreq_platdrv = {
 535         .driver = {
 536                 .name   = "imx6q-cpufreq",
 537         },
 538         .probe          = imx6q_cpufreq_probe,
 539         .remove         = imx6q_cpufreq_remove,
 540 };
 541 module_platform_driver(imx6q_cpufreq_platdrv);
 542
 543 MODULE_ALIAS("platform:imx6q-cpufreq");
 544 MODULE_AUTHOR("Shawn Guo <[email protected]>");
 545 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 546 MODULE_LICENSE("GPL");