2 * Thunderbolt control channel messages
5 * Copyright (C) 2017, Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #include <linux/types.h>
16 #include <linux/uuid.h>
18 enum tb_cfg_pkg_type {
22 TB_CFG_PKG_NOTIFY_ACK = 4,
24 TB_CFG_PKG_XDOMAIN_REQ = 6,
25 TB_CFG_PKG_XDOMAIN_RESP = 7,
26 TB_CFG_PKG_OVERRIDE = 8,
28 TB_CFG_PKG_ICM_EVENT = 10,
29 TB_CFG_PKG_ICM_CMD = 11,
30 TB_CFG_PKG_ICM_RESP = 12,
31 TB_CFG_PKG_PREPARE_TO_SLEEP = 0xd,
43 TB_CFG_ERROR_PORT_NOT_CONNECTED = 0,
44 TB_CFG_ERROR_LINK_ERROR = 1,
45 TB_CFG_ERROR_INVALID_CONFIG_SPACE = 2,
46 TB_CFG_ERROR_NO_SUCH_PORT = 4,
47 TB_CFG_ERROR_ACK_PLUG_EVENT = 7, /* send as reply to TB_CFG_PKG_EVENT */
48 TB_CFG_ERROR_LOOP = 8,
49 TB_CFG_ERROR_HEC_ERROR_DETECTED = 12,
50 TB_CFG_ERROR_FLOW_CONTROL_ERROR = 13,
54 struct tb_cfg_header {
56 u32 unknown:10; /* highest order bit is set on replies */
60 /* additional header for read/write packets */
61 struct tb_cfg_address {
62 u32 offset:13; /* in dwords */
63 u32 length:6; /* in dwords */
65 enum tb_cfg_space space:2;
66 u32 seq:2; /* sequence number */
70 /* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
72 struct tb_cfg_header header;
73 struct tb_cfg_address addr;
76 /* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
77 struct cfg_write_pkg {
78 struct tb_cfg_header header;
79 struct tb_cfg_address addr;
80 u32 data[64]; /* maximum size, tb_cfg_address.length has 6 bits */
83 /* TB_CFG_PKG_ERROR */
84 struct cfg_error_pkg {
85 struct tb_cfg_header header;
86 enum tb_cfg_error error:4;
89 u32 zero2:2; /* Both should be zero, still they are different fields. */
93 /* TB_CFG_PKG_EVENT */
94 struct cfg_event_pkg {
95 struct tb_cfg_header header;
101 /* TB_CFG_PKG_RESET */
102 struct cfg_reset_pkg {
103 struct tb_cfg_header header;
106 /* TB_CFG_PKG_PREPARE_TO_SLEEP */
108 struct tb_cfg_header header;
115 ICM_GET_TOPOLOGY = 0x1,
116 ICM_DRIVER_READY = 0x3,
117 ICM_APPROVE_DEVICE = 0x4,
118 ICM_CHALLENGE_DEVICE = 0x5,
119 ICM_ADD_DEVICE_KEY = 0x6,
123 enum icm_event_code {
124 ICM_EVENT_DEVICE_CONNECTED = 3,
125 ICM_EVENT_DEVICE_DISCONNECTED = 4,
128 struct icm_pkg_header {
135 #define ICM_FLAGS_ERROR BIT(0)
136 #define ICM_FLAGS_NO_KEY BIT(1)
137 #define ICM_FLAGS_SLEVEL_SHIFT 3
138 #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3)
140 struct icm_pkg_driver_ready {
141 struct icm_pkg_header hdr;
144 struct icm_pkg_driver_ready_response {
145 struct icm_pkg_header hdr;
151 /* Falcon Ridge & Alpine Ridge common messages */
153 struct icm_fr_pkg_get_topology {
154 struct icm_pkg_header hdr;
157 #define ICM_GET_TOPOLOGY_PACKETS 14
159 struct icm_fr_pkg_get_topology_response {
160 struct icm_pkg_header hdr;
165 u8 drom_i2c_address_index;
169 u32 port_hop_info[16];
172 #define ICM_SWITCH_USED BIT(0)
173 #define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1)
174 #define ICM_SWITCH_UPSTREAM_PORT_SHIFT 1
176 #define ICM_PORT_TYPE_MASK GENMASK(23, 0)
177 #define ICM_PORT_INDEX_SHIFT 24
178 #define ICM_PORT_INDEX_MASK GENMASK(31, 24)
180 struct icm_fr_event_device_connected {
181 struct icm_pkg_header hdr;
189 #define ICM_LINK_INFO_LINK_MASK 0x7
190 #define ICM_LINK_INFO_DEPTH_SHIFT 4
191 #define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4)
192 #define ICM_LINK_INFO_APPROVED BIT(8)
194 struct icm_fr_pkg_approve_device {
195 struct icm_pkg_header hdr;
202 struct icm_fr_event_device_disconnected {
203 struct icm_pkg_header hdr;
208 struct icm_fr_pkg_add_device_key {
209 struct icm_pkg_header hdr;
217 struct icm_fr_pkg_add_device_key_response {
218 struct icm_pkg_header hdr;
225 struct icm_fr_pkg_challenge_device {
226 struct icm_pkg_header hdr;
234 struct icm_fr_pkg_challenge_device_response {
235 struct icm_pkg_header hdr;
244 /* Alpine Ridge only messages */
246 struct icm_ar_pkg_get_route {
247 struct icm_pkg_header hdr;
252 struct icm_ar_pkg_get_route_response {
253 struct icm_pkg_header hdr;