drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "ta_ras_if.h"
  32 #include "amdgpu_ras_eeprom.h"
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET         (0x1 << 1)
  36 #define AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV      (0x1 << 2)
  37
  38 enum amdgpu_ras_block {
  39         AMDGPU_RAS_BLOCK__UMC = 0,
  40         AMDGPU_RAS_BLOCK__SDMA,
  41         AMDGPU_RAS_BLOCK__GFX,
  42         AMDGPU_RAS_BLOCK__MMHUB,
  43         AMDGPU_RAS_BLOCK__ATHUB,
  44         AMDGPU_RAS_BLOCK__PCIE_BIF,
  45         AMDGPU_RAS_BLOCK__HDP,
  46         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  47         AMDGPU_RAS_BLOCK__DF,
  48         AMDGPU_RAS_BLOCK__SMN,
  49         AMDGPU_RAS_BLOCK__SEM,
  50         AMDGPU_RAS_BLOCK__MP0,
  51         AMDGPU_RAS_BLOCK__MP1,
  52         AMDGPU_RAS_BLOCK__FUSE,
  53
  54         AMDGPU_RAS_BLOCK__LAST
  55 };
  56
  57 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  58 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  59
  60 enum amdgpu_ras_gfx_subblock {
  61         /* CPC */
  62         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  63         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  64                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  65         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  66         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  67         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  68         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  69         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  70         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  71         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  72         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  73                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  74         /* CPF */
  75         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  76         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  77                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  78         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  79         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  80         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  81         /* CPG */
  82         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  83         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
  84                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  85         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
  86         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  87         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  88         /* GDS */
  89         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  90         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  91         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
  92         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
  93         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
  94         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  95         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
  96                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  97         /* SPI */
  98         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
  99         /* SQ */
 100         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 101         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 102         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 103         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 104         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 105         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 106         /* SQC (3 ranges) */
 107         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 108         /* SQC range 0 */
 109         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 110                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 111         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 112                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 113         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 114         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 115         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 116         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 117         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 118         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 119         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 120                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 121         /* SQC range 1 */
 122         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 123         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 124                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 125         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 126         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 128         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 129         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 130         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 131         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 133         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 134                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 135         /* SQC range 2 */
 136         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 137         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 138                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 140         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 143         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 144         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 145         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 147         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 148                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 149         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 150                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 151         /* TA */
 152         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 153         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 154                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 155         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 156         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 157         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 158         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 159         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 160         /* TCA */
 161         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 162         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 163                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 164         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 165         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 166                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 167         /* TCC (5 sub-ranges) */
 168         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 169         /* TCC range 0 */
 170         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 171                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 172         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 173                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 174         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 175         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 176         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 177         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 178         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 179         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 180         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 181         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 182                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 183         /* TCC range 1 */
 184         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 185         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 186                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 187         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 188         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 189                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 190         /* TCC range 2 */
 191         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 192         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 193                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 195         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 198         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 199         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 200         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 201         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 202                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 203         /* TCC range 3 */
 204         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 205         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 206                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 207         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 208         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 209                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 210         /* TCC range 4 */
 211         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 212         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 213                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 215         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 216                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 217         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 218                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 219         /* TCI */
 220         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 221         /* TCP */
 222         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 223         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 224                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 225         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 226         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 227         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 228         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 229         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 230         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 231         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 232                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 233         /* TD */
 234         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 235         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 236                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 237         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 238         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 239         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 240         /* EA (3 sub-ranges) */
 241         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 242         /* EA range 0 */
 243         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 244                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 245         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 246                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 247         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 248         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 249         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 250         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 251         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 252         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 253         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 254         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 255                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 256         /* EA range 1 */
 257         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 258         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 259                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 260         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 261         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 262         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 263         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 264         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 265         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 266         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 267                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 268         /* EA range 2 */
 269         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 270         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 271                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 272         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 273         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 274         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 275         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 276                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 277         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 278                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 279         /* UTC VM L2 bank */
 280         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 281         /* UTC VM walker */
 282         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 283         /* UTC ATC L2 2MB cache */
 284         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 285         /* UTC ATC L2 4KB cache */
 286         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 287         AMDGPU_RAS_BLOCK__GFX_MAX
 288 };
 289
 290 enum amdgpu_ras_error_type {
 291         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 292         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 293         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 294         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 295         AMDGPU_RAS_ERROR__POISON                                                = 8,
 296 };
 297
 298 enum amdgpu_ras_ret {
 299         AMDGPU_RAS_SUCCESS = 0,
 300         AMDGPU_RAS_FAIL,
 301         AMDGPU_RAS_UE,
 302         AMDGPU_RAS_CE,
 303         AMDGPU_RAS_PT,
 304 };
 305
 306 struct ras_common_if {
 307         enum amdgpu_ras_block block;
 308         enum amdgpu_ras_error_type type;
 309         uint32_t sub_block_index;
 310         /* block name */
 311         char name[32];
 312 };
 313
 314 struct amdgpu_ras {
 315         /* ras infrastructure */
 316         /* for ras itself. */
 317         uint32_t hw_supported;
 318         /* for IP to check its ras ability. */
 319         uint32_t supported;
 320         uint32_t features;
 321         struct list_head head;
 322         /* debugfs */
 323         struct dentry *dir;
 324         /* sysfs */
 325         struct device_attribute features_attr;
 326         struct bin_attribute badpages_attr;
 327         /* block array */
 328         struct ras_manager *objs;
 329
 330         /* gpu recovery */
 331         struct work_struct recovery_work;
 332         atomic_t in_recovery;
 333         struct amdgpu_device *adev;
 334         /* error handler data */
 335         struct ras_err_handler_data *eh_data;
 336         struct mutex recovery_lock;
 337
 338         uint32_t flags;
 339         bool reboot;
 340         struct amdgpu_ras_eeprom_control eeprom_control;
 341
 342         bool error_query_ready;
 343
 344         /* bad page count threshold */
 345         uint32_t bad_page_cnt_threshold;
 346
 347         /* disable ras error count harvest in recovery */
 348         bool disable_ras_err_cnt_harvest;
 349 };
 350
 351 struct ras_fs_data {
 352         char sysfs_name[32];
 353         char debugfs_name[32];
 354 };
 355
 356 struct ras_err_data {
 357         unsigned long ue_count;
 358         unsigned long ce_count;
 359         unsigned long err_addr_cnt;
 360         struct eeprom_table_record *err_addr;
 361 };
 362
 363 struct ras_err_handler_data {
 364         /* point to bad page records array */
 365         struct eeprom_table_record *bps;
 366         /* point to reserved bo array */
 367         struct amdgpu_bo **bps_bo;
 368         /* the count of entries */
 369         int count;
 370         /* the space can place new entries */
 371         int space_left;
 372         /* last reserved entry's index + 1 */
 373         int last_reserved;
 374 };
 375
 376 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 377                 void *err_data,
 378                 struct amdgpu_iv_entry *entry);
 379
 380 struct ras_ih_data {
 381         /* interrupt bottom half */
 382         struct work_struct ih_work;
 383         int inuse;
 384         /* IP callback */
 385         ras_ih_cb cb;
 386         /* full of entries */
 387         unsigned char *ring;
 388         unsigned int ring_size;
 389         unsigned int element_size;
 390         unsigned int aligned_element_size;
 391         unsigned int rptr;
 392         unsigned int wptr;
 393 };
 394
 395 struct ras_manager {
 396         struct ras_common_if head;
 397         /* reference count */
 398         int use;
 399         /* ras block link */
 400         struct list_head node;
 401         /* the device */
 402         struct amdgpu_device *adev;
 403         /* debugfs */
 404         struct dentry *ent;
 405         /* sysfs */
 406         struct device_attribute sysfs_attr;
 407         int attr_inuse;
 408
 409         /* fs node name */
 410         struct ras_fs_data fs_data;
 411
 412         /* IH data */
 413         struct ras_ih_data ih_data;
 414
 415         struct ras_err_data err_data;
 416 };
 417
 418 struct ras_badpage {
 419         unsigned int bp;
 420         unsigned int size;
 421         unsigned int flags;
 422 };
 423
 424 /* interfaces for IP */
 425 struct ras_fs_if {
 426         struct ras_common_if head;
 427         char sysfs_name[32];
 428         char debugfs_name[32];
 429 };
 430
 431 struct ras_query_if {
 432         struct ras_common_if head;
 433         unsigned long ue_count;
 434         unsigned long ce_count;
 435 };
 436
 437 struct ras_inject_if {
 438         struct ras_common_if head;
 439         uint64_t address;
 440         uint64_t value;
 441 };
 442
 443 struct ras_cure_if {
 444         struct ras_common_if head;
 445         uint64_t address;
 446 };
 447
 448 struct ras_ih_if {
 449         struct ras_common_if head;
 450         ras_ih_cb cb;
 451 };
 452
 453 struct ras_dispatch_if {
 454         struct ras_common_if head;
 455         struct amdgpu_iv_entry *entry;
 456 };
 457
 458 struct ras_debug_if {
 459         union {
 460                 struct ras_common_if head;
 461                 struct ras_inject_if inject;
 462         };
 463         int op;
 464 };
 465 /* work flow
 466  * vbios
 467  * 1: ras feature enable (enabled by default)
 468  * psp
 469  * 2: ras framework init (in ip_init)
 470  * IP
 471  * 3: IH add
 472  * 4: debugfs/sysfs create
 473  * 5: query/inject
 474  * 6: debugfs/sysfs remove
 475  * 7: IH remove
 476  * 8: feature disable
 477  */
 478
 479 #define amdgpu_ras_get_context(adev)            ((adev)->psp.ras.ras)
 480 #define amdgpu_ras_set_context(adev, ras_con)   ((adev)->psp.ras.ras = (ras_con))
 481
 482 /* check if ras is supported on block, say, sdma, gfx */
 483 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 484                 unsigned int block)
 485 {
 486         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 487
 488         if (block >= AMDGPU_RAS_BLOCK_COUNT)
 489                 return 0;
 490         return ras && (ras->supported & (1 << block));
 491 }
 492
 493 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 494 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
 495                 unsigned int block);
 496
 497 void amdgpu_ras_resume(struct amdgpu_device *adev);
 498 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 499
 500 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 501                 bool is_ce);
 502
 503 bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev);
 504
 505 /* error handling functions */
 506 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 507                 struct eeprom_table_record *bps, int pages);
 508
 509 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
 510
 511 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 512 {
 513         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 514
 515         /*
 516          * Save bad page to eeprom before gpu reset, i2c may be unstable
 517          * in gpu reset.
 518          *
 519          * Also, exclude the case when ras recovery issuer is
 520          * eeprom page write itself.
 521          */
 522         if (!(ras->flags & AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV) && in_task())
 523                 amdgpu_ras_reserve_bad_pages(adev);
 524
 525         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
 526                 schedule_work(&ras->recovery_work);
 527         return 0;
 528 }
 529
 530 static inline enum ta_ras_block
 531 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 532         switch (block) {
 533         case AMDGPU_RAS_BLOCK__UMC:
 534                 return TA_RAS_BLOCK__UMC;
 535         case AMDGPU_RAS_BLOCK__SDMA:
 536                 return TA_RAS_BLOCK__SDMA;
 537         case AMDGPU_RAS_BLOCK__GFX:
 538                 return TA_RAS_BLOCK__GFX;
 539         case AMDGPU_RAS_BLOCK__MMHUB:
 540                 return TA_RAS_BLOCK__MMHUB;
 541         case AMDGPU_RAS_BLOCK__ATHUB:
 542                 return TA_RAS_BLOCK__ATHUB;
 543         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 544                 return TA_RAS_BLOCK__PCIE_BIF;
 545         case AMDGPU_RAS_BLOCK__HDP:
 546                 return TA_RAS_BLOCK__HDP;
 547         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 548                 return TA_RAS_BLOCK__XGMI_WAFL;
 549         case AMDGPU_RAS_BLOCK__DF:
 550                 return TA_RAS_BLOCK__DF;
 551         case AMDGPU_RAS_BLOCK__SMN:
 552                 return TA_RAS_BLOCK__SMN;
 553         case AMDGPU_RAS_BLOCK__SEM:
 554                 return TA_RAS_BLOCK__SEM;
 555         case AMDGPU_RAS_BLOCK__MP0:
 556                 return TA_RAS_BLOCK__MP0;
 557         case AMDGPU_RAS_BLOCK__MP1:
 558                 return TA_RAS_BLOCK__MP1;
 559         case AMDGPU_RAS_BLOCK__FUSE:
 560                 return TA_RAS_BLOCK__FUSE;
 561         default:
 562                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 563                 return TA_RAS_BLOCK__UMC;
 564         }
 565 }
 566
 567 static inline enum ta_ras_error_type
 568 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 569         switch (error) {
 570         case AMDGPU_RAS_ERROR__NONE:
 571                 return TA_RAS_ERROR__NONE;
 572         case AMDGPU_RAS_ERROR__PARITY:
 573                 return TA_RAS_ERROR__PARITY;
 574         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 575                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 576         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 577                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 578         case AMDGPU_RAS_ERROR__POISON:
 579                 return TA_RAS_ERROR__POISON;
 580         default:
 581                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 582                 return TA_RAS_ERROR__NONE;
 583         }
 584 }
 585
 586 /* called in ip_init and ip_fini */
 587 int amdgpu_ras_init(struct amdgpu_device *adev);
 588 int amdgpu_ras_fini(struct amdgpu_device *adev);
 589 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 590 int amdgpu_ras_late_init(struct amdgpu_device *adev,
 591                          struct ras_common_if *ras_block,
 592                          struct ras_fs_if *fs_info,
 593                          struct ras_ih_if *ih_info);
 594 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
 595                           struct ras_common_if *ras_block,
 596                           struct ras_ih_if *ih_info);
 597
 598 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 599                 struct ras_common_if *head, bool enable);
 600
 601 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 602                 struct ras_common_if *head, bool enable);
 603
 604 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 605                 struct ras_fs_if *head);
 606
 607 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 608                 struct ras_common_if *head);
 609
 610 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
 611                 struct ras_fs_if *head);
 612
 613 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 614
 615 void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
 616                 struct ras_common_if *head);
 617
 618 int amdgpu_ras_error_query(struct amdgpu_device *adev,
 619                 struct ras_query_if *info);
 620
 621 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 622                 struct ras_inject_if *info);
 623
 624 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 625                 struct ras_ih_if *info);
 626
 627 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 628                 struct ras_ih_if *info);
 629
 630 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 631                 struct ras_dispatch_if *info);
 632
 633 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 634                 struct ras_common_if *head);
 635
 636 extern atomic_t amdgpu_ras_in_intr;
 637
 638 static inline bool amdgpu_ras_intr_triggered(void)
 639 {
 640         return !!atomic_read(&amdgpu_ras_in_intr);
 641 }
 642
 643 static inline void amdgpu_ras_intr_cleared(void)
 644 {
 645         atomic_set(&amdgpu_ras_in_intr, 0);
 646 }
 647
 648 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 649
 650 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 651
 652 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 653 #endif