drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 #ifndef __AMDGPU_PSP_H__
  26 #define __AMDGPU_PSP_H__
  27
  28 #include "amdgpu.h"
  29 #include "psp_gfx_if.h"
  30 #include "ta_xgmi_if.h"
  31 #include "ta_ras_if.h"
  32 #include "ta_rap_if.h"
  33
  34 #define PSP_FENCE_BUFFER_SIZE   0x1000
  35 #define PSP_CMD_BUFFER_SIZE     0x1000
  36 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
  37 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
  38 #define PSP_1_MEG               0x100000
  39 #define PSP_TMR_SIZE    0x400000
  40 #define PSP_HDCP_SHARED_MEM_SIZE        0x4000
  41 #define PSP_DTM_SHARED_MEM_SIZE 0x4000
  42 #define PSP_RAP_SHARED_MEM_SIZE 0x4000
  43 #define PSP_SHARED_MEM_SIZE             0x4000
  44
  45 struct psp_context;
  46 struct psp_xgmi_node_info;
  47 struct psp_xgmi_topology_info;
  48
  49 enum psp_bootloader_cmd {
  50         PSP_BL__LOAD_SYSDRV             = 0x10000,
  51         PSP_BL__LOAD_SOSDRV             = 0x20000,
  52         PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
  53         PSP_BL__DRAM_LONG_TRAIN         = 0x100000,
  54         PSP_BL__DRAM_SHORT_TRAIN        = 0x200000,
  55         PSP_BL__LOAD_TOS_SPL_TABLE      = 0x10000000,
  56 };
  57
  58 enum psp_ring_type
  59 {
  60         PSP_RING_TYPE__INVALID = 0,
  61         /*
  62          * These values map to the way the PSP kernel identifies the
  63          * rings.
  64          */
  65         PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
  66         PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
  67 };
  68
  69 struct psp_ring
  70 {
  71         enum psp_ring_type              ring_type;
  72         struct psp_gfx_rb_frame         *ring_mem;
  73         uint64_t                        ring_mem_mc_addr;
  74         void                            *ring_mem_handle;
  75         uint32_t                        ring_size;
  76 };
  77
  78 /* More registers may will be supported */
  79 enum psp_reg_prog_id {
  80         PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
  81         PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
  82         PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
  83         PSP_REG_LAST
  84 };
  85
  86 struct psp_funcs
  87 {
  88         int (*init_microcode)(struct psp_context *psp);
  89         int (*bootloader_load_kdb)(struct psp_context *psp);
  90         int (*bootloader_load_spl)(struct psp_context *psp);
  91         int (*bootloader_load_sysdrv)(struct psp_context *psp);
  92         int (*bootloader_load_sos)(struct psp_context *psp);
  93         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
  94         int (*ring_create)(struct psp_context *psp,
  95                            enum psp_ring_type ring_type);
  96         int (*ring_stop)(struct psp_context *psp,
  97                             enum psp_ring_type ring_type);
  98         int (*ring_destroy)(struct psp_context *psp,
  99                             enum psp_ring_type ring_type);
 100         bool (*smu_reload_quirk)(struct psp_context *psp);
 101         int (*mode1_reset)(struct psp_context *psp);
 102         int (*mem_training)(struct psp_context *psp, uint32_t ops);
 103         uint32_t (*ring_get_wptr)(struct psp_context *psp);
 104         void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
 105         int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr);
 106         int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
 107 };
 108
 109 #define AMDGPU_XGMI_MAX_CONNECTED_NODES         64
 110 struct psp_xgmi_node_info {
 111         uint64_t                                node_id;
 112         uint8_t                                 num_hops;
 113         uint8_t                                 is_sharing_enabled;
 114         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
 115 };
 116
 117 struct psp_xgmi_topology_info {
 118         uint32_t                        num_nodes;
 119         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 120 };
 121
 122 struct psp_asd_context {
 123         bool                    asd_initialized;
 124         uint32_t                session_id;
 125 };
 126
 127 struct psp_xgmi_context {
 128         uint8_t                         initialized;
 129         uint32_t                        session_id;
 130         struct amdgpu_bo                *xgmi_shared_bo;
 131         uint64_t                        xgmi_shared_mc_addr;
 132         void                            *xgmi_shared_buf;
 133         struct psp_xgmi_topology_info   top_info;
 134 };
 135
 136 struct psp_ras_context {
 137         /*ras fw*/
 138         bool                    ras_initialized;
 139         uint32_t                session_id;
 140         struct amdgpu_bo        *ras_shared_bo;
 141         uint64_t                ras_shared_mc_addr;
 142         void                    *ras_shared_buf;
 143         struct amdgpu_ras       *ras;
 144 };
 145
 146 struct psp_hdcp_context {
 147         bool                    hdcp_initialized;
 148         uint32_t                session_id;
 149         struct amdgpu_bo        *hdcp_shared_bo;
 150         uint64_t                hdcp_shared_mc_addr;
 151         void                    *hdcp_shared_buf;
 152         struct mutex            mutex;
 153 };
 154
 155 struct psp_dtm_context {
 156         bool                    dtm_initialized;
 157         uint32_t                session_id;
 158         struct amdgpu_bo        *dtm_shared_bo;
 159         uint64_t                dtm_shared_mc_addr;
 160         void                    *dtm_shared_buf;
 161         struct mutex            mutex;
 162 };
 163
 164 struct psp_rap_context {
 165         bool                    rap_initialized;
 166         uint32_t                session_id;
 167         struct amdgpu_bo        *rap_shared_bo;
 168         uint64_t                rap_shared_mc_addr;
 169         void                    *rap_shared_buf;
 170         struct mutex            mutex;
 171 };
 172
 173 #define MEM_TRAIN_SYSTEM_SIGNATURE              0x54534942
 174 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES   0x1000
 175 #define GDDR6_MEM_TRAINING_OFFSET               0x8000
 176 /*Define the VRAM size that will be encroached by BIST training.*/
 177 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE      0x2000000
 178
 179 enum psp_memory_training_init_flag {
 180         PSP_MEM_TRAIN_NOT_SUPPORT       = 0x0,
 181         PSP_MEM_TRAIN_SUPPORT           = 0x1,
 182         PSP_MEM_TRAIN_INIT_FAILED       = 0x2,
 183         PSP_MEM_TRAIN_RESERVE_SUCCESS   = 0x4,
 184         PSP_MEM_TRAIN_INIT_SUCCESS      = 0x8,
 185 };
 186
 187 enum psp_memory_training_ops {
 188         PSP_MEM_TRAIN_SEND_LONG_MSG     = 0x1,
 189         PSP_MEM_TRAIN_SAVE              = 0x2,
 190         PSP_MEM_TRAIN_RESTORE           = 0x4,
 191         PSP_MEM_TRAIN_SEND_SHORT_MSG    = 0x8,
 192         PSP_MEM_TRAIN_COLD_BOOT         = PSP_MEM_TRAIN_SEND_LONG_MSG,
 193         PSP_MEM_TRAIN_RESUME            = PSP_MEM_TRAIN_SEND_SHORT_MSG,
 194 };
 195
 196 struct psp_memory_training_context {
 197         /*training data size*/
 198         u64 train_data_size;
 199         /*
 200          * sys_cache
 201          * cpu virtual address
 202          * system memory buffer that used to store the training data.
 203          */
 204         void *sys_cache;
 205
 206         /*vram offset of the p2c training data*/
 207         u64 p2c_train_data_offset;
 208
 209         /*vram offset of the c2p training data*/
 210         u64 c2p_train_data_offset;
 211         struct amdgpu_bo *c2p_bo;
 212
 213         enum psp_memory_training_init_flag init;
 214         u32 training_cnt;
 215 };
 216
 217 struct psp_context
 218 {
 219         struct amdgpu_device            *adev;
 220         struct psp_ring                 km_ring;
 221         struct psp_gfx_cmd_resp         *cmd;
 222
 223         const struct psp_funcs          *funcs;
 224
 225         /* firmware buffer */
 226         struct amdgpu_bo                *fw_pri_bo;
 227         uint64_t                        fw_pri_mc_addr;
 228         void                            *fw_pri_buf;
 229
 230         /* sos firmware */
 231         const struct firmware           *sos_fw;
 232         uint32_t                        sos_fw_version;
 233         uint32_t                        sos_feature_version;
 234         uint32_t                        sys_bin_size;
 235         uint32_t                        sos_bin_size;
 236         uint32_t                        toc_bin_size;
 237         uint32_t                        kdb_bin_size;
 238         uint32_t                        spl_bin_size;
 239         uint8_t                         *sys_start_addr;
 240         uint8_t                         *sos_start_addr;
 241         uint8_t                         *toc_start_addr;
 242         uint8_t                         *kdb_start_addr;
 243         uint8_t                         *spl_start_addr;
 244
 245         /* tmr buffer */
 246         struct amdgpu_bo                *tmr_bo;
 247         uint64_t                        tmr_mc_addr;
 248
 249         /* asd firmware */
 250         const struct firmware           *asd_fw;
 251         uint32_t                        asd_fw_version;
 252         uint32_t                        asd_feature_version;
 253         uint32_t                        asd_ucode_size;
 254         uint8_t                         *asd_start_addr;
 255
 256         /* fence buffer */
 257         struct amdgpu_bo                *fence_buf_bo;
 258         uint64_t                        fence_buf_mc_addr;
 259         void                            *fence_buf;
 260
 261         /* cmd buffer */
 262         struct amdgpu_bo                *cmd_buf_bo;
 263         uint64_t                        cmd_buf_mc_addr;
 264         struct psp_gfx_cmd_resp         *cmd_buf_mem;
 265
 266         /* fence value associated with cmd buffer */
 267         atomic_t                        fence_value;
 268         /* flag to mark whether gfx fw autoload is supported or not */
 269         bool                            autoload_supported;
 270         /* flag to mark whether df cstate management centralized to PMFW */
 271         bool                            pmfw_centralized_cstate_management;
 272
 273         /* xgmi ta firmware and buffer */
 274         const struct firmware           *ta_fw;
 275         uint32_t                        ta_fw_version;
 276         uint32_t                        ta_xgmi_ucode_version;
 277         uint32_t                        ta_xgmi_ucode_size;
 278         uint8_t                         *ta_xgmi_start_addr;
 279         uint32_t                        ta_ras_ucode_version;
 280         uint32_t                        ta_ras_ucode_size;
 281         uint8_t                         *ta_ras_start_addr;
 282
 283         uint32_t                        ta_hdcp_ucode_version;
 284         uint32_t                        ta_hdcp_ucode_size;
 285         uint8_t                         *ta_hdcp_start_addr;
 286
 287         uint32_t                        ta_dtm_ucode_version;
 288         uint32_t                        ta_dtm_ucode_size;
 289         uint8_t                         *ta_dtm_start_addr;
 290
 291         uint32_t                        ta_rap_ucode_version;
 292         uint32_t                        ta_rap_ucode_size;
 293         uint8_t                         *ta_rap_start_addr;
 294
 295         struct psp_asd_context          asd_context;
 296         struct psp_xgmi_context         xgmi_context;
 297         struct psp_ras_context          ras;
 298         struct psp_hdcp_context         hdcp_context;
 299         struct psp_dtm_context          dtm_context;
 300         struct psp_rap_context          rap_context;
 301         struct mutex                    mutex;
 302         struct psp_memory_training_context mem_train_ctx;
 303 };
 304
 305 struct amdgpu_psp_funcs {
 306         bool (*check_fw_loading_status)(struct amdgpu_device *adev,
 307                                         enum AMDGPU_UCODE_ID);
 308 };
 309
 310
 311 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 312 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 313 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 314 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
 315 #define psp_init_microcode(psp) \
 316                 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
 317 #define psp_bootloader_load_kdb(psp) \
 318                 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 319 #define psp_bootloader_load_spl(psp) \
 320                 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
 321 #define psp_bootloader_load_sysdrv(psp) \
 322                 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 323 #define psp_bootloader_load_sos(psp) \
 324                 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 325 #define psp_smu_reload_quirk(psp) \
 326                 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
 327 #define psp_mode1_reset(psp) \
 328                 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
 329 #define psp_mem_training(psp, ops) \
 330         ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
 331
 332 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
 333 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
 334
 335 #define psp_load_usbc_pd_fw(psp, dma_addr) \
 336         ((psp)->funcs->load_usbc_pd_fw ? \
 337         (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL)
 338
 339 #define psp_read_usbc_pd_fw(psp, fw_ver) \
 340         ((psp)->funcs->read_usbc_pd_fw ? \
 341         (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
 342
 343 extern const struct amd_ip_funcs psp_ip_funcs;
 344
 345 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
 346 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 347                         uint32_t field_val, uint32_t mask, bool check_changed);
 348
 349 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 350 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 351
 352 int psp_gpu_reset(struct amdgpu_device *adev);
 353 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
 354                         uint64_t cmd_gpu_addr, int cmd_size);
 355
 356 int psp_xgmi_initialize(struct psp_context *psp);
 357 int psp_xgmi_terminate(struct psp_context *psp);
 358 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 359 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
 360 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
 361 int psp_xgmi_get_topology_info(struct psp_context *psp,
 362                                int number_devices,
 363                                struct psp_xgmi_topology_info *topology);
 364 int psp_xgmi_set_topology_info(struct psp_context *psp,
 365                                int number_devices,
 366                                struct psp_xgmi_topology_info *topology);
 367
 368 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 369 int psp_ras_enable_features(struct psp_context *psp,
 370                 union ta_ras_cmd_input *info, bool enable);
 371 int psp_ras_trigger_error(struct psp_context *psp,
 372                           struct ta_ras_trigger_error_input *info);
 373
 374 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 375 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 376 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 377
 378 int psp_rlc_autoload_start(struct psp_context *psp);
 379
 380 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 381 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 382                 uint32_t value);
 383 int psp_ring_cmd_submit(struct psp_context *psp,
 384                         uint64_t cmd_buf_mc_addr,
 385                         uint64_t fence_mc_addr,
 386                         int index);
 387 int psp_init_asd_microcode(struct psp_context *psp,
 388                            const char *chip_name);
 389 int psp_init_sos_microcode(struct psp_context *psp,
 390                            const char *chip_name);
 391 int psp_init_ta_microcode(struct psp_context *psp,
 392                           const char *chip_name);
 393 #endif