drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_psp.h"
  25 #include "amdgpu_ucode.h"
  26 #include "soc15_common.h"
  27 #include "psp_v13_0_4.h"
  28
  29 #include "mp/mp_13_0_4_offset.h"
  30 #include "mp/mp_13_0_4_sh_mask.h"
  31
  32 MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
  33 MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
  34
  35 static int psp_v13_0_4_init_microcode(struct psp_context *psp)
  36 {
  37         struct amdgpu_device *adev = psp->adev;
  38         const char *chip_name;
  39         char ucode_prefix[30];
  40         int err = 0;
  41
  42         switch (adev->ip_versions[MP0_HWIP][0]) {
  43         case IP_VERSION(13, 0, 4):
  44                 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  45                 chip_name = ucode_prefix;
  46                 break;
  47         default:
  48                 BUG();
  49         }
  50
  51         switch (adev->ip_versions[MP0_HWIP][0]) {
  52         case IP_VERSION(13, 0, 4):
  53                 err = psp_init_toc_microcode(psp, chip_name);
  54                 if (err)
  55                         return err;
  56                 err = psp_init_ta_microcode(psp, chip_name);
  57                 if (err)
  58                         return err;
  59                 break;
  60         default:
  61                 BUG();
  62         }
  63
  64         return 0;
  65 }
  66
  67 static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70         uint32_t sol_reg;
  71
  72         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
  73
  74         return sol_reg != 0x0;
  75 }
  76
  77 static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80
  81         int ret;
  82         int retry_loop;
  83
  84         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
  85                 /* Wait for bootloader to signify that is
  86                     ready having bit 31 of C2PMSG_35 set to 1 */
  87                 ret = psp_wait_for(psp,
  88                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
  89                                    0x80000000,
  90                                    0x80000000,
  91                                    false);
  92
  93                 if (ret == 0)
  94                         return 0;
  95         }
  96
  97         return ret;
  98 }
  99
 100 static int psp_v13_0_4_bootloader_load_component(struct psp_context     *psp,
 101                                                struct psp_bin_desc      *bin_desc,
 102                                                enum psp_bootloader_cmd  bl_cmd)
 103 {
 104         int ret;
 105         uint32_t psp_gfxdrv_command_reg = 0;
 106         struct amdgpu_device *adev = psp->adev;
 107
 108         /* Check tOS sign of life register to confirm sys driver and sOS
 109          * are already been loaded.
 110          */
 111         if (psp_v13_0_4_is_sos_alive(psp))
 112                 return 0;
 113
 114         ret = psp_v13_0_4_wait_for_bootloader(psp);
 115         if (ret)
 116                 return ret;
 117
 118         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 119
 120         /* Copy PSP KDB binary to memory */
 121         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 122
 123         /* Provide the PSP KDB to bootloader */
 124         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 125                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 126         psp_gfxdrv_command_reg = bl_cmd;
 127         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 128                psp_gfxdrv_command_reg);
 129
 130         ret = psp_v13_0_4_wait_for_bootloader(psp);
 131
 132         return ret;
 133 }
 134
 135 static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
 136 {
 137         return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 138 }
 139
 140 static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
 141 {
 142         return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 143 }
 144
 145 static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
 146 {
 147         return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 148 }
 149
 150 static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
 151 {
 152         return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 153 }
 154
 155 static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
 156 {
 157         return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 158 }
 159
 160 static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
 161 {
 162         return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 163 }
 164
 165 static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
 166 {
 167         int ret;
 168         unsigned int psp_gfxdrv_command_reg = 0;
 169         struct amdgpu_device *adev = psp->adev;
 170
 171         /* Check sOS sign of life register to confirm sys driver and sOS
 172          * are already been loaded.
 173          */
 174         if (psp_v13_0_4_is_sos_alive(psp))
 175                 return 0;
 176
 177         ret = psp_v13_0_4_wait_for_bootloader(psp);
 178         if (ret)
 179                 return ret;
 180
 181         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 182
 183         /* Copy Secure OS binary to PSP memory */
 184         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 185
 186         /* Provide the PSP secure OS to bootloader */
 187         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 188                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 189         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 190         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 191                psp_gfxdrv_command_reg);
 192
 193         /* there might be handshake issue with hardware which needs delay */
 194         mdelay(20);
 195         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 196                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 197                            0, true);
 198
 199         return ret;
 200 }
 201
 202 static int psp_v13_0_4_ring_init(struct psp_context *psp,
 203                               enum psp_ring_type ring_type)
 204 {
 205         int ret = 0;
 206         struct psp_ring *ring;
 207         struct amdgpu_device *adev = psp->adev;
 208
 209         ring = &psp->km_ring;
 210
 211         ring->ring_type = ring_type;
 212
 213         /* allocate 4k Page of Local Frame Buffer memory for ring */
 214         ring->ring_size = 0x1000;
 215         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 216                                       AMDGPU_GEM_DOMAIN_VRAM,
 217                                       &adev->firmware.rbuf,
 218                                       &ring->ring_mem_mc_addr,
 219                                       (void **)&ring->ring_mem);
 220         if (ret) {
 221                 ring->ring_size = 0;
 222                 return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int psp_v13_0_4_ring_stop(struct psp_context *psp,
 229                                enum psp_ring_type ring_type)
 230 {
 231         int ret = 0;
 232         struct amdgpu_device *adev = psp->adev;
 233
 234         if (amdgpu_sriov_vf(adev)) {
 235                 /* Write the ring destroy command*/
 236                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 237                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 238                 /* there might be handshake issue with hardware which needs delay */
 239                 mdelay(20);
 240                 /* Wait for response flag (bit 31) */
 241                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 242                                    0x80000000, 0x80000000, false);
 243         } else {
 244                 /* Write the ring destroy command*/
 245                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 246                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 247                 /* there might be handshake issue with hardware which needs delay */
 248                 mdelay(20);
 249                 /* Wait for response flag (bit 31) */
 250                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 251                                    0x80000000, 0x80000000, false);
 252         }
 253
 254         return ret;
 255 }
 256
 257 static int psp_v13_0_4_ring_create(struct psp_context *psp,
 258                                  enum psp_ring_type ring_type)
 259 {
 260         int ret = 0;
 261         unsigned int psp_ring_reg = 0;
 262         struct psp_ring *ring = &psp->km_ring;
 263         struct amdgpu_device *adev = psp->adev;
 264
 265         if (amdgpu_sriov_vf(adev)) {
 266                 ret = psp_v13_0_4_ring_stop(psp, ring_type);
 267                 if (ret) {
 268                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 269                         return ret;
 270                 }
 271
 272                 /* Write low address of the ring to C2PMSG_102 */
 273                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 274                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 275                 /* Write high address of the ring to C2PMSG_103 */
 276                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 277                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 278
 279                 /* Write the ring initialization command to C2PMSG_101 */
 280                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 281                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 282
 283                 /* there might be handshake issue with hardware which needs delay */
 284                 mdelay(20);
 285
 286                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 287                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 288                                    0x80000000, 0x8000FFFF, false);
 289
 290         } else {
 291                 /* Wait for sOS ready for ring creation */
 292                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 293                                    0x80000000, 0x80000000, false);
 294                 if (ret) {
 295                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 296                         return ret;
 297                 }
 298
 299                 /* Write low address of the ring to C2PMSG_69 */
 300                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 301                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 302                 /* Write high address of the ring to C2PMSG_70 */
 303                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 304                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 305                 /* Write size of ring to C2PMSG_71 */
 306                 psp_ring_reg = ring->ring_size;
 307                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 308                 /* Write the ring initialization command to C2PMSG_64 */
 309                 psp_ring_reg = ring_type;
 310                 psp_ring_reg = psp_ring_reg << 16;
 311                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 312
 313                 /* there might be handshake issue with hardware which needs delay */
 314                 mdelay(20);
 315
 316                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 317                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 318                                    0x80000000, 0x8000FFFF, false);
 319         }
 320
 321         return ret;
 322 }
 323
 324 static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
 325                                   enum psp_ring_type ring_type)
 326 {
 327         int ret = 0;
 328         struct psp_ring *ring = &psp->km_ring;
 329         struct amdgpu_device *adev = psp->adev;
 330
 331         ret = psp_v13_0_4_ring_stop(psp, ring_type);
 332         if (ret)
 333                 DRM_ERROR("Fail to stop psp ring\n");
 334
 335         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 336                               &ring->ring_mem_mc_addr,
 337                               (void **)&ring->ring_mem);
 338
 339         return ret;
 340 }
 341
 342 static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
 343 {
 344         uint32_t data;
 345         struct amdgpu_device *adev = psp->adev;
 346
 347         if (amdgpu_sriov_vf(adev))
 348                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 349         else
 350                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 351
 352         return data;
 353 }
 354
 355 static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
 356 {
 357         struct amdgpu_device *adev = psp->adev;
 358
 359         if (amdgpu_sriov_vf(adev)) {
 360                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 361                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 362                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 363         } else
 364                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 365 }
 366
 367 static const struct psp_funcs psp_v13_0_4_funcs = {
 368         .init_microcode = psp_v13_0_4_init_microcode,
 369         .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
 370         .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
 371         .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
 372         .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
 373         .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
 374         .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
 375         .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
 376         .ring_init = psp_v13_0_4_ring_init,
 377         .ring_create = psp_v13_0_4_ring_create,
 378         .ring_stop = psp_v13_0_4_ring_stop,
 379         .ring_destroy = psp_v13_0_4_ring_destroy,
 380         .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
 381         .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
 382 };
 383
 384 void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
 385 {
 386         psp->funcs = &psp_v13_0_4_funcs;
 387 }