1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2008 Renesas Solutions Corp.
10 * Based on ov772x driver,
14 * Copyright (C) 2008 Magnus Damm
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/v4l2-mediabus.h>
27 #include <linux/videodev2.h>
29 #include <media/i2c/tw9910.h>
30 #include <media/v4l2-subdev.h>
32 #define GET_ID(val) ((val & 0xF8) >> 3)
33 #define GET_REV(val) (val & 0x07)
38 #define ID 0x00 /* Product ID Code Register */
39 #define STATUS1 0x01 /* Chip Status Register I */
40 #define INFORM 0x02 /* Input Format */
41 #define OPFORM 0x03 /* Output Format Control Register */
42 #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
43 #define OUTCTR1 0x05 /* Output Control I */
44 #define ACNTL1 0x06 /* Analog Control Register 1 */
45 #define CROP_HI 0x07 /* Cropping Register, High */
46 #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
47 #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
48 #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
49 #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
50 #define CNTRL1 0x0C /* Control Register I */
51 #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
52 #define SCALE_HI 0x0E /* Scaling Register, High */
53 #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
54 #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
55 #define CONTRAST 0x11 /* CONTRAST Control Register */
56 #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
57 #define SAT_U 0x13 /* Chroma (U) Gain Register */
58 #define SAT_V 0x14 /* Chroma (V) Gain Register */
59 #define HUE 0x15 /* Hue Control Register */
61 #define CORING2 0x18 /* Coring and IF compensation */
62 #define VBICNTL 0x19 /* VBI Control Register */
63 #define ACNTL2 0x1A /* Analog Control 2 */
64 #define OUTCTR2 0x1B /* Output Control 2 */
65 #define SDT 0x1C /* Standard Selection */
66 #define SDTR 0x1D /* Standard Recognition */
67 #define TEST 0x1F /* Test Control Register */
68 #define CLMPG 0x20 /* Clamping Gain */
69 #define IAGC 0x21 /* Individual AGC Gain */
70 #define AGCGAIN 0x22 /* AGC Gain */
71 #define PEAKWT 0x23 /* White Peak Threshold */
72 #define CLMPL 0x24 /* Clamp level */
73 #define SYNCT 0x25 /* Sync Amplitude */
74 #define MISSCNT 0x26 /* Sync Miss Count Register */
75 #define PCLAMP 0x27 /* Clamp Position Register */
76 #define VCNTL1 0x28 /* Vertical Control I */
77 #define VCNTL2 0x29 /* Vertical Control II */
78 #define CKILL 0x2A /* Color Killer Level Control */
79 #define COMB 0x2B /* Comb Filter Control */
80 #define LDLY 0x2C /* Luma Delay and H Filter Control */
81 #define MISC1 0x2D /* Miscellaneous Control I */
82 #define LOOP 0x2E /* LOOP Control Register */
83 #define MISC2 0x2F /* Miscellaneous Control II */
84 #define MVSN 0x30 /* Macrovision Detection */
85 #define STATUS2 0x31 /* Chip STATUS II */
86 #define HFREF 0x32 /* H monitor */
87 #define CLMD 0x33 /* CLAMP MODE */
88 #define IDCNTL 0x34 /* ID Detection Control */
89 #define CLCNTL1 0x35 /* Clamp Control I */
90 #define ANAPLLCTL 0x4C
125 #define VBIDELAY 0x6F
132 #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
133 #define FC27_FF 0x00 /* 0 : Square pixel mode. */
134 /* Must use 24.54MHz for 60Hz field rate */
135 /* source or 29.5MHz for 50Hz field rate */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
137 #define IFSEL_C 0x00 /* 00 : Composite video decoding */
138 /* Y input video selection */
139 #define YSEL_M0 0x00 /* 00 : Mux0 selected */
140 #define YSEL_M1 0x04 /* 01 : Mux1 selected */
141 #define YSEL_M2 0x08 /* 10 : Mux2 selected */
142 #define YSEL_M3 0x10 /* 11 : Mux3 selected */
145 #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
149 #define LLCMODE 0x20 /* 1 : LLC output mode. */
150 /* 0 : free-run output mode */
151 #define AINC 0x10 /* Serial interface auto-indexing control */
152 /* 0 : auto-increment */
154 #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
155 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
156 #define OEN_TRI_SEL_MASK 0x07
157 #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
158 #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
159 #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
162 #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
163 #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
164 /* VS pin output control */
165 #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
166 #define VSSL_VACT 0x10 /* 1 : VACT */
167 #define VSSL_FIELD 0x20 /* 2 : FIELD */
168 #define VSSL_VVALID 0x30 /* 3 : VVALID */
169 #define VSSL_ZERO 0x70 /* 7 : 0 */
170 #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
171 #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
172 /* HS pin output control */
173 #define HSSL_HACT 0x00 /* 0 : HACT */
174 #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
175 #define HSSL_DVALID 0x02 /* 2 : DVALID */
176 #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
177 #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
178 #define HSSL_ZERO 0x07 /* 7 : 0 */
181 #define SRESET 0x80 /* resets the device to its default state
182 * but all register content remain unchanged.
183 * This bit is self-resetting.
185 #define ACNTL1_PDN_MASK 0x0e
186 #define CLK_PDN 0x08 /* system clock power down */
187 #define Y_PDN 0x04 /* Luma ADC power down */
188 #define C_PDN 0x02 /* Chroma ADC power down */
191 #define ACNTL2_PDN_MASK 0x40
192 #define PLL_PDN 0x40 /* PLL power down */
196 /* RTSEL : control the real time signal output from the MPOUT pin */
197 #define RTSEL_MASK 0x07
198 #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
199 #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
200 #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
201 #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
202 #define RTSEL_MONO 0x04 /* 0100 = MONO */
203 #define RTSEL_DET50 0x05 /* 0101 = DET50 */
204 #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
205 #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
207 /* HSYNC start and end are constant for now */
208 #define HSYNC_START 0x0260
209 #define HSYNC_END 0x0300
216 unsigned char reg_num;
220 struct tw9910_scale_ctrl {
222 unsigned short width;
223 unsigned short height;
229 struct v4l2_subdev subdev;
231 struct tw9910_video_info *info;
232 struct gpio_desc *pdn_gpio;
233 struct gpio_desc *rstb_gpio;
234 const struct tw9910_scale_ctrl *scale;
239 static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
248 .name = "NTSC CCIR601",
255 .name = "NTSC SQ (CIF)",
262 .name = "NTSC CCIR601 (CIF)",
269 .name = "NTSC SQ (QCIF)",
276 .name = "NTSC CCIR601 (QCIF)",
284 static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
293 .name = "PAL CCIR601",
300 .name = "PAL SQ (CIF)",
307 .name = "PAL CCIR601 (CIF)",
314 .name = "PAL SQ (QCIF)",
321 .name = "PAL CCIR601 (QCIF)",
332 static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
334 return container_of(i2c_get_clientdata(client), struct tw9910_priv,
338 static int tw9910_mask_set(struct i2c_client *client, u8 command,
341 s32 val = i2c_smbus_read_byte_data(client, command);
349 return i2c_smbus_write_byte_data(client, command, val);
352 static int tw9910_set_scale(struct i2c_client *client,
353 const struct tw9910_scale_ctrl *scale)
357 ret = i2c_smbus_write_byte_data(client, SCALE_HI,
358 (scale->vscale & 0x0F00) >> 4 |
359 (scale->hscale & 0x0F00) >> 8);
363 ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
364 scale->hscale & 0x00FF);
368 ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
369 scale->vscale & 0x00FF);
374 static int tw9910_set_hsync(struct i2c_client *client)
376 struct tw9910_priv *priv = to_tw9910(client);
380 ret = i2c_smbus_write_byte_data(client, HSBEGIN,
381 (HSYNC_START & 0x07F8) >> 3);
386 ret = i2c_smbus_write_byte_data(client, HSEND,
387 (HSYNC_END & 0x07F8) >> 3);
391 /* So far only revisions 0 and 1 have been seen. */
393 if (priv->revision == 1)
394 ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
395 (HSYNC_START & 0x0007) << 4 |
396 (HSYNC_END & 0x0007));
401 static void tw9910_reset(struct i2c_client *client)
403 tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
404 usleep_range(1000, 5000);
407 static int tw9910_power(struct i2c_client *client, int enable)
417 acntl1 = CLK_PDN | Y_PDN | C_PDN;
421 ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
425 return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
428 static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
429 u32 width, u32 height)
431 const struct tw9910_scale_ctrl *scale;
432 const struct tw9910_scale_ctrl *ret = NULL;
433 __u32 diff = 0xffffffff, tmp;
436 if (norm & V4L2_STD_NTSC) {
437 scale = tw9910_ntsc_scales;
438 size = ARRAY_SIZE(tw9910_ntsc_scales);
439 } else if (norm & V4L2_STD_PAL) {
440 scale = tw9910_pal_scales;
441 size = ARRAY_SIZE(tw9910_pal_scales);
446 for (i = 0; i < size; i++) {
447 tmp = abs(width - scale[i].width) +
448 abs(height - scale[i].height);
459 * subdevice operations
461 static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
463 struct i2c_client *client = v4l2_get_subdevdata(sd);
464 struct tw9910_priv *priv = to_tw9910(client);
469 switch (priv->revision) {
471 val = OEN_TRI_SEL_ALL_OFF_r0;
474 val = OEN_TRI_SEL_ALL_OFF_r1;
477 dev_err(&client->dev, "un-supported revision\n");
481 val = OEN_TRI_SEL_ALL_ON;
484 dev_err(&client->dev, "norm select error\n");
488 dev_dbg(&client->dev, "%s %dx%d\n",
491 priv->scale->height);
494 ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
498 return tw9910_power(client, enable);
501 static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
503 struct i2c_client *client = v4l2_get_subdevdata(sd);
504 struct tw9910_priv *priv = to_tw9910(client);
511 static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
513 struct i2c_client *client = v4l2_get_subdevdata(sd);
514 struct tw9910_priv *priv = to_tw9910(client);
515 const unsigned int hact = 720;
516 const unsigned int hdelay = 15;
521 if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
525 if (norm & V4L2_STD_525_60) {
528 ret = tw9910_mask_set(client, VVBI, 0x10, 0x10);
532 ret = tw9910_mask_set(client, VVBI, 0x10, 0x00);
535 ret = i2c_smbus_write_byte_data(client, CROP_HI,
536 ((vdelay >> 2) & 0xc0) |
537 ((vact >> 4) & 0x30) |
538 ((hdelay >> 6) & 0x0c) |
539 ((hact >> 8) & 0x03));
541 ret = i2c_smbus_write_byte_data(client, VDELAY_LO,
544 ret = i2c_smbus_write_byte_data(client, VACTIVE_LO,
550 #ifdef CONFIG_VIDEO_ADV_DEBUG
551 static int tw9910_g_register(struct v4l2_subdev *sd,
552 struct v4l2_dbg_register *reg)
554 struct i2c_client *client = v4l2_get_subdevdata(sd);
561 ret = i2c_smbus_read_byte_data(client, reg->reg);
569 reg->val = (__u64)ret;
574 static int tw9910_s_register(struct v4l2_subdev *sd,
575 const struct v4l2_dbg_register *reg)
577 struct i2c_client *client = v4l2_get_subdevdata(sd);
579 if (reg->reg > 0xff ||
583 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
587 static void tw9910_set_gpio_value(struct gpio_desc *desc, int value)
590 gpiod_set_value(desc, value);
591 usleep_range(500, 1000);
595 static int tw9910_power_on(struct tw9910_priv *priv)
597 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
601 ret = clk_prepare_enable(priv->clk);
606 tw9910_set_gpio_value(priv->pdn_gpio, 0);
609 * FIXME: The reset signal is connected to a shared GPIO on some
610 * platforms (namely the SuperH Migo-R). Until a framework becomes
611 * available to handle this cleanly, request the GPIO temporarily
612 * to avoid conflicts.
614 priv->rstb_gpio = gpiod_get_optional(&client->dev, "rstb",
616 if (IS_ERR(priv->rstb_gpio)) {
617 dev_info(&client->dev, "Unable to get GPIO \"rstb\"");
618 clk_disable_unprepare(priv->clk);
619 tw9910_set_gpio_value(priv->pdn_gpio, 1);
620 return PTR_ERR(priv->rstb_gpio);
623 if (priv->rstb_gpio) {
624 tw9910_set_gpio_value(priv->rstb_gpio, 1);
625 tw9910_set_gpio_value(priv->rstb_gpio, 0);
627 gpiod_put(priv->rstb_gpio);
633 static int tw9910_power_off(struct tw9910_priv *priv)
635 clk_disable_unprepare(priv->clk);
636 tw9910_set_gpio_value(priv->pdn_gpio, 1);
641 static int tw9910_s_power(struct v4l2_subdev *sd, int on)
643 struct i2c_client *client = v4l2_get_subdevdata(sd);
644 struct tw9910_priv *priv = to_tw9910(client);
646 return on ? tw9910_power_on(priv) : tw9910_power_off(priv);
649 static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
651 struct i2c_client *client = v4l2_get_subdevdata(sd);
652 struct tw9910_priv *priv = to_tw9910(client);
656 /* Select suitable norm. */
657 priv->scale = tw9910_select_norm(priv->norm, *width, *height);
659 goto tw9910_set_fmt_error;
661 /* Reset hardware. */
662 tw9910_reset(client);
666 if (priv->info->buswidth == 16)
669 ret = tw9910_mask_set(client, OPFORM, LEN, val);
671 goto tw9910_set_fmt_error;
673 /* Select MPOUT behavior. */
674 switch (priv->info->mpout) {
675 case TW9910_MPO_VLOSS:
676 val = RTSEL_VLOSS; break;
677 case TW9910_MPO_HLOCK:
678 val = RTSEL_HLOCK; break;
679 case TW9910_MPO_SLOCK:
680 val = RTSEL_SLOCK; break;
681 case TW9910_MPO_VLOCK:
682 val = RTSEL_VLOCK; break;
683 case TW9910_MPO_MONO:
684 val = RTSEL_MONO; break;
685 case TW9910_MPO_DET50:
686 val = RTSEL_DET50; break;
687 case TW9910_MPO_FIELD:
688 val = RTSEL_FIELD; break;
689 case TW9910_MPO_RTCO:
690 val = RTSEL_RTCO; break;
695 ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
697 goto tw9910_set_fmt_error;
700 ret = tw9910_set_scale(client, priv->scale);
702 goto tw9910_set_fmt_error;
705 ret = tw9910_set_hsync(client);
707 goto tw9910_set_fmt_error;
709 *width = priv->scale->width;
710 *height = priv->scale->height;
714 tw9910_set_fmt_error:
716 tw9910_reset(client);
722 static int tw9910_get_selection(struct v4l2_subdev *sd,
723 struct v4l2_subdev_pad_config *cfg,
724 struct v4l2_subdev_selection *sel)
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
727 struct tw9910_priv *priv = to_tw9910(client);
729 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
731 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported. */
732 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
737 if (priv->norm & V4L2_STD_NTSC) {
748 static int tw9910_get_fmt(struct v4l2_subdev *sd,
749 struct v4l2_subdev_pad_config *cfg,
750 struct v4l2_subdev_format *format)
752 struct v4l2_mbus_framefmt *mf = &format->format;
753 struct i2c_client *client = v4l2_get_subdevdata(sd);
754 struct tw9910_priv *priv = to_tw9910(client);
760 priv->scale = tw9910_select_norm(priv->norm, 640, 480);
765 mf->width = priv->scale->width;
766 mf->height = priv->scale->height;
767 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
768 mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
769 mf->field = V4L2_FIELD_INTERLACED_BT;
774 static int tw9910_s_fmt(struct v4l2_subdev *sd,
775 struct v4l2_mbus_framefmt *mf)
777 u32 width = mf->width, height = mf->height;
780 WARN_ON(mf->field != V4L2_FIELD_ANY &&
781 mf->field != V4L2_FIELD_INTERLACED_BT);
783 /* Check color format. */
784 if (mf->code != MEDIA_BUS_FMT_UYVY8_2X8)
787 mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
789 ret = tw9910_set_frame(sd, &width, &height);
799 static int tw9910_set_fmt(struct v4l2_subdev *sd,
800 struct v4l2_subdev_pad_config *cfg,
801 struct v4l2_subdev_format *format)
803 struct v4l2_mbus_framefmt *mf = &format->format;
804 struct i2c_client *client = v4l2_get_subdevdata(sd);
805 struct tw9910_priv *priv = to_tw9910(client);
806 const struct tw9910_scale_ctrl *scale;
811 if (mf->field == V4L2_FIELD_ANY) {
812 mf->field = V4L2_FIELD_INTERLACED_BT;
813 } else if (mf->field != V4L2_FIELD_INTERLACED_BT) {
814 dev_err(&client->dev, "Field type %d invalid\n", mf->field);
818 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
819 mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
821 /* Select suitable norm. */
822 scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
826 mf->width = scale->width;
827 mf->height = scale->height;
829 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
830 return tw9910_s_fmt(sd, mf);
837 static int tw9910_video_probe(struct i2c_client *client)
839 struct tw9910_priv *priv = to_tw9910(client);
843 /* TW9910 only use 8 or 16 bit bus width. */
844 if (priv->info->buswidth != 16 && priv->info->buswidth != 8) {
845 dev_err(&client->dev, "bus width error\n");
849 ret = tw9910_s_power(&priv->subdev, 1);
854 * Check and show Product ID.
855 * So far only revisions 0 and 1 have been seen.
857 id = i2c_smbus_read_byte_data(client, ID);
858 priv->revision = GET_REV(id);
861 if (id != 0x0b || priv->revision > 0x01) {
862 dev_err(&client->dev, "Product ID error %x:%x\n",
868 dev_info(&client->dev, "tw9910 Product ID %0x:%0x\n",
871 priv->norm = V4L2_STD_NTSC;
872 priv->scale = &tw9910_ntsc_scales[0];
875 tw9910_s_power(&priv->subdev, 0);
880 static const struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
881 #ifdef CONFIG_VIDEO_ADV_DEBUG
882 .g_register = tw9910_g_register,
883 .s_register = tw9910_s_register,
885 .s_power = tw9910_s_power,
888 static int tw9910_enum_mbus_code(struct v4l2_subdev *sd,
889 struct v4l2_subdev_pad_config *cfg,
890 struct v4l2_subdev_mbus_code_enum *code)
892 if (code->pad || code->index)
895 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
900 static int tw9910_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
902 *norm = V4L2_STD_NTSC | V4L2_STD_PAL;
907 static const struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
908 .s_std = tw9910_s_std,
909 .g_std = tw9910_g_std,
910 .s_stream = tw9910_s_stream,
911 .g_tvnorms = tw9910_g_tvnorms,
914 static const struct v4l2_subdev_pad_ops tw9910_subdev_pad_ops = {
915 .enum_mbus_code = tw9910_enum_mbus_code,
916 .get_selection = tw9910_get_selection,
917 .get_fmt = tw9910_get_fmt,
918 .set_fmt = tw9910_set_fmt,
921 static const struct v4l2_subdev_ops tw9910_subdev_ops = {
922 .core = &tw9910_subdev_core_ops,
923 .video = &tw9910_subdev_video_ops,
924 .pad = &tw9910_subdev_pad_ops,
928 * i2c_driver function
931 static int tw9910_probe(struct i2c_client *client,
932 const struct i2c_device_id *did)
935 struct tw9910_priv *priv;
936 struct tw9910_video_info *info;
937 struct i2c_adapter *adapter = client->adapter;
940 if (!client->dev.platform_data) {
941 dev_err(&client->dev, "TW9910: missing platform data!\n");
945 info = client->dev.platform_data;
947 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
948 dev_err(&client->dev,
949 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE_DATA\n");
953 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
959 v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
961 priv->clk = clk_get(&client->dev, "xti");
962 if (PTR_ERR(priv->clk) == -ENOENT) {
964 } else if (IS_ERR(priv->clk)) {
965 dev_err(&client->dev, "Unable to get xti clock\n");
966 return PTR_ERR(priv->clk);
969 priv->pdn_gpio = gpiod_get_optional(&client->dev, "pdn",
971 if (IS_ERR(priv->pdn_gpio)) {
972 dev_info(&client->dev, "Unable to get GPIO \"pdn\"");
973 ret = PTR_ERR(priv->pdn_gpio);
977 ret = tw9910_video_probe(client);
981 ret = v4l2_async_register_subdev(&priv->subdev);
989 gpiod_put(priv->pdn_gpio);
996 static int tw9910_remove(struct i2c_client *client)
998 struct tw9910_priv *priv = to_tw9910(client);
1001 gpiod_put(priv->pdn_gpio);
1003 v4l2_async_unregister_subdev(&priv->subdev);
1008 static const struct i2c_device_id tw9910_id[] = {
1012 MODULE_DEVICE_TABLE(i2c, tw9910_id);
1014 static struct i2c_driver tw9910_i2c_driver = {
1018 .probe = tw9910_probe,
1019 .remove = tw9910_remove,
1020 .id_table = tw9910_id,
1023 module_i2c_driver(tw9910_i2c_driver);
1025 MODULE_DESCRIPTION("V4L2 driver for TW9910 video decoder");
1026 MODULE_AUTHOR("Kuninori Morimoto");
1027 MODULE_LICENSE("GPL v2");