2 * Copyright (c) 2000-2010 LSI Corporation.
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
9 * mpi2_cnfg.h Version: 02.00.17
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
100 * Added expander reduced functionality data to SAS
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
137 * --------------------------------------------------------------------------
143 /*****************************************************************************
144 * Configuration Page Header and defines
145 *****************************************************************************/
147 /* Config Page Header */
148 typedef struct _MPI2_CONFIG_PAGE_HEADER
150 U8 PageVersion; /* 0x00 */
151 U8 PageLength; /* 0x01 */
152 U8 PageNumber; /* 0x02 */
153 U8 PageType; /* 0x03 */
154 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
155 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
157 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
159 MPI2_CONFIG_PAGE_HEADER Struct;
163 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
164 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
166 /* Extended Config Page Header */
167 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
169 U8 PageVersion; /* 0x00 */
170 U8 Reserved1; /* 0x01 */
171 U8 PageNumber; /* 0x02 */
172 U8 PageType; /* 0x03 */
173 U16 ExtPageLength; /* 0x04 */
174 U8 ExtPageType; /* 0x06 */
175 U8 Reserved2; /* 0x07 */
176 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
177 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
178 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
180 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
182 MPI2_CONFIG_PAGE_HEADER Struct;
183 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
187 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
188 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
191 /* PageType field values */
192 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
193 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
194 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
195 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
197 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
198 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
199 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
200 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
201 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
202 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
203 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
204 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
206 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
209 /* ExtPageType field values */
210 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
211 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
212 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
213 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
214 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
215 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
216 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
217 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
218 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
219 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
220 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
223 /*****************************************************************************
224 * PageAddress defines
225 *****************************************************************************/
227 /* RAID Volume PageAddress format */
228 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
229 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
230 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
232 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
235 /* RAID Physical Disk PageAddress format */
236 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
237 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
238 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
239 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
241 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
242 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
245 /* SAS Expander PageAddress format */
246 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
247 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
248 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
249 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
251 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
252 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
253 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
256 /* SAS Device PageAddress format */
257 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
258 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
259 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
261 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
264 /* SAS PHY PageAddress format */
265 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
266 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
267 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
269 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
270 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
273 /* SAS Port PageAddress format */
274 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
275 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
276 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
278 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
281 /* SAS Enclosure PageAddress format */
282 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
283 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
284 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
286 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
289 /* RAID Configuration PageAddress format */
290 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
291 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
292 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
293 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
295 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
298 /* Driver Persistent Mapping PageAddress format */
299 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
300 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
302 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
303 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
304 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
307 /* Ethernet PageAddress format */
308 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
309 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
311 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
315 /****************************************************************************
316 * Configuration messages
317 ****************************************************************************/
319 /* Configuration Request Message */
320 typedef struct _MPI2_CONFIG_REQUEST
322 U8 Action; /* 0x00 */
323 U8 SGLFlags; /* 0x01 */
324 U8 ChainOffset; /* 0x02 */
325 U8 Function; /* 0x03 */
326 U16 ExtPageLength; /* 0x04 */
327 U8 ExtPageType; /* 0x06 */
328 U8 MsgFlags; /* 0x07 */
331 U16 Reserved1; /* 0x0A */
332 U32 Reserved2; /* 0x0C */
333 U32 Reserved3; /* 0x10 */
334 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
335 U32 PageAddress; /* 0x18 */
336 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
337 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
338 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
340 /* values for the Action field */
341 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
342 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
343 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
344 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
345 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
346 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
347 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
348 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
350 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
353 /* Config Reply Message */
354 typedef struct _MPI2_CONFIG_REPLY
356 U8 Action; /* 0x00 */
357 U8 SGLFlags; /* 0x01 */
358 U8 MsgLength; /* 0x02 */
359 U8 Function; /* 0x03 */
360 U16 ExtPageLength; /* 0x04 */
361 U8 ExtPageType; /* 0x06 */
362 U8 MsgFlags; /* 0x07 */
365 U16 Reserved1; /* 0x0A */
366 U16 Reserved2; /* 0x0C */
367 U16 IOCStatus; /* 0x0E */
368 U32 IOCLogInfo; /* 0x10 */
369 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
370 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
371 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
375 /*****************************************************************************
377 * C o n f i g u r a t i o n P a g e s
379 *****************************************************************************/
381 /****************************************************************************
382 * Manufacturing Config pages
383 ****************************************************************************/
385 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
388 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
389 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
390 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
391 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
392 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
393 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
394 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
396 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
398 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
399 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
400 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
401 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
402 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
403 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
404 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
405 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
406 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
411 /* Manufacturing Page 0 */
413 typedef struct _MPI2_CONFIG_PAGE_MAN_0
415 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
416 U8 ChipName[16]; /* 0x04 */
417 U8 ChipRevision[8]; /* 0x14 */
418 U8 BoardName[16]; /* 0x1C */
419 U8 BoardAssembly[16]; /* 0x2C */
420 U8 BoardTracerNumber[16]; /* 0x3C */
421 } MPI2_CONFIG_PAGE_MAN_0,
422 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
423 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
425 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
428 /* Manufacturing Page 1 */
430 typedef struct _MPI2_CONFIG_PAGE_MAN_1
432 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
433 U8 VPD[256]; /* 0x04 */
434 } MPI2_CONFIG_PAGE_MAN_1,
435 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
436 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
438 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
441 typedef struct _MPI2_CHIP_REVISION_ID
443 U16 DeviceID; /* 0x00 */
444 U8 PCIRevisionID; /* 0x02 */
445 U8 Reserved; /* 0x03 */
446 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
447 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
450 /* Manufacturing Page 2 */
453 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
454 * one and check Header.PageLength at runtime.
456 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
457 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
460 typedef struct _MPI2_CONFIG_PAGE_MAN_2
462 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
463 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
464 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
465 } MPI2_CONFIG_PAGE_MAN_2,
466 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
467 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
469 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
472 /* Manufacturing Page 3 */
475 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
476 * one and check Header.PageLength at runtime.
478 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
479 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
482 typedef struct _MPI2_CONFIG_PAGE_MAN_3
484 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
485 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
486 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
487 } MPI2_CONFIG_PAGE_MAN_3,
488 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
489 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
491 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
494 /* Manufacturing Page 4 */
496 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
498 U8 PowerSaveFlags; /* 0x00 */
499 U8 InternalOperationsSleepTime; /* 0x01 */
500 U8 InternalOperationsRunTime; /* 0x02 */
501 U8 HostIdleTime; /* 0x03 */
502 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
503 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
504 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
506 /* defines for the PowerSaveFlags field */
507 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
508 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
509 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
510 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
512 typedef struct _MPI2_CONFIG_PAGE_MAN_4
514 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
515 U32 Reserved1; /* 0x04 */
516 U32 Flags; /* 0x08 */
517 U8 InquirySize; /* 0x0C */
518 U8 Reserved2; /* 0x0D */
519 U16 Reserved3; /* 0x0E */
520 U8 InquiryData[56]; /* 0x10 */
521 U32 RAID0VolumeSettings; /* 0x48 */
522 U32 RAID1EVolumeSettings; /* 0x4C */
523 U32 RAID1VolumeSettings; /* 0x50 */
524 U32 RAID10VolumeSettings; /* 0x54 */
525 U32 Reserved4; /* 0x58 */
526 U32 Reserved5; /* 0x5C */
527 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
528 U8 MaxOCEDisks; /* 0x64 */
529 U8 ResyncRate; /* 0x65 */
530 U16 DataScrubDuration; /* 0x66 */
531 U8 MaxHotSpares; /* 0x68 */
532 U8 MaxPhysDisksPerVol; /* 0x69 */
533 U8 MaxPhysDisks; /* 0x6A */
534 U8 MaxVolumes; /* 0x6B */
535 } MPI2_CONFIG_PAGE_MAN_4,
536 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
537 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
539 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
541 /* Manufacturing Page 4 Flags field */
542 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
543 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
545 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
546 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
547 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
549 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
550 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
551 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
552 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
553 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
555 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
556 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
557 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
558 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
560 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
561 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
562 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
563 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
564 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
565 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
566 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
567 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
570 /* Manufacturing Page 5 */
573 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
574 * one and check the value returned for NumPhys at runtime.
576 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
577 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
580 typedef struct _MPI2_MANUFACTURING5_ENTRY
583 U64 DeviceName; /* 0x08 */
584 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
585 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
587 typedef struct _MPI2_CONFIG_PAGE_MAN_5
589 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
590 U8 NumPhys; /* 0x04 */
591 U8 Reserved1; /* 0x05 */
592 U16 Reserved2; /* 0x06 */
593 U32 Reserved3; /* 0x08 */
594 U32 Reserved4; /* 0x0C */
595 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
596 } MPI2_CONFIG_PAGE_MAN_5,
597 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
598 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
600 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
603 /* Manufacturing Page 6 */
605 typedef struct _MPI2_CONFIG_PAGE_MAN_6
607 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
608 U32 ProductSpecificInfo;/* 0x04 */
609 } MPI2_CONFIG_PAGE_MAN_6,
610 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
611 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
613 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
616 /* Manufacturing Page 7 */
618 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
620 U32 Pinout; /* 0x00 */
621 U8 Connector[16]; /* 0x04 */
622 U8 Location; /* 0x14 */
623 U8 ReceptacleID; /* 0x15 */
625 U32 Reserved2; /* 0x18 */
626 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
627 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
629 /* defines for the Pinout field */
630 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
631 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
633 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
634 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
635 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
636 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
637 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
638 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
639 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
640 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
641 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
642 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
643 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
644 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
645 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
646 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
647 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
649 /* defines for the Location field */
650 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
651 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
652 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
653 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
654 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
655 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
656 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
659 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
660 * one and check the value returned for NumPhys at runtime.
662 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
663 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
666 typedef struct _MPI2_CONFIG_PAGE_MAN_7
668 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
669 U32 Reserved1; /* 0x04 */
670 U32 Reserved2; /* 0x08 */
671 U32 Flags; /* 0x0C */
672 U8 EnclosureName[16]; /* 0x10 */
673 U8 NumPhys; /* 0x20 */
674 U8 Reserved3; /* 0x21 */
675 U16 Reserved4; /* 0x22 */
676 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
677 } MPI2_CONFIG_PAGE_MAN_7,
678 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
679 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
681 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
683 /* defines for the Flags field */
684 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
688 * Generic structure to use for product-specific manufacturing pages
689 * (currently Manufacturing Page 8 through Manufacturing Page 31).
692 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
694 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
695 U32 ProductSpecificInfo;/* 0x04 */
696 } MPI2_CONFIG_PAGE_MAN_PS,
697 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
698 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
700 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
701 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
702 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
703 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
704 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
705 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
706 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
707 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
708 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
709 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
710 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
711 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
712 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
713 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
714 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
715 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
716 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
717 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
718 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
719 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
720 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
721 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
722 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
723 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
726 /****************************************************************************
727 * IO Unit Config Pages
728 ****************************************************************************/
732 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
734 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
735 U64 UniqueValue; /* 0x04 */
736 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
737 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
738 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
739 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
741 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
746 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
748 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
749 U32 Flags; /* 0x04 */
750 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
751 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
753 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
755 /* IO Unit Page 1 Flags defines */
756 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
757 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
758 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
759 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
760 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
761 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
762 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
763 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
764 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
765 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
771 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
772 * one and check the value returned for GPIOCount at runtime.
774 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
775 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
778 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
780 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
781 U8 GPIOCount; /* 0x04 */
782 U8 Reserved1; /* 0x05 */
783 U16 Reserved2; /* 0x06 */
784 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
785 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
786 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
788 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
790 /* defines for IO Unit Page 3 GPIOVal field */
791 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
792 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
793 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
794 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
800 * Upper layer code (drivers, utilities, etc.) should leave this define set to
801 * one and check the value returned for NumDmaEngines at runtime.
803 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
804 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
807 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
808 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
809 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
810 U64 RaidAcceleratorBufferSize; /* 0x0C */
811 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
812 U8 RAControlSize; /* 0x1C */
813 U8 NumDmaEngines; /* 0x1D */
814 U8 RAMinControlSize; /* 0x1E */
815 U8 RAMaxControlSize; /* 0x1F */
816 U32 Reserved1; /* 0x20 */
817 U32 Reserved2; /* 0x24 */
818 U32 Reserved3; /* 0x28 */
819 U32 DmaEngineCapabilities
820 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
821 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
822 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
824 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
826 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
827 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
828 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
830 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
831 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
832 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
833 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
838 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
839 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
840 U16 Flags; /* 0x04 */
841 U8 RAHostControlSize; /* 0x06 */
842 U8 Reserved0; /* 0x07 */
843 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
844 U32 Reserved1; /* 0x10 */
845 U32 Reserved2; /* 0x14 */
846 U32 Reserved3; /* 0x18 */
847 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
848 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
850 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
852 /* defines for IO Unit Page 6 Flags field */
853 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
858 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
859 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
860 U16 Reserved1; /* 0x04 */
861 U8 PCIeWidth; /* 0x06 */
862 U8 PCIeSpeed; /* 0x07 */
863 U32 ProcessorState; /* 0x08 */
864 U32 PowerManagementCapabilities; /* 0x0C */
865 U16 IOCTemperature; /* 0x10 */
866 U8 IOCTemperatureUnits; /* 0x12 */
867 U8 IOCSpeed; /* 0x13 */
868 U16 BoardTemperature; /* 0x14 */
869 U8 BoardTemperatureUnits; /* 0x16 */
870 U8 Reserved3; /* 0x17 */
871 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
872 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
874 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
876 /* defines for IO Unit Page 7 PCIeWidth field */
877 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
878 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
879 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
880 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
882 /* defines for IO Unit Page 7 PCIeSpeed field */
883 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
884 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
885 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
887 /* defines for IO Unit Page 7 ProcessorState field */
888 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
889 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
891 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
892 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
893 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
895 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
896 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
897 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
898 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
899 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
900 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
902 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
903 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
904 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
905 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
907 /* defines for IO Unit Page 7 IOCSpeed field */
908 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
909 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
910 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
911 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
913 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
914 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
915 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
916 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
920 /****************************************************************************
922 ****************************************************************************/
926 typedef struct _MPI2_CONFIG_PAGE_IOC_0
928 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
929 U32 Reserved1; /* 0x04 */
930 U32 Reserved2; /* 0x08 */
931 U16 VendorID; /* 0x0C */
932 U16 DeviceID; /* 0x0E */
933 U8 RevisionID; /* 0x10 */
934 U8 Reserved3; /* 0x11 */
935 U16 Reserved4; /* 0x12 */
936 U32 ClassCode; /* 0x14 */
937 U16 SubsystemVendorID; /* 0x18 */
938 U16 SubsystemID; /* 0x1A */
939 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
940 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
942 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
947 typedef struct _MPI2_CONFIG_PAGE_IOC_1
949 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
950 U32 Flags; /* 0x04 */
951 U32 CoalescingTimeout; /* 0x08 */
952 U8 CoalescingDepth; /* 0x0C */
953 U8 PCISlotNum; /* 0x0D */
954 U8 PCIBusNum; /* 0x0E */
955 U8 PCIDomainSegment; /* 0x0F */
956 U32 Reserved1; /* 0x10 */
957 U32 Reserved2; /* 0x14 */
958 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
959 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
961 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
963 /* defines for IOC Page 1 Flags field */
964 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
966 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
967 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
968 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
972 typedef struct _MPI2_CONFIG_PAGE_IOC_6
974 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
975 U32 CapabilitiesFlags; /* 0x04 */
976 U8 MaxDrivesRAID0; /* 0x08 */
977 U8 MaxDrivesRAID1; /* 0x09 */
978 U8 MaxDrivesRAID1E; /* 0x0A */
979 U8 MaxDrivesRAID10; /* 0x0B */
980 U8 MinDrivesRAID0; /* 0x0C */
981 U8 MinDrivesRAID1; /* 0x0D */
982 U8 MinDrivesRAID1E; /* 0x0E */
983 U8 MinDrivesRAID10; /* 0x0F */
984 U32 Reserved1; /* 0x10 */
985 U8 MaxGlobalHotSpares; /* 0x14 */
986 U8 MaxPhysDisks; /* 0x15 */
987 U8 MaxVolumes; /* 0x16 */
988 U8 MaxConfigs; /* 0x17 */
989 U8 MaxOCEDisks; /* 0x18 */
990 U8 Reserved2; /* 0x19 */
991 U16 Reserved3; /* 0x1A */
992 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
993 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
994 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
995 U32 Reserved4; /* 0x28 */
996 U32 Reserved5; /* 0x2C */
997 U16 DefaultMetadataSize; /* 0x30 */
998 U16 Reserved6; /* 0x32 */
999 U16 MaxBadBlockTableEntries; /* 0x34 */
1000 U16 Reserved7; /* 0x36 */
1001 U32 IRNvsramVersion; /* 0x38 */
1002 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1003 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1005 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
1007 /* defines for IOC Page 6 CapabilitiesFlags */
1008 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1009 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1010 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1011 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1012 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1017 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1019 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1021 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1022 U32 Reserved1; /* 0x04 */
1023 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1024 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1025 U16 Reserved2; /* 0x1A */
1026 U32 Reserved3; /* 0x1C */
1027 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1028 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1030 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
1035 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1037 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1038 U8 NumDevsPerEnclosure; /* 0x04 */
1039 U8 Reserved1; /* 0x05 */
1040 U16 Reserved2; /* 0x06 */
1041 U16 MaxPersistentEntries; /* 0x08 */
1042 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1043 U16 Flags; /* 0x0C */
1044 U16 Reserved3; /* 0x0E */
1045 U16 IRVolumeMappingFlags; /* 0x10 */
1046 U16 Reserved4; /* 0x12 */
1047 U32 Reserved5; /* 0x14 */
1048 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1049 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1051 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1053 /* defines for IOC Page 8 Flags field */
1054 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1055 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1057 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1058 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1059 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1061 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1062 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1064 /* defines for IOC Page 8 IRVolumeMappingFlags */
1065 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1066 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1067 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1070 /****************************************************************************
1072 ****************************************************************************/
1076 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1078 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1079 U32 BiosOptions; /* 0x04 */
1080 U32 IOCSettings; /* 0x08 */
1081 U32 Reserved1; /* 0x0C */
1082 U32 DeviceSettings; /* 0x10 */
1083 U16 NumberOfDevices; /* 0x14 */
1084 U16 Reserved2; /* 0x16 */
1085 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1086 U16 IOTimeoutSequential; /* 0x1A */
1087 U16 IOTimeoutOther; /* 0x1C */
1088 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1089 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1090 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1092 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1094 /* values for BIOS Page 1 BiosOptions field */
1095 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1097 /* values for BIOS Page 1 IOCSettings field */
1098 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1099 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1100 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1102 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1103 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1104 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1105 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1107 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1108 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1109 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1110 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1111 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1113 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1115 /* values for BIOS Page 1 DeviceSettings field */
1116 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1117 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1118 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1119 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1120 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1125 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1127 U32 Reserved1; /* 0x00 */
1128 U32 Reserved2; /* 0x04 */
1129 U32 Reserved3; /* 0x08 */
1130 U32 Reserved4; /* 0x0C */
1131 U32 Reserved5; /* 0x10 */
1132 U32 Reserved6; /* 0x14 */
1133 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1134 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1135 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1137 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1139 U64 SASAddress; /* 0x00 */
1140 U8 LUN[8]; /* 0x08 */
1141 U32 Reserved1; /* 0x10 */
1142 U32 Reserved2; /* 0x14 */
1143 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1144 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1146 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1148 U64 EnclosureLogicalID; /* 0x00 */
1149 U32 Reserved1; /* 0x08 */
1150 U32 Reserved2; /* 0x0C */
1151 U16 SlotNumber; /* 0x10 */
1152 U16 Reserved3; /* 0x12 */
1153 U32 Reserved4; /* 0x14 */
1154 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1155 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1156 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1158 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1160 U64 DeviceName; /* 0x00 */
1161 U8 LUN[8]; /* 0x08 */
1162 U32 Reserved1; /* 0x10 */
1163 U32 Reserved2; /* 0x14 */
1164 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1165 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1167 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1169 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1170 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1171 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1172 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1173 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1174 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1176 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1178 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1179 U32 Reserved1; /* 0x04 */
1180 U32 Reserved2; /* 0x08 */
1181 U32 Reserved3; /* 0x0C */
1182 U32 Reserved4; /* 0x10 */
1183 U32 Reserved5; /* 0x14 */
1184 U32 Reserved6; /* 0x18 */
1185 U8 ReqBootDeviceForm; /* 0x1C */
1186 U8 Reserved7; /* 0x1D */
1187 U16 Reserved8; /* 0x1E */
1188 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1189 U8 ReqAltBootDeviceForm; /* 0x38 */
1190 U8 Reserved9; /* 0x39 */
1191 U16 Reserved10; /* 0x3A */
1192 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1193 U8 CurrentBootDeviceForm; /* 0x58 */
1194 U8 Reserved11; /* 0x59 */
1195 U16 Reserved12; /* 0x5A */
1196 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1197 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1198 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1200 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1202 /* values for BIOS Page 2 BootDeviceForm fields */
1203 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1204 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1205 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1206 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1207 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1212 typedef struct _MPI2_ADAPTER_INFO
1214 U8 PciBusNumber; /* 0x00 */
1215 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1216 U16 AdapterFlags; /* 0x02 */
1217 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1218 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1220 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1221 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1223 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1225 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1226 U32 GlobalFlags; /* 0x04 */
1227 U32 BiosVersion; /* 0x08 */
1228 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1229 U32 Reserved1; /* 0x1C */
1230 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1231 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1233 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1235 /* values for BIOS Page 3 GlobalFlags */
1236 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1237 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1238 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1240 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1241 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1242 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1243 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1249 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1250 * one and check the value returned for NumPhys at runtime.
1252 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1253 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1256 typedef struct _MPI2_BIOS4_ENTRY
1258 U64 ReassignmentWWID; /* 0x00 */
1259 U64 ReassignmentDeviceName; /* 0x08 */
1260 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1261 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1263 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1265 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1266 U8 NumPhys; /* 0x04 */
1267 U8 Reserved1; /* 0x05 */
1268 U16 Reserved2; /* 0x06 */
1269 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1270 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1271 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1273 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1276 /****************************************************************************
1277 * RAID Volume Config Pages
1278 ****************************************************************************/
1280 /* RAID Volume Page 0 */
1282 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1284 U8 RAIDSetNum; /* 0x00 */
1285 U8 PhysDiskMap; /* 0x01 */
1286 U8 PhysDiskNum; /* 0x02 */
1287 U8 Reserved; /* 0x03 */
1288 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1289 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1291 /* defines for the PhysDiskMap field */
1292 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1293 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1295 typedef struct _MPI2_RAIDVOL0_SETTINGS
1297 U16 Settings; /* 0x00 */
1298 U8 HotSparePool; /* 0x01 */
1299 U8 Reserved; /* 0x02 */
1300 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1301 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1303 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1304 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1305 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1306 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1307 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1308 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1309 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1310 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1311 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1313 /* RAID Volume Page 0 VolumeSettings defines */
1314 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1315 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1317 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1318 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1319 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1320 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1323 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1324 * one and check the value returned for NumPhysDisks at runtime.
1326 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1327 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1330 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1332 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1333 U16 DevHandle; /* 0x04 */
1334 U8 VolumeState; /* 0x06 */
1335 U8 VolumeType; /* 0x07 */
1336 U32 VolumeStatusFlags; /* 0x08 */
1337 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1338 U64 MaxLBA; /* 0x10 */
1339 U32 StripeSize; /* 0x18 */
1340 U16 BlockSize; /* 0x1C */
1341 U16 Reserved1; /* 0x1E */
1342 U8 SupportedPhysDisks; /* 0x20 */
1343 U8 ResyncRate; /* 0x21 */
1344 U16 DataScrubDuration; /* 0x22 */
1345 U8 NumPhysDisks; /* 0x24 */
1346 U8 Reserved2; /* 0x25 */
1347 U8 Reserved3; /* 0x26 */
1348 U8 InactiveStatus; /* 0x27 */
1349 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1350 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1351 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1353 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1355 /* values for RAID VolumeState */
1356 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1357 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1358 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1359 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1360 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1361 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1363 /* values for RAID VolumeType */
1364 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1365 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1366 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1367 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1368 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1370 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1371 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1372 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1373 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1374 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1375 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1376 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1377 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1378 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1379 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1380 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1381 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1382 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1383 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1384 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1385 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1386 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1387 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1388 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1389 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1391 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1392 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1393 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1394 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1395 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1397 /* values for RAID Volume Page 0 InactiveStatus field */
1398 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1399 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1400 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1401 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1402 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1403 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1404 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1407 /* RAID Volume Page 1 */
1409 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1411 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1412 U16 DevHandle; /* 0x04 */
1413 U16 Reserved0; /* 0x06 */
1414 U8 GUID[24]; /* 0x08 */
1415 U8 Name[16]; /* 0x20 */
1416 U64 WWID; /* 0x30 */
1417 U32 Reserved1; /* 0x38 */
1418 U32 Reserved2; /* 0x3C */
1419 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1420 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1422 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1425 /****************************************************************************
1426 * RAID Physical Disk Config Pages
1427 ****************************************************************************/
1429 /* RAID Physical Disk Page 0 */
1431 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1433 U16 Reserved1; /* 0x00 */
1434 U8 HotSparePool; /* 0x02 */
1435 U8 Reserved2; /* 0x03 */
1436 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1437 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1439 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1441 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1443 U8 VendorID[8]; /* 0x00 */
1444 U8 ProductID[16]; /* 0x08 */
1445 U8 ProductRevLevel[4]; /* 0x18 */
1446 U8 SerialNum[32]; /* 0x1C */
1447 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1448 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1449 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1451 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1453 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1454 U16 DevHandle; /* 0x04 */
1455 U8 Reserved1; /* 0x06 */
1456 U8 PhysDiskNum; /* 0x07 */
1457 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1458 U32 Reserved2; /* 0x0C */
1459 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1460 U32 Reserved3; /* 0x4C */
1461 U8 PhysDiskState; /* 0x50 */
1462 U8 OfflineReason; /* 0x51 */
1463 U8 IncompatibleReason; /* 0x52 */
1464 U8 PhysDiskAttributes; /* 0x53 */
1465 U32 PhysDiskStatusFlags; /* 0x54 */
1466 U64 DeviceMaxLBA; /* 0x58 */
1467 U64 HostMaxLBA; /* 0x60 */
1468 U64 CoercedMaxLBA; /* 0x68 */
1469 U16 BlockSize; /* 0x70 */
1470 U16 Reserved5; /* 0x72 */
1471 U32 Reserved6; /* 0x74 */
1472 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1473 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1474 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1476 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1478 /* PhysDiskState defines */
1479 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1480 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1481 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1482 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1483 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1484 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1485 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1486 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1488 /* OfflineReason defines */
1489 #define MPI2_PHYSDISK0_ONLINE (0x00)
1490 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1491 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1492 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1493 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1494 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1495 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1497 /* IncompatibleReason defines */
1498 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1499 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1500 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1501 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1502 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1503 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1504 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1505 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1507 /* PhysDiskAttributes defines */
1508 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1509 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1510 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1512 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1513 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1514 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1516 /* PhysDiskStatusFlags defines */
1517 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1518 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1519 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1520 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1521 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1522 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1523 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1524 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1527 /* RAID Physical Disk Page 1 */
1530 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1531 * one and check the value returned for NumPhysDiskPaths at runtime.
1533 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1534 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1537 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1539 U16 DevHandle; /* 0x00 */
1540 U16 Reserved1; /* 0x02 */
1541 U64 WWID; /* 0x04 */
1542 U64 OwnerWWID; /* 0x0C */
1543 U8 OwnerIdentifier; /* 0x14 */
1544 U8 Reserved2; /* 0x15 */
1545 U16 Flags; /* 0x16 */
1546 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1547 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1549 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1550 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1551 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1552 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1554 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1556 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1557 U8 NumPhysDiskPaths; /* 0x04 */
1558 U8 PhysDiskNum; /* 0x05 */
1559 U16 Reserved1; /* 0x06 */
1560 U32 Reserved2; /* 0x08 */
1561 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1562 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1563 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1564 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1566 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1569 /****************************************************************************
1570 * values for fields used by several types of SAS Config Pages
1571 ****************************************************************************/
1573 /* values for NegotiatedLinkRates fields */
1574 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1575 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1576 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1577 /* link rates used for Negotiated Physical and Logical Link Rate */
1578 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1579 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1580 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1581 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1582 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1583 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1584 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1585 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1586 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1587 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1590 /* values for AttachedPhyInfo fields */
1591 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1592 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1593 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1595 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1596 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1597 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1598 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1599 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1600 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1601 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1602 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1603 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1604 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1607 /* values for PhyInfo fields */
1608 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1610 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1611 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1612 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1613 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1614 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1616 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1617 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1618 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1619 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1620 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1621 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1623 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1624 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1625 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1626 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1627 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1628 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1629 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1630 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1631 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1632 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1634 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1635 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1636 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1637 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1639 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1640 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1642 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1643 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1644 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1645 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1648 /* values for SAS ProgrammedLinkRate fields */
1649 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1650 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1651 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1652 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1653 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1654 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1655 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1656 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1657 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1658 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1661 /* values for SAS HwLinkRate fields */
1662 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1663 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1664 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1665 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1666 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1667 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1668 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1669 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1673 /****************************************************************************
1674 * SAS IO Unit Config Pages
1675 ****************************************************************************/
1677 /* SAS IO Unit Page 0 */
1679 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1682 U8 PortFlags; /* 0x01 */
1683 U8 PhyFlags; /* 0x02 */
1684 U8 NegotiatedLinkRate; /* 0x03 */
1685 U32 ControllerPhyDeviceInfo;/* 0x04 */
1686 U16 AttachedDevHandle; /* 0x08 */
1687 U16 ControllerDevHandle; /* 0x0A */
1688 U32 DiscoveryStatus; /* 0x0C */
1689 U32 Reserved; /* 0x10 */
1690 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1691 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1694 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1695 * one and check the value returned for NumPhys at runtime.
1697 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1698 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1701 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1703 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1704 U32 Reserved1; /* 0x08 */
1705 U8 NumPhys; /* 0x0C */
1706 U8 Reserved2; /* 0x0D */
1707 U16 Reserved3; /* 0x0E */
1708 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1709 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1710 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1711 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1713 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1715 /* values for SAS IO Unit Page 0 PortFlags */
1716 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1717 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1719 /* values for SAS IO Unit Page 0 PhyFlags */
1720 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1721 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1723 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1725 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1727 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1728 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1729 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1730 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1731 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1732 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1733 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1734 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1735 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1736 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1737 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1738 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1739 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1740 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1741 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1742 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1743 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1744 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1745 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1746 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1747 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1750 /* SAS IO Unit Page 1 */
1752 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1755 U8 PortFlags; /* 0x01 */
1756 U8 PhyFlags; /* 0x02 */
1757 U8 MaxMinLinkRate; /* 0x03 */
1758 U32 ControllerPhyDeviceInfo; /* 0x04 */
1759 U16 MaxTargetPortConnectTime; /* 0x08 */
1760 U16 Reserved1; /* 0x0A */
1761 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1762 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1765 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1766 * one and check the value returned for NumPhys at runtime.
1768 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1769 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1772 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1774 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1775 U16 ControlFlags; /* 0x08 */
1776 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1777 U16 AdditionalControlFlags; /* 0x0C */
1778 U16 SASWideMaxQueueDepth; /* 0x0E */
1779 U8 NumPhys; /* 0x10 */
1780 U8 SATAMaxQDepth; /* 0x11 */
1781 U8 ReportDeviceMissingDelay; /* 0x12 */
1782 U8 IODeviceMissingDelay; /* 0x13 */
1783 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1784 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1785 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1786 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1788 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1790 /* values for SAS IO Unit Page 1 ControlFlags */
1791 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1792 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1793 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1794 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1796 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1797 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1798 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1799 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1800 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1802 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1803 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1804 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1805 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1806 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1807 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1808 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1809 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1811 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1812 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1813 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1814 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1815 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1816 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1817 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1818 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1819 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1821 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1822 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1823 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1825 /* values for SAS IO Unit Page 1 PortFlags */
1826 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1828 /* values for SAS IO Unit Page 1 PhyFlags */
1829 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1830 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1832 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1833 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1834 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1835 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1836 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1837 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1838 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1839 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1840 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1842 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1845 /* SAS IO Unit Page 4 */
1847 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1849 U8 MaxTargetSpinup; /* 0x00 */
1850 U8 SpinupDelay; /* 0x01 */
1851 U16 Reserved1; /* 0x02 */
1852 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1853 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1856 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1857 * one and check the value returned for NumPhys at runtime.
1859 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1860 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1863 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1865 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1866 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1867 U32 Reserved1; /* 0x18 */
1868 U32 Reserved2; /* 0x1C */
1869 U32 Reserved3; /* 0x20 */
1870 U8 BootDeviceWaitTime; /* 0x24 */
1871 U8 Reserved4; /* 0x25 */
1872 U16 Reserved5; /* 0x26 */
1873 U8 NumPhys; /* 0x28 */
1874 U8 PEInitialSpinupDelay; /* 0x29 */
1875 U8 PEReplyDelay; /* 0x2A */
1876 U8 Flags; /* 0x2B */
1877 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1878 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1879 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1880 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1882 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1884 /* defines for Flags field */
1885 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1887 /* defines for PHY field */
1888 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1891 /* SAS IO Unit Page 5 */
1893 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
1894 U8 ControlFlags; /* 0x00 */
1895 U8 PortWidthModGroup; /* 0x01 */
1896 U16 InactivityTimerExponent; /* 0x02 */
1897 U8 SATAPartialTimeout; /* 0x04 */
1898 U8 Reserved2; /* 0x05 */
1899 U8 SATASlumberTimeout; /* 0x06 */
1900 U8 Reserved3; /* 0x07 */
1901 U8 SASPartialTimeout; /* 0x08 */
1902 U8 Reserved4; /* 0x09 */
1903 U8 SASSlumberTimeout; /* 0x0A */
1904 U8 Reserved5; /* 0x0B */
1905 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1906 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1907 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1909 /* defines for ControlFlags field */
1910 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1911 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1912 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1913 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1915 /* defines for PortWidthModeGroup field */
1916 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
1918 /* defines for InactivityTimerExponent field */
1919 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1920 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1921 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1922 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1923 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1924 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1925 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1926 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1928 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1929 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1930 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1931 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1932 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1933 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1934 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1935 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1938 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1939 * one and check the value returned for NumPhys at runtime.
1941 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1942 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1945 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
1946 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1947 U8 NumPhys; /* 0x08 */
1948 U8 Reserved1; /* 0x09 */
1949 U16 Reserved2; /* 0x0A */
1950 U32 Reserved3; /* 0x0C */
1951 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
1952 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1953 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1954 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1955 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1957 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
1960 /* SAS IO Unit Page 6 */
1962 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
1963 U8 CurrentStatus; /* 0x00 */
1964 U8 CurrentModulation; /* 0x01 */
1965 U8 CurrentUtilization; /* 0x02 */
1966 U8 Reserved1; /* 0x03 */
1967 U32 Reserved2; /* 0x04 */
1968 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
1969 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
1970 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
1971 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
1973 /* defines for CurrentStatus field */
1974 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
1975 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
1976 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
1977 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
1978 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
1979 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
1980 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
1981 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
1983 /* defines for CurrentModulation field */
1984 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
1985 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
1986 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
1987 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
1990 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1991 * one and check the value returned for NumGroups at runtime.
1993 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
1994 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
1997 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
1998 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1999 U32 Reserved1; /* 0x08 */
2000 U32 Reserved2; /* 0x0C */
2001 U8 NumGroups; /* 0x10 */
2002 U8 Reserved3; /* 0x11 */
2003 U16 Reserved4; /* 0x12 */
2004 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2005 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2006 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2007 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2008 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2010 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2013 /* SAS IO Unit Page 7 */
2015 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2016 U8 Flags; /* 0x00 */
2017 U8 Reserved1; /* 0x01 */
2018 U16 Reserved2; /* 0x02 */
2019 U8 Threshold75Pct; /* 0x04 */
2020 U8 Threshold50Pct; /* 0x05 */
2021 U8 Threshold25Pct; /* 0x06 */
2022 U8 Reserved3; /* 0x07 */
2023 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2024 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2025 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2026 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2028 /* defines for Flags field */
2029 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2033 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2034 * one and check the value returned for NumGroups at runtime.
2036 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2037 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2040 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2041 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2042 U8 SamplingInterval; /* 0x08 */
2043 U8 WindowLength; /* 0x09 */
2044 U16 Reserved1; /* 0x0A */
2045 U32 Reserved2; /* 0x0C */
2046 U32 Reserved3; /* 0x10 */
2047 U8 NumGroups; /* 0x14 */
2048 U8 Reserved4; /* 0x15 */
2049 U16 Reserved5; /* 0x16 */
2050 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2051 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2052 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2053 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2054 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2056 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2059 /* SAS IO Unit Page 8 */
2061 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2062 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2063 U32 Reserved1; /* 0x08 */
2064 U32 PowerManagementCapabilities;/* 0x0C */
2065 U32 Reserved2; /* 0x10 */
2066 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2067 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2068 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2070 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2072 /* defines for PowerManagementCapabilities field */
2073 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
2074 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
2075 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
2076 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
2077 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
2078 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
2079 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
2080 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
2081 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
2082 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
2087 /****************************************************************************
2088 * SAS Expander Config Pages
2089 ****************************************************************************/
2091 /* SAS Expander Page 0 */
2093 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2095 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2096 U8 PhysicalPort; /* 0x08 */
2097 U8 ReportGenLength; /* 0x09 */
2098 U16 EnclosureHandle; /* 0x0A */
2099 U64 SASAddress; /* 0x0C */
2100 U32 DiscoveryStatus; /* 0x14 */
2101 U16 DevHandle; /* 0x18 */
2102 U16 ParentDevHandle; /* 0x1A */
2103 U16 ExpanderChangeCount; /* 0x1C */
2104 U16 ExpanderRouteIndexes; /* 0x1E */
2105 U8 NumPhys; /* 0x20 */
2106 U8 SASLevel; /* 0x21 */
2107 U16 Flags; /* 0x22 */
2108 U16 STPBusInactivityTimeLimit; /* 0x24 */
2109 U16 STPMaxConnectTimeLimit; /* 0x26 */
2110 U16 STP_SMP_NexusLossTime; /* 0x28 */
2111 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2112 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2113 U16 ZoneLockInactivityLimit; /* 0x34 */
2114 U16 Reserved1; /* 0x36 */
2115 U8 TimeToReducedFunc; /* 0x38 */
2116 U8 InitialTimeToReducedFunc; /* 0x39 */
2117 U8 MaxReducedFuncTime; /* 0x3A */
2118 U8 Reserved2; /* 0x3B */
2119 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2120 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2122 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2124 /* values for SAS Expander Page 0 DiscoveryStatus field */
2125 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2126 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2127 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2128 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2129 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2130 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2131 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2132 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2133 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2134 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2135 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2136 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2137 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2138 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2139 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2140 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2141 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2142 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2143 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2144 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2146 /* values for SAS Expander Page 0 Flags field */
2147 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2148 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2149 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2150 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2151 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2152 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2153 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2154 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2155 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2156 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2157 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2160 /* SAS Expander Page 1 */
2162 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2164 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2165 U8 PhysicalPort; /* 0x08 */
2166 U8 Reserved1; /* 0x09 */
2167 U16 Reserved2; /* 0x0A */
2168 U8 NumPhys; /* 0x0C */
2170 U16 NumTableEntriesProgrammed; /* 0x0E */
2171 U8 ProgrammedLinkRate; /* 0x10 */
2172 U8 HwLinkRate; /* 0x11 */
2173 U16 AttachedDevHandle; /* 0x12 */
2174 U32 PhyInfo; /* 0x14 */
2175 U32 AttachedDeviceInfo; /* 0x18 */
2176 U16 ExpanderDevHandle; /* 0x1C */
2177 U8 ChangeCount; /* 0x1E */
2178 U8 NegotiatedLinkRate; /* 0x1F */
2179 U8 PhyIdentifier; /* 0x20 */
2180 U8 AttachedPhyIdentifier; /* 0x21 */
2181 U8 Reserved3; /* 0x22 */
2182 U8 DiscoveryInfo; /* 0x23 */
2183 U32 AttachedPhyInfo; /* 0x24 */
2184 U8 ZoneGroup; /* 0x28 */
2185 U8 SelfConfigStatus; /* 0x29 */
2186 U16 Reserved4; /* 0x2A */
2187 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2188 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2190 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2192 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2194 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2196 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2198 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2200 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2202 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2204 /* values for SAS Expander Page 1 DiscoveryInfo field */
2205 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2206 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2207 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2210 /****************************************************************************
2211 * SAS Device Config Pages
2212 ****************************************************************************/
2214 /* SAS Device Page 0 */
2216 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2218 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2219 U16 Slot; /* 0x08 */
2220 U16 EnclosureHandle; /* 0x0A */
2221 U64 SASAddress; /* 0x0C */
2222 U16 ParentDevHandle; /* 0x14 */
2223 U8 PhyNum; /* 0x16 */
2224 U8 AccessStatus; /* 0x17 */
2225 U16 DevHandle; /* 0x18 */
2226 U8 AttachedPhyIdentifier; /* 0x1A */
2227 U8 ZoneGroup; /* 0x1B */
2228 U32 DeviceInfo; /* 0x1C */
2229 U16 Flags; /* 0x20 */
2230 U8 PhysicalPort; /* 0x22 */
2231 U8 MaxPortConnections; /* 0x23 */
2232 U64 DeviceName; /* 0x24 */
2233 U8 PortGroups; /* 0x2C */
2234 U8 DmaGroup; /* 0x2D */
2235 U8 ControlGroup; /* 0x2E */
2236 U8 Reserved1; /* 0x2F */
2237 U32 Reserved2; /* 0x30 */
2238 U32 Reserved3; /* 0x34 */
2239 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2240 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2242 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2244 /* values for SAS Device Page 0 AccessStatus field */
2245 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2246 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2247 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2248 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2249 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2250 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2251 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2252 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2253 /* specific values for SATA Init failures */
2254 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2255 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2256 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2257 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2258 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2259 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2260 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2261 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2262 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2263 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2264 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2266 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2268 /* values for SAS Device Page 0 Flags field */
2269 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2270 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2271 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2272 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2273 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2274 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2275 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2276 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2277 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2278 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2279 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2282 /* SAS Device Page 1 */
2284 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2286 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2287 U32 Reserved1; /* 0x08 */
2288 U64 SASAddress; /* 0x0C */
2289 U32 Reserved2; /* 0x14 */
2290 U16 DevHandle; /* 0x18 */
2291 U16 Reserved3; /* 0x1A */
2292 U8 InitialRegDeviceFIS[20];/* 0x1C */
2293 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2294 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2296 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2299 /****************************************************************************
2300 * SAS PHY Config Pages
2301 ****************************************************************************/
2303 /* SAS PHY Page 0 */
2305 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2307 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2308 U16 OwnerDevHandle; /* 0x08 */
2309 U16 Reserved1; /* 0x0A */
2310 U16 AttachedDevHandle; /* 0x0C */
2311 U8 AttachedPhyIdentifier; /* 0x0E */
2312 U8 Reserved2; /* 0x0F */
2313 U32 AttachedPhyInfo; /* 0x10 */
2314 U8 ProgrammedLinkRate; /* 0x14 */
2315 U8 HwLinkRate; /* 0x15 */
2316 U8 ChangeCount; /* 0x16 */
2317 U8 Flags; /* 0x17 */
2318 U32 PhyInfo; /* 0x18 */
2319 U8 NegotiatedLinkRate; /* 0x1C */
2320 U8 Reserved3; /* 0x1D */
2321 U16 Reserved4; /* 0x1E */
2322 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2323 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2325 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2327 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2329 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2331 /* values for SAS PHY Page 0 Flags field */
2332 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2334 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2336 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2338 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2341 /* SAS PHY Page 1 */
2343 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2345 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2346 U32 Reserved1; /* 0x08 */
2347 U32 InvalidDwordCount; /* 0x0C */
2348 U32 RunningDisparityErrorCount; /* 0x10 */
2349 U32 LossDwordSynchCount; /* 0x14 */
2350 U32 PhyResetProblemCount; /* 0x18 */
2351 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2352 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2354 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2357 /* SAS PHY Page 2 */
2359 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2360 U8 PhyEventCode; /* 0x00 */
2361 U8 Reserved1; /* 0x01 */
2362 U16 Reserved2; /* 0x02 */
2363 U32 PhyEventInfo; /* 0x04 */
2364 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2365 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2367 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2371 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2372 * one and check the value returned for NumPhyEvents at runtime.
2374 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2375 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2378 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2379 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2380 U32 Reserved1; /* 0x08 */
2381 U8 NumPhyEvents; /* 0x0C */
2382 U8 Reserved2; /* 0x0D */
2383 U16 Reserved3; /* 0x0E */
2384 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2386 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2387 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2389 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2392 /* SAS PHY Page 3 */
2394 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2395 U8 PhyEventCode; /* 0x00 */
2396 U8 Reserved1; /* 0x01 */
2397 U16 Reserved2; /* 0x02 */
2398 U8 CounterType; /* 0x04 */
2399 U8 ThresholdWindow; /* 0x05 */
2400 U8 TimeUnits; /* 0x06 */
2401 U8 Reserved3; /* 0x07 */
2402 U32 EventThreshold; /* 0x08 */
2403 U16 ThresholdFlags; /* 0x0C */
2404 U16 Reserved4; /* 0x0E */
2405 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2406 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2408 /* values for PhyEventCode field */
2409 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2410 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2411 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2412 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2413 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2414 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2415 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2416 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2417 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2418 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2419 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2420 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2421 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2422 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2423 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2424 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2425 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2426 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2427 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2428 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2429 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2430 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2431 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2432 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2433 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2434 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2435 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2436 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2437 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2438 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2439 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2440 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2441 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2442 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2443 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2444 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2445 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2447 /* values for the CounterType field */
2448 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2449 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2450 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2452 /* values for the TimeUnits field */
2453 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2454 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2455 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2456 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2458 /* values for the ThresholdFlags field */
2459 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2460 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2463 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2464 * one and check the value returned for NumPhyEvents at runtime.
2466 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2467 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2470 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2471 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2472 U32 Reserved1; /* 0x08 */
2473 U8 NumPhyEvents; /* 0x0C */
2474 U8 Reserved2; /* 0x0D */
2475 U16 Reserved3; /* 0x0E */
2476 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2477 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2478 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2479 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2481 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2484 /* SAS PHY Page 4 */
2486 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2487 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2488 U16 Reserved1; /* 0x08 */
2489 U8 Reserved2; /* 0x0A */
2490 U8 Flags; /* 0x0B */
2491 U8 InitialFrame[28]; /* 0x0C */
2492 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2493 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2495 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2497 /* values for the Flags field */
2498 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2499 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2504 /****************************************************************************
2505 * SAS Port Config Pages
2506 ****************************************************************************/
2508 /* SAS Port Page 0 */
2510 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2512 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2513 U8 PortNumber; /* 0x08 */
2514 U8 PhysicalPort; /* 0x09 */
2515 U8 PortWidth; /* 0x0A */
2516 U8 PhysicalPortWidth; /* 0x0B */
2517 U8 ZoneGroup; /* 0x0C */
2518 U8 Reserved1; /* 0x0D */
2519 U16 Reserved2; /* 0x0E */
2520 U64 SASAddress; /* 0x10 */
2521 U32 DeviceInfo; /* 0x18 */
2522 U32 Reserved3; /* 0x1C */
2523 U32 Reserved4; /* 0x20 */
2524 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2525 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2527 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2529 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2532 /****************************************************************************
2533 * SAS Enclosure Config Pages
2534 ****************************************************************************/
2536 /* SAS Enclosure Page 0 */
2538 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2540 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2541 U32 Reserved1; /* 0x08 */
2542 U64 EnclosureLogicalID; /* 0x0C */
2543 U16 Flags; /* 0x14 */
2544 U16 EnclosureHandle; /* 0x16 */
2545 U16 NumSlots; /* 0x18 */
2546 U16 StartSlot; /* 0x1A */
2547 U16 Reserved2; /* 0x1C */
2548 U16 SEPDevHandle; /* 0x1E */
2549 U32 Reserved3; /* 0x20 */
2550 U32 Reserved4; /* 0x24 */
2551 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2552 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2553 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2555 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2557 /* values for SAS Enclosure Page 0 Flags field */
2558 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2559 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2560 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2561 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2562 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2563 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2564 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2567 /****************************************************************************
2569 ****************************************************************************/
2574 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2575 * one and check the value returned for NumLogEntries at runtime.
2577 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2578 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2581 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2583 typedef struct _MPI2_LOG_0_ENTRY
2585 U64 TimeStamp; /* 0x00 */
2586 U32 Reserved1; /* 0x08 */
2587 U16 LogSequence; /* 0x0C */
2588 U16 LogEntryQualifier; /* 0x0E */
2589 U8 VP_ID; /* 0x10 */
2590 U8 VF_ID; /* 0x11 */
2591 U16 Reserved2; /* 0x12 */
2592 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2593 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2594 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2596 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2597 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2598 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2599 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2600 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2601 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2603 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2605 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2606 U32 Reserved1; /* 0x08 */
2607 U32 Reserved2; /* 0x0C */
2608 U16 NumLogEntries; /* 0x10 */
2609 U16 Reserved3; /* 0x12 */
2610 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2611 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2612 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2614 #define MPI2_LOG_0_PAGEVERSION (0x02)
2617 /****************************************************************************
2619 ****************************************************************************/
2624 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2625 * one and check the value returned for NumElements at runtime.
2627 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2628 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2631 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2633 U16 ElementFlags; /* 0x00 */
2634 U16 VolDevHandle; /* 0x02 */
2635 U8 HotSparePool; /* 0x04 */
2636 U8 PhysDiskNum; /* 0x05 */
2637 U16 PhysDiskDevHandle; /* 0x06 */
2638 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2639 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2640 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2642 /* values for the ElementFlags field */
2643 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2644 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2645 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2646 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2647 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2650 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2652 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2653 U8 NumHotSpares; /* 0x08 */
2654 U8 NumPhysDisks; /* 0x09 */
2655 U8 NumVolumes; /* 0x0A */
2656 U8 ConfigNum; /* 0x0B */
2657 U32 Flags; /* 0x0C */
2658 U8 ConfigGUID[24]; /* 0x10 */
2659 U32 Reserved1; /* 0x28 */
2660 U8 NumElements; /* 0x2C */
2661 U8 Reserved2; /* 0x2D */
2662 U16 Reserved3; /* 0x2E */
2663 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2664 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2665 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2666 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2668 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2670 /* values for RAID Configuration Page 0 Flags field */
2671 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2674 /****************************************************************************
2675 * Driver Persistent Mapping Config Pages
2676 ****************************************************************************/
2678 /* Driver Persistent Mapping Page 0 */
2680 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2682 U64 PhysicalIdentifier; /* 0x00 */
2683 U16 MappingInformation; /* 0x08 */
2684 U16 DeviceIndex; /* 0x0A */
2685 U32 PhysicalBitsMapping; /* 0x0C */
2686 U32 Reserved1; /* 0x10 */
2687 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2688 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2689 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2691 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2693 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2694 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2695 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2696 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2697 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2699 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2701 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2702 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2703 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2704 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2707 /****************************************************************************
2708 * Ethernet Config Pages
2709 ****************************************************************************/
2711 /* Ethernet Page 0 */
2713 /* IP address (union of IPv4 and IPv6) */
2714 typedef union _MPI2_ETHERNET_IP_ADDR {
2717 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2718 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2720 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2722 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2723 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2724 U8 NumInterfaces; /* 0x08 */
2725 U8 Reserved0; /* 0x09 */
2726 U16 Reserved1; /* 0x0A */
2727 U32 Status; /* 0x0C */
2728 U8 MediaState; /* 0x10 */
2729 U8 Reserved2; /* 0x11 */
2730 U16 Reserved3; /* 0x12 */
2731 U8 MacAddress[6]; /* 0x14 */
2732 U8 Reserved4; /* 0x1A */
2733 U8 Reserved5; /* 0x1B */
2734 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2735 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2736 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2737 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2738 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2739 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2741 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2742 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2743 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2745 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2747 /* values for Ethernet Page 0 Status field */
2748 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2749 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2750 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2751 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2752 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2753 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2754 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2755 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2756 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2757 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2758 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2759 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2761 /* values for Ethernet Page 0 MediaState field */
2762 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2763 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2764 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2766 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2767 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2768 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2769 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2770 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2773 /* Ethernet Page 1 */
2775 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2776 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2777 U32 Reserved0; /* 0x08 */
2778 U32 Flags; /* 0x0C */
2779 U8 MediaState; /* 0x10 */
2780 U8 Reserved1; /* 0x11 */
2781 U16 Reserved2; /* 0x12 */
2782 U8 MacAddress[6]; /* 0x14 */
2783 U8 Reserved3; /* 0x1A */
2784 U8 Reserved4; /* 0x1B */
2785 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2786 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2787 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2788 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2789 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2790 U32 Reserved5; /* 0x6C */
2791 U32 Reserved6; /* 0x70 */
2792 U32 Reserved7; /* 0x74 */
2793 U32 Reserved8; /* 0x78 */
2795 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2796 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2797 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2799 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2801 /* values for Ethernet Page 1 Flags field */
2802 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2803 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2804 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2805 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2806 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2807 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2808 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2809 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2810 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2812 /* values for Ethernet Page 1 MediaState field */
2813 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2814 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2815 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2817 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2818 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2819 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2820 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2821 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2824 /****************************************************************************
2825 * Extended Manufacturing Config Pages
2826 ****************************************************************************/
2829 * Generic structure to use for product-specific extended manufacturing pages
2830 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2834 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
2835 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2836 U32 ProductSpecificInfo; /* 0x08 */
2837 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
2838 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2839 Mpi2ExtManufacturingPagePS_t,
2840 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2842 /* PageVersion should be provided by product-specific code */
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