drivers/soc/imx/gpcv2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 Impinj, Inc
   4  * Author: Andrey Smirnov <[email protected]>
   5  *
   6  * Based on the code of analogus driver:
   7  *
   8  * Copyright 2015-2017 Pengutronix, Lucas Stach <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19 #include <linux/sizes.h>
  20 #include <dt-bindings/power/imx7-power.h>
  21 #include <dt-bindings/power/imx8mq-power.h>
  22 #include <dt-bindings/power/imx8mm-power.h>
  23 #include <dt-bindings/power/imx8mn-power.h>
  24
  25 #define GPC_LPCR_A_CORE_BSC                     0x000
  26
  27 #define GPC_PGC_CPU_MAPPING             0x0ec
  28
  29 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN         BIT(6)
  30 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN         BIT(5)
  31 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN         BIT(4)
  32 #define IMX7_PCIE_PHY_A_CORE_DOMAIN             BIT(3)
  33 #define IMX7_MIPI_PHY_A_CORE_DOMAIN             BIT(2)
  34
  35 #define IMX8M_PCIE2_A53_DOMAIN                  BIT(15)
  36 #define IMX8M_MIPI_CSI2_A53_DOMAIN              BIT(14)
  37 #define IMX8M_MIPI_CSI1_A53_DOMAIN              BIT(13)
  38 #define IMX8M_DISP_A53_DOMAIN                   BIT(12)
  39 #define IMX8M_HDMI_A53_DOMAIN                   BIT(11)
  40 #define IMX8M_VPU_A53_DOMAIN                    BIT(10)
  41 #define IMX8M_GPU_A53_DOMAIN                    BIT(9)
  42 #define IMX8M_DDR2_A53_DOMAIN                   BIT(8)
  43 #define IMX8M_DDR1_A53_DOMAIN                   BIT(7)
  44 #define IMX8M_OTG2_A53_DOMAIN                   BIT(5)
  45 #define IMX8M_OTG1_A53_DOMAIN                   BIT(4)
  46 #define IMX8M_PCIE1_A53_DOMAIN                  BIT(3)
  47 #define IMX8M_MIPI_A53_DOMAIN                   BIT(2)
  48
  49 #define IMX8MM_VPUH1_A53_DOMAIN                 BIT(15)
  50 #define IMX8MM_VPUG2_A53_DOMAIN                 BIT(14)
  51 #define IMX8MM_VPUG1_A53_DOMAIN                 BIT(13)
  52 #define IMX8MM_DISPMIX_A53_DOMAIN               BIT(12)
  53 #define IMX8MM_VPUMIX_A53_DOMAIN                BIT(10)
  54 #define IMX8MM_GPUMIX_A53_DOMAIN                BIT(9)
  55 #define IMX8MM_GPU_A53_DOMAIN                   (BIT(8) | BIT(11))
  56 #define IMX8MM_DDR1_A53_DOMAIN                  BIT(7)
  57 #define IMX8MM_OTG2_A53_DOMAIN                  BIT(5)
  58 #define IMX8MM_OTG1_A53_DOMAIN                  BIT(4)
  59 #define IMX8MM_PCIE_A53_DOMAIN                  BIT(3)
  60 #define IMX8MM_MIPI_A53_DOMAIN                  BIT(2)
  61
  62 #define IMX8MN_DISPMIX_A53_DOMAIN               BIT(12)
  63 #define IMX8MN_GPUMIX_A53_DOMAIN                BIT(9)
  64 #define IMX8MN_DDR1_A53_DOMAIN          BIT(7)
  65 #define IMX8MN_OTG1_A53_DOMAIN          BIT(4)
  66 #define IMX8MN_MIPI_A53_DOMAIN          BIT(2)
  67
  68 #define GPC_PU_PGC_SW_PUP_REQ           0x0f8
  69 #define GPC_PU_PGC_SW_PDN_REQ           0x104
  70
  71 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ            BIT(4)
  72 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ            BIT(3)
  73 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ            BIT(2)
  74 #define IMX7_PCIE_PHY_SW_Pxx_REQ                BIT(1)
  75 #define IMX7_MIPI_PHY_SW_Pxx_REQ                BIT(0)
  76
  77 #define IMX8M_PCIE2_SW_Pxx_REQ                  BIT(13)
  78 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ              BIT(12)
  79 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ              BIT(11)
  80 #define IMX8M_DISP_SW_Pxx_REQ                   BIT(10)
  81 #define IMX8M_HDMI_SW_Pxx_REQ                   BIT(9)
  82 #define IMX8M_VPU_SW_Pxx_REQ                    BIT(8)
  83 #define IMX8M_GPU_SW_Pxx_REQ                    BIT(7)
  84 #define IMX8M_DDR2_SW_Pxx_REQ                   BIT(6)
  85 #define IMX8M_DDR1_SW_Pxx_REQ                   BIT(5)
  86 #define IMX8M_OTG2_SW_Pxx_REQ                   BIT(3)
  87 #define IMX8M_OTG1_SW_Pxx_REQ                   BIT(2)
  88 #define IMX8M_PCIE1_SW_Pxx_REQ                  BIT(1)
  89 #define IMX8M_MIPI_SW_Pxx_REQ                   BIT(0)
  90
  91 #define IMX8MM_VPUH1_SW_Pxx_REQ                 BIT(13)
  92 #define IMX8MM_VPUG2_SW_Pxx_REQ                 BIT(12)
  93 #define IMX8MM_VPUG1_SW_Pxx_REQ                 BIT(11)
  94 #define IMX8MM_DISPMIX_SW_Pxx_REQ               BIT(10)
  95 #define IMX8MM_VPUMIX_SW_Pxx_REQ                BIT(8)
  96 #define IMX8MM_GPUMIX_SW_Pxx_REQ                BIT(7)
  97 #define IMX8MM_GPU_SW_Pxx_REQ                   (BIT(6) | BIT(9))
  98 #define IMX8MM_DDR1_SW_Pxx_REQ                  BIT(5)
  99 #define IMX8MM_OTG2_SW_Pxx_REQ                  BIT(3)
 100 #define IMX8MM_OTG1_SW_Pxx_REQ                  BIT(2)
 101 #define IMX8MM_PCIE_SW_Pxx_REQ                  BIT(1)
 102 #define IMX8MM_MIPI_SW_Pxx_REQ                  BIT(0)
 103
 104 #define IMX8MN_DISPMIX_SW_Pxx_REQ               BIT(10)
 105 #define IMX8MN_GPUMIX_SW_Pxx_REQ                BIT(7)
 106 #define IMX8MN_DDR1_SW_Pxx_REQ          BIT(5)
 107 #define IMX8MN_OTG1_SW_Pxx_REQ          BIT(2)
 108 #define IMX8MN_MIPI_SW_Pxx_REQ          BIT(0)
 109
 110 #define GPC_M4_PU_PDN_FLG               0x1bc
 111
 112 #define GPC_PU_PWRHSK                   0x1fc
 113
 114 #define IMX8M_GPU_HSK_PWRDNACKN                 BIT(26)
 115 #define IMX8M_VPU_HSK_PWRDNACKN                 BIT(25)
 116 #define IMX8M_DISP_HSK_PWRDNACKN                BIT(24)
 117 #define IMX8M_GPU_HSK_PWRDNREQN                 BIT(6)
 118 #define IMX8M_VPU_HSK_PWRDNREQN                 BIT(5)
 119 #define IMX8M_DISP_HSK_PWRDNREQN                BIT(4)
 120
 121
 122 #define IMX8MM_GPUMIX_HSK_PWRDNACKN             BIT(29)
 123 #define IMX8MM_GPU_HSK_PWRDNACKN                (BIT(27) | BIT(28))
 124 #define IMX8MM_VPUMIX_HSK_PWRDNACKN             BIT(26)
 125 #define IMX8MM_DISPMIX_HSK_PWRDNACKN            BIT(25)
 126 #define IMX8MM_HSIO_HSK_PWRDNACKN               (BIT(23) | BIT(24))
 127 #define IMX8MM_GPUMIX_HSK_PWRDNREQN             BIT(11)
 128 #define IMX8MM_GPU_HSK_PWRDNREQN                (BIT(9) | BIT(10))
 129 #define IMX8MM_VPUMIX_HSK_PWRDNREQN             BIT(8)
 130 #define IMX8MM_DISPMIX_HSK_PWRDNREQN            BIT(7)
 131 #define IMX8MM_HSIO_HSK_PWRDNREQN               (BIT(5) | BIT(6))
 132
 133 #define IMX8MN_GPUMIX_HSK_PWRDNACKN             (BIT(29) | BIT(27))
 134 #define IMX8MN_DISPMIX_HSK_PWRDNACKN            BIT(25)
 135 #define IMX8MN_HSIO_HSK_PWRDNACKN               BIT(23)
 136 #define IMX8MN_GPUMIX_HSK_PWRDNREQN             (BIT(11) | BIT(9))
 137 #define IMX8MN_DISPMIX_HSK_PWRDNREQN            BIT(7)
 138 #define IMX8MN_HSIO_HSK_PWRDNREQN               BIT(5)
 139
 140 /*
 141  * The PGC offset values in Reference Manual
 142  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
 143  * GPC_PGC memory map are incorrect, below offset
 144  * values are from design RTL.
 145  */
 146 #define IMX7_PGC_MIPI                   16
 147 #define IMX7_PGC_PCIE                   17
 148 #define IMX7_PGC_USB_HSIC               20
 149
 150 #define IMX8M_PGC_MIPI                  16
 151 #define IMX8M_PGC_PCIE1                 17
 152 #define IMX8M_PGC_OTG1                  18
 153 #define IMX8M_PGC_OTG2                  19
 154 #define IMX8M_PGC_DDR1                  21
 155 #define IMX8M_PGC_GPU                   23
 156 #define IMX8M_PGC_VPU                   24
 157 #define IMX8M_PGC_DISP                  26
 158 #define IMX8M_PGC_MIPI_CSI1             27
 159 #define IMX8M_PGC_MIPI_CSI2             28
 160 #define IMX8M_PGC_PCIE2                 29
 161
 162 #define IMX8MM_PGC_MIPI                 16
 163 #define IMX8MM_PGC_PCIE                 17
 164 #define IMX8MM_PGC_OTG1                 18
 165 #define IMX8MM_PGC_OTG2                 19
 166 #define IMX8MM_PGC_DDR1                 21
 167 #define IMX8MM_PGC_GPU2D                22
 168 #define IMX8MM_PGC_GPUMIX               23
 169 #define IMX8MM_PGC_VPUMIX               24
 170 #define IMX8MM_PGC_GPU3D                25
 171 #define IMX8MM_PGC_DISPMIX              26
 172 #define IMX8MM_PGC_VPUG1                27
 173 #define IMX8MM_PGC_VPUG2                28
 174 #define IMX8MM_PGC_VPUH1                29
 175
 176 #define IMX8MN_PGC_MIPI         16
 177 #define IMX8MN_PGC_OTG1         18
 178 #define IMX8MN_PGC_DDR1         21
 179 #define IMX8MN_PGC_GPUMIX               23
 180 #define IMX8MN_PGC_DISPMIX              26
 181
 182 #define GPC_PGC_CTRL(n)                 (0x800 + (n) * 0x40)
 183 #define GPC_PGC_SR(n)                   (GPC_PGC_CTRL(n) + 0xc)
 184
 185 #define GPC_PGC_CTRL_PCR                BIT(0)
 186
 187 struct imx_pgc_domain {
 188         struct generic_pm_domain genpd;
 189         struct regmap *regmap;
 190         struct regulator *regulator;
 191         struct reset_control *reset;
 192         struct clk_bulk_data *clks;
 193         int num_clks;
 194
 195         unsigned int pgc;
 196
 197         const struct {
 198                 u32 pxx;
 199                 u32 map;
 200                 u32 hskreq;
 201                 u32 hskack;
 202         } bits;
 203
 204         const int voltage;
 205         struct device *dev;
 206 };
 207
 208 struct imx_pgc_domain_data {
 209         const struct imx_pgc_domain *domains;
 210         size_t domains_num;
 211         const struct regmap_access_table *reg_access_table;
 212 };
 213
 214 static inline struct imx_pgc_domain *
 215 to_imx_pgc_domain(struct generic_pm_domain *genpd)
 216 {
 217         return container_of(genpd, struct imx_pgc_domain, genpd);
 218 }
 219
 220 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 221 {
 222         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 223         u32 reg_val;
 224         int ret;
 225
 226         ret = pm_runtime_get_sync(domain->dev);
 227         if (ret < 0) {
 228                 pm_runtime_put_noidle(domain->dev);
 229                 return ret;
 230         }
 231
 232         if (!IS_ERR(domain->regulator)) {
 233                 ret = regulator_enable(domain->regulator);
 234                 if (ret) {
 235                         dev_err(domain->dev, "failed to enable regulator\n");
 236                         goto out_put_pm;
 237                 }
 238         }
 239
 240         /* Enable reset clocks for all devices in the domain */
 241         ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 242         if (ret) {
 243                 dev_err(domain->dev, "failed to enable reset clocks\n");
 244                 goto out_regulator_disable;
 245         }
 246
 247         if (domain->bits.pxx) {
 248                 /* request the domain to power up */
 249                 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
 250                                    domain->bits.pxx, domain->bits.pxx);
 251                 /*
 252                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 253                  * for PUP_REQ/PDN_REQ bit to be cleared
 254                  */
 255                 ret = regmap_read_poll_timeout(domain->regmap,
 256                                                GPC_PU_PGC_SW_PUP_REQ, reg_val,
 257                                                !(reg_val & domain->bits.pxx),
 258                                                0, USEC_PER_MSEC);
 259                 if (ret) {
 260                         dev_err(domain->dev, "failed to command PGC\n");
 261                         goto out_clk_disable;
 262                 }
 263
 264                 /* disable power control */
 265                 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
 266                                   GPC_PGC_CTRL_PCR);
 267         }
 268
 269         reset_control_assert(domain->reset);
 270
 271         /* delay for reset to propagate */
 272         udelay(5);
 273
 274         reset_control_deassert(domain->reset);
 275
 276         /* request the ADB400 to power up */
 277         if (domain->bits.hskreq) {
 278                 regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
 279                                    domain->bits.hskreq, domain->bits.hskreq);
 280
 281                 /*
 282                  * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
 283                  *                                (reg_val & domain->bits.hskack), 0,
 284                  *                                USEC_PER_MSEC);
 285                  * Technically we need the commented code to wait handshake. But that needs
 286                  * the BLK-CTL module BUS clk-en bit being set.
 287                  *
 288                  * There is a separate BLK-CTL module and we will have such a driver for it,
 289                  * that driver will set the BUS clk-en bit and handshake will be triggered
 290                  * automatically there. Just add a delay and suppose the handshake finish
 291                  * after that.
 292                  */
 293         }
 294
 295         /* Disable reset clocks for all devices in the domain */
 296         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 297
 298         return 0;
 299
 300 out_clk_disable:
 301         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 302 out_regulator_disable:
 303         if (!IS_ERR(domain->regulator))
 304                 regulator_disable(domain->regulator);
 305 out_put_pm:
 306         pm_runtime_put(domain->dev);
 307
 308         return ret;
 309 }
 310
 311 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 312 {
 313         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 314         u32 reg_val;
 315         int ret;
 316
 317         /* Enable reset clocks for all devices in the domain */
 318         ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 319         if (ret) {
 320                 dev_err(domain->dev, "failed to enable reset clocks\n");
 321                 return ret;
 322         }
 323
 324         /* request the ADB400 to power down */
 325         if (domain->bits.hskreq) {
 326                 regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
 327                                   domain->bits.hskreq);
 328
 329                 ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
 330                                                reg_val,
 331                                                !(reg_val & domain->bits.hskack),
 332                                                0, USEC_PER_MSEC);
 333                 if (ret) {
 334                         dev_err(domain->dev, "failed to power down ADB400\n");
 335                         goto out_clk_disable;
 336                 }
 337         }
 338
 339         if (domain->bits.pxx) {
 340                 /* enable power control */
 341                 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
 342                                    GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
 343
 344                 /* request the domain to power down */
 345                 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
 346                                    domain->bits.pxx, domain->bits.pxx);
 347                 /*
 348                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 349                  * for PUP_REQ/PDN_REQ bit to be cleared
 350                  */
 351                 ret = regmap_read_poll_timeout(domain->regmap,
 352                                                GPC_PU_PGC_SW_PDN_REQ, reg_val,
 353                                                !(reg_val & domain->bits.pxx),
 354                                                0, USEC_PER_MSEC);
 355                 if (ret) {
 356                         dev_err(domain->dev, "failed to command PGC\n");
 357                         goto out_clk_disable;
 358                 }
 359         }
 360
 361         /* Disable reset clocks for all devices in the domain */
 362         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 363
 364         if (!IS_ERR(domain->regulator)) {
 365                 ret = regulator_disable(domain->regulator);
 366                 if (ret) {
 367                         dev_err(domain->dev, "failed to disable regulator\n");
 368                         return ret;
 369                 }
 370         }
 371
 372         pm_runtime_put(domain->dev);
 373
 374         return 0;
 375
 376 out_clk_disable:
 377         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 378
 379         return ret;
 380 }
 381
 382 static const struct imx_pgc_domain imx7_pgc_domains[] = {
 383         [IMX7_POWER_DOMAIN_MIPI_PHY] = {
 384                 .genpd = {
 385                         .name      = "mipi-phy",
 386                 },
 387                 .bits  = {
 388                         .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
 389                         .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 390                 },
 391                 .voltage   = 1000000,
 392                 .pgc       = IMX7_PGC_MIPI,
 393         },
 394
 395         [IMX7_POWER_DOMAIN_PCIE_PHY] = {
 396                 .genpd = {
 397                         .name      = "pcie-phy",
 398                 },
 399                 .bits  = {
 400                         .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
 401                         .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 402                 },
 403                 .voltage   = 1000000,
 404                 .pgc       = IMX7_PGC_PCIE,
 405         },
 406
 407         [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
 408                 .genpd = {
 409                         .name      = "usb-hsic-phy",
 410                 },
 411                 .bits  = {
 412                         .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
 413                         .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 414                 },
 415                 .voltage   = 1200000,
 416                 .pgc       = IMX7_PGC_USB_HSIC,
 417         },
 418 };
 419
 420 static const struct regmap_range imx7_yes_ranges[] = {
 421                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 422                                  GPC_M4_PU_PDN_FLG),
 423                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
 424                                  GPC_PGC_SR(IMX7_PGC_MIPI)),
 425                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
 426                                  GPC_PGC_SR(IMX7_PGC_PCIE)),
 427                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
 428                                  GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
 429 };
 430
 431 static const struct regmap_access_table imx7_access_table = {
 432         .yes_ranges     = imx7_yes_ranges,
 433         .n_yes_ranges   = ARRAY_SIZE(imx7_yes_ranges),
 434 };
 435
 436 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
 437         .domains = imx7_pgc_domains,
 438         .domains_num = ARRAY_SIZE(imx7_pgc_domains),
 439         .reg_access_table = &imx7_access_table,
 440 };
 441
 442 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 443         [IMX8M_POWER_DOMAIN_MIPI] = {
 444                 .genpd = {
 445                         .name      = "mipi",
 446                 },
 447                 .bits  = {
 448                         .pxx = IMX8M_MIPI_SW_Pxx_REQ,
 449                         .map = IMX8M_MIPI_A53_DOMAIN,
 450                 },
 451                 .pgc       = IMX8M_PGC_MIPI,
 452         },
 453
 454         [IMX8M_POWER_DOMAIN_PCIE1] = {
 455                 .genpd = {
 456                         .name = "pcie1",
 457                 },
 458                 .bits  = {
 459                         .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 460                         .map = IMX8M_PCIE1_A53_DOMAIN,
 461                 },
 462                 .pgc   = IMX8M_PGC_PCIE1,
 463         },
 464
 465         [IMX8M_POWER_DOMAIN_USB_OTG1] = {
 466                 .genpd = {
 467                         .name = "usb-otg1",
 468                 },
 469                 .bits  = {
 470                         .pxx = IMX8M_OTG1_SW_Pxx_REQ,
 471                         .map = IMX8M_OTG1_A53_DOMAIN,
 472                 },
 473                 .pgc   = IMX8M_PGC_OTG1,
 474         },
 475
 476         [IMX8M_POWER_DOMAIN_USB_OTG2] = {
 477                 .genpd = {
 478                         .name = "usb-otg2",
 479                 },
 480                 .bits  = {
 481                         .pxx = IMX8M_OTG2_SW_Pxx_REQ,
 482                         .map = IMX8M_OTG2_A53_DOMAIN,
 483                 },
 484                 .pgc   = IMX8M_PGC_OTG2,
 485         },
 486
 487         [IMX8M_POWER_DOMAIN_DDR1] = {
 488                 .genpd = {
 489                         .name = "ddr1",
 490                 },
 491                 .bits  = {
 492                         .pxx = IMX8M_DDR1_SW_Pxx_REQ,
 493                         .map = IMX8M_DDR2_A53_DOMAIN,
 494                 },
 495                 .pgc   = IMX8M_PGC_DDR1,
 496         },
 497
 498         [IMX8M_POWER_DOMAIN_GPU] = {
 499                 .genpd = {
 500                         .name = "gpu",
 501                 },
 502                 .bits  = {
 503                         .pxx = IMX8M_GPU_SW_Pxx_REQ,
 504                         .map = IMX8M_GPU_A53_DOMAIN,
 505                         .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 506                         .hskack = IMX8M_GPU_HSK_PWRDNACKN,
 507                 },
 508                 .pgc   = IMX8M_PGC_GPU,
 509         },
 510
 511         [IMX8M_POWER_DOMAIN_VPU] = {
 512                 .genpd = {
 513                         .name = "vpu",
 514                 },
 515                 .bits  = {
 516                         .pxx = IMX8M_VPU_SW_Pxx_REQ,
 517                         .map = IMX8M_VPU_A53_DOMAIN,
 518                         .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 519                         .hskack = IMX8M_VPU_HSK_PWRDNACKN,
 520                 },
 521                 .pgc   = IMX8M_PGC_VPU,
 522         },
 523
 524         [IMX8M_POWER_DOMAIN_DISP] = {
 525                 .genpd = {
 526                         .name = "disp",
 527                 },
 528                 .bits  = {
 529                         .pxx = IMX8M_DISP_SW_Pxx_REQ,
 530                         .map = IMX8M_DISP_A53_DOMAIN,
 531                         .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 532                         .hskack = IMX8M_DISP_HSK_PWRDNACKN,
 533                 },
 534                 .pgc   = IMX8M_PGC_DISP,
 535         },
 536
 537         [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
 538                 .genpd = {
 539                         .name = "mipi-csi1",
 540                 },
 541                 .bits  = {
 542                         .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 543                         .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 544                 },
 545                 .pgc   = IMX8M_PGC_MIPI_CSI1,
 546         },
 547
 548         [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
 549                 .genpd = {
 550                         .name = "mipi-csi2",
 551                 },
 552                 .bits  = {
 553                         .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 554                         .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 555                 },
 556                 .pgc   = IMX8M_PGC_MIPI_CSI2,
 557         },
 558
 559         [IMX8M_POWER_DOMAIN_PCIE2] = {
 560                 .genpd = {
 561                         .name = "pcie2",
 562                 },
 563                 .bits  = {
 564                         .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 565                         .map = IMX8M_PCIE2_A53_DOMAIN,
 566                 },
 567                 .pgc   = IMX8M_PGC_PCIE2,
 568         },
 569 };
 570
 571 static const struct regmap_range imx8m_yes_ranges[] = {
 572                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 573                                  GPC_PU_PWRHSK),
 574                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
 575                                  GPC_PGC_SR(IMX8M_PGC_MIPI)),
 576                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
 577                                  GPC_PGC_SR(IMX8M_PGC_PCIE1)),
 578                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
 579                                  GPC_PGC_SR(IMX8M_PGC_OTG1)),
 580                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
 581                                  GPC_PGC_SR(IMX8M_PGC_OTG2)),
 582                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
 583                                  GPC_PGC_SR(IMX8M_PGC_DDR1)),
 584                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
 585                                  GPC_PGC_SR(IMX8M_PGC_GPU)),
 586                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
 587                                  GPC_PGC_SR(IMX8M_PGC_VPU)),
 588                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
 589                                  GPC_PGC_SR(IMX8M_PGC_DISP)),
 590                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
 591                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
 592                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
 593                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
 594                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
 595                                  GPC_PGC_SR(IMX8M_PGC_PCIE2)),
 596 };
 597
 598 static const struct regmap_access_table imx8m_access_table = {
 599         .yes_ranges     = imx8m_yes_ranges,
 600         .n_yes_ranges   = ARRAY_SIZE(imx8m_yes_ranges),
 601 };
 602
 603 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
 604         .domains = imx8m_pgc_domains,
 605         .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
 606         .reg_access_table = &imx8m_access_table,
 607 };
 608
 609 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 610         [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
 611                 .genpd = {
 612                         .name = "hsiomix",
 613                 },
 614                 .bits  = {
 615                         .pxx = 0, /* no power sequence control */
 616                         .map = 0, /* no power sequence control */
 617                         .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 618                         .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 619                 },
 620         },
 621
 622         [IMX8MM_POWER_DOMAIN_PCIE] = {
 623                 .genpd = {
 624                         .name = "pcie",
 625                 },
 626                 .bits  = {
 627                         .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 628                         .map = IMX8MM_PCIE_A53_DOMAIN,
 629                 },
 630                 .pgc   = IMX8MM_PGC_PCIE,
 631         },
 632
 633         [IMX8MM_POWER_DOMAIN_OTG1] = {
 634                 .genpd = {
 635                         .name = "usb-otg1",
 636                 },
 637                 .bits  = {
 638                         .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 639                         .map = IMX8MM_OTG1_A53_DOMAIN,
 640                 },
 641                 .pgc   = IMX8MM_PGC_OTG1,
 642         },
 643
 644         [IMX8MM_POWER_DOMAIN_OTG2] = {
 645                 .genpd = {
 646                         .name = "usb-otg2",
 647                 },
 648                 .bits  = {
 649                         .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 650                         .map = IMX8MM_OTG2_A53_DOMAIN,
 651                 },
 652                 .pgc   = IMX8MM_PGC_OTG2,
 653         },
 654
 655         [IMX8MM_POWER_DOMAIN_GPUMIX] = {
 656                 .genpd = {
 657                         .name = "gpumix",
 658                 },
 659                 .bits  = {
 660                         .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
 661                         .map = IMX8MM_GPUMIX_A53_DOMAIN,
 662                         .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 663                         .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 664                 },
 665                 .pgc   = IMX8MM_PGC_GPUMIX,
 666         },
 667
 668         [IMX8MM_POWER_DOMAIN_GPU] = {
 669                 .genpd = {
 670                         .name = "gpu",
 671                 },
 672                 .bits  = {
 673                         .pxx = IMX8MM_GPU_SW_Pxx_REQ,
 674                         .map = IMX8MM_GPU_A53_DOMAIN,
 675                         .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 676                         .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 677                 },
 678                 .pgc   = IMX8MM_PGC_GPU2D,
 679         },
 680
 681         [IMX8MM_POWER_DOMAIN_VPUMIX] = {
 682                 .genpd = {
 683                         .name = "vpumix",
 684                 },
 685                 .bits  = {
 686                         .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
 687                         .map = IMX8MM_VPUMIX_A53_DOMAIN,
 688                         .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 689                         .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 690                 },
 691                 .pgc   = IMX8MM_PGC_VPUMIX,
 692         },
 693
 694         [IMX8MM_POWER_DOMAIN_VPUG1] = {
 695                 .genpd = {
 696                         .name = "vpu-g1",
 697                 },
 698                 .bits  = {
 699                         .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 700                         .map = IMX8MM_VPUG1_A53_DOMAIN,
 701                 },
 702                 .pgc   = IMX8MM_PGC_VPUG1,
 703         },
 704
 705         [IMX8MM_POWER_DOMAIN_VPUG2] = {
 706                 .genpd = {
 707                         .name = "vpu-g2",
 708                 },
 709                 .bits  = {
 710                         .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 711                         .map = IMX8MM_VPUG2_A53_DOMAIN,
 712                 },
 713                 .pgc   = IMX8MM_PGC_VPUG2,
 714         },
 715
 716         [IMX8MM_POWER_DOMAIN_VPUH1] = {
 717                 .genpd = {
 718                         .name = "vpu-h1",
 719                 },
 720                 .bits  = {
 721                         .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 722                         .map = IMX8MM_VPUH1_A53_DOMAIN,
 723                 },
 724                 .pgc   = IMX8MM_PGC_VPUH1,
 725         },
 726
 727         [IMX8MM_POWER_DOMAIN_DISPMIX] = {
 728                 .genpd = {
 729                         .name = "dispmix",
 730                 },
 731                 .bits  = {
 732                         .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
 733                         .map = IMX8MM_DISPMIX_A53_DOMAIN,
 734                         .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 735                         .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 736                 },
 737                 .pgc   = IMX8MM_PGC_DISPMIX,
 738         },
 739
 740         [IMX8MM_POWER_DOMAIN_MIPI] = {
 741                 .genpd = {
 742                         .name = "mipi",
 743                 },
 744                 .bits  = {
 745                         .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 746                         .map = IMX8MM_MIPI_A53_DOMAIN,
 747                 },
 748                 .pgc   = IMX8MM_PGC_MIPI,
 749         },
 750 };
 751
 752 static const struct regmap_range imx8mm_yes_ranges[] = {
 753                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 754                                  GPC_PU_PWRHSK),
 755                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
 756                                  GPC_PGC_SR(IMX8MM_PGC_MIPI)),
 757                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
 758                                  GPC_PGC_SR(IMX8MM_PGC_PCIE)),
 759                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
 760                                  GPC_PGC_SR(IMX8MM_PGC_OTG1)),
 761                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
 762                                  GPC_PGC_SR(IMX8MM_PGC_OTG2)),
 763                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
 764                                  GPC_PGC_SR(IMX8MM_PGC_DDR1)),
 765                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
 766                                  GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
 767                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
 768                                  GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
 769                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
 770                                  GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
 771                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
 772                                  GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
 773                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
 774                                  GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
 775                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
 776                                  GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
 777                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
 778                                  GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
 779                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
 780                                  GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
 781 };
 782
 783 static const struct regmap_access_table imx8mm_access_table = {
 784         .yes_ranges     = imx8mm_yes_ranges,
 785         .n_yes_ranges   = ARRAY_SIZE(imx8mm_yes_ranges),
 786 };
 787
 788 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 789         .domains = imx8mm_pgc_domains,
 790         .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
 791         .reg_access_table = &imx8mm_access_table,
 792 };
 793
 794 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 795         [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
 796                 .genpd = {
 797                         .name = "hsiomix",
 798                 },
 799                 .bits  = {
 800                         .pxx = 0, /* no power sequence control */
 801                         .map = 0, /* no power sequence control */
 802                         .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 803                         .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 804                 },
 805         },
 806
 807         [IMX8MN_POWER_DOMAIN_OTG1] = {
 808                 .genpd = {
 809                         .name = "usb-otg1",
 810                 },
 811                 .bits  = {
 812                         .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 813                         .map = IMX8MN_OTG1_A53_DOMAIN,
 814                 },
 815                 .pgc   = IMX8MN_PGC_OTG1,
 816         },
 817
 818         [IMX8MN_POWER_DOMAIN_GPUMIX] = {
 819                 .genpd = {
 820                         .name = "gpumix",
 821                 },
 822                 .bits  = {
 823                         .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
 824                         .map = IMX8MN_GPUMIX_A53_DOMAIN,
 825                         .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 826                         .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 827                 },
 828                 .pgc   = IMX8MN_PGC_GPUMIX,
 829         },
 830 };
 831
 832 static const struct regmap_range imx8mn_yes_ranges[] = {
 833         regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 834                          GPC_PU_PWRHSK),
 835         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
 836                          GPC_PGC_SR(IMX8MN_PGC_MIPI)),
 837         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
 838                          GPC_PGC_SR(IMX8MN_PGC_OTG1)),
 839         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
 840                          GPC_PGC_SR(IMX8MN_PGC_DDR1)),
 841         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
 842                          GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
 843         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
 844                          GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
 845 };
 846
 847 static const struct regmap_access_table imx8mn_access_table = {
 848         .yes_ranges     = imx8mn_yes_ranges,
 849         .n_yes_ranges   = ARRAY_SIZE(imx8mn_yes_ranges),
 850 };
 851
 852 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
 853         .domains = imx8mn_pgc_domains,
 854         .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
 855         .reg_access_table = &imx8mn_access_table,
 856 };
 857
 858 static int imx_pgc_domain_probe(struct platform_device *pdev)
 859 {
 860         struct imx_pgc_domain *domain = pdev->dev.platform_data;
 861         int ret;
 862
 863         domain->dev = &pdev->dev;
 864
 865         domain->regulator = devm_regulator_get_optional(domain->dev, "power");
 866         if (IS_ERR(domain->regulator)) {
 867                 if (PTR_ERR(domain->regulator) != -ENODEV)
 868                         return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
 869                                              "Failed to get domain's regulator\n");
 870         } else if (domain->voltage) {
 871                 regulator_set_voltage(domain->regulator,
 872                                       domain->voltage, domain->voltage);
 873         }
 874
 875         domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
 876         if (domain->num_clks < 0)
 877                 return dev_err_probe(domain->dev, domain->num_clks,
 878                                      "Failed to get domain's clocks\n");
 879
 880         domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
 881         if (IS_ERR(domain->reset))
 882                 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
 883                                      "Failed to get domain's resets\n");
 884
 885         pm_runtime_enable(domain->dev);
 886
 887         if (domain->bits.map)
 888                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 889                                    domain->bits.map, domain->bits.map);
 890
 891         ret = pm_genpd_init(&domain->genpd, NULL, true);
 892         if (ret) {
 893                 dev_err(domain->dev, "Failed to init power domain\n");
 894                 goto out_domain_unmap;
 895         }
 896
 897         ret = of_genpd_add_provider_simple(domain->dev->of_node,
 898                                            &domain->genpd);
 899         if (ret) {
 900                 dev_err(domain->dev, "Failed to add genpd provider\n");
 901                 goto out_genpd_remove;
 902         }
 903
 904         return 0;
 905
 906 out_genpd_remove:
 907         pm_genpd_remove(&domain->genpd);
 908 out_domain_unmap:
 909         if (domain->bits.map)
 910                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 911                                    domain->bits.map, 0);
 912         pm_runtime_disable(domain->dev);
 913
 914         return ret;
 915 }
 916
 917 static int imx_pgc_domain_remove(struct platform_device *pdev)
 918 {
 919         struct imx_pgc_domain *domain = pdev->dev.platform_data;
 920
 921         of_genpd_del_provider(domain->dev->of_node);
 922         pm_genpd_remove(&domain->genpd);
 923
 924         if (domain->bits.map)
 925                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 926                                    domain->bits.map, 0);
 927
 928         pm_runtime_disable(domain->dev);
 929
 930         return 0;
 931 }
 932
 933 static const struct platform_device_id imx_pgc_domain_id[] = {
 934         { "imx-pgc-domain", },
 935         { },
 936 };
 937
 938 static struct platform_driver imx_pgc_domain_driver = {
 939         .driver = {
 940                 .name = "imx-pgc",
 941         },
 942         .probe    = imx_pgc_domain_probe,
 943         .remove   = imx_pgc_domain_remove,
 944         .id_table = imx_pgc_domain_id,
 945 };
 946 builtin_platform_driver(imx_pgc_domain_driver)
 947
 948 static int imx_gpcv2_probe(struct platform_device *pdev)
 949 {
 950         const struct imx_pgc_domain_data *domain_data =
 951                         of_device_get_match_data(&pdev->dev);
 952
 953         struct regmap_config regmap_config = {
 954                 .reg_bits       = 32,
 955                 .val_bits       = 32,
 956                 .reg_stride     = 4,
 957                 .rd_table       = domain_data->reg_access_table,
 958                 .wr_table       = domain_data->reg_access_table,
 959                 .max_register   = SZ_4K,
 960         };
 961         struct device *dev = &pdev->dev;
 962         struct device_node *pgc_np, *np;
 963         struct regmap *regmap;
 964         void __iomem *base;
 965         int ret;
 966
 967         pgc_np = of_get_child_by_name(dev->of_node, "pgc");
 968         if (!pgc_np) {
 969                 dev_err(dev, "No power domains specified in DT\n");
 970                 return -EINVAL;
 971         }
 972
 973         base = devm_platform_ioremap_resource(pdev, 0);
 974         if (IS_ERR(base))
 975                 return PTR_ERR(base);
 976
 977         regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
 978         if (IS_ERR(regmap)) {
 979                 ret = PTR_ERR(regmap);
 980                 dev_err(dev, "failed to init regmap (%d)\n", ret);
 981                 return ret;
 982         }
 983
 984         for_each_child_of_node(pgc_np, np) {
 985                 struct platform_device *pd_pdev;
 986                 struct imx_pgc_domain *domain;
 987                 u32 domain_index;
 988
 989                 ret = of_property_read_u32(np, "reg", &domain_index);
 990                 if (ret) {
 991                         dev_err(dev, "Failed to read 'reg' property\n");
 992                         of_node_put(np);
 993                         return ret;
 994                 }
 995
 996                 if (domain_index >= domain_data->domains_num) {
 997                         dev_warn(dev,
 998                                  "Domain index %d is out of bounds\n",
 999                                  domain_index);
1000                         continue;
1001                 }
1002
1003                 pd_pdev = platform_device_alloc("imx-pgc-domain",
1004                                                 domain_index);
1005                 if (!pd_pdev) {
1006                         dev_err(dev, "Failed to allocate platform device\n");
1007                         of_node_put(np);
1008                         return -ENOMEM;
1009                 }
1010
1011                 ret = platform_device_add_data(pd_pdev,
1012                                                &domain_data->domains[domain_index],
1013                                                sizeof(domain_data->domains[domain_index]));
1014                 if (ret) {
1015                         platform_device_put(pd_pdev);
1016                         of_node_put(np);
1017                         return ret;
1018                 }
1019
1020                 domain = pd_pdev->dev.platform_data;
1021                 domain->regmap = regmap;
1022                 domain->genpd.power_on  = imx_pgc_power_up;
1023                 domain->genpd.power_off = imx_pgc_power_down;
1024
1025                 pd_pdev->dev.parent = dev;
1026                 pd_pdev->dev.of_node = np;
1027
1028                 ret = platform_device_add(pd_pdev);
1029                 if (ret) {
1030                         platform_device_put(pd_pdev);
1031                         of_node_put(np);
1032                         return ret;
1033                 }
1034         }
1035
1036         return 0;
1037 }
1038
1039 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1040         { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1041         { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1042         { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1043         { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1044         { }
1045 };
1046
1047 static struct platform_driver imx_gpc_driver = {
1048         .driver = {
1049                 .name = "imx-gpcv2",
1050                 .of_match_table = imx_gpcv2_dt_ids,
1051         },
1052         .probe = imx_gpcv2_probe,
1053 };
1054 builtin_platform_driver(imx_gpc_driver)