drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_uvd.h"
  30 #include "vid.h"
  31 #include "uvd/uvd_5_0_d.h"
  32 #include "uvd/uvd_5_0_sh_mask.h"
  33 #include "oss/oss_2_0_d.h"
  34 #include "oss/oss_2_0_sh_mask.h"
  35 #include "bif/bif_5_0_d.h"
  36 #include "vi.h"
  37 #include "smu/smu_7_1_2_d.h"
  38 #include "smu/smu_7_1_2_sh_mask.h"
  39 #include "ivsrcid/ivsrcid_vislands30.h"
  40
  41 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  42 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  43 static int uvd_v5_0_start(struct amdgpu_device *adev);
  44 static void uvd_v5_0_stop(struct amdgpu_device *adev);
  45 static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
  46                                           enum amd_clockgating_state state);
  47 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  48                                  bool enable);
  49 /**
  50  * uvd_v5_0_ring_get_rptr - get read pointer
  51  *
  52  * @ring: amdgpu_ring pointer
  53  *
  54  * Returns the current hardware read pointer
  55  */
  56 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
  57 {
  58         struct amdgpu_device *adev = ring->adev;
  59
  60         return RREG32(mmUVD_RBC_RB_RPTR);
  61 }
  62
  63 /**
  64  * uvd_v5_0_ring_get_wptr - get write pointer
  65  *
  66  * @ring: amdgpu_ring pointer
  67  *
  68  * Returns the current hardware write pointer
  69  */
  70 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
  71 {
  72         struct amdgpu_device *adev = ring->adev;
  73
  74         return RREG32(mmUVD_RBC_RB_WPTR);
  75 }
  76
  77 /**
  78  * uvd_v5_0_ring_set_wptr - set write pointer
  79  *
  80  * @ring: amdgpu_ring pointer
  81  *
  82  * Commits the write pointer to the hardware
  83  */
  84 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
  85 {
  86         struct amdgpu_device *adev = ring->adev;
  87
  88         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  89 }
  90
  91 static int uvd_v5_0_early_init(struct amdgpu_ip_block *ip_block)
  92 {
  93         struct amdgpu_device *adev = ip_block->adev;
  94         adev->uvd.num_uvd_inst = 1;
  95
  96         uvd_v5_0_set_ring_funcs(adev);
  97         uvd_v5_0_set_irq_funcs(adev);
  98
  99         return 0;
 100 }
 101
 102 static int uvd_v5_0_sw_init(struct amdgpu_ip_block *ip_block)
 103 {
 104         struct amdgpu_ring *ring;
 105         struct amdgpu_device *adev = ip_block->adev;
 106         int r;
 107
 108         /* UVD TRAP */
 109         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 110         if (r)
 111                 return r;
 112
 113         r = amdgpu_uvd_sw_init(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->uvd.inst->ring;
 118         sprintf(ring->name, "uvd");
 119         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
 120                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 121         if (r)
 122                 return r;
 123
 124         r = amdgpu_uvd_resume(adev);
 125         if (r)
 126                 return r;
 127
 128         return r;
 129 }
 130
 131 static int uvd_v5_0_sw_fini(struct amdgpu_ip_block *ip_block)
 132 {
 133         int r;
 134         struct amdgpu_device *adev = ip_block->adev;
 135
 136         r = amdgpu_uvd_suspend(adev);
 137         if (r)
 138                 return r;
 139
 140         return amdgpu_uvd_sw_fini(adev);
 141 }
 142
 143 /**
 144  * uvd_v5_0_hw_init - start and test UVD block
 145  *
 146  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 147  *
 148  * Initialize the hardware, boot up the VCPU and do some testing
 149  */
 150 static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
 151 {
 152         struct amdgpu_device *adev = ip_block->adev;
 153         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 154         uint32_t tmp;
 155         int r;
 156
 157         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 158         uvd_v5_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
 159         uvd_v5_0_enable_mgcg(adev, true);
 160
 161         r = amdgpu_ring_test_helper(ring);
 162         if (r)
 163                 goto done;
 164
 165         r = amdgpu_ring_alloc(ring, 10);
 166         if (r) {
 167                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 168                 goto done;
 169         }
 170
 171         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 172         amdgpu_ring_write(ring, tmp);
 173         amdgpu_ring_write(ring, 0xFFFFF);
 174
 175         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 176         amdgpu_ring_write(ring, tmp);
 177         amdgpu_ring_write(ring, 0xFFFFF);
 178
 179         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 180         amdgpu_ring_write(ring, tmp);
 181         amdgpu_ring_write(ring, 0xFFFFF);
 182
 183         /* Clear timeout status bits */
 184         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 185         amdgpu_ring_write(ring, 0x8);
 186
 187         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 188         amdgpu_ring_write(ring, 3);
 189
 190         amdgpu_ring_commit(ring);
 191
 192 done:
 193         if (!r)
 194                 DRM_INFO("UVD initialized successfully.\n");
 195
 196         return r;
 197
 198 }
 199
 200 /**
 201  * uvd_v5_0_hw_fini - stop the hardware block
 202  *
 203  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 204  *
 205  * Stop the UVD block, mark ring as not ready any more
 206  */
 207 static int uvd_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)
 208 {
 209         struct amdgpu_device *adev = ip_block->adev;
 210
 211         cancel_delayed_work_sync(&adev->uvd.idle_work);
 212
 213         if (RREG32(mmUVD_STATUS) != 0)
 214                 uvd_v5_0_stop(adev);
 215
 216         return 0;
 217 }
 218
 219 static int uvd_v5_0_prepare_suspend(struct amdgpu_ip_block *ip_block)
 220 {
 221         struct amdgpu_device *adev = ip_block->adev;
 222
 223         return amdgpu_uvd_prepare_suspend(adev);
 224 }
 225
 226 static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block)
 227 {
 228         int r;
 229         struct amdgpu_device *adev = ip_block->adev;
 230
 231         /*
 232          * Proper cleanups before halting the HW engine:
 233          *   - cancel the delayed idle work
 234          *   - enable powergating
 235          *   - enable clockgating
 236          *   - disable dpm
 237          *
 238          * TODO: to align with the VCN implementation, move the
 239          * jobs for clockgating/powergating/dpm setting to
 240          * ->set_powergating_state().
 241          */
 242         cancel_delayed_work_sync(&adev->uvd.idle_work);
 243
 244         if (adev->pm.dpm_enabled) {
 245                 amdgpu_dpm_enable_uvd(adev, false);
 246         } else {
 247                 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 248                 /* shutdown the UVD block */
 249                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 250                                                        AMD_PG_STATE_GATE);
 251                 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 252                                                        AMD_CG_STATE_GATE);
 253         }
 254
 255         r = uvd_v5_0_hw_fini(ip_block);
 256         if (r)
 257                 return r;
 258
 259         return amdgpu_uvd_suspend(adev);
 260 }
 261
 262 static int uvd_v5_0_resume(struct amdgpu_ip_block *ip_block)
 263 {
 264         int r;
 265
 266         r = amdgpu_uvd_resume(ip_block->adev);
 267         if (r)
 268                 return r;
 269
 270         return uvd_v5_0_hw_init(ip_block);
 271 }
 272
 273 /**
 274  * uvd_v5_0_mc_resume - memory controller programming
 275  *
 276  * @adev: amdgpu_device pointer
 277  *
 278  * Let the UVD memory controller know it's offsets
 279  */
 280 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 281 {
 282         uint64_t offset;
 283         uint32_t size;
 284
 285         /* program memory controller bits 0-27 */
 286         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 287                         lower_32_bits(adev->uvd.inst->gpu_addr));
 288         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 289                         upper_32_bits(adev->uvd.inst->gpu_addr));
 290
 291         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 292         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 293         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 294         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 295
 296         offset += size;
 297         size = AMDGPU_UVD_HEAP_SIZE;
 298         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 299         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 300
 301         offset += size;
 302         size = AMDGPU_UVD_STACK_SIZE +
 303                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 304         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 305         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 306
 307         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 308         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 309         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 310 }
 311
 312 /**
 313  * uvd_v5_0_start - start UVD block
 314  *
 315  * @adev: amdgpu_device pointer
 316  *
 317  * Setup and start the UVD block
 318  */
 319 static int uvd_v5_0_start(struct amdgpu_device *adev)
 320 {
 321         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 322         uint32_t rb_bufsz, tmp;
 323         uint32_t lmi_swap_cntl;
 324         uint32_t mp_swap_cntl;
 325         int i, j, r;
 326
 327         /*disable DPG */
 328         WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
 329
 330         /* disable byte swapping */
 331         lmi_swap_cntl = 0;
 332         mp_swap_cntl = 0;
 333
 334         uvd_v5_0_mc_resume(adev);
 335
 336         /* disable interupt */
 337         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 338
 339         /* stall UMC and register bus before resetting VCPU */
 340         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 341         mdelay(1);
 342
 343         /* put LMI, VCPU, RBC etc... into reset */
 344         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 345                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 346                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 347                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 348                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 349         mdelay(5);
 350
 351         /* take UVD block out of reset */
 352         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 353         mdelay(5);
 354
 355         /* initialize UVD memory controller */
 356         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 357                              (1 << 21) | (1 << 9) | (1 << 20));
 358
 359 #ifdef __BIG_ENDIAN
 360         /* swap (8 in 32) RB and IB */
 361         lmi_swap_cntl = 0xa;
 362         mp_swap_cntl = 0;
 363 #endif
 364         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 365         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 366
 367         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 368         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 369         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 370         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 371         WREG32(mmUVD_MPC_SET_ALU, 0);
 372         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 373
 374         /* take all subblocks out of reset, except VCPU */
 375         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 376         mdelay(5);
 377
 378         /* enable VCPU clock */
 379         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 380
 381         /* enable UMC */
 382         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 383
 384         /* boot up the VCPU */
 385         WREG32(mmUVD_SOFT_RESET, 0);
 386         mdelay(10);
 387
 388         for (i = 0; i < 10; ++i) {
 389                 uint32_t status;
 390                 for (j = 0; j < 100; ++j) {
 391                         status = RREG32(mmUVD_STATUS);
 392                         if (status & 2)
 393                                 break;
 394                         mdelay(10);
 395                 }
 396                 r = 0;
 397                 if (status & 2)
 398                         break;
 399
 400                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 401                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 402                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 403                 mdelay(10);
 404                 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 405                 mdelay(10);
 406                 r = -1;
 407         }
 408
 409         if (r) {
 410                 DRM_ERROR("UVD not responding, giving up!!!\n");
 411                 return r;
 412         }
 413         /* enable master interrupt */
 414         WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
 415
 416         /* clear the bit 4 of UVD_STATUS */
 417         WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
 418
 419         rb_bufsz = order_base_2(ring->ring_size);
 420         tmp = 0;
 421         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 422         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 423         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 424         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 425         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 426         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 427         /* force RBC into idle state */
 428         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 429
 430         /* set the write pointer delay */
 431         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 432
 433         /* set the wb address */
 434         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 435
 436         /* program the RB_BASE for ring buffer */
 437         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 438                         lower_32_bits(ring->gpu_addr));
 439         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 440                         upper_32_bits(ring->gpu_addr));
 441
 442         /* Initialize the ring buffer's read and write pointers */
 443         WREG32(mmUVD_RBC_RB_RPTR, 0);
 444
 445         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 446         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 447
 448         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 449
 450         return 0;
 451 }
 452
 453 /**
 454  * uvd_v5_0_stop - stop UVD block
 455  *
 456  * @adev: amdgpu_device pointer
 457  *
 458  * stop the UVD block
 459  */
 460 static void uvd_v5_0_stop(struct amdgpu_device *adev)
 461 {
 462         /* force RBC into idle state */
 463         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 464
 465         /* Stall UMC and register bus before resetting VCPU */
 466         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 467         mdelay(1);
 468
 469         /* put VCPU into reset */
 470         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 471         mdelay(5);
 472
 473         /* disable VCPU clock */
 474         WREG32(mmUVD_VCPU_CNTL, 0x0);
 475
 476         /* Unstall UMC and register bus */
 477         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 478
 479         WREG32(mmUVD_STATUS, 0);
 480 }
 481
 482 /**
 483  * uvd_v5_0_ring_emit_fence - emit an fence & trap command
 484  *
 485  * @ring: amdgpu_ring pointer
 486  * @addr: address
 487  * @seq: sequence number
 488  * @flags: fence related flags
 489  *
 490  * Write a fence and a trap command to the ring.
 491  */
 492 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 493                                      unsigned flags)
 494 {
 495         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 496
 497         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 498         amdgpu_ring_write(ring, seq);
 499         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 500         amdgpu_ring_write(ring, addr & 0xffffffff);
 501         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 502         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 503         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 504         amdgpu_ring_write(ring, 0);
 505
 506         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 507         amdgpu_ring_write(ring, 0);
 508         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 509         amdgpu_ring_write(ring, 0);
 510         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 511         amdgpu_ring_write(ring, 2);
 512 }
 513
 514 /**
 515  * uvd_v5_0_ring_test_ring - register write test
 516  *
 517  * @ring: amdgpu_ring pointer
 518  *
 519  * Test if we can successfully write to the context register
 520  */
 521 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 522 {
 523         struct amdgpu_device *adev = ring->adev;
 524         uint32_t tmp = 0;
 525         unsigned i;
 526         int r;
 527
 528         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 529         r = amdgpu_ring_alloc(ring, 3);
 530         if (r)
 531                 return r;
 532         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 533         amdgpu_ring_write(ring, 0xDEADBEEF);
 534         amdgpu_ring_commit(ring);
 535         for (i = 0; i < adev->usec_timeout; i++) {
 536                 tmp = RREG32(mmUVD_CONTEXT_ID);
 537                 if (tmp == 0xDEADBEEF)
 538                         break;
 539                 udelay(1);
 540         }
 541
 542         if (i >= adev->usec_timeout)
 543                 r = -ETIMEDOUT;
 544
 545         return r;
 546 }
 547
 548 /**
 549  * uvd_v5_0_ring_emit_ib - execute indirect buffer
 550  *
 551  * @ring: amdgpu_ring pointer
 552  * @job: job to retrieve vmid from
 553  * @ib: indirect buffer to execute
 554  * @flags: unused
 555  *
 556  * Write ring commands to execute the indirect buffer
 557  */
 558 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 559                                   struct amdgpu_job *job,
 560                                   struct amdgpu_ib *ib,
 561                                   uint32_t flags)
 562 {
 563         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 564         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 565         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 566         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 567         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 568         amdgpu_ring_write(ring, ib->length_dw);
 569 }
 570
 571 static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 572 {
 573         int i;
 574
 575         WARN_ON(ring->wptr % 2 || count % 2);
 576
 577         for (i = 0; i < count / 2; i++) {
 578                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
 579                 amdgpu_ring_write(ring, 0);
 580         }
 581 }
 582
 583 static bool uvd_v5_0_is_idle(void *handle)
 584 {
 585         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 586
 587         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 588 }
 589
 590 static int uvd_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 591 {
 592         unsigned i;
 593         struct amdgpu_device *adev = ip_block->adev;
 594
 595         for (i = 0; i < adev->usec_timeout; i++) {
 596                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 597                         return 0;
 598         }
 599         return -ETIMEDOUT;
 600 }
 601
 602 static int uvd_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
 603 {
 604         struct amdgpu_device *adev = ip_block->adev;
 605
 606         uvd_v5_0_stop(adev);
 607
 608         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 609                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 610         mdelay(5);
 611
 612         return uvd_v5_0_start(adev);
 613 }
 614
 615 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
 616                                         struct amdgpu_irq_src *source,
 617                                         unsigned type,
 618                                         enum amdgpu_interrupt_state state)
 619 {
 620         // TODO
 621         return 0;
 622 }
 623
 624 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
 625                                       struct amdgpu_irq_src *source,
 626                                       struct amdgpu_iv_entry *entry)
 627 {
 628         DRM_DEBUG("IH: UVD TRAP\n");
 629         amdgpu_fence_process(&adev->uvd.inst->ring);
 630         return 0;
 631 }
 632
 633 static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
 634 {
 635         uint32_t data1, data3, suvd_flags;
 636
 637         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 638         data3 = RREG32(mmUVD_CGC_GATE);
 639
 640         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 641                      UVD_SUVD_CGC_GATE__SIT_MASK |
 642                      UVD_SUVD_CGC_GATE__SMP_MASK |
 643                      UVD_SUVD_CGC_GATE__SCM_MASK |
 644                      UVD_SUVD_CGC_GATE__SDB_MASK;
 645
 646         if (enable) {
 647                 data3 |= (UVD_CGC_GATE__SYS_MASK     |
 648                         UVD_CGC_GATE__UDEC_MASK      |
 649                         UVD_CGC_GATE__MPEG2_MASK     |
 650                         UVD_CGC_GATE__RBC_MASK       |
 651                         UVD_CGC_GATE__LMI_MC_MASK    |
 652                         UVD_CGC_GATE__IDCT_MASK      |
 653                         UVD_CGC_GATE__MPRD_MASK      |
 654                         UVD_CGC_GATE__MPC_MASK       |
 655                         UVD_CGC_GATE__LBSI_MASK      |
 656                         UVD_CGC_GATE__LRBBM_MASK     |
 657                         UVD_CGC_GATE__UDEC_RE_MASK   |
 658                         UVD_CGC_GATE__UDEC_CM_MASK   |
 659                         UVD_CGC_GATE__UDEC_IT_MASK   |
 660                         UVD_CGC_GATE__UDEC_DB_MASK   |
 661                         UVD_CGC_GATE__UDEC_MP_MASK   |
 662                         UVD_CGC_GATE__WCB_MASK       |
 663                         UVD_CGC_GATE__JPEG_MASK      |
 664                         UVD_CGC_GATE__SCPU_MASK);
 665                 /* only in pg enabled, we can gate clock to vcpu*/
 666                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 667                         data3 |= UVD_CGC_GATE__VCPU_MASK;
 668                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
 669                 data1 |= suvd_flags;
 670         } else {
 671                 data3 = 0;
 672                 data1 = 0;
 673         }
 674
 675         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 676         WREG32(mmUVD_CGC_GATE, data3);
 677 }
 678
 679 static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
 680 {
 681         uint32_t data, data2;
 682
 683         data = RREG32(mmUVD_CGC_CTRL);
 684         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 685
 686
 687         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 688                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 689
 690
 691         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 692                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 693                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 694
 695         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 696                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 697                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 698                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 699                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 700                         UVD_CGC_CTRL__SYS_MODE_MASK |
 701                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 702                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 703                         UVD_CGC_CTRL__REGS_MODE_MASK |
 704                         UVD_CGC_CTRL__RBC_MODE_MASK |
 705                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 706                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 707                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 708                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 709                         UVD_CGC_CTRL__MPC_MODE_MASK |
 710                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 711                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 712                         UVD_CGC_CTRL__WCB_MODE_MASK |
 713                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 714                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 715                         UVD_CGC_CTRL__SCPU_MODE_MASK);
 716         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 717                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 718                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 719                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 720                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 721
 722         WREG32(mmUVD_CGC_CTRL, data);
 723         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 724 }
 725
 726 #if 0
 727 static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
 728 {
 729         uint32_t data, data1, cgc_flags, suvd_flags;
 730
 731         data = RREG32(mmUVD_CGC_GATE);
 732         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 733
 734         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 735                                 UVD_CGC_GATE__UDEC_MASK |
 736                                 UVD_CGC_GATE__MPEG2_MASK |
 737                                 UVD_CGC_GATE__RBC_MASK |
 738                                 UVD_CGC_GATE__LMI_MC_MASK |
 739                                 UVD_CGC_GATE__IDCT_MASK |
 740                                 UVD_CGC_GATE__MPRD_MASK |
 741                                 UVD_CGC_GATE__MPC_MASK |
 742                                 UVD_CGC_GATE__LBSI_MASK |
 743                                 UVD_CGC_GATE__LRBBM_MASK |
 744                                 UVD_CGC_GATE__UDEC_RE_MASK |
 745                                 UVD_CGC_GATE__UDEC_CM_MASK |
 746                                 UVD_CGC_GATE__UDEC_IT_MASK |
 747                                 UVD_CGC_GATE__UDEC_DB_MASK |
 748                                 UVD_CGC_GATE__UDEC_MP_MASK |
 749                                 UVD_CGC_GATE__WCB_MASK |
 750                                 UVD_CGC_GATE__VCPU_MASK |
 751                                 UVD_CGC_GATE__SCPU_MASK;
 752
 753         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 754                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 755                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 756                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 757                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 758
 759         data |= cgc_flags;
 760         data1 |= suvd_flags;
 761
 762         WREG32(mmUVD_CGC_GATE, data);
 763         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 764 }
 765 #endif
 766
 767 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
 768                                  bool enable)
 769 {
 770         u32 orig, data;
 771
 772         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 773                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 774                 data |= 0xfff;
 775                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 776
 777                 orig = data = RREG32(mmUVD_CGC_CTRL);
 778                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 779                 if (orig != data)
 780                         WREG32(mmUVD_CGC_CTRL, data);
 781         } else {
 782                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 783                 data &= ~0xfff;
 784                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 785
 786                 orig = data = RREG32(mmUVD_CGC_CTRL);
 787                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 788                 if (orig != data)
 789                         WREG32(mmUVD_CGC_CTRL, data);
 790         }
 791 }
 792
 793 static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 794                                           enum amd_clockgating_state state)
 795 {
 796         struct amdgpu_device *adev = ip_block->adev;
 797         bool enable = (state == AMD_CG_STATE_GATE);
 798
 799         if (enable) {
 800                 /* wait for STATUS to clear */
 801                 if (uvd_v5_0_wait_for_idle(ip_block))
 802                         return -EBUSY;
 803                 uvd_v5_0_enable_clock_gating(adev, true);
 804
 805                 /* enable HW gates because UVD is idle */
 806 /*              uvd_v5_0_set_hw_clock_gating(adev); */
 807         } else {
 808                 uvd_v5_0_enable_clock_gating(adev, false);
 809         }
 810
 811         uvd_v5_0_set_sw_clock_gating(adev);
 812         return 0;
 813 }
 814
 815 static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
 816                                           enum amd_powergating_state state)
 817 {
 818         /* This doesn't actually powergate the UVD block.
 819          * That's done in the dpm code via the SMC.  This
 820          * just re-inits the block as necessary.  The actual
 821          * gating still happens in the dpm code.  We should
 822          * revisit this when there is a cleaner line between
 823          * the smc and the hw blocks
 824          */
 825         struct amdgpu_device *adev = ip_block->adev;
 826         int ret = 0;
 827
 828         if (state == AMD_PG_STATE_GATE) {
 829                 uvd_v5_0_stop(adev);
 830         } else {
 831                 ret = uvd_v5_0_start(adev);
 832                 if (ret)
 833                         goto out;
 834         }
 835
 836 out:
 837         return ret;
 838 }
 839
 840 static void uvd_v5_0_get_clockgating_state(void *handle, u64 *flags)
 841 {
 842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 843         int data;
 844
 845         mutex_lock(&adev->pm.mutex);
 846
 847         if (RREG32_SMC(ixCURRENT_PG_STATUS) &
 848                                 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
 849                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
 850                 goto out;
 851         }
 852
 853         /* AMD_CG_SUPPORT_UVD_MGCG */
 854         data = RREG32(mmUVD_CGC_CTRL);
 855         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
 856                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
 857
 858 out:
 859         mutex_unlock(&adev->pm.mutex);
 860 }
 861
 862 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 863         .name = "uvd_v5_0",
 864         .early_init = uvd_v5_0_early_init,
 865         .sw_init = uvd_v5_0_sw_init,
 866         .sw_fini = uvd_v5_0_sw_fini,
 867         .hw_init = uvd_v5_0_hw_init,
 868         .hw_fini = uvd_v5_0_hw_fini,
 869         .prepare_suspend = uvd_v5_0_prepare_suspend,
 870         .suspend = uvd_v5_0_suspend,
 871         .resume = uvd_v5_0_resume,
 872         .is_idle = uvd_v5_0_is_idle,
 873         .wait_for_idle = uvd_v5_0_wait_for_idle,
 874         .soft_reset = uvd_v5_0_soft_reset,
 875         .set_clockgating_state = uvd_v5_0_set_clockgating_state,
 876         .set_powergating_state = uvd_v5_0_set_powergating_state,
 877         .get_clockgating_state = uvd_v5_0_get_clockgating_state,
 878 };
 879
 880 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
 881         .type = AMDGPU_RING_TYPE_UVD,
 882         .align_mask = 0xf,
 883         .support_64bit_ptrs = false,
 884         .no_user_fence = true,
 885         .get_rptr = uvd_v5_0_ring_get_rptr,
 886         .get_wptr = uvd_v5_0_ring_get_wptr,
 887         .set_wptr = uvd_v5_0_ring_set_wptr,
 888         .parse_cs = amdgpu_uvd_ring_parse_cs,
 889         .emit_frame_size =
 890                 14, /* uvd_v5_0_ring_emit_fence  x1 no user fence */
 891         .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
 892         .emit_ib = uvd_v5_0_ring_emit_ib,
 893         .emit_fence = uvd_v5_0_ring_emit_fence,
 894         .test_ring = uvd_v5_0_ring_test_ring,
 895         .test_ib = amdgpu_uvd_ring_test_ib,
 896         .insert_nop = uvd_v5_0_ring_insert_nop,
 897         .pad_ib = amdgpu_ring_generic_pad_ib,
 898         .begin_use = amdgpu_uvd_ring_begin_use,
 899         .end_use = amdgpu_uvd_ring_end_use,
 900 };
 901
 902 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
 903 {
 904         adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
 905 }
 906
 907 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
 908         .set = uvd_v5_0_set_interrupt_state,
 909         .process = uvd_v5_0_process_interrupt,
 910 };
 911
 912 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 913 {
 914         adev->uvd.inst->irq.num_types = 1;
 915         adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
 916 }
 917
 918 const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
 919 {
 920                 .type = AMD_IP_BLOCK_TYPE_UVD,
 921                 .major = 5,
 922                 .minor = 0,
 923                 .rev = 0,
 924                 .funcs = &uvd_v5_0_ip_funcs,
 925 };