drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include <linux/hmm.h>
  47 #include "amdgpu.h"
  48 #include "amdgpu_object.h"
  49 #include "amdgpu_trace.h"
  50 #include "amdgpu_amdkfd.h"
  51 #include "amdgpu_sdma.h"
  52 #include "bif/bif_4_1_d.h"
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  64 {
  65         return 0;
  66 }
  67
  68 /**
  69  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  70  * memory request.
  71  *
  72  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  73  * @type: The type of memory requested
  74  * @man: The memory type manager for each domain
  75  *
  76  * This is called by ttm_bo_init_mm() when a buffer object is being
  77  * initialized.
  78  */
  79 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  80                                 struct ttm_mem_type_manager *man)
  81 {
  82         struct amdgpu_device *adev;
  83
  84         adev = amdgpu_ttm_adev(bdev);
  85
  86         switch (type) {
  87         case TTM_PL_SYSTEM:
  88                 /* System memory */
  89                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  90                 man->available_caching = TTM_PL_MASK_CACHING;
  91                 man->default_caching = TTM_PL_FLAG_CACHED;
  92                 break;
  93         case TTM_PL_TT:
  94                 /* GTT memory  */
  95                 man->func = &amdgpu_gtt_mgr_func;
  96                 man->gpu_offset = adev->gmc.gart_start;
  97                 man->available_caching = TTM_PL_MASK_CACHING;
  98                 man->default_caching = TTM_PL_FLAG_CACHED;
  99                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 100                 break;
 101         case TTM_PL_VRAM:
 102                 /* "On-card" video ram */
 103                 man->func = &amdgpu_vram_mgr_func;
 104                 man->gpu_offset = adev->gmc.vram_start;
 105                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 106                              TTM_MEMTYPE_FLAG_MAPPABLE;
 107                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 108                 man->default_caching = TTM_PL_FLAG_WC;
 109                 break;
 110         case AMDGPU_PL_GDS:
 111         case AMDGPU_PL_GWS:
 112         case AMDGPU_PL_OA:
 113                 /* On-chip GDS memory*/
 114                 man->func = &ttm_bo_manager_func;
 115                 man->gpu_offset = 0;
 116                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 117                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 118                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 119                 break;
 120         default:
 121                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 122                 return -EINVAL;
 123         }
 124         return 0;
 125 }
 126
 127 /**
 128  * amdgpu_evict_flags - Compute placement flags
 129  *
 130  * @bo: The buffer object to evict
 131  * @placement: Possible destination(s) for evicted BO
 132  *
 133  * Fill in placement data when ttm_bo_evict() is called
 134  */
 135 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 136                                 struct ttm_placement *placement)
 137 {
 138         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 139         struct amdgpu_bo *abo;
 140         static const struct ttm_place placements = {
 141                 .fpfn = 0,
 142                 .lpfn = 0,
 143                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 144         };
 145
 146         /* Don't handle scatter gather BOs */
 147         if (bo->type == ttm_bo_type_sg) {
 148                 placement->num_placement = 0;
 149                 placement->num_busy_placement = 0;
 150                 return;
 151         }
 152
 153         /* Object isn't an AMDGPU object so ignore */
 154         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 155                 placement->placement = &placements;
 156                 placement->busy_placement = &placements;
 157                 placement->num_placement = 1;
 158                 placement->num_busy_placement = 1;
 159                 return;
 160         }
 161
 162         abo = ttm_to_amdgpu_bo(bo);
 163         switch (bo->mem.mem_type) {
 164         case AMDGPU_PL_GDS:
 165         case AMDGPU_PL_GWS:
 166         case AMDGPU_PL_OA:
 167                 placement->num_placement = 0;
 168                 placement->num_busy_placement = 0;
 169                 return;
 170
 171         case TTM_PL_VRAM:
 172                 if (!adev->mman.buffer_funcs_enabled) {
 173                         /* Move to system memory */
 174                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 175                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 176                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 177                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 178
 179                         /* Try evicting to the CPU inaccessible part of VRAM
 180                          * first, but only set GTT as busy placement, so this
 181                          * BO will be evicted to GTT rather than causing other
 182                          * BOs to be evicted from VRAM
 183                          */
 184                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 185                                                          AMDGPU_GEM_DOMAIN_GTT);
 186                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 187                         abo->placements[0].lpfn = 0;
 188                         abo->placement.busy_placement = &abo->placements[1];
 189                         abo->placement.num_busy_placement = 1;
 190                 } else {
 191                         /* Move to GTT memory */
 192                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 193                 }
 194                 break;
 195         case TTM_PL_TT:
 196         default:
 197                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 198                 break;
 199         }
 200         *placement = abo->placement;
 201 }
 202
 203 /**
 204  * amdgpu_verify_access - Verify access for a mmap call
 205  *
 206  * @bo: The buffer object to map
 207  * @filp: The file pointer from the process performing the mmap
 208  *
 209  * This is called by ttm_bo_mmap() to verify whether a process
 210  * has the right to mmap a BO to their process space.
 211  */
 212 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 213 {
 214         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 215
 216         /*
 217          * Don't verify access for KFD BOs. They don't have a GEM
 218          * object associated with them.
 219          */
 220         if (abo->kfd_bo)
 221                 return 0;
 222
 223         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 224                 return -EPERM;
 225         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 226                                           filp->private_data);
 227 }
 228
 229 /**
 230  * amdgpu_move_null - Register memory for a buffer object
 231  *
 232  * @bo: The bo to assign the memory to
 233  * @new_mem: The memory to be assigned.
 234  *
 235  * Assign the memory from new_mem to the memory of the buffer object bo.
 236  */
 237 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 238                              struct ttm_mem_reg *new_mem)
 239 {
 240         struct ttm_mem_reg *old_mem = &bo->mem;
 241
 242         BUG_ON(old_mem->mm_node != NULL);
 243         *old_mem = *new_mem;
 244         new_mem->mm_node = NULL;
 245 }
 246
 247 /**
 248  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 249  *
 250  * @bo: The bo to assign the memory to.
 251  * @mm_node: Memory manager node for drm allocator.
 252  * @mem: The region where the bo resides.
 253  *
 254  */
 255 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 256                                     struct drm_mm_node *mm_node,
 257                                     struct ttm_mem_reg *mem)
 258 {
 259         uint64_t addr = 0;
 260
 261         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 262                 addr = mm_node->start << PAGE_SHIFT;
 263                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 264         }
 265         return addr;
 266 }
 267
 268 /**
 269  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 270  * @offset. It also modifies the offset to be within the drm_mm_node returned
 271  *
 272  * @mem: The region where the bo resides.
 273  * @offset: The offset that drm_mm_node is used for finding.
 274  *
 275  */
 276 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 277                                                unsigned long *offset)
 278 {
 279         struct drm_mm_node *mm_node = mem->mm_node;
 280
 281         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 282                 *offset -= (mm_node->size << PAGE_SHIFT);
 283                 ++mm_node;
 284         }
 285         return mm_node;
 286 }
 287
 288 /**
 289  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  * @f: Returns the last fence if multiple jobs are submitted.
 296  */
 297 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 298                                struct amdgpu_copy_mem *src,
 299                                struct amdgpu_copy_mem *dst,
 300                                uint64_t size,
 301                                struct reservation_object *resv,
 302                                struct dma_fence **f)
 303 {
 304         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 305         struct drm_mm_node *src_mm, *dst_mm;
 306         uint64_t src_node_start, dst_node_start, src_node_size,
 307                  dst_node_size, src_page_offset, dst_page_offset;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 311                                         AMDGPU_GPU_PAGE_SIZE);
 312
 313         if (!adev->mman.buffer_funcs_enabled) {
 314                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 315                 return -EINVAL;
 316         }
 317
 318         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 319         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 320                                              src->offset;
 321         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 322         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 323
 324         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 325         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 326                                              dst->offset;
 327         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 328         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 329
 330         mutex_lock(&adev->mman.gtt_window_lock);
 331
 332         while (size) {
 333                 unsigned long cur_size;
 334                 uint64_t from = src_node_start, to = dst_node_start;
 335                 struct dma_fence *next;
 336
 337                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 338                  * begins at an offset, then adjust the size accordingly
 339                  */
 340                 cur_size = min3(min(src_node_size, dst_node_size), size,
 341                                 GTT_MAX_BYTES);
 342                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 343                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 344                         cur_size -= max(src_page_offset, dst_page_offset);
 345
 346                 /* Map only what needs to be accessed. Map src to window 0 and
 347                  * dst to window 1
 348                  */
 349                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 350                         r = amdgpu_map_buffer(src->bo, src->mem,
 351                                         PFN_UP(cur_size + src_page_offset),
 352                                         src_node_start, 0, ring,
 353                                         &from);
 354                         if (r)
 355                                 goto error;
 356                         /* Adjust the offset because amdgpu_map_buffer returns
 357                          * start of mapped page
 358                          */
 359                         from += src_page_offset;
 360                 }
 361
 362                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 363                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 364                                         PFN_UP(cur_size + dst_page_offset),
 365                                         dst_node_start, 1, ring,
 366                                         &to);
 367                         if (r)
 368                                 goto error;
 369                         to += dst_page_offset;
 370                 }
 371
 372                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 373                                        resv, &next, false, true);
 374                 if (r)
 375                         goto error;
 376
 377                 dma_fence_put(fence);
 378                 fence = next;
 379
 380                 size -= cur_size;
 381                 if (!size)
 382                         break;
 383
 384                 src_node_size -= cur_size;
 385                 if (!src_node_size) {
 386                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 387                                                              src->mem);
 388                         src_node_size = (src_mm->size << PAGE_SHIFT);
 389                 } else {
 390                         src_node_start += cur_size;
 391                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 392                 }
 393                 dst_node_size -= cur_size;
 394                 if (!dst_node_size) {
 395                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 396                                                              dst->mem);
 397                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 398                 } else {
 399                         dst_node_start += cur_size;
 400                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 401                 }
 402         }
 403 error:
 404         mutex_unlock(&adev->mman.gtt_window_lock);
 405         if (f)
 406                 *f = dma_fence_get(fence);
 407         dma_fence_put(fence);
 408         return r;
 409 }
 410
 411 /**
 412  * amdgpu_move_blit - Copy an entire buffer to another buffer
 413  *
 414  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 415  * help move buffers to and from VRAM.
 416  */
 417 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 418                             bool evict, bool no_wait_gpu,
 419                             struct ttm_mem_reg *new_mem,
 420                             struct ttm_mem_reg *old_mem)
 421 {
 422         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 423         struct amdgpu_copy_mem src, dst;
 424         struct dma_fence *fence = NULL;
 425         int r;
 426
 427         src.bo = bo;
 428         dst.bo = bo;
 429         src.mem = old_mem;
 430         dst.mem = new_mem;
 431         src.offset = 0;
 432         dst.offset = 0;
 433
 434         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 435                                        new_mem->num_pages << PAGE_SHIFT,
 436                                        bo->resv, &fence);
 437         if (r)
 438                 goto error;
 439
 440         /* Always block for VM page tables before committing the new location */
 441         if (bo->type == ttm_bo_type_kernel)
 442                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 443         else
 444                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 445         dma_fence_put(fence);
 446         return r;
 447
 448 error:
 449         if (fence)
 450                 dma_fence_wait(fence, false);
 451         dma_fence_put(fence);
 452         return r;
 453 }
 454
 455 /**
 456  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 457  *
 458  * Called by amdgpu_bo_move().
 459  */
 460 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 461                                 struct ttm_operation_ctx *ctx,
 462                                 struct ttm_mem_reg *new_mem)
 463 {
 464         struct amdgpu_device *adev;
 465         struct ttm_mem_reg *old_mem = &bo->mem;
 466         struct ttm_mem_reg tmp_mem;
 467         struct ttm_place placements;
 468         struct ttm_placement placement;
 469         int r;
 470
 471         adev = amdgpu_ttm_adev(bo->bdev);
 472
 473         /* create space/pages for new_mem in GTT space */
 474         tmp_mem = *new_mem;
 475         tmp_mem.mm_node = NULL;
 476         placement.num_placement = 1;
 477         placement.placement = &placements;
 478         placement.num_busy_placement = 1;
 479         placement.busy_placement = &placements;
 480         placements.fpfn = 0;
 481         placements.lpfn = 0;
 482         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 483         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 484         if (unlikely(r)) {
 485                 return r;
 486         }
 487
 488         /* set caching flags */
 489         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 490         if (unlikely(r)) {
 491                 goto out_cleanup;
 492         }
 493
 494         /* Bind the memory to the GTT space */
 495         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 496         if (unlikely(r)) {
 497                 goto out_cleanup;
 498         }
 499
 500         /* blit VRAM to GTT */
 501         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 502         if (unlikely(r)) {
 503                 goto out_cleanup;
 504         }
 505
 506         /* move BO (in tmp_mem) to new_mem */
 507         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 508 out_cleanup:
 509         ttm_bo_mem_put(bo, &tmp_mem);
 510         return r;
 511 }
 512
 513 /**
 514  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 515  *
 516  * Called by amdgpu_bo_move().
 517  */
 518 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 519                                 struct ttm_operation_ctx *ctx,
 520                                 struct ttm_mem_reg *new_mem)
 521 {
 522         struct amdgpu_device *adev;
 523         struct ttm_mem_reg *old_mem = &bo->mem;
 524         struct ttm_mem_reg tmp_mem;
 525         struct ttm_placement placement;
 526         struct ttm_place placements;
 527         int r;
 528
 529         adev = amdgpu_ttm_adev(bo->bdev);
 530
 531         /* make space in GTT for old_mem buffer */
 532         tmp_mem = *new_mem;
 533         tmp_mem.mm_node = NULL;
 534         placement.num_placement = 1;
 535         placement.placement = &placements;
 536         placement.num_busy_placement = 1;
 537         placement.busy_placement = &placements;
 538         placements.fpfn = 0;
 539         placements.lpfn = 0;
 540         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 541         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 542         if (unlikely(r)) {
 543                 return r;
 544         }
 545
 546         /* move/bind old memory to GTT space */
 547         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 548         if (unlikely(r)) {
 549                 goto out_cleanup;
 550         }
 551
 552         /* copy to VRAM */
 553         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 554         if (unlikely(r)) {
 555                 goto out_cleanup;
 556         }
 557 out_cleanup:
 558         ttm_bo_mem_put(bo, &tmp_mem);
 559         return r;
 560 }
 561
 562 /**
 563  * amdgpu_bo_move - Move a buffer object to a new memory location
 564  *
 565  * Called by ttm_bo_handle_move_mem()
 566  */
 567 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 568                           struct ttm_operation_ctx *ctx,
 569                           struct ttm_mem_reg *new_mem)
 570 {
 571         struct amdgpu_device *adev;
 572         struct amdgpu_bo *abo;
 573         struct ttm_mem_reg *old_mem = &bo->mem;
 574         int r;
 575
 576         /* Can't move a pinned BO */
 577         abo = ttm_to_amdgpu_bo(bo);
 578         if (WARN_ON_ONCE(abo->pin_count > 0))
 579                 return -EINVAL;
 580
 581         adev = amdgpu_ttm_adev(bo->bdev);
 582
 583         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 584                 amdgpu_move_null(bo, new_mem);
 585                 return 0;
 586         }
 587         if ((old_mem->mem_type == TTM_PL_TT &&
 588              new_mem->mem_type == TTM_PL_SYSTEM) ||
 589             (old_mem->mem_type == TTM_PL_SYSTEM &&
 590              new_mem->mem_type == TTM_PL_TT)) {
 591                 /* bind is enough */
 592                 amdgpu_move_null(bo, new_mem);
 593                 return 0;
 594         }
 595         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 596             old_mem->mem_type == AMDGPU_PL_GWS ||
 597             old_mem->mem_type == AMDGPU_PL_OA ||
 598             new_mem->mem_type == AMDGPU_PL_GDS ||
 599             new_mem->mem_type == AMDGPU_PL_GWS ||
 600             new_mem->mem_type == AMDGPU_PL_OA) {
 601                 /* Nothing to save here */
 602                 amdgpu_move_null(bo, new_mem);
 603                 return 0;
 604         }
 605
 606         if (!adev->mman.buffer_funcs_enabled)
 607                 goto memcpy;
 608
 609         if (old_mem->mem_type == TTM_PL_VRAM &&
 610             new_mem->mem_type == TTM_PL_SYSTEM) {
 611                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 612         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 613                    new_mem->mem_type == TTM_PL_VRAM) {
 614                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 615         } else {
 616                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 617                                      new_mem, old_mem);
 618         }
 619
 620         if (r) {
 621 memcpy:
 622                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 623                 if (r) {
 624                         return r;
 625                 }
 626         }
 627
 628         if (bo->type == ttm_bo_type_device &&
 629             new_mem->mem_type == TTM_PL_VRAM &&
 630             old_mem->mem_type != TTM_PL_VRAM) {
 631                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 632                  * accesses the BO after it's moved.
 633                  */
 634                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 635         }
 636
 637         /* update statistics */
 638         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 639         return 0;
 640 }
 641
 642 /**
 643  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 644  *
 645  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 646  */
 647 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 648 {
 649         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 650         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 651         struct drm_mm_node *mm_node = mem->mm_node;
 652
 653         mem->bus.addr = NULL;
 654         mem->bus.offset = 0;
 655         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 656         mem->bus.base = 0;
 657         mem->bus.is_iomem = false;
 658         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 659                 return -EINVAL;
 660         switch (mem->mem_type) {
 661         case TTM_PL_SYSTEM:
 662                 /* system memory */
 663                 return 0;
 664         case TTM_PL_TT:
 665                 break;
 666         case TTM_PL_VRAM:
 667                 mem->bus.offset = mem->start << PAGE_SHIFT;
 668                 /* check if it's visible */
 669                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 670                         return -EINVAL;
 671                 /* Only physically contiguous buffers apply. In a contiguous
 672                  * buffer, size of the first mm_node would match the number of
 673                  * pages in ttm_mem_reg.
 674                  */
 675                 if (adev->mman.aper_base_kaddr &&
 676                     (mm_node->size == mem->num_pages))
 677                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 678                                         mem->bus.offset;
 679
 680                 mem->bus.base = adev->gmc.aper_base;
 681                 mem->bus.is_iomem = true;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686         return 0;
 687 }
 688
 689 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 690 {
 691 }
 692
 693 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 694                                            unsigned long page_offset)
 695 {
 696         struct drm_mm_node *mm;
 697         unsigned long offset = (page_offset << PAGE_SHIFT);
 698
 699         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 700         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 701                 (offset >> PAGE_SHIFT);
 702 }
 703
 704 /*
 705  * TTM backend functions.
 706  */
 707 struct amdgpu_ttm_tt {
 708         struct ttm_dma_tt       ttm;
 709         u64                     offset;
 710         uint64_t                userptr;
 711         struct task_struct      *usertask;
 712         uint32_t                userflags;
 713 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 714         struct hmm_range        range;
 715 #endif
 716 };
 717
 718 /**
 719  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 720  * memory and start HMM tracking CPU page table update
 721  *
 722  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 723  * once afterwards to stop HMM tracking
 724  */
 725 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 726 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 727 {
 728         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 729         struct mm_struct *mm = gtt->usertask->mm;
 730         unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 731         struct hmm_range *range = &gtt->range;
 732         int r = 0, i;
 733
 734         if (!mm) /* Happens during process shutdown */
 735                 return -ESRCH;
 736
 737         amdgpu_hmm_init_range(range);
 738
 739         down_read(&mm->mmap_sem);
 740
 741         range->vma = find_vma(mm, gtt->userptr);
 742         if (!range_in_vma(range->vma, gtt->userptr, end))
 743                 r = -EFAULT;
 744         else if ((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 745                 range->vma->vm_file)
 746                 r = -EPERM;
 747         if (r)
 748                 goto out;
 749
 750         range->pfns = kvmalloc_array(ttm->num_pages, sizeof(uint64_t),
 751                                      GFP_KERNEL);
 752         if (range->pfns == NULL) {
 753                 r = -ENOMEM;
 754                 goto out;
 755         }
 756         range->start = gtt->userptr;
 757         range->end = end;
 758
 759         range->pfns[0] = range->flags[HMM_PFN_VALID];
 760         range->pfns[0] |= amdgpu_ttm_tt_is_readonly(ttm) ?
 761                                 0 : range->flags[HMM_PFN_WRITE];
 762         for (i = 1; i < ttm->num_pages; i++)
 763                 range->pfns[i] = range->pfns[0];
 764
 765         /* This may trigger page table update */
 766         r = hmm_vma_fault(range, true);
 767         if (r)
 768                 goto out_free_pfns;
 769
 770         up_read(&mm->mmap_sem);
 771
 772         for (i = 0; i < ttm->num_pages; i++)
 773                 pages[i] = hmm_pfn_to_page(range, range->pfns[i]);
 774
 775         return 0;
 776
 777 out_free_pfns:
 778         kvfree(range->pfns);
 779         range->pfns = NULL;
 780 out:
 781         up_read(&mm->mmap_sem);
 782         return r;
 783 }
 784
 785 /**
 786  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 787  * Check if the pages backing this ttm range have been invalidated
 788  *
 789  * Returns: true if pages are still valid
 790  */
 791 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 792 {
 793         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 794         bool r = false;
 795
 796         if (!gtt || !gtt->userptr)
 797                 return false;
 798
 799         WARN_ONCE(!gtt->range.pfns, "No user pages to check\n");
 800         if (gtt->range.pfns) {
 801                 r = hmm_vma_range_done(&gtt->range);
 802                 kvfree(gtt->range.pfns);
 803                 gtt->range.pfns = NULL;
 804         }
 805
 806         return r;
 807 }
 808 #endif
 809
 810 /**
 811  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 812  *
 813  * Called by amdgpu_cs_list_validate(). This creates the page list
 814  * that backs user memory and will ultimately be mapped into the device
 815  * address space.
 816  */
 817 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 818 {
 819         unsigned i;
 820
 821         for (i = 0; i < ttm->num_pages; ++i)
 822                 ttm->pages[i] = pages ? pages[i] : NULL;
 823 }
 824
 825 /**
 826  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 827  *
 828  * Called by amdgpu_ttm_backend_bind()
 829  **/
 830 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 831 {
 832         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 833         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 834         unsigned nents;
 835         int r;
 836
 837         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 838         enum dma_data_direction direction = write ?
 839                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 840
 841         /* Allocate an SG array and squash pages into it */
 842         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 843                                       ttm->num_pages << PAGE_SHIFT,
 844                                       GFP_KERNEL);
 845         if (r)
 846                 goto release_sg;
 847
 848         /* Map SG to device */
 849         r = -ENOMEM;
 850         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 851         if (nents != ttm->sg->nents)
 852                 goto release_sg;
 853
 854         /* convert SG to linear array of pages and dma addresses */
 855         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 856                                          gtt->ttm.dma_address, ttm->num_pages);
 857
 858         return 0;
 859
 860 release_sg:
 861         kfree(ttm->sg);
 862         return r;
 863 }
 864
 865 /**
 866  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 867  */
 868 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 869 {
 870         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 871         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 872
 873         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 874         enum dma_data_direction direction = write ?
 875                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 876
 877         /* double check that we don't free the table twice */
 878         if (!ttm->sg->sgl)
 879                 return;
 880
 881         /* unmap the pages mapped to the device */
 882         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 883
 884         sg_free_table(ttm->sg);
 885
 886 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 887         if (gtt->range.pfns &&
 888             ttm->pages[0] == hmm_pfn_to_page(&gtt->range, gtt->range.pfns[0]))
 889                 WARN_ONCE(1, "Missing get_user_page_done\n");
 890 #endif
 891 }
 892
 893 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 894                                 struct ttm_buffer_object *tbo,
 895                                 uint64_t flags)
 896 {
 897         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 898         struct ttm_tt *ttm = tbo->ttm;
 899         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 900         int r;
 901
 902         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 903                 uint64_t page_idx = 1;
 904
 905                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 906                                 ttm->pages, gtt->ttm.dma_address, flags);
 907                 if (r)
 908                         goto gart_bind_fail;
 909
 910                 /* Patch mtype of the second part BO */
 911                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
 912                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
 913
 914                 r = amdgpu_gart_bind(adev,
 915                                 gtt->offset + (page_idx << PAGE_SHIFT),
 916                                 ttm->num_pages - page_idx,
 917                                 &ttm->pages[page_idx],
 918                                 &(gtt->ttm.dma_address[page_idx]), flags);
 919         } else {
 920                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 921                                      ttm->pages, gtt->ttm.dma_address, flags);
 922         }
 923
 924 gart_bind_fail:
 925         if (r)
 926                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 927                           ttm->num_pages, gtt->offset);
 928
 929         return r;
 930 }
 931
 932 /**
 933  * amdgpu_ttm_backend_bind - Bind GTT memory
 934  *
 935  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 936  * This handles binding GTT memory to the device address space.
 937  */
 938 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 939                                    struct ttm_mem_reg *bo_mem)
 940 {
 941         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 942         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 943         uint64_t flags;
 944         int r = 0;
 945
 946         if (gtt->userptr) {
 947                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 948                 if (r) {
 949                         DRM_ERROR("failed to pin userptr\n");
 950                         return r;
 951                 }
 952         }
 953         if (!ttm->num_pages) {
 954                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 955                      ttm->num_pages, bo_mem, ttm);
 956         }
 957
 958         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 959             bo_mem->mem_type == AMDGPU_PL_GWS ||
 960             bo_mem->mem_type == AMDGPU_PL_OA)
 961                 return -EINVAL;
 962
 963         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 964                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 965                 return 0;
 966         }
 967
 968         /* compute PTE flags relevant to this BO memory */
 969         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 970
 971         /* bind pages into GART page tables */
 972         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 973         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 974                 ttm->pages, gtt->ttm.dma_address, flags);
 975
 976         if (r)
 977                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 978                           ttm->num_pages, gtt->offset);
 979         return r;
 980 }
 981
 982 /**
 983  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
 984  */
 985 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 986 {
 987         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 988         struct ttm_operation_ctx ctx = { false, false };
 989         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
 990         struct ttm_mem_reg tmp;
 991         struct ttm_placement placement;
 992         struct ttm_place placements;
 993         uint64_t addr, flags;
 994         int r;
 995
 996         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 997                 return 0;
 998
 999         addr = amdgpu_gmc_agp_addr(bo);
1000         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1001                 bo->mem.start = addr >> PAGE_SHIFT;
1002         } else {
1003
1004                 /* allocate GART space */
1005                 tmp = bo->mem;
1006                 tmp.mm_node = NULL;
1007                 placement.num_placement = 1;
1008                 placement.placement = &placements;
1009                 placement.num_busy_placement = 1;
1010                 placement.busy_placement = &placements;
1011                 placements.fpfn = 0;
1012                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1013                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1014                         TTM_PL_FLAG_TT;
1015
1016                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1017                 if (unlikely(r))
1018                         return r;
1019
1020                 /* compute PTE flags for this buffer object */
1021                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1022
1023                 /* Bind pages */
1024                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1025                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1026                 if (unlikely(r)) {
1027                         ttm_bo_mem_put(bo, &tmp);
1028                         return r;
1029                 }
1030
1031                 ttm_bo_mem_put(bo, &bo->mem);
1032                 bo->mem = tmp;
1033         }
1034
1035         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1036                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1037
1038         return 0;
1039 }
1040
1041 /**
1042  * amdgpu_ttm_recover_gart - Rebind GTT pages
1043  *
1044  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1045  * rebind GTT pages during a GPU reset.
1046  */
1047 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1048 {
1049         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1050         uint64_t flags;
1051         int r;
1052
1053         if (!tbo->ttm)
1054                 return 0;
1055
1056         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1057         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1058
1059         return r;
1060 }
1061
1062 /**
1063  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1064  *
1065  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1066  * ttm_tt_destroy().
1067  */
1068 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1069 {
1070         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1071         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1072         int r;
1073
1074         /* if the pages have userptr pinning then clear that first */
1075         if (gtt->userptr)
1076                 amdgpu_ttm_tt_unpin_userptr(ttm);
1077
1078         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1079                 return 0;
1080
1081         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1082         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1083         if (r)
1084                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1085                           gtt->ttm.ttm.num_pages, gtt->offset);
1086         return r;
1087 }
1088
1089 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1090 {
1091         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1092
1093         if (gtt->usertask)
1094                 put_task_struct(gtt->usertask);
1095
1096         ttm_dma_tt_fini(&gtt->ttm);
1097         kfree(gtt);
1098 }
1099
1100 static struct ttm_backend_func amdgpu_backend_func = {
1101         .bind = &amdgpu_ttm_backend_bind,
1102         .unbind = &amdgpu_ttm_backend_unbind,
1103         .destroy = &amdgpu_ttm_backend_destroy,
1104 };
1105
1106 /**
1107  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1108  *
1109  * @bo: The buffer object to create a GTT ttm_tt object around
1110  *
1111  * Called by ttm_tt_create().
1112  */
1113 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1114                                            uint32_t page_flags)
1115 {
1116         struct amdgpu_device *adev;
1117         struct amdgpu_ttm_tt *gtt;
1118
1119         adev = amdgpu_ttm_adev(bo->bdev);
1120
1121         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1122         if (gtt == NULL) {
1123                 return NULL;
1124         }
1125         gtt->ttm.ttm.func = &amdgpu_backend_func;
1126
1127         /* allocate space for the uninitialized page entries */
1128         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1129                 kfree(gtt);
1130                 return NULL;
1131         }
1132         return &gtt->ttm.ttm;
1133 }
1134
1135 /**
1136  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1137  *
1138  * Map the pages of a ttm_tt object to an address space visible
1139  * to the underlying device.
1140  */
1141 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1142                         struct ttm_operation_ctx *ctx)
1143 {
1144         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1145         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1146         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1147
1148         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1149         if (gtt && gtt->userptr) {
1150                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1151                 if (!ttm->sg)
1152                         return -ENOMEM;
1153
1154                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1155                 ttm->state = tt_unbound;
1156                 return 0;
1157         }
1158
1159         if (slave && ttm->sg) {
1160                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1161                                                  gtt->ttm.dma_address,
1162                                                  ttm->num_pages);
1163                 ttm->state = tt_unbound;
1164                 return 0;
1165         }
1166
1167 #ifdef CONFIG_SWIOTLB
1168         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1169                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1170         }
1171 #endif
1172
1173         /* fall back to generic helper to populate the page array
1174          * and map them to the device */
1175         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1176 }
1177
1178 /**
1179  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1180  *
1181  * Unmaps pages of a ttm_tt object from the device address space and
1182  * unpopulates the page array backing it.
1183  */
1184 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1185 {
1186         struct amdgpu_device *adev;
1187         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1188         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1189
1190         if (gtt && gtt->userptr) {
1191                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1192                 kfree(ttm->sg);
1193                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1194                 return;
1195         }
1196
1197         if (slave)
1198                 return;
1199
1200         adev = amdgpu_ttm_adev(ttm->bdev);
1201
1202 #ifdef CONFIG_SWIOTLB
1203         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1204                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1205                 return;
1206         }
1207 #endif
1208
1209         /* fall back to generic helper to unmap and unpopulate array */
1210         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1211 }
1212
1213 /**
1214  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1215  * task
1216  *
1217  * @ttm: The ttm_tt object to bind this userptr object to
1218  * @addr:  The address in the current tasks VM space to use
1219  * @flags: Requirements of userptr object.
1220  *
1221  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1222  * to current task
1223  */
1224 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1225                               uint32_t flags)
1226 {
1227         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1228
1229         if (gtt == NULL)
1230                 return -EINVAL;
1231
1232         gtt->userptr = addr;
1233         gtt->userflags = flags;
1234
1235         if (gtt->usertask)
1236                 put_task_struct(gtt->usertask);
1237         gtt->usertask = current->group_leader;
1238         get_task_struct(gtt->usertask);
1239
1240         return 0;
1241 }
1242
1243 /**
1244  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1245  */
1246 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1247 {
1248         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1249
1250         if (gtt == NULL)
1251                 return NULL;
1252
1253         if (gtt->usertask == NULL)
1254                 return NULL;
1255
1256         return gtt->usertask->mm;
1257 }
1258
1259 /**
1260  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1261  * address range for the current task.
1262  *
1263  */
1264 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1265                                   unsigned long end)
1266 {
1267         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1268         unsigned long size;
1269
1270         if (gtt == NULL || !gtt->userptr)
1271                 return false;
1272
1273         /* Return false if no part of the ttm_tt object lies within
1274          * the range
1275          */
1276         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1277         if (gtt->userptr > end || gtt->userptr + size <= start)
1278                 return false;
1279
1280         return true;
1281 }
1282
1283 /**
1284  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1285  */
1286 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1287 {
1288         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1289
1290         if (gtt == NULL || !gtt->userptr)
1291                 return false;
1292
1293         return true;
1294 }
1295
1296 /**
1297  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1298  */
1299 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1300 {
1301         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1302
1303         if (gtt == NULL)
1304                 return false;
1305
1306         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1307 }
1308
1309 /**
1310  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1311  *
1312  * @ttm: The ttm_tt object to compute the flags for
1313  * @mem: The memory registry backing this ttm_tt object
1314  *
1315  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1316  */
1317 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1318 {
1319         uint64_t flags = 0;
1320
1321         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1322                 flags |= AMDGPU_PTE_VALID;
1323
1324         if (mem && mem->mem_type == TTM_PL_TT) {
1325                 flags |= AMDGPU_PTE_SYSTEM;
1326
1327                 if (ttm->caching_state == tt_cached)
1328                         flags |= AMDGPU_PTE_SNOOPED;
1329         }
1330
1331         return flags;
1332 }
1333
1334 /**
1335  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1336  *
1337  * @ttm: The ttm_tt object to compute the flags for
1338  * @mem: The memory registry backing this ttm_tt object
1339
1340  * Figure out the flags to use for a VM PTE (Page Table Entry).
1341  */
1342 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1343                                  struct ttm_mem_reg *mem)
1344 {
1345         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1346
1347         flags |= adev->gart.gart_pte_flags;
1348         flags |= AMDGPU_PTE_READABLE;
1349
1350         if (!amdgpu_ttm_tt_is_readonly(ttm))
1351                 flags |= AMDGPU_PTE_WRITEABLE;
1352
1353         return flags;
1354 }
1355
1356 /**
1357  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1358  * object.
1359  *
1360  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1361  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1362  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1363  * used to clean out a memory space.
1364  */
1365 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1366                                             const struct ttm_place *place)
1367 {
1368         unsigned long num_pages = bo->mem.num_pages;
1369         struct drm_mm_node *node = bo->mem.mm_node;
1370         struct reservation_object_list *flist;
1371         struct dma_fence *f;
1372         int i;
1373
1374         /* If bo is a KFD BO, check if the bo belongs to the current process.
1375          * If true, then return false as any KFD process needs all its BOs to
1376          * be resident to run successfully
1377          */
1378         flist = reservation_object_get_list(bo->resv);
1379         if (flist) {
1380                 for (i = 0; i < flist->shared_count; ++i) {
1381                         f = rcu_dereference_protected(flist->shared[i],
1382                                 reservation_object_held(bo->resv));
1383                         if (amdkfd_fence_check_mm(f, current->mm))
1384                                 return false;
1385                 }
1386         }
1387
1388         switch (bo->mem.mem_type) {
1389         case TTM_PL_TT:
1390                 return true;
1391
1392         case TTM_PL_VRAM:
1393                 /* Check each drm MM node individually */
1394                 while (num_pages) {
1395                         if (place->fpfn < (node->start + node->size) &&
1396                             !(place->lpfn && place->lpfn <= node->start))
1397                                 return true;
1398
1399                         num_pages -= node->size;
1400                         ++node;
1401                 }
1402                 return false;
1403
1404         default:
1405                 break;
1406         }
1407
1408         return ttm_bo_eviction_valuable(bo, place);
1409 }
1410
1411 /**
1412  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1413  *
1414  * @bo:  The buffer object to read/write
1415  * @offset:  Offset into buffer object
1416  * @buf:  Secondary buffer to write/read from
1417  * @len: Length in bytes of access
1418  * @write:  true if writing
1419  *
1420  * This is used to access VRAM that backs a buffer object via MMIO
1421  * access for debugging purposes.
1422  */
1423 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1424                                     unsigned long offset,
1425                                     void *buf, int len, int write)
1426 {
1427         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1428         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1429         struct drm_mm_node *nodes;
1430         uint32_t value = 0;
1431         int ret = 0;
1432         uint64_t pos;
1433         unsigned long flags;
1434
1435         if (bo->mem.mem_type != TTM_PL_VRAM)
1436                 return -EIO;
1437
1438         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1439         pos = (nodes->start << PAGE_SHIFT) + offset;
1440
1441         while (len && pos < adev->gmc.mc_vram_size) {
1442                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1443                 uint32_t bytes = 4 - (pos & 3);
1444                 uint32_t shift = (pos & 3) * 8;
1445                 uint32_t mask = 0xffffffff << shift;
1446
1447                 if (len < bytes) {
1448                         mask &= 0xffffffff >> (bytes - len) * 8;
1449                         bytes = len;
1450                 }
1451
1452                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1453                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1454                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1455                 if (!write || mask != 0xffffffff)
1456                         value = RREG32_NO_KIQ(mmMM_DATA);
1457                 if (write) {
1458                         value &= ~mask;
1459                         value |= (*(uint32_t *)buf << shift) & mask;
1460                         WREG32_NO_KIQ(mmMM_DATA, value);
1461                 }
1462                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1463                 if (!write) {
1464                         value = (value & mask) >> shift;
1465                         memcpy(buf, &value, bytes);
1466                 }
1467
1468                 ret += bytes;
1469                 buf = (uint8_t *)buf + bytes;
1470                 pos += bytes;
1471                 len -= bytes;
1472                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1473                         ++nodes;
1474                         pos = (nodes->start << PAGE_SHIFT);
1475                 }
1476         }
1477
1478         return ret;
1479 }
1480
1481 static struct ttm_bo_driver amdgpu_bo_driver = {
1482         .ttm_tt_create = &amdgpu_ttm_tt_create,
1483         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1484         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1485         .invalidate_caches = &amdgpu_invalidate_caches,
1486         .init_mem_type = &amdgpu_init_mem_type,
1487         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1488         .evict_flags = &amdgpu_evict_flags,
1489         .move = &amdgpu_bo_move,
1490         .verify_access = &amdgpu_verify_access,
1491         .move_notify = &amdgpu_bo_move_notify,
1492         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1493         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1494         .io_mem_free = &amdgpu_ttm_io_mem_free,
1495         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1496         .access_memory = &amdgpu_ttm_access_memory,
1497         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1498 };
1499
1500 /*
1501  * Firmware Reservation functions
1502  */
1503 /**
1504  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1505  *
1506  * @adev: amdgpu_device pointer
1507  *
1508  * free fw reserved vram if it has been reserved.
1509  */
1510 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1511 {
1512         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1513                 NULL, &adev->fw_vram_usage.va);
1514 }
1515
1516 /**
1517  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1518  *
1519  * @adev: amdgpu_device pointer
1520  *
1521  * create bo vram reservation from fw.
1522  */
1523 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1524 {
1525         struct ttm_operation_ctx ctx = { false, false };
1526         struct amdgpu_bo_param bp;
1527         int r = 0;
1528         int i;
1529         u64 vram_size = adev->gmc.visible_vram_size;
1530         u64 offset = adev->fw_vram_usage.start_offset;
1531         u64 size = adev->fw_vram_usage.size;
1532         struct amdgpu_bo *bo;
1533
1534         memset(&bp, 0, sizeof(bp));
1535         bp.size = adev->fw_vram_usage.size;
1536         bp.byte_align = PAGE_SIZE;
1537         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1538         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1539                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1540         bp.type = ttm_bo_type_kernel;
1541         bp.resv = NULL;
1542         adev->fw_vram_usage.va = NULL;
1543         adev->fw_vram_usage.reserved_bo = NULL;
1544
1545         if (adev->fw_vram_usage.size > 0 &&
1546                 adev->fw_vram_usage.size <= vram_size) {
1547
1548                 r = amdgpu_bo_create(adev, &bp,
1549                                      &adev->fw_vram_usage.reserved_bo);
1550                 if (r)
1551                         goto error_create;
1552
1553                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1554                 if (r)
1555                         goto error_reserve;
1556
1557                 /* remove the original mem node and create a new one at the
1558                  * request position
1559                  */
1560                 bo = adev->fw_vram_usage.reserved_bo;
1561                 offset = ALIGN(offset, PAGE_SIZE);
1562                 for (i = 0; i < bo->placement.num_placement; ++i) {
1563                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1564                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1565                 }
1566
1567                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1568                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1569                                      &bo->tbo.mem, &ctx);
1570                 if (r)
1571                         goto error_pin;
1572
1573                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1574                         AMDGPU_GEM_DOMAIN_VRAM,
1575                         adev->fw_vram_usage.start_offset,
1576                         (adev->fw_vram_usage.start_offset +
1577                         adev->fw_vram_usage.size));
1578                 if (r)
1579                         goto error_pin;
1580                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1581                         &adev->fw_vram_usage.va);
1582                 if (r)
1583                         goto error_kmap;
1584
1585                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1586         }
1587         return r;
1588
1589 error_kmap:
1590         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1591 error_pin:
1592         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1593 error_reserve:
1594         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1595 error_create:
1596         adev->fw_vram_usage.va = NULL;
1597         adev->fw_vram_usage.reserved_bo = NULL;
1598         return r;
1599 }
1600 /**
1601  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1602  * gtt/vram related fields.
1603  *
1604  * This initializes all of the memory space pools that the TTM layer
1605  * will need such as the GTT space (system memory mapped to the device),
1606  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1607  * can be mapped per VMID.
1608  */
1609 int amdgpu_ttm_init(struct amdgpu_device *adev)
1610 {
1611         uint64_t gtt_size;
1612         int r;
1613         u64 vis_vram_limit;
1614
1615         mutex_init(&adev->mman.gtt_window_lock);
1616
1617         /* No others user of address space so set it to 0 */
1618         r = ttm_bo_device_init(&adev->mman.bdev,
1619                                &amdgpu_bo_driver,
1620                                adev->ddev->anon_inode->i_mapping,
1621                                adev->need_dma32);
1622         if (r) {
1623                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1624                 return r;
1625         }
1626         adev->mman.initialized = true;
1627
1628         /* We opt to avoid OOM on system pages allocations */
1629         adev->mman.bdev.no_retry = true;
1630
1631         /* Initialize VRAM pool with all of VRAM divided into pages */
1632         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1633                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1634         if (r) {
1635                 DRM_ERROR("Failed initializing VRAM heap.\n");
1636                 return r;
1637         }
1638
1639         /* Reduce size of CPU-visible VRAM if requested */
1640         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1641         if (amdgpu_vis_vram_limit > 0 &&
1642             vis_vram_limit <= adev->gmc.visible_vram_size)
1643                 adev->gmc.visible_vram_size = vis_vram_limit;
1644
1645         /* Change the size here instead of the init above so only lpfn is affected */
1646         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1647 #ifdef CONFIG_64BIT
1648         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1649                                                 adev->gmc.visible_vram_size);
1650 #endif
1651
1652         /*
1653          *The reserved vram for firmware must be pinned to the specified
1654          *place on the VRAM, so reserve it early.
1655          */
1656         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1657         if (r) {
1658                 return r;
1659         }
1660
1661         /* allocate memory as required for VGA
1662          * This is used for VGA emulation and pre-OS scanout buffers to
1663          * avoid display artifacts while transitioning between pre-OS
1664          * and driver.  */
1665         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1666                                     AMDGPU_GEM_DOMAIN_VRAM,
1667                                     &adev->stolen_vga_memory,
1668                                     NULL, NULL);
1669         if (r)
1670                 return r;
1671         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1672                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1673
1674         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1675          * or whatever the user passed on module init */
1676         if (amdgpu_gtt_size == -1) {
1677                 struct sysinfo si;
1678
1679                 si_meminfo(&si);
1680                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1681                                adev->gmc.mc_vram_size),
1682                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1683         }
1684         else
1685                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1686
1687         /* Initialize GTT memory pool */
1688         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1689         if (r) {
1690                 DRM_ERROR("Failed initializing GTT heap.\n");
1691                 return r;
1692         }
1693         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1694                  (unsigned)(gtt_size / (1024 * 1024)));
1695
1696         /* Initialize various on-chip memory pools */
1697         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1698                            adev->gds.mem.total_size);
1699         if (r) {
1700                 DRM_ERROR("Failed initializing GDS heap.\n");
1701                 return r;
1702         }
1703
1704         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1705                                     4, AMDGPU_GEM_DOMAIN_GDS,
1706                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1707         if (r)
1708                 return r;
1709
1710         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1711                            adev->gds.gws.total_size);
1712         if (r) {
1713                 DRM_ERROR("Failed initializing gws heap.\n");
1714                 return r;
1715         }
1716
1717         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1718                                     1, AMDGPU_GEM_DOMAIN_GWS,
1719                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1720         if (r)
1721                 return r;
1722
1723         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1724                            adev->gds.oa.total_size);
1725         if (r) {
1726                 DRM_ERROR("Failed initializing oa heap.\n");
1727                 return r;
1728         }
1729
1730         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1731                                     1, AMDGPU_GEM_DOMAIN_OA,
1732                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1733         if (r)
1734                 return r;
1735
1736         /* Register debugfs entries for amdgpu_ttm */
1737         r = amdgpu_ttm_debugfs_init(adev);
1738         if (r) {
1739                 DRM_ERROR("Failed to init debugfs\n");
1740                 return r;
1741         }
1742         return 0;
1743 }
1744
1745 /**
1746  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1747  */
1748 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1749 {
1750         /* return the VGA stolen memory (if any) back to VRAM */
1751         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1752 }
1753
1754 /**
1755  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1756  */
1757 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1758 {
1759         if (!adev->mman.initialized)
1760                 return;
1761
1762         amdgpu_ttm_debugfs_fini(adev);
1763         amdgpu_ttm_fw_reserve_vram_fini(adev);
1764         if (adev->mman.aper_base_kaddr)
1765                 iounmap(adev->mman.aper_base_kaddr);
1766         adev->mman.aper_base_kaddr = NULL;
1767
1768         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1769         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1770         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1771         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1772         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1773         ttm_bo_device_release(&adev->mman.bdev);
1774         adev->mman.initialized = false;
1775         DRM_INFO("amdgpu: ttm finalized\n");
1776 }
1777
1778 /**
1779  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1780  *
1781  * @adev: amdgpu_device pointer
1782  * @enable: true when we can use buffer functions.
1783  *
1784  * Enable/disable use of buffer functions during suspend/resume. This should
1785  * only be called at bootup or when userspace isn't running.
1786  */
1787 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1788 {
1789         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1790         uint64_t size;
1791         int r;
1792
1793         if (!adev->mman.initialized || adev->in_gpu_reset ||
1794             adev->mman.buffer_funcs_enabled == enable)
1795                 return;
1796
1797         if (enable) {
1798                 struct amdgpu_ring *ring;
1799                 struct drm_sched_rq *rq;
1800
1801                 ring = adev->mman.buffer_funcs_ring;
1802                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1803                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1804                 if (r) {
1805                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1806                                   r);
1807                         return;
1808                 }
1809         } else {
1810                 drm_sched_entity_destroy(&adev->mman.entity);
1811                 dma_fence_put(man->move);
1812                 man->move = NULL;
1813         }
1814
1815         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1816         if (enable)
1817                 size = adev->gmc.real_vram_size;
1818         else
1819                 size = adev->gmc.visible_vram_size;
1820         man->size = size >> PAGE_SHIFT;
1821         adev->mman.buffer_funcs_enabled = enable;
1822 }
1823
1824 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1825 {
1826         struct drm_file *file_priv = filp->private_data;
1827         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1828
1829         if (adev == NULL)
1830                 return -EINVAL;
1831
1832         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1833 }
1834
1835 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1836                              struct ttm_mem_reg *mem, unsigned num_pages,
1837                              uint64_t offset, unsigned window,
1838                              struct amdgpu_ring *ring,
1839                              uint64_t *addr)
1840 {
1841         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1842         struct amdgpu_device *adev = ring->adev;
1843         struct ttm_tt *ttm = bo->ttm;
1844         struct amdgpu_job *job;
1845         unsigned num_dw, num_bytes;
1846         dma_addr_t *dma_address;
1847         struct dma_fence *fence;
1848         uint64_t src_addr, dst_addr;
1849         uint64_t flags;
1850         int r;
1851
1852         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1853                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1854
1855         *addr = adev->gmc.gart_start;
1856         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1857                 AMDGPU_GPU_PAGE_SIZE;
1858
1859         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1860         while (num_dw & 0x7)
1861                 num_dw++;
1862
1863         num_bytes = num_pages * 8;
1864
1865         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1866         if (r)
1867                 return r;
1868
1869         src_addr = num_dw * 4;
1870         src_addr += job->ibs[0].gpu_addr;
1871
1872         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1873         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1874         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1875                                 dst_addr, num_bytes);
1876
1877         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1878         WARN_ON(job->ibs[0].length_dw > num_dw);
1879
1880         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1881         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1882         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1883                             &job->ibs[0].ptr[num_dw]);
1884         if (r)
1885                 goto error_free;
1886
1887         r = amdgpu_job_submit(job, &adev->mman.entity,
1888                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1889         if (r)
1890                 goto error_free;
1891
1892         dma_fence_put(fence);
1893
1894         return r;
1895
1896 error_free:
1897         amdgpu_job_free(job);
1898         return r;
1899 }
1900
1901 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1902                        uint64_t dst_offset, uint32_t byte_count,
1903                        struct reservation_object *resv,
1904                        struct dma_fence **fence, bool direct_submit,
1905                        bool vm_needs_flush)
1906 {
1907         struct amdgpu_device *adev = ring->adev;
1908         struct amdgpu_job *job;
1909
1910         uint32_t max_bytes;
1911         unsigned num_loops, num_dw;
1912         unsigned i;
1913         int r;
1914
1915         if (direct_submit && !ring->sched.ready) {
1916                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1917                 return -EINVAL;
1918         }
1919
1920         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1921         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1922         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1923
1924         /* for IB padding */
1925         while (num_dw & 0x7)
1926                 num_dw++;
1927
1928         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1929         if (r)
1930                 return r;
1931
1932         if (vm_needs_flush) {
1933                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1934                 job->vm_needs_flush = true;
1935         }
1936         if (resv) {
1937                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1938                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1939                                      false);
1940                 if (r) {
1941                         DRM_ERROR("sync failed (%d).\n", r);
1942                         goto error_free;
1943                 }
1944         }
1945
1946         for (i = 0; i < num_loops; i++) {
1947                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1948
1949                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1950                                         dst_offset, cur_size_in_bytes);
1951
1952                 src_offset += cur_size_in_bytes;
1953                 dst_offset += cur_size_in_bytes;
1954                 byte_count -= cur_size_in_bytes;
1955         }
1956
1957         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1958         WARN_ON(job->ibs[0].length_dw > num_dw);
1959         if (direct_submit)
1960                 r = amdgpu_job_submit_direct(job, ring, fence);
1961         else
1962                 r = amdgpu_job_submit(job, &adev->mman.entity,
1963                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1964         if (r)
1965                 goto error_free;
1966
1967         return r;
1968
1969 error_free:
1970         amdgpu_job_free(job);
1971         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1972         return r;
1973 }
1974
1975 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1976                        uint32_t src_data,
1977                        struct reservation_object *resv,
1978                        struct dma_fence **fence)
1979 {
1980         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1981         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1982         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1983
1984         struct drm_mm_node *mm_node;
1985         unsigned long num_pages;
1986         unsigned int num_loops, num_dw;
1987
1988         struct amdgpu_job *job;
1989         int r;
1990
1991         if (!adev->mman.buffer_funcs_enabled) {
1992                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1993                 return -EINVAL;
1994         }
1995
1996         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1997                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1998                 if (r)
1999                         return r;
2000         }
2001
2002         num_pages = bo->tbo.num_pages;
2003         mm_node = bo->tbo.mem.mm_node;
2004         num_loops = 0;
2005         while (num_pages) {
2006                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2007
2008                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2009                 num_pages -= mm_node->size;
2010                 ++mm_node;
2011         }
2012         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2013
2014         /* for IB padding */
2015         num_dw += 64;
2016
2017         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2018         if (r)
2019                 return r;
2020
2021         if (resv) {
2022                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2023                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2024                 if (r) {
2025                         DRM_ERROR("sync failed (%d).\n", r);
2026                         goto error_free;
2027                 }
2028         }
2029
2030         num_pages = bo->tbo.num_pages;
2031         mm_node = bo->tbo.mem.mm_node;
2032
2033         while (num_pages) {
2034                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2035                 uint64_t dst_addr;
2036
2037                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2038                 while (byte_count) {
2039                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2040
2041                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2042                                                 dst_addr, cur_size_in_bytes);
2043
2044                         dst_addr += cur_size_in_bytes;
2045                         byte_count -= cur_size_in_bytes;
2046                 }
2047
2048                 num_pages -= mm_node->size;
2049                 ++mm_node;
2050         }
2051
2052         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2053         WARN_ON(job->ibs[0].length_dw > num_dw);
2054         r = amdgpu_job_submit(job, &adev->mman.entity,
2055                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2056         if (r)
2057                 goto error_free;
2058
2059         return 0;
2060
2061 error_free:
2062         amdgpu_job_free(job);
2063         return r;
2064 }
2065
2066 #if defined(CONFIG_DEBUG_FS)
2067
2068 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2069 {
2070         struct drm_info_node *node = (struct drm_info_node *)m->private;
2071         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2072         struct drm_device *dev = node->minor->dev;
2073         struct amdgpu_device *adev = dev->dev_private;
2074         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2075         struct drm_printer p = drm_seq_file_printer(m);
2076
2077         man->func->debug(man, &p);
2078         return 0;
2079 }
2080
2081 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2082         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2083         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2084         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2085         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2086         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2087         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2088 #ifdef CONFIG_SWIOTLB
2089         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2090 #endif
2091 };
2092
2093 /**
2094  * amdgpu_ttm_vram_read - Linear read access to VRAM
2095  *
2096  * Accesses VRAM via MMIO for debugging purposes.
2097  */
2098 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2099                                     size_t size, loff_t *pos)
2100 {
2101         struct amdgpu_device *adev = file_inode(f)->i_private;
2102         ssize_t result = 0;
2103         int r;
2104
2105         if (size & 0x3 || *pos & 0x3)
2106                 return -EINVAL;
2107
2108         if (*pos >= adev->gmc.mc_vram_size)
2109                 return -ENXIO;
2110
2111         while (size) {
2112                 unsigned long flags;
2113                 uint32_t value;
2114
2115                 if (*pos >= adev->gmc.mc_vram_size)
2116                         return result;
2117
2118                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2119                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2120                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2121                 value = RREG32_NO_KIQ(mmMM_DATA);
2122                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2123
2124                 r = put_user(value, (uint32_t *)buf);
2125                 if (r)
2126                         return r;
2127
2128                 result += 4;
2129                 buf += 4;
2130                 *pos += 4;
2131                 size -= 4;
2132         }
2133
2134         return result;
2135 }
2136
2137 /**
2138  * amdgpu_ttm_vram_write - Linear write access to VRAM
2139  *
2140  * Accesses VRAM via MMIO for debugging purposes.
2141  */
2142 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2143                                     size_t size, loff_t *pos)
2144 {
2145         struct amdgpu_device *adev = file_inode(f)->i_private;
2146         ssize_t result = 0;
2147         int r;
2148
2149         if (size & 0x3 || *pos & 0x3)
2150                 return -EINVAL;
2151
2152         if (*pos >= adev->gmc.mc_vram_size)
2153                 return -ENXIO;
2154
2155         while (size) {
2156                 unsigned long flags;
2157                 uint32_t value;
2158
2159                 if (*pos >= adev->gmc.mc_vram_size)
2160                         return result;
2161
2162                 r = get_user(value, (uint32_t *)buf);
2163                 if (r)
2164                         return r;
2165
2166                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2167                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2168                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2169                 WREG32_NO_KIQ(mmMM_DATA, value);
2170                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2171
2172                 result += 4;
2173                 buf += 4;
2174                 *pos += 4;
2175                 size -= 4;
2176         }
2177
2178         return result;
2179 }
2180
2181 static const struct file_operations amdgpu_ttm_vram_fops = {
2182         .owner = THIS_MODULE,
2183         .read = amdgpu_ttm_vram_read,
2184         .write = amdgpu_ttm_vram_write,
2185         .llseek = default_llseek,
2186 };
2187
2188 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2189
2190 /**
2191  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2192  */
2193 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2194                                    size_t size, loff_t *pos)
2195 {
2196         struct amdgpu_device *adev = file_inode(f)->i_private;
2197         ssize_t result = 0;
2198         int r;
2199
2200         while (size) {
2201                 loff_t p = *pos / PAGE_SIZE;
2202                 unsigned off = *pos & ~PAGE_MASK;
2203                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2204                 struct page *page;
2205                 void *ptr;
2206
2207                 if (p >= adev->gart.num_cpu_pages)
2208                         return result;
2209
2210                 page = adev->gart.pages[p];
2211                 if (page) {
2212                         ptr = kmap(page);
2213                         ptr += off;
2214
2215                         r = copy_to_user(buf, ptr, cur_size);
2216                         kunmap(adev->gart.pages[p]);
2217                 } else
2218                         r = clear_user(buf, cur_size);
2219
2220                 if (r)
2221                         return -EFAULT;
2222
2223                 result += cur_size;
2224                 buf += cur_size;
2225                 *pos += cur_size;
2226                 size -= cur_size;
2227         }
2228
2229         return result;
2230 }
2231
2232 static const struct file_operations amdgpu_ttm_gtt_fops = {
2233         .owner = THIS_MODULE,
2234         .read = amdgpu_ttm_gtt_read,
2235         .llseek = default_llseek
2236 };
2237
2238 #endif
2239
2240 /**
2241  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2242  *
2243  * This function is used to read memory that has been mapped to the
2244  * GPU and the known addresses are not physical addresses but instead
2245  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2246  */
2247 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2248                                  size_t size, loff_t *pos)
2249 {
2250         struct amdgpu_device *adev = file_inode(f)->i_private;
2251         struct iommu_domain *dom;
2252         ssize_t result = 0;
2253         int r;
2254
2255         /* retrieve the IOMMU domain if any for this device */
2256         dom = iommu_get_domain_for_dev(adev->dev);
2257
2258         while (size) {
2259                 phys_addr_t addr = *pos & PAGE_MASK;
2260                 loff_t off = *pos & ~PAGE_MASK;
2261                 size_t bytes = PAGE_SIZE - off;
2262                 unsigned long pfn;
2263                 struct page *p;
2264                 void *ptr;
2265
2266                 bytes = bytes < size ? bytes : size;
2267
2268                 /* Translate the bus address to a physical address.  If
2269                  * the domain is NULL it means there is no IOMMU active
2270                  * and the address translation is the identity
2271                  */
2272                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2273
2274                 pfn = addr >> PAGE_SHIFT;
2275                 if (!pfn_valid(pfn))
2276                         return -EPERM;
2277
2278                 p = pfn_to_page(pfn);
2279                 if (p->mapping != adev->mman.bdev.dev_mapping)
2280                         return -EPERM;
2281
2282                 ptr = kmap(p);
2283                 r = copy_to_user(buf, ptr + off, bytes);
2284                 kunmap(p);
2285                 if (r)
2286                         return -EFAULT;
2287
2288                 size -= bytes;
2289                 *pos += bytes;
2290                 result += bytes;
2291         }
2292
2293         return result;
2294 }
2295
2296 /**
2297  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2298  *
2299  * This function is used to write memory that has been mapped to the
2300  * GPU and the known addresses are not physical addresses but instead
2301  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2302  */
2303 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2304                                  size_t size, loff_t *pos)
2305 {
2306         struct amdgpu_device *adev = file_inode(f)->i_private;
2307         struct iommu_domain *dom;
2308         ssize_t result = 0;
2309         int r;
2310
2311         dom = iommu_get_domain_for_dev(adev->dev);
2312
2313         while (size) {
2314                 phys_addr_t addr = *pos & PAGE_MASK;
2315                 loff_t off = *pos & ~PAGE_MASK;
2316                 size_t bytes = PAGE_SIZE - off;
2317                 unsigned long pfn;
2318                 struct page *p;
2319                 void *ptr;
2320
2321                 bytes = bytes < size ? bytes : size;
2322
2323                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2324
2325                 pfn = addr >> PAGE_SHIFT;
2326                 if (!pfn_valid(pfn))
2327                         return -EPERM;
2328
2329                 p = pfn_to_page(pfn);
2330                 if (p->mapping != adev->mman.bdev.dev_mapping)
2331                         return -EPERM;
2332
2333                 ptr = kmap(p);
2334                 r = copy_from_user(ptr + off, buf, bytes);
2335                 kunmap(p);
2336                 if (r)
2337                         return -EFAULT;
2338
2339                 size -= bytes;
2340                 *pos += bytes;
2341                 result += bytes;
2342         }
2343
2344         return result;
2345 }
2346
2347 static const struct file_operations amdgpu_ttm_iomem_fops = {
2348         .owner = THIS_MODULE,
2349         .read = amdgpu_iomem_read,
2350         .write = amdgpu_iomem_write,
2351         .llseek = default_llseek
2352 };
2353
2354 static const struct {
2355         char *name;
2356         const struct file_operations *fops;
2357         int domain;
2358 } ttm_debugfs_entries[] = {
2359         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2360 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2361         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2362 #endif
2363         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2364 };
2365
2366 #endif
2367
2368 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2369 {
2370 #if defined(CONFIG_DEBUG_FS)
2371         unsigned count;
2372
2373         struct drm_minor *minor = adev->ddev->primary;
2374         struct dentry *ent, *root = minor->debugfs_root;
2375
2376         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2377                 ent = debugfs_create_file(
2378                                 ttm_debugfs_entries[count].name,
2379                                 S_IFREG | S_IRUGO, root,
2380                                 adev,
2381                                 ttm_debugfs_entries[count].fops);
2382                 if (IS_ERR(ent))
2383                         return PTR_ERR(ent);
2384                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2385                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2386                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2387                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2388                 adev->mman.debugfs_entries[count] = ent;
2389         }
2390
2391         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2392
2393 #ifdef CONFIG_SWIOTLB
2394         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2395                 --count;
2396 #endif
2397
2398         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2399 #else
2400         return 0;
2401 #endif
2402 }
2403
2404 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2405 {
2406 #if defined(CONFIG_DEBUG_FS)
2407         unsigned i;
2408
2409         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2410                 debugfs_remove(adev->mman.debugfs_entries[i]);
2411 #endif
2412 }