drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34 #include "amdgpu_gmc.h"
  35 #include "amdgpu_gem.h"
  36
  37 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  38                                       struct drm_amdgpu_cs_chunk_fence *data,
  39                                       uint32_t *offset)
  40 {
  41         struct drm_gem_object *gobj;
  42         struct amdgpu_bo *bo;
  43         unsigned long size;
  44         int r;
  45
  46         gobj = drm_gem_object_lookup(p->filp, data->handle);
  47         if (gobj == NULL)
  48                 return -EINVAL;
  49
  50         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  51         p->uf_entry.priority = 0;
  52         p->uf_entry.tv.bo = &bo->tbo;
  53         /* One for TTM and one for the CS job */
  54         p->uf_entry.tv.num_shared = 2;
  55
  56         drm_gem_object_put_unlocked(gobj);
  57
  58         size = amdgpu_bo_size(bo);
  59         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  60                 r = -EINVAL;
  61                 goto error_unref;
  62         }
  63
  64         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  65                 r = -EINVAL;
  66                 goto error_unref;
  67         }
  68
  69         *offset = data->offset;
  70
  71         return 0;
  72
  73 error_unref:
  74         amdgpu_bo_unref(&bo);
  75         return r;
  76 }
  77
  78 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  79                                       struct drm_amdgpu_bo_list_in *data)
  80 {
  81         int r;
  82         struct drm_amdgpu_bo_list_entry *info = NULL;
  83
  84         r = amdgpu_bo_create_list_entry_array(data, &info);
  85         if (r)
  86                 return r;
  87
  88         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  89                                   &p->bo_list);
  90         if (r)
  91                 goto error_free;
  92
  93         kvfree(info);
  94         return 0;
  95
  96 error_free:
  97         if (info)
  98                 kvfree(info);
  99
 100         return r;
 101 }
 102
 103 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 104 {
 105         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 106         struct amdgpu_vm *vm = &fpriv->vm;
 107         uint64_t *chunk_array_user;
 108         uint64_t *chunk_array;
 109         unsigned size, num_ibs = 0;
 110         uint32_t uf_offset = 0;
 111         int i;
 112         int ret;
 113
 114         if (cs->in.num_chunks == 0)
 115                 return 0;
 116
 117         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 118         if (!chunk_array)
 119                 return -ENOMEM;
 120
 121         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 122         if (!p->ctx) {
 123                 ret = -EINVAL;
 124                 goto free_chunk;
 125         }
 126
 127         mutex_lock(&p->ctx->lock);
 128
 129         /* skip guilty context job */
 130         if (atomic_read(&p->ctx->guilty) == 1) {
 131                 ret = -ECANCELED;
 132                 goto free_chunk;
 133         }
 134
 135         /* get chunks */
 136         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 137         if (copy_from_user(chunk_array, chunk_array_user,
 138                            sizeof(uint64_t)*cs->in.num_chunks)) {
 139                 ret = -EFAULT;
 140                 goto free_chunk;
 141         }
 142
 143         p->nchunks = cs->in.num_chunks;
 144         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 145                             GFP_KERNEL);
 146         if (!p->chunks) {
 147                 ret = -ENOMEM;
 148                 goto free_chunk;
 149         }
 150
 151         for (i = 0; i < p->nchunks; i++) {
 152                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 153                 struct drm_amdgpu_cs_chunk user_chunk;
 154                 uint32_t __user *cdata;
 155
 156                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 157                 if (copy_from_user(&user_chunk, chunk_ptr,
 158                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 159                         ret = -EFAULT;
 160                         i--;
 161                         goto free_partial_kdata;
 162                 }
 163                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 164                 p->chunks[i].length_dw = user_chunk.length_dw;
 165
 166                 size = p->chunks[i].length_dw;
 167                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 168
 169                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 170                 if (p->chunks[i].kdata == NULL) {
 171                         ret = -ENOMEM;
 172                         i--;
 173                         goto free_partial_kdata;
 174                 }
 175                 size *= sizeof(uint32_t);
 176                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 177                         ret = -EFAULT;
 178                         goto free_partial_kdata;
 179                 }
 180
 181                 switch (p->chunks[i].chunk_id) {
 182                 case AMDGPU_CHUNK_ID_IB:
 183                         ++num_ibs;
 184                         break;
 185
 186                 case AMDGPU_CHUNK_ID_FENCE:
 187                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 188                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 189                                 ret = -EINVAL;
 190                                 goto free_partial_kdata;
 191                         }
 192
 193                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 194                                                          &uf_offset);
 195                         if (ret)
 196                                 goto free_partial_kdata;
 197
 198                         break;
 199
 200                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 201                         size = sizeof(struct drm_amdgpu_bo_list_in);
 202                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 203                                 ret = -EINVAL;
 204                                 goto free_partial_kdata;
 205                         }
 206
 207                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 208                         if (ret)
 209                                 goto free_partial_kdata;
 210
 211                         break;
 212
 213                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 214                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 215                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 216                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 217                         break;
 218
 219                 default:
 220                         ret = -EINVAL;
 221                         goto free_partial_kdata;
 222                 }
 223         }
 224
 225         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 226         if (ret)
 227                 goto free_all_kdata;
 228
 229         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 230                 ret = -ECANCELED;
 231                 goto free_all_kdata;
 232         }
 233
 234         if (p->uf_entry.tv.bo)
 235                 p->job->uf_addr = uf_offset;
 236         kfree(chunk_array);
 237
 238         /* Use this opportunity to fill in task info for the vm */
 239         amdgpu_vm_set_task_info(vm);
 240
 241         return 0;
 242
 243 free_all_kdata:
 244         i = p->nchunks - 1;
 245 free_partial_kdata:
 246         for (; i >= 0; i--)
 247                 kvfree(p->chunks[i].kdata);
 248         kfree(p->chunks);
 249         p->chunks = NULL;
 250         p->nchunks = 0;
 251 free_chunk:
 252         kfree(chunk_array);
 253
 254         return ret;
 255 }
 256
 257 /* Convert microseconds to bytes. */
 258 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 259 {
 260         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 261                 return 0;
 262
 263         /* Since accum_us is incremented by a million per second, just
 264          * multiply it by the number of MB/s to get the number of bytes.
 265          */
 266         return us << adev->mm_stats.log2_max_MBps;
 267 }
 268
 269 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 270 {
 271         if (!adev->mm_stats.log2_max_MBps)
 272                 return 0;
 273
 274         return bytes >> adev->mm_stats.log2_max_MBps;
 275 }
 276
 277 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 278  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 279  * which means it can go over the threshold once. If that happens, the driver
 280  * will be in debt and no other buffer migrations can be done until that debt
 281  * is repaid.
 282  *
 283  * This approach allows moving a buffer of any size (it's important to allow
 284  * that).
 285  *
 286  * The currency is simply time in microseconds and it increases as the clock
 287  * ticks. The accumulated microseconds (us) are converted to bytes and
 288  * returned.
 289  */
 290 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 291                                               u64 *max_bytes,
 292                                               u64 *max_vis_bytes)
 293 {
 294         s64 time_us, increment_us;
 295         u64 free_vram, total_vram, used_vram;
 296
 297         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 298          * throttling.
 299          *
 300          * It means that in order to get full max MBps, at least 5 IBs per
 301          * second must be submitted and not more than 200ms apart from each
 302          * other.
 303          */
 304         const s64 us_upper_bound = 200000;
 305
 306         if (!adev->mm_stats.log2_max_MBps) {
 307                 *max_bytes = 0;
 308                 *max_vis_bytes = 0;
 309                 return;
 310         }
 311
 312         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 313         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 314         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 315
 316         spin_lock(&adev->mm_stats.lock);
 317
 318         /* Increase the amount of accumulated us. */
 319         time_us = ktime_to_us(ktime_get());
 320         increment_us = time_us - adev->mm_stats.last_update_us;
 321         adev->mm_stats.last_update_us = time_us;
 322         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 323                                       us_upper_bound);
 324
 325         /* This prevents the short period of low performance when the VRAM
 326          * usage is low and the driver is in debt or doesn't have enough
 327          * accumulated us to fill VRAM quickly.
 328          *
 329          * The situation can occur in these cases:
 330          * - a lot of VRAM is freed by userspace
 331          * - the presence of a big buffer causes a lot of evictions
 332          *   (solution: split buffers into smaller ones)
 333          *
 334          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 335          * accum_us to a positive number.
 336          */
 337         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 338                 s64 min_us;
 339
 340                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 341                  * VRAM now.
 342                  */
 343                 if (!(adev->flags & AMD_IS_APU))
 344                         min_us = bytes_to_us(adev, free_vram / 4);
 345                 else
 346                         min_us = 0; /* Reset accum_us on APUs. */
 347
 348                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 349         }
 350
 351         /* This is set to 0 if the driver is in debt to disallow (optional)
 352          * buffer moves.
 353          */
 354         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 355
 356         /* Do the same for visible VRAM if half of it is free */
 357         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 358                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 359                 u64 used_vis_vram =
 360                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 361
 362                 if (used_vis_vram < total_vis_vram) {
 363                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 364                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 365                                                           increment_us, us_upper_bound);
 366
 367                         if (free_vis_vram >= total_vis_vram / 2)
 368                                 adev->mm_stats.accum_us_vis =
 369                                         max(bytes_to_us(adev, free_vis_vram / 2),
 370                                             adev->mm_stats.accum_us_vis);
 371                 }
 372
 373                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 374         } else {
 375                 *max_vis_bytes = 0;
 376         }
 377
 378         spin_unlock(&adev->mm_stats.lock);
 379 }
 380
 381 /* Report how many bytes have really been moved for the last command
 382  * submission. This can result in a debt that can stop buffer migrations
 383  * temporarily.
 384  */
 385 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 386                                   u64 num_vis_bytes)
 387 {
 388         spin_lock(&adev->mm_stats.lock);
 389         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 390         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 391         spin_unlock(&adev->mm_stats.lock);
 392 }
 393
 394 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 395                                  struct amdgpu_bo *bo)
 396 {
 397         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 398         struct ttm_operation_ctx ctx = {
 399                 .interruptible = true,
 400                 .no_wait_gpu = false,
 401                 .resv = bo->tbo.resv,
 402                 .flags = 0
 403         };
 404         uint32_t domain;
 405         int r;
 406
 407         if (bo->pin_count)
 408                 return 0;
 409
 410         /* Don't move this buffer if we have depleted our allowance
 411          * to move it. Don't move anything if the threshold is zero.
 412          */
 413         if (p->bytes_moved < p->bytes_moved_threshold) {
 414                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 415                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 416                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 417                          * visible VRAM if we've depleted our allowance to do
 418                          * that.
 419                          */
 420                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 421                                 domain = bo->preferred_domains;
 422                         else
 423                                 domain = bo->allowed_domains;
 424                 } else {
 425                         domain = bo->preferred_domains;
 426                 }
 427         } else {
 428                 domain = bo->allowed_domains;
 429         }
 430
 431 retry:
 432         amdgpu_bo_placement_from_domain(bo, domain);
 433         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 434
 435         p->bytes_moved += ctx.bytes_moved;
 436         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 437             amdgpu_bo_in_cpu_visible_vram(bo))
 438                 p->bytes_moved_vis += ctx.bytes_moved;
 439
 440         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 441                 domain = bo->allowed_domains;
 442                 goto retry;
 443         }
 444
 445         return r;
 446 }
 447
 448 /* Last resort, try to evict something from the current working set */
 449 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 450                                 struct amdgpu_bo *validated)
 451 {
 452         uint32_t domain = validated->allowed_domains;
 453         struct ttm_operation_ctx ctx = { true, false };
 454         int r;
 455
 456         if (!p->evictable)
 457                 return false;
 458
 459         for (;&p->evictable->tv.head != &p->validated;
 460              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 461
 462                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 463                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
 464                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 465                 bool update_bytes_moved_vis;
 466                 uint32_t other;
 467
 468                 /* If we reached our current BO we can forget it */
 469                 if (bo == validated)
 470                         break;
 471
 472                 /* We can't move pinned BOs here */
 473                 if (bo->pin_count)
 474                         continue;
 475
 476                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 477
 478                 /* Check if this BO is in one of the domains we need space for */
 479                 if (!(other & domain))
 480                         continue;
 481
 482                 /* Check if we can move this BO somewhere else */
 483                 other = bo->allowed_domains & ~domain;
 484                 if (!other)
 485                         continue;
 486
 487                 /* Good we can try to move this BO somewhere else */
 488                 update_bytes_moved_vis =
 489                                 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 490                                 amdgpu_bo_in_cpu_visible_vram(bo);
 491                 amdgpu_bo_placement_from_domain(bo, other);
 492                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 493                 p->bytes_moved += ctx.bytes_moved;
 494                 if (update_bytes_moved_vis)
 495                         p->bytes_moved_vis += ctx.bytes_moved;
 496
 497                 if (unlikely(r))
 498                         break;
 499
 500                 p->evictable = list_prev_entry(p->evictable, tv.head);
 501                 list_move(&candidate->tv.head, &p->validated);
 502
 503                 return true;
 504         }
 505
 506         return false;
 507 }
 508
 509 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 510 {
 511         struct amdgpu_cs_parser *p = param;
 512         int r;
 513
 514         do {
 515                 r = amdgpu_cs_bo_validate(p, bo);
 516         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 517         if (r)
 518                 return r;
 519
 520         if (bo->shadow)
 521                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 522
 523         return r;
 524 }
 525
 526 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 527                             struct list_head *validated)
 528 {
 529         struct ttm_operation_ctx ctx = { true, false };
 530         struct amdgpu_bo_list_entry *lobj;
 531         int r;
 532
 533         list_for_each_entry(lobj, validated, tv.head) {
 534                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 535                 bool binding_userptr = false;
 536                 struct mm_struct *usermm;
 537
 538                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 539                 if (usermm && usermm != current->mm)
 540                         return -EPERM;
 541
 542                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 543                     lobj->user_invalidated && lobj->user_pages) {
 544                         amdgpu_bo_placement_from_domain(bo,
 545                                                         AMDGPU_GEM_DOMAIN_CPU);
 546                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 547                         if (r)
 548                                 return r;
 549
 550                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 551                                                      lobj->user_pages);
 552                         binding_userptr = true;
 553                 }
 554
 555                 if (p->evictable == lobj)
 556                         p->evictable = NULL;
 557
 558                 r = amdgpu_cs_validate(p, bo);
 559                 if (r)
 560                         return r;
 561
 562                 if (binding_userptr) {
 563                         kvfree(lobj->user_pages);
 564                         lobj->user_pages = NULL;
 565                 }
 566         }
 567         return 0;
 568 }
 569
 570 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 571                                 union drm_amdgpu_cs *cs)
 572 {
 573         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 574         struct amdgpu_vm *vm = &fpriv->vm;
 575         struct amdgpu_bo_list_entry *e;
 576         struct list_head duplicates;
 577         struct amdgpu_bo *gds;
 578         struct amdgpu_bo *gws;
 579         struct amdgpu_bo *oa;
 580         int r;
 581
 582         INIT_LIST_HEAD(&p->validated);
 583
 584         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 585         if (cs->in.bo_list_handle) {
 586                 if (p->bo_list)
 587                         return -EINVAL;
 588
 589                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 590                                        &p->bo_list);
 591                 if (r)
 592                         return r;
 593         } else if (!p->bo_list) {
 594                 /* Create a empty bo_list when no handle is provided */
 595                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 596                                           &p->bo_list);
 597                 if (r)
 598                         return r;
 599         }
 600
 601         /* One for TTM and one for the CS job */
 602         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 603                 e->tv.num_shared = 2;
 604
 605         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 606         if (p->bo_list->first_userptr != p->bo_list->num_entries)
 607                 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 608
 609         INIT_LIST_HEAD(&duplicates);
 610         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 611
 612         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 613                 list_add(&p->uf_entry.tv.head, &p->validated);
 614
 615         /* Get userptr backing pages. If pages are updated after registered
 616          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 617          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 618          */
 619         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 620                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 621                 bool userpage_invalidated = false;
 622                 int i;
 623
 624                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 625                                         sizeof(struct page *),
 626                                         GFP_KERNEL | __GFP_ZERO);
 627                 if (!e->user_pages) {
 628                         DRM_ERROR("calloc failure\n");
 629                         return -ENOMEM;
 630                 }
 631
 632                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, e->user_pages);
 633                 if (r) {
 634                         kvfree(e->user_pages);
 635                         e->user_pages = NULL;
 636                         return r;
 637                 }
 638
 639                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 640                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 641                                 userpage_invalidated = true;
 642                                 break;
 643                         }
 644                 }
 645                 e->user_invalidated = userpage_invalidated;
 646         }
 647
 648         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 649                                    &duplicates);
 650         if (unlikely(r != 0)) {
 651                 if (r != -ERESTARTSYS)
 652                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 653                 goto out;
 654         }
 655
 656         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 657                                           &p->bytes_moved_vis_threshold);
 658         p->bytes_moved = 0;
 659         p->bytes_moved_vis = 0;
 660         p->evictable = list_last_entry(&p->validated,
 661                                        struct amdgpu_bo_list_entry,
 662                                        tv.head);
 663
 664         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 665                                       amdgpu_cs_validate, p);
 666         if (r) {
 667                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 668                 goto error_validate;
 669         }
 670
 671         r = amdgpu_cs_list_validate(p, &duplicates);
 672         if (r) {
 673                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 674                 goto error_validate;
 675         }
 676
 677         r = amdgpu_cs_list_validate(p, &p->validated);
 678         if (r) {
 679                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 680                 goto error_validate;
 681         }
 682
 683         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 684                                      p->bytes_moved_vis);
 685
 686         gds = p->bo_list->gds_obj;
 687         gws = p->bo_list->gws_obj;
 688         oa = p->bo_list->oa_obj;
 689
 690         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 691                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 692
 693                 /* Make sure we use the exclusive slot for shared BOs */
 694                 if (bo->prime_shared_count)
 695                         e->tv.num_shared = 0;
 696                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 697         }
 698
 699         if (gds) {
 700                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 701                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 702         }
 703         if (gws) {
 704                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 705                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 706         }
 707         if (oa) {
 708                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 709                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 710         }
 711
 712         if (!r && p->uf_entry.tv.bo) {
 713                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 714
 715                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 716                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 717         }
 718
 719 error_validate:
 720         if (r)
 721                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 722 out:
 723         return r;
 724 }
 725
 726 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 727 {
 728         struct amdgpu_bo_list_entry *e;
 729         int r;
 730
 731         list_for_each_entry(e, &p->validated, tv.head) {
 732                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 733                 struct reservation_object *resv = bo->tbo.resv;
 734
 735                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 736                                      amdgpu_bo_explicit_sync(bo));
 737
 738                 if (r)
 739                         return r;
 740         }
 741         return 0;
 742 }
 743
 744 /**
 745  * cs_parser_fini() - clean parser states
 746  * @parser:     parser structure holding parsing context.
 747  * @error:      error number
 748  *
 749  * If error is set than unvalidate buffer, otherwise just free memory
 750  * used by parsing context.
 751  **/
 752 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 753                                   bool backoff)
 754 {
 755         unsigned i;
 756
 757         if (error && backoff)
 758                 ttm_eu_backoff_reservation(&parser->ticket,
 759                                            &parser->validated);
 760
 761         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 762                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 763         kfree(parser->post_dep_syncobjs);
 764
 765         dma_fence_put(parser->fence);
 766
 767         if (parser->ctx) {
 768                 mutex_unlock(&parser->ctx->lock);
 769                 amdgpu_ctx_put(parser->ctx);
 770         }
 771         if (parser->bo_list)
 772                 amdgpu_bo_list_put(parser->bo_list);
 773
 774         for (i = 0; i < parser->nchunks; i++)
 775                 kvfree(parser->chunks[i].kdata);
 776         kfree(parser->chunks);
 777         if (parser->job)
 778                 amdgpu_job_free(parser->job);
 779         if (parser->uf_entry.tv.bo) {
 780                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 781
 782                 amdgpu_bo_unref(&uf);
 783         }
 784 }
 785
 786 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 787 {
 788         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 789         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 790         struct amdgpu_device *adev = p->adev;
 791         struct amdgpu_vm *vm = &fpriv->vm;
 792         struct amdgpu_bo_list_entry *e;
 793         struct amdgpu_bo_va *bo_va;
 794         struct amdgpu_bo *bo;
 795         int r;
 796
 797         /* Only for UVD/VCE VM emulation */
 798         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 799                 unsigned i, j;
 800
 801                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 802                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 803                         struct amdgpu_bo_va_mapping *m;
 804                         struct amdgpu_bo *aobj = NULL;
 805                         struct amdgpu_cs_chunk *chunk;
 806                         uint64_t offset, va_start;
 807                         struct amdgpu_ib *ib;
 808                         uint8_t *kptr;
 809
 810                         chunk = &p->chunks[i];
 811                         ib = &p->job->ibs[j];
 812                         chunk_ib = chunk->kdata;
 813
 814                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 815                                 continue;
 816
 817                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 818                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 819                         if (r) {
 820                                 DRM_ERROR("IB va_start is invalid\n");
 821                                 return r;
 822                         }
 823
 824                         if ((va_start + chunk_ib->ib_bytes) >
 825                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 826                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 827                                 return -EINVAL;
 828                         }
 829
 830                         /* the IB should be reserved at this point */
 831                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 832                         if (r) {
 833                                 return r;
 834                         }
 835
 836                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 837                         kptr += va_start - offset;
 838
 839                         if (ring->funcs->parse_cs) {
 840                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 841                                 amdgpu_bo_kunmap(aobj);
 842
 843                                 r = amdgpu_ring_parse_cs(ring, p, j);
 844                                 if (r)
 845                                         return r;
 846                         } else {
 847                                 ib->ptr = (uint32_t *)kptr;
 848                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 849                                 amdgpu_bo_kunmap(aobj);
 850                                 if (r)
 851                                         return r;
 852                         }
 853
 854                         j++;
 855                 }
 856         }
 857
 858         if (!p->job->vm)
 859                 return amdgpu_cs_sync_rings(p);
 860
 861
 862         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 863         if (r)
 864                 return r;
 865
 866         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 867         if (r)
 868                 return r;
 869
 870         r = amdgpu_sync_fence(adev, &p->job->sync,
 871                               fpriv->prt_va->last_pt_update, false);
 872         if (r)
 873                 return r;
 874
 875         if (amdgpu_sriov_vf(adev)) {
 876                 struct dma_fence *f;
 877
 878                 bo_va = fpriv->csa_va;
 879                 BUG_ON(!bo_va);
 880                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 881                 if (r)
 882                         return r;
 883
 884                 f = bo_va->last_pt_update;
 885                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 886                 if (r)
 887                         return r;
 888         }
 889
 890         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 891                 struct dma_fence *f;
 892
 893                 /* ignore duplicates */
 894                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 895                 if (!bo)
 896                         continue;
 897
 898                 bo_va = e->bo_va;
 899                 if (bo_va == NULL)
 900                         continue;
 901
 902                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 903                 if (r)
 904                         return r;
 905
 906                 f = bo_va->last_pt_update;
 907                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 908                 if (r)
 909                         return r;
 910         }
 911
 912         r = amdgpu_vm_handle_moved(adev, vm);
 913         if (r)
 914                 return r;
 915
 916         r = amdgpu_vm_update_directories(adev, vm);
 917         if (r)
 918                 return r;
 919
 920         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 921         if (r)
 922                 return r;
 923
 924         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 925
 926         if (amdgpu_vm_debug) {
 927                 /* Invalidate all BOs to test for userspace bugs */
 928                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 929                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 930
 931                         /* ignore duplicates */
 932                         if (!bo)
 933                                 continue;
 934
 935                         amdgpu_vm_bo_invalidate(adev, bo, false);
 936                 }
 937         }
 938
 939         return amdgpu_cs_sync_rings(p);
 940 }
 941
 942 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 943                              struct amdgpu_cs_parser *parser)
 944 {
 945         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 946         struct amdgpu_vm *vm = &fpriv->vm;
 947         int r, ce_preempt = 0, de_preempt = 0;
 948         struct amdgpu_ring *ring;
 949         int i, j;
 950
 951         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 952                 struct amdgpu_cs_chunk *chunk;
 953                 struct amdgpu_ib *ib;
 954                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 955                 struct drm_sched_entity *entity;
 956
 957                 chunk = &parser->chunks[i];
 958                 ib = &parser->job->ibs[j];
 959                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 960
 961                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 962                         continue;
 963
 964                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 965                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 966                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 967                                         ce_preempt++;
 968                                 else
 969                                         de_preempt++;
 970                         }
 971
 972                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 973                         if (ce_preempt > 1 || de_preempt > 1)
 974                                 return -EINVAL;
 975                 }
 976
 977                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 978                                           chunk_ib->ip_instance, chunk_ib->ring,
 979                                           &entity);
 980                 if (r)
 981                         return r;
 982
 983                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 984                         parser->job->preamble_status |=
 985                                 AMDGPU_PREAMBLE_IB_PRESENT;
 986
 987                 if (parser->entity && parser->entity != entity)
 988                         return -EINVAL;
 989
 990                 parser->entity = entity;
 991
 992                 ring = to_amdgpu_ring(entity->rq->sched);
 993                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 994                                    chunk_ib->ib_bytes : 0, ib);
 995                 if (r) {
 996                         DRM_ERROR("Failed to get ib !\n");
 997                         return r;
 998                 }
 999
1000                 ib->gpu_addr = chunk_ib->va_start;
1001                 ib->length_dw = chunk_ib->ib_bytes / 4;
1002                 ib->flags = chunk_ib->flags;
1003
1004                 j++;
1005         }
1006
1007         /* UVD & VCE fw doesn't support user fences */
1008         ring = to_amdgpu_ring(parser->entity->rq->sched);
1009         if (parser->job->uf_addr && (
1010             ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1011             ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1012                 return -EINVAL;
1013
1014         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
1015 }
1016
1017 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1018                                        struct amdgpu_cs_chunk *chunk)
1019 {
1020         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1021         unsigned num_deps;
1022         int i, r;
1023         struct drm_amdgpu_cs_chunk_dep *deps;
1024
1025         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1026         num_deps = chunk->length_dw * 4 /
1027                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1028
1029         for (i = 0; i < num_deps; ++i) {
1030                 struct amdgpu_ctx *ctx;
1031                 struct drm_sched_entity *entity;
1032                 struct dma_fence *fence;
1033
1034                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1035                 if (ctx == NULL)
1036                         return -EINVAL;
1037
1038                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
1039                                           deps[i].ip_instance,
1040                                           deps[i].ring, &entity);
1041                 if (r) {
1042                         amdgpu_ctx_put(ctx);
1043                         return r;
1044                 }
1045
1046                 fence = amdgpu_ctx_get_fence(ctx, entity,
1047                                              deps[i].handle);
1048
1049                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1050                         struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1051                         struct dma_fence *old = fence;
1052
1053                         fence = dma_fence_get(&s_fence->scheduled);
1054                         dma_fence_put(old);
1055                 }
1056
1057                 if (IS_ERR(fence)) {
1058                         r = PTR_ERR(fence);
1059                         amdgpu_ctx_put(ctx);
1060                         return r;
1061                 } else if (fence) {
1062                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1063                                         true);
1064                         dma_fence_put(fence);
1065                         amdgpu_ctx_put(ctx);
1066                         if (r)
1067                                 return r;
1068                 }
1069         }
1070         return 0;
1071 }
1072
1073 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1074                                                  uint32_t handle)
1075 {
1076         int r;
1077         struct dma_fence *fence;
1078         r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);
1079         if (r)
1080                 return r;
1081
1082         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1083         dma_fence_put(fence);
1084
1085         return r;
1086 }
1087
1088 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1089                                             struct amdgpu_cs_chunk *chunk)
1090 {
1091         unsigned num_deps;
1092         int i, r;
1093         struct drm_amdgpu_cs_chunk_sem *deps;
1094
1095         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1096         num_deps = chunk->length_dw * 4 /
1097                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1098
1099         for (i = 0; i < num_deps; ++i) {
1100                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1101                 if (r)
1102                         return r;
1103         }
1104         return 0;
1105 }
1106
1107 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1108                                              struct amdgpu_cs_chunk *chunk)
1109 {
1110         unsigned num_deps;
1111         int i;
1112         struct drm_amdgpu_cs_chunk_sem *deps;
1113         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1114         num_deps = chunk->length_dw * 4 /
1115                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1116
1117         p->post_dep_syncobjs = kmalloc_array(num_deps,
1118                                              sizeof(struct drm_syncobj *),
1119                                              GFP_KERNEL);
1120         p->num_post_dep_syncobjs = 0;
1121
1122         if (!p->post_dep_syncobjs)
1123                 return -ENOMEM;
1124
1125         for (i = 0; i < num_deps; ++i) {
1126                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1127                 if (!p->post_dep_syncobjs[i])
1128                         return -EINVAL;
1129                 p->num_post_dep_syncobjs++;
1130         }
1131         return 0;
1132 }
1133
1134 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1135                                   struct amdgpu_cs_parser *p)
1136 {
1137         int i, r;
1138
1139         for (i = 0; i < p->nchunks; ++i) {
1140                 struct amdgpu_cs_chunk *chunk;
1141
1142                 chunk = &p->chunks[i];
1143
1144                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||
1145                     chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1146                         r = amdgpu_cs_process_fence_dep(p, chunk);
1147                         if (r)
1148                                 return r;
1149                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1150                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1151                         if (r)
1152                                 return r;
1153                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1154                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1155                         if (r)
1156                                 return r;
1157                 }
1158         }
1159
1160         return 0;
1161 }
1162
1163 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1164 {
1165         int i;
1166
1167         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1168                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1169 }
1170
1171 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1172                             union drm_amdgpu_cs *cs)
1173 {
1174         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1175         struct drm_sched_entity *entity = p->entity;
1176         enum drm_sched_priority priority;
1177         struct amdgpu_ring *ring;
1178         struct amdgpu_bo_list_entry *e;
1179         struct amdgpu_job *job;
1180         uint64_t seq;
1181         int r;
1182
1183         job = p->job;
1184         p->job = NULL;
1185
1186         r = drm_sched_job_init(&job->base, entity, p->filp);
1187         if (r)
1188                 goto error_unlock;
1189
1190         /* No memory allocation is allowed while holding the mn lock.
1191          * p->mn is hold until amdgpu_cs_submit is finished and fence is added
1192          * to BOs.
1193          */
1194         amdgpu_mn_lock(p->mn);
1195
1196         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1197          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1198          */
1199         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1200                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1201
1202                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1203         }
1204         if (r) {
1205                 r = -EAGAIN;
1206                 goto error_abort;
1207         }
1208
1209         job->owner = p->filp;
1210         p->fence = dma_fence_get(&job->base.s_fence->finished);
1211
1212         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1213         amdgpu_cs_post_dependencies(p);
1214
1215         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1216             !p->ctx->preamble_presented) {
1217                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1218                 p->ctx->preamble_presented = true;
1219         }
1220
1221         cs->out.handle = seq;
1222         job->uf_sequence = seq;
1223
1224         amdgpu_job_free_resources(job);
1225
1226         trace_amdgpu_cs_ioctl(job);
1227         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1228         priority = job->base.s_priority;
1229         drm_sched_entity_push_job(&job->base, entity);
1230
1231         ring = to_amdgpu_ring(entity->rq->sched);
1232         amdgpu_ring_priority_get(ring, priority);
1233
1234         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1235
1236         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1237         amdgpu_mn_unlock(p->mn);
1238
1239         return 0;
1240
1241 error_abort:
1242         drm_sched_job_cleanup(&job->base);
1243         amdgpu_mn_unlock(p->mn);
1244
1245 error_unlock:
1246         amdgpu_job_free(job);
1247         return r;
1248 }
1249
1250 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1251 {
1252         struct amdgpu_device *adev = dev->dev_private;
1253         union drm_amdgpu_cs *cs = data;
1254         struct amdgpu_cs_parser parser = {};
1255         bool reserved_buffers = false;
1256         int i, r;
1257
1258         if (!adev->accel_working)
1259                 return -EBUSY;
1260
1261         parser.adev = adev;
1262         parser.filp = filp;
1263
1264         r = amdgpu_cs_parser_init(&parser, data);
1265         if (r) {
1266                 DRM_ERROR("Failed to initialize parser %d!\n", r);
1267                 goto out;
1268         }
1269
1270         r = amdgpu_cs_ib_fill(adev, &parser);
1271         if (r)
1272                 goto out;
1273
1274         r = amdgpu_cs_dependencies(adev, &parser);
1275         if (r) {
1276                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1277                 goto out;
1278         }
1279
1280         r = amdgpu_cs_parser_bos(&parser, data);
1281         if (r) {
1282                 if (r == -ENOMEM)
1283                         DRM_ERROR("Not enough memory for command submission!\n");
1284                 else if (r != -ERESTARTSYS)
1285                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1286                 goto out;
1287         }
1288
1289         reserved_buffers = true;
1290
1291         for (i = 0; i < parser.job->num_ibs; i++)
1292                 trace_amdgpu_cs(&parser, i);
1293
1294         r = amdgpu_cs_vm_handling(&parser);
1295         if (r)
1296                 goto out;
1297
1298         r = amdgpu_cs_submit(&parser, cs);
1299
1300 out:
1301         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1302
1303         return r;
1304 }
1305
1306 /**
1307  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1308  *
1309  * @dev: drm device
1310  * @data: data from userspace
1311  * @filp: file private
1312  *
1313  * Wait for the command submission identified by handle to finish.
1314  */
1315 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1316                          struct drm_file *filp)
1317 {
1318         union drm_amdgpu_wait_cs *wait = data;
1319         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1320         struct drm_sched_entity *entity;
1321         struct amdgpu_ctx *ctx;
1322         struct dma_fence *fence;
1323         long r;
1324
1325         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1326         if (ctx == NULL)
1327                 return -EINVAL;
1328
1329         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1330                                   wait->in.ring, &entity);
1331         if (r) {
1332                 amdgpu_ctx_put(ctx);
1333                 return r;
1334         }
1335
1336         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1337         if (IS_ERR(fence))
1338                 r = PTR_ERR(fence);
1339         else if (fence) {
1340                 r = dma_fence_wait_timeout(fence, true, timeout);
1341                 if (r > 0 && fence->error)
1342                         r = fence->error;
1343                 dma_fence_put(fence);
1344         } else
1345                 r = 1;
1346
1347         amdgpu_ctx_put(ctx);
1348         if (r < 0)
1349                 return r;
1350
1351         memset(wait, 0, sizeof(*wait));
1352         wait->out.status = (r == 0);
1353
1354         return 0;
1355 }
1356
1357 /**
1358  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1359  *
1360  * @adev: amdgpu device
1361  * @filp: file private
1362  * @user: drm_amdgpu_fence copied from user space
1363  */
1364 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1365                                              struct drm_file *filp,
1366                                              struct drm_amdgpu_fence *user)
1367 {
1368         struct drm_sched_entity *entity;
1369         struct amdgpu_ctx *ctx;
1370         struct dma_fence *fence;
1371         int r;
1372
1373         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1374         if (ctx == NULL)
1375                 return ERR_PTR(-EINVAL);
1376
1377         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1378                                   user->ring, &entity);
1379         if (r) {
1380                 amdgpu_ctx_put(ctx);
1381                 return ERR_PTR(r);
1382         }
1383
1384         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1385         amdgpu_ctx_put(ctx);
1386
1387         return fence;
1388 }
1389
1390 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1391                                     struct drm_file *filp)
1392 {
1393         struct amdgpu_device *adev = dev->dev_private;
1394         union drm_amdgpu_fence_to_handle *info = data;
1395         struct dma_fence *fence;
1396         struct drm_syncobj *syncobj;
1397         struct sync_file *sync_file;
1398         int fd, r;
1399
1400         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1401         if (IS_ERR(fence))
1402                 return PTR_ERR(fence);
1403
1404         if (!fence)
1405                 fence = dma_fence_get_stub();
1406
1407         switch (info->in.what) {
1408         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1409                 r = drm_syncobj_create(&syncobj, 0, fence);
1410                 dma_fence_put(fence);
1411                 if (r)
1412                         return r;
1413                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1414                 drm_syncobj_put(syncobj);
1415                 return r;
1416
1417         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1418                 r = drm_syncobj_create(&syncobj, 0, fence);
1419                 dma_fence_put(fence);
1420                 if (r)
1421                         return r;
1422                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1423                 drm_syncobj_put(syncobj);
1424                 return r;
1425
1426         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1427                 fd = get_unused_fd_flags(O_CLOEXEC);
1428                 if (fd < 0) {
1429                         dma_fence_put(fence);
1430                         return fd;
1431                 }
1432
1433                 sync_file = sync_file_create(fence);
1434                 dma_fence_put(fence);
1435                 if (!sync_file) {
1436                         put_unused_fd(fd);
1437                         return -ENOMEM;
1438                 }
1439
1440                 fd_install(fd, sync_file->file);
1441                 info->out.handle = fd;
1442                 return 0;
1443
1444         default:
1445                 return -EINVAL;
1446         }
1447 }
1448
1449 /**
1450  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1451  *
1452  * @adev: amdgpu device
1453  * @filp: file private
1454  * @wait: wait parameters
1455  * @fences: array of drm_amdgpu_fence
1456  */
1457 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1458                                      struct drm_file *filp,
1459                                      union drm_amdgpu_wait_fences *wait,
1460                                      struct drm_amdgpu_fence *fences)
1461 {
1462         uint32_t fence_count = wait->in.fence_count;
1463         unsigned int i;
1464         long r = 1;
1465
1466         for (i = 0; i < fence_count; i++) {
1467                 struct dma_fence *fence;
1468                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1469
1470                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1471                 if (IS_ERR(fence))
1472                         return PTR_ERR(fence);
1473                 else if (!fence)
1474                         continue;
1475
1476                 r = dma_fence_wait_timeout(fence, true, timeout);
1477                 dma_fence_put(fence);
1478                 if (r < 0)
1479                         return r;
1480
1481                 if (r == 0)
1482                         break;
1483
1484                 if (fence->error)
1485                         return fence->error;
1486         }
1487
1488         memset(wait, 0, sizeof(*wait));
1489         wait->out.status = (r > 0);
1490
1491         return 0;
1492 }
1493
1494 /**
1495  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1496  *
1497  * @adev: amdgpu device
1498  * @filp: file private
1499  * @wait: wait parameters
1500  * @fences: array of drm_amdgpu_fence
1501  */
1502 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1503                                     struct drm_file *filp,
1504                                     union drm_amdgpu_wait_fences *wait,
1505                                     struct drm_amdgpu_fence *fences)
1506 {
1507         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1508         uint32_t fence_count = wait->in.fence_count;
1509         uint32_t first = ~0;
1510         struct dma_fence **array;
1511         unsigned int i;
1512         long r;
1513
1514         /* Prepare the fence array */
1515         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1516
1517         if (array == NULL)
1518                 return -ENOMEM;
1519
1520         for (i = 0; i < fence_count; i++) {
1521                 struct dma_fence *fence;
1522
1523                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1524                 if (IS_ERR(fence)) {
1525                         r = PTR_ERR(fence);
1526                         goto err_free_fence_array;
1527                 } else if (fence) {
1528                         array[i] = fence;
1529                 } else { /* NULL, the fence has been already signaled */
1530                         r = 1;
1531                         first = i;
1532                         goto out;
1533                 }
1534         }
1535
1536         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1537                                        &first);
1538         if (r < 0)
1539                 goto err_free_fence_array;
1540
1541 out:
1542         memset(wait, 0, sizeof(*wait));
1543         wait->out.status = (r > 0);
1544         wait->out.first_signaled = first;
1545
1546         if (first < fence_count && array[first])
1547                 r = array[first]->error;
1548         else
1549                 r = 0;
1550
1551 err_free_fence_array:
1552         for (i = 0; i < fence_count; i++)
1553                 dma_fence_put(array[i]);
1554         kfree(array);
1555
1556         return r;
1557 }
1558
1559 /**
1560  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1561  *
1562  * @dev: drm device
1563  * @data: data from userspace
1564  * @filp: file private
1565  */
1566 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1567                                 struct drm_file *filp)
1568 {
1569         struct amdgpu_device *adev = dev->dev_private;
1570         union drm_amdgpu_wait_fences *wait = data;
1571         uint32_t fence_count = wait->in.fence_count;
1572         struct drm_amdgpu_fence *fences_user;
1573         struct drm_amdgpu_fence *fences;
1574         int r;
1575
1576         /* Get the fences from userspace */
1577         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1578                         GFP_KERNEL);
1579         if (fences == NULL)
1580                 return -ENOMEM;
1581
1582         fences_user = u64_to_user_ptr(wait->in.fences);
1583         if (copy_from_user(fences, fences_user,
1584                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1585                 r = -EFAULT;
1586                 goto err_free_fences;
1587         }
1588
1589         if (wait->in.wait_all)
1590                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1591         else
1592                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1593
1594 err_free_fences:
1595         kfree(fences);
1596
1597         return r;
1598 }
1599
1600 /**
1601  * amdgpu_cs_find_bo_va - find bo_va for VM address
1602  *
1603  * @parser: command submission parser context
1604  * @addr: VM address
1605  * @bo: resulting BO of the mapping found
1606  *
1607  * Search the buffer objects in the command submission context for a certain
1608  * virtual memory address. Returns allocation structure when found, NULL
1609  * otherwise.
1610  */
1611 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1612                            uint64_t addr, struct amdgpu_bo **bo,
1613                            struct amdgpu_bo_va_mapping **map)
1614 {
1615         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1616         struct ttm_operation_ctx ctx = { false, false };
1617         struct amdgpu_vm *vm = &fpriv->vm;
1618         struct amdgpu_bo_va_mapping *mapping;
1619         int r;
1620
1621         addr /= AMDGPU_GPU_PAGE_SIZE;
1622
1623         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1624         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1625                 return -EINVAL;
1626
1627         *bo = mapping->bo_va->base.bo;
1628         *map = mapping;
1629
1630         /* Double check that the BO is reserved by this CS */
1631         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1632                 return -EINVAL;
1633
1634         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1635                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1636                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1637                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1638                 if (r)
1639                         return r;
1640         }
1641
1642         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1643 }