drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48 #include <drm/ttm/ttm_range_manager.h>
  49
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_atomfirmware.h"
  59 #include "amdgpu_res_cursor.h"
  60 #include "bif/bif_4_1_d.h"
  61
  62 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  63
  64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  65                                    struct ttm_tt *ttm,
  66                                    struct ttm_resource *bo_mem);
  67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  68                                       struct ttm_tt *ttm);
  69
  70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  71                                     unsigned int type,
  72                                     uint64_t size_in_page)
  73 {
  74         return ttm_range_man_init(&adev->mman.bdev, type,
  75                                   false, size_in_page);
  76 }
  77
  78 /**
  79  * amdgpu_evict_flags - Compute placement flags
  80  *
  81  * @bo: The buffer object to evict
  82  * @placement: Possible destination(s) for evicted BO
  83  *
  84  * Fill in placement data when ttm_bo_evict() is called
  85  */
  86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  87                                 struct ttm_placement *placement)
  88 {
  89         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  90         struct amdgpu_bo *abo;
  91         static const struct ttm_place placements = {
  92                 .fpfn = 0,
  93                 .lpfn = 0,
  94                 .mem_type = TTM_PL_SYSTEM,
  95                 .flags = 0
  96         };
  97
  98         /* Don't handle scatter gather BOs */
  99         if (bo->type == ttm_bo_type_sg) {
 100                 placement->num_placement = 0;
 101                 placement->num_busy_placement = 0;
 102                 return;
 103         }
 104
 105         /* Object isn't an AMDGPU object so ignore */
 106         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 107                 placement->placement = &placements;
 108                 placement->busy_placement = &placements;
 109                 placement->num_placement = 1;
 110                 placement->num_busy_placement = 1;
 111                 return;
 112         }
 113
 114         abo = ttm_to_amdgpu_bo(bo);
 115         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 116                 struct dma_fence *fence;
 117                 struct dma_resv *resv = &bo->base._resv;
 118
 119                 rcu_read_lock();
 120                 fence = rcu_dereference(resv->fence_excl);
 121                 if (fence && !fence->ops->signaled)
 122                         dma_fence_enable_sw_signaling(fence);
 123
 124                 placement->num_placement = 0;
 125                 placement->num_busy_placement = 0;
 126                 rcu_read_unlock();
 127                 return;
 128         }
 129
 130         switch (bo->resource->mem_type) {
 131         case AMDGPU_PL_GDS:
 132         case AMDGPU_PL_GWS:
 133         case AMDGPU_PL_OA:
 134                 placement->num_placement = 0;
 135                 placement->num_busy_placement = 0;
 136                 return;
 137
 138         case TTM_PL_VRAM:
 139                 if (!adev->mman.buffer_funcs_enabled) {
 140                         /* Move to system memory */
 141                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 142                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 143                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 144                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 145
 146                         /* Try evicting to the CPU inaccessible part of VRAM
 147                          * first, but only set GTT as busy placement, so this
 148                          * BO will be evicted to GTT rather than causing other
 149                          * BOs to be evicted from VRAM
 150                          */
 151                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 152                                                          AMDGPU_GEM_DOMAIN_GTT);
 153                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 154                         abo->placements[0].lpfn = 0;
 155                         abo->placement.busy_placement = &abo->placements[1];
 156                         abo->placement.num_busy_placement = 1;
 157                 } else {
 158                         /* Move to GTT memory */
 159                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 160                 }
 161                 break;
 162         case TTM_PL_TT:
 163         case AMDGPU_PL_PREEMPT:
 164         default:
 165                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 166                 break;
 167         }
 168         *placement = abo->placement;
 169 }
 170
 171 /**
 172  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 173  * @bo: buffer object to map
 174  * @mem: memory object to map
 175  * @mm_cur: range to map
 176  * @num_pages: number of pages to map
 177  * @window: which GART window to use
 178  * @ring: DMA ring to use for the copy
 179  * @tmz: if we should setup a TMZ enabled mapping
 180  * @addr: resulting address inside the MC address space
 181  *
 182  * Setup one of the GART windows to access a specific piece of memory or return
 183  * the physical address for local memory.
 184  */
 185 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 186                                  struct ttm_resource *mem,
 187                                  struct amdgpu_res_cursor *mm_cur,
 188                                  unsigned num_pages, unsigned window,
 189                                  struct amdgpu_ring *ring, bool tmz,
 190                                  uint64_t *addr)
 191 {
 192         struct amdgpu_device *adev = ring->adev;
 193         struct amdgpu_job *job;
 194         unsigned num_dw, num_bytes;
 195         struct dma_fence *fence;
 196         uint64_t src_addr, dst_addr;
 197         void *cpu_addr;
 198         uint64_t flags;
 199         unsigned int i;
 200         int r;
 201
 202         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 203                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 204         BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
 205
 206         /* Map only what can't be accessed directly */
 207         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 208                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 209                         mm_cur->start;
 210                 return 0;
 211         }
 212
 213         *addr = adev->gmc.gart_start;
 214         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 215                 AMDGPU_GPU_PAGE_SIZE;
 216         *addr += mm_cur->start & ~PAGE_MASK;
 217
 218         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 219         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 220
 221         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 222                                      AMDGPU_IB_POOL_DELAYED, &job);
 223         if (r)
 224                 return r;
 225
 226         src_addr = num_dw * 4;
 227         src_addr += job->ibs[0].gpu_addr;
 228
 229         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 230         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 231         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 232                                 dst_addr, num_bytes, false);
 233
 234         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 235         WARN_ON(job->ibs[0].length_dw > num_dw);
 236
 237         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 238         if (tmz)
 239                 flags |= AMDGPU_PTE_TMZ;
 240
 241         cpu_addr = &job->ibs[0].ptr[num_dw];
 242
 243         if (mem->mem_type == TTM_PL_TT) {
 244                 dma_addr_t *dma_addr;
 245
 246                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 247                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 248                                     cpu_addr);
 249                 if (r)
 250                         goto error_free;
 251         } else {
 252                 dma_addr_t dma_address;
 253
 254                 dma_address = mm_cur->start;
 255                 dma_address += adev->vm_manager.vram_base_offset;
 256
 257                 for (i = 0; i < num_pages; ++i) {
 258                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 259                                             &dma_address, flags, cpu_addr);
 260                         if (r)
 261                                 goto error_free;
 262
 263                         dma_address += PAGE_SIZE;
 264                 }
 265         }
 266
 267         r = amdgpu_job_submit(job, &adev->mman.entity,
 268                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 269         if (r)
 270                 goto error_free;
 271
 272         dma_fence_put(fence);
 273
 274         return r;
 275
 276 error_free:
 277         amdgpu_job_free(job);
 278         return r;
 279 }
 280
 281 /**
 282  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 283  * @adev: amdgpu device
 284  * @src: buffer/address where to read from
 285  * @dst: buffer/address where to write to
 286  * @size: number of bytes to copy
 287  * @tmz: if a secure copy should be used
 288  * @resv: resv object to sync to
 289  * @f: Returns the last fence if multiple jobs are submitted.
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  */
 296 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 297                                const struct amdgpu_copy_mem *src,
 298                                const struct amdgpu_copy_mem *dst,
 299                                uint64_t size, bool tmz,
 300                                struct dma_resv *resv,
 301                                struct dma_fence **f)
 302 {
 303         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 304                                         AMDGPU_GPU_PAGE_SIZE);
 305
 306         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 307         struct amdgpu_res_cursor src_mm, dst_mm;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310
 311         if (!adev->mman.buffer_funcs_enabled) {
 312                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 313                 return -EINVAL;
 314         }
 315
 316         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 317         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 318
 319         mutex_lock(&adev->mman.gtt_window_lock);
 320         while (src_mm.remaining) {
 321                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 322                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 323                 struct dma_fence *next;
 324                 uint32_t cur_size;
 325                 uint64_t from, to;
 326
 327                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 328                  * begins at an offset, then adjust the size accordingly
 329                  */
 330                 cur_size = max(src_page_offset, dst_page_offset);
 331                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 332                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 333
 334                 /* Map src to window 0 and dst to window 1. */
 335                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 336                                           PFN_UP(cur_size + src_page_offset),
 337                                           0, ring, tmz, &from);
 338                 if (r)
 339                         goto error;
 340
 341                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 342                                           PFN_UP(cur_size + dst_page_offset),
 343                                           1, ring, tmz, &to);
 344                 if (r)
 345                         goto error;
 346
 347                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 348                                        resv, &next, false, true, tmz);
 349                 if (r)
 350                         goto error;
 351
 352                 dma_fence_put(fence);
 353                 fence = next;
 354
 355                 amdgpu_res_next(&src_mm, cur_size);
 356                 amdgpu_res_next(&dst_mm, cur_size);
 357         }
 358 error:
 359         mutex_unlock(&adev->mman.gtt_window_lock);
 360         if (f)
 361                 *f = dma_fence_get(fence);
 362         dma_fence_put(fence);
 363         return r;
 364 }
 365
 366 /*
 367  * amdgpu_move_blit - Copy an entire buffer to another buffer
 368  *
 369  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 370  * help move buffers to and from VRAM.
 371  */
 372 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 373                             bool evict,
 374                             struct ttm_resource *new_mem,
 375                             struct ttm_resource *old_mem)
 376 {
 377         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 378         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 379         struct amdgpu_copy_mem src, dst;
 380         struct dma_fence *fence = NULL;
 381         int r;
 382
 383         src.bo = bo;
 384         dst.bo = bo;
 385         src.mem = old_mem;
 386         dst.mem = new_mem;
 387         src.offset = 0;
 388         dst.offset = 0;
 389
 390         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 391                                        new_mem->num_pages << PAGE_SHIFT,
 392                                        amdgpu_bo_encrypted(abo),
 393                                        bo->base.resv, &fence);
 394         if (r)
 395                 goto error;
 396
 397         /* clear the space being freed */
 398         if (old_mem->mem_type == TTM_PL_VRAM &&
 399             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 400                 struct dma_fence *wipe_fence = NULL;
 401
 402                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 403                                        NULL, &wipe_fence);
 404                 if (r) {
 405                         goto error;
 406                 } else if (wipe_fence) {
 407                         dma_fence_put(fence);
 408                         fence = wipe_fence;
 409                 }
 410         }
 411
 412         /* Always block for VM page tables before committing the new location */
 413         if (bo->type == ttm_bo_type_kernel)
 414                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 415         else
 416                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 417         dma_fence_put(fence);
 418         return r;
 419
 420 error:
 421         if (fence)
 422                 dma_fence_wait(fence, false);
 423         dma_fence_put(fence);
 424         return r;
 425 }
 426
 427 /*
 428  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 429  *
 430  * Called by amdgpu_bo_move()
 431  */
 432 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 433                                struct ttm_resource *mem)
 434 {
 435         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 436         struct amdgpu_res_cursor cursor;
 437
 438         if (mem->mem_type == TTM_PL_SYSTEM ||
 439             mem->mem_type == TTM_PL_TT)
 440                 return true;
 441         if (mem->mem_type != TTM_PL_VRAM)
 442                 return false;
 443
 444         amdgpu_res_first(mem, 0, mem_size, &cursor);
 445
 446         /* ttm_resource_ioremap only supports contiguous memory */
 447         if (cursor.size != mem_size)
 448                 return false;
 449
 450         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 451 }
 452
 453 /*
 454  * amdgpu_bo_move - Move a buffer object to a new memory location
 455  *
 456  * Called by ttm_bo_handle_move_mem()
 457  */
 458 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 459                           struct ttm_operation_ctx *ctx,
 460                           struct ttm_resource *new_mem,
 461                           struct ttm_place *hop)
 462 {
 463         struct amdgpu_device *adev;
 464         struct amdgpu_bo *abo;
 465         struct ttm_resource *old_mem = bo->resource;
 466         int r;
 467
 468         if (new_mem->mem_type == TTM_PL_TT ||
 469             new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 470                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 471                 if (r)
 472                         return r;
 473         }
 474
 475         /* Can't move a pinned BO */
 476         abo = ttm_to_amdgpu_bo(bo);
 477         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 478                 return -EINVAL;
 479
 480         adev = amdgpu_ttm_adev(bo->bdev);
 481
 482         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 483                 ttm_bo_move_null(bo, new_mem);
 484                 goto out;
 485         }
 486         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 487             (new_mem->mem_type == TTM_PL_TT ||
 488              new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 489                 ttm_bo_move_null(bo, new_mem);
 490                 goto out;
 491         }
 492         if ((old_mem->mem_type == TTM_PL_TT ||
 493              old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 494             new_mem->mem_type == TTM_PL_SYSTEM) {
 495                 r = ttm_bo_wait_ctx(bo, ctx);
 496                 if (r)
 497                         return r;
 498
 499                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 500                 ttm_resource_free(bo, &bo->resource);
 501                 ttm_bo_assign_mem(bo, new_mem);
 502                 goto out;
 503         }
 504
 505         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 506             old_mem->mem_type == AMDGPU_PL_GWS ||
 507             old_mem->mem_type == AMDGPU_PL_OA ||
 508             new_mem->mem_type == AMDGPU_PL_GDS ||
 509             new_mem->mem_type == AMDGPU_PL_GWS ||
 510             new_mem->mem_type == AMDGPU_PL_OA) {
 511                 /* Nothing to save here */
 512                 ttm_bo_move_null(bo, new_mem);
 513                 goto out;
 514         }
 515
 516         if (adev->mman.buffer_funcs_enabled) {
 517                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 518                       new_mem->mem_type == TTM_PL_VRAM) ||
 519                      (old_mem->mem_type == TTM_PL_VRAM &&
 520                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 521                         hop->fpfn = 0;
 522                         hop->lpfn = 0;
 523                         hop->mem_type = TTM_PL_TT;
 524                         hop->flags = 0;
 525                         return -EMULTIHOP;
 526                 }
 527
 528                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 529         } else {
 530                 r = -ENODEV;
 531         }
 532
 533         if (r) {
 534                 /* Check that all memory is CPU accessible */
 535                 if (!amdgpu_mem_visible(adev, old_mem) ||
 536                     !amdgpu_mem_visible(adev, new_mem)) {
 537                         pr_err("Move buffer fallback to memcpy unavailable\n");
 538                         return r;
 539                 }
 540
 541                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 542                 if (r)
 543                         return r;
 544         }
 545
 546         if (bo->type == ttm_bo_type_device &&
 547             new_mem->mem_type == TTM_PL_VRAM &&
 548             old_mem->mem_type != TTM_PL_VRAM) {
 549                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 550                  * accesses the BO after it's moved.
 551                  */
 552                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 553         }
 554
 555 out:
 556         /* update statistics */
 557         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 558         amdgpu_bo_move_notify(bo, evict, new_mem);
 559         return 0;
 560 }
 561
 562 /*
 563  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 564  *
 565  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 566  */
 567 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 568                                      struct ttm_resource *mem)
 569 {
 570         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 571         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 572
 573         switch (mem->mem_type) {
 574         case TTM_PL_SYSTEM:
 575                 /* system memory */
 576                 return 0;
 577         case TTM_PL_TT:
 578         case AMDGPU_PL_PREEMPT:
 579                 break;
 580         case TTM_PL_VRAM:
 581                 mem->bus.offset = mem->start << PAGE_SHIFT;
 582                 /* check if it's visible */
 583                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 584                         return -EINVAL;
 585
 586                 if (adev->mman.aper_base_kaddr &&
 587                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 588                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 589                                         mem->bus.offset;
 590
 591                 mem->bus.offset += adev->gmc.aper_base;
 592                 mem->bus.is_iomem = true;
 593                 if (adev->gmc.xgmi.connected_to_cpu)
 594                         mem->bus.caching = ttm_cached;
 595                 else
 596                         mem->bus.caching = ttm_write_combined;
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         return 0;
 602 }
 603
 604 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 605                                            unsigned long page_offset)
 606 {
 607         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 608         struct amdgpu_res_cursor cursor;
 609
 610         amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 611                          &cursor);
 612         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 613 }
 614
 615 /**
 616  * amdgpu_ttm_domain_start - Returns GPU start address
 617  * @adev: amdgpu device object
 618  * @type: type of the memory
 619  *
 620  * Returns:
 621  * GPU start address of a memory domain
 622  */
 623
 624 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 625 {
 626         switch (type) {
 627         case TTM_PL_TT:
 628                 return adev->gmc.gart_start;
 629         case TTM_PL_VRAM:
 630                 return adev->gmc.vram_start;
 631         }
 632
 633         return 0;
 634 }
 635
 636 /*
 637  * TTM backend functions.
 638  */
 639 struct amdgpu_ttm_tt {
 640         struct ttm_tt   ttm;
 641         struct drm_gem_object   *gobj;
 642         u64                     offset;
 643         uint64_t                userptr;
 644         struct task_struct      *usertask;
 645         uint32_t                userflags;
 646         bool                    bound;
 647 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 648         struct hmm_range        *range;
 649 #endif
 650 };
 651
 652 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 653 /*
 654  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 655  * memory and start HMM tracking CPU page table update
 656  *
 657  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 658  * once afterwards to stop HMM tracking
 659  */
 660 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 661 {
 662         struct ttm_tt *ttm = bo->tbo.ttm;
 663         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 664         unsigned long start = gtt->userptr;
 665         struct vm_area_struct *vma;
 666         struct mm_struct *mm;
 667         bool readonly;
 668         int r = 0;
 669
 670         mm = bo->notifier.mm;
 671         if (unlikely(!mm)) {
 672                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 673                 return -EFAULT;
 674         }
 675
 676         /* Another get_user_pages is running at the same time?? */
 677         if (WARN_ON(gtt->range))
 678                 return -EFAULT;
 679
 680         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 681                 return -ESRCH;
 682
 683         mmap_read_lock(mm);
 684         vma = vma_lookup(mm, start);
 685         if (unlikely(!vma)) {
 686                 r = -EFAULT;
 687                 goto out_unlock;
 688         }
 689         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 690                 vma->vm_file)) {
 691                 r = -EPERM;
 692                 goto out_unlock;
 693         }
 694
 695         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 696         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 697                                        ttm->num_pages, &gtt->range, readonly,
 698                                        true);
 699 out_unlock:
 700         mmap_read_unlock(mm);
 701         mmput(mm);
 702
 703         return r;
 704 }
 705
 706 /*
 707  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 708  * Check if the pages backing this ttm range have been invalidated
 709  *
 710  * Returns: true if pages are still valid
 711  */
 712 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 713 {
 714         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 715         bool r = false;
 716
 717         if (!gtt || !gtt->userptr)
 718                 return false;
 719
 720         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 721                 gtt->userptr, ttm->num_pages);
 722
 723         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 724                 "No user pages to check\n");
 725
 726         if (gtt->range) {
 727                 /*
 728                  * FIXME: Must always hold notifier_lock for this, and must
 729                  * not ignore the return code.
 730                  */
 731                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 732                 gtt->range = NULL;
 733         }
 734
 735         return !r;
 736 }
 737 #endif
 738
 739 /*
 740  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 741  *
 742  * Called by amdgpu_cs_list_validate(). This creates the page list
 743  * that backs user memory and will ultimately be mapped into the device
 744  * address space.
 745  */
 746 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 747 {
 748         unsigned long i;
 749
 750         for (i = 0; i < ttm->num_pages; ++i)
 751                 ttm->pages[i] = pages ? pages[i] : NULL;
 752 }
 753
 754 /*
 755  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 756  *
 757  * Called by amdgpu_ttm_backend_bind()
 758  **/
 759 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 760                                      struct ttm_tt *ttm)
 761 {
 762         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 763         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 764         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 765         enum dma_data_direction direction = write ?
 766                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 767         int r;
 768
 769         /* Allocate an SG array and squash pages into it */
 770         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 771                                       (u64)ttm->num_pages << PAGE_SHIFT,
 772                                       GFP_KERNEL);
 773         if (r)
 774                 goto release_sg;
 775
 776         /* Map SG to device */
 777         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 778         if (r)
 779                 goto release_sg;
 780
 781         /* convert SG to linear array of pages and dma addresses */
 782         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 783                                        ttm->num_pages);
 784
 785         return 0;
 786
 787 release_sg:
 788         kfree(ttm->sg);
 789         ttm->sg = NULL;
 790         return r;
 791 }
 792
 793 /*
 794  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 795  */
 796 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 797                                         struct ttm_tt *ttm)
 798 {
 799         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 800         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 801         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 802         enum dma_data_direction direction = write ?
 803                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 804
 805         /* double check that we don't free the table twice */
 806         if (!ttm->sg || !ttm->sg->sgl)
 807                 return;
 808
 809         /* unmap the pages mapped to the device */
 810         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 811         sg_free_table(ttm->sg);
 812
 813 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 814         if (gtt->range) {
 815                 unsigned long i;
 816
 817                 for (i = 0; i < ttm->num_pages; i++) {
 818                         if (ttm->pages[i] !=
 819                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 820                                 break;
 821                 }
 822
 823                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 824         }
 825 #endif
 826 }
 827
 828 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 829                                 struct ttm_buffer_object *tbo,
 830                                 uint64_t flags)
 831 {
 832         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 833         struct ttm_tt *ttm = tbo->ttm;
 834         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 835         int r;
 836
 837         if (amdgpu_bo_encrypted(abo))
 838                 flags |= AMDGPU_PTE_TMZ;
 839
 840         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 841                 uint64_t page_idx = 1;
 842
 843                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 844                                 gtt->ttm.dma_address, flags);
 845                 if (r)
 846                         goto gart_bind_fail;
 847
 848                 /* The memory type of the first page defaults to UC. Now
 849                  * modify the memory type to NC from the second page of
 850                  * the BO onward.
 851                  */
 852                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 853                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 854
 855                 r = amdgpu_gart_bind(adev,
 856                                 gtt->offset + (page_idx << PAGE_SHIFT),
 857                                 ttm->num_pages - page_idx,
 858                                 &(gtt->ttm.dma_address[page_idx]), flags);
 859         } else {
 860                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 861                                      gtt->ttm.dma_address, flags);
 862         }
 863
 864 gart_bind_fail:
 865         if (r)
 866                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 867                           ttm->num_pages, gtt->offset);
 868
 869         return r;
 870 }
 871
 872 /*
 873  * amdgpu_ttm_backend_bind - Bind GTT memory
 874  *
 875  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 876  * This handles binding GTT memory to the device address space.
 877  */
 878 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 879                                    struct ttm_tt *ttm,
 880                                    struct ttm_resource *bo_mem)
 881 {
 882         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 883         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 884         uint64_t flags;
 885         int r = 0;
 886
 887         if (!bo_mem)
 888                 return -EINVAL;
 889
 890         if (gtt->bound)
 891                 return 0;
 892
 893         if (gtt->userptr) {
 894                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 895                 if (r) {
 896                         DRM_ERROR("failed to pin userptr\n");
 897                         return r;
 898                 }
 899         } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
 900                 if (!ttm->sg) {
 901                         struct dma_buf_attachment *attach;
 902                         struct sg_table *sgt;
 903
 904                         attach = gtt->gobj->import_attach;
 905                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 906                         if (IS_ERR(sgt))
 907                                 return PTR_ERR(sgt);
 908
 909                         ttm->sg = sgt;
 910                 }
 911
 912                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 913                                                ttm->num_pages);
 914         }
 915
 916         if (!ttm->num_pages) {
 917                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 918                      ttm->num_pages, bo_mem, ttm);
 919         }
 920
 921         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 922             bo_mem->mem_type == AMDGPU_PL_GWS ||
 923             bo_mem->mem_type == AMDGPU_PL_OA)
 924                 return -EINVAL;
 925
 926         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 927                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 928                 return 0;
 929         }
 930
 931         /* compute PTE flags relevant to this BO memory */
 932         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 933
 934         /* bind pages into GART page tables */
 935         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 936         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 937                 gtt->ttm.dma_address, flags);
 938
 939         if (r)
 940                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 941                           ttm->num_pages, gtt->offset);
 942         gtt->bound = true;
 943         return r;
 944 }
 945
 946 /*
 947  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 948  * through AGP or GART aperture.
 949  *
 950  * If bo is accessible through AGP aperture, then use AGP aperture
 951  * to access bo; otherwise allocate logical space in GART aperture
 952  * and map bo to GART aperture.
 953  */
 954 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 955 {
 956         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 957         struct ttm_operation_ctx ctx = { false, false };
 958         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 959         struct ttm_placement placement;
 960         struct ttm_place placements;
 961         struct ttm_resource *tmp;
 962         uint64_t addr, flags;
 963         int r;
 964
 965         if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 966                 return 0;
 967
 968         addr = amdgpu_gmc_agp_addr(bo);
 969         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 970                 bo->resource->start = addr >> PAGE_SHIFT;
 971                 return 0;
 972         }
 973
 974         /* allocate GART space */
 975         placement.num_placement = 1;
 976         placement.placement = &placements;
 977         placement.num_busy_placement = 1;
 978         placement.busy_placement = &placements;
 979         placements.fpfn = 0;
 980         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 981         placements.mem_type = TTM_PL_TT;
 982         placements.flags = bo->resource->placement;
 983
 984         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 985         if (unlikely(r))
 986                 return r;
 987
 988         /* compute PTE flags for this buffer object */
 989         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 990
 991         /* Bind pages */
 992         gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 993         r = amdgpu_ttm_gart_bind(adev, bo, flags);
 994         if (unlikely(r)) {
 995                 ttm_resource_free(bo, &tmp);
 996                 return r;
 997         }
 998
 999         amdgpu_gart_invalidate_tlb(adev);
1000         ttm_resource_free(bo, &bo->resource);
1001         ttm_bo_assign_mem(bo, tmp);
1002
1003         return 0;
1004 }
1005
1006 /*
1007  * amdgpu_ttm_recover_gart - Rebind GTT pages
1008  *
1009  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1010  * rebind GTT pages during a GPU reset.
1011  */
1012 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1013 {
1014         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1015         uint64_t flags;
1016         int r;
1017
1018         if (!tbo->ttm)
1019                 return 0;
1020
1021         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1022         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1023
1024         return r;
1025 }
1026
1027 /*
1028  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1029  *
1030  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1031  * ttm_tt_destroy().
1032  */
1033 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1034                                       struct ttm_tt *ttm)
1035 {
1036         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1037         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1038         int r;
1039
1040         /* if the pages have userptr pinning then clear that first */
1041         if (gtt->userptr) {
1042                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1043         } else if (ttm->sg && gtt->gobj->import_attach) {
1044                 struct dma_buf_attachment *attach;
1045
1046                 attach = gtt->gobj->import_attach;
1047                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1048                 ttm->sg = NULL;
1049         }
1050
1051         if (!gtt->bound)
1052                 return;
1053
1054         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1055                 return;
1056
1057         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1058         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1059         if (r)
1060                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1061                           gtt->ttm.num_pages, gtt->offset);
1062         gtt->bound = false;
1063 }
1064
1065 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1066                                        struct ttm_tt *ttm)
1067 {
1068         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1069
1070         amdgpu_ttm_backend_unbind(bdev, ttm);
1071         ttm_tt_destroy_common(bdev, ttm);
1072         if (gtt->usertask)
1073                 put_task_struct(gtt->usertask);
1074
1075         ttm_tt_fini(&gtt->ttm);
1076         kfree(gtt);
1077 }
1078
1079 /**
1080  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1081  *
1082  * @bo: The buffer object to create a GTT ttm_tt object around
1083  * @page_flags: Page flags to be added to the ttm_tt object
1084  *
1085  * Called by ttm_tt_create().
1086  */
1087 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1088                                            uint32_t page_flags)
1089 {
1090         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1091         struct amdgpu_ttm_tt *gtt;
1092         enum ttm_caching caching;
1093
1094         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1095         if (gtt == NULL) {
1096                 return NULL;
1097         }
1098         gtt->gobj = &bo->base;
1099
1100         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1101                 caching = ttm_write_combined;
1102         else
1103                 caching = ttm_cached;
1104
1105         /* allocate space for the uninitialized page entries */
1106         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1107                 kfree(gtt);
1108                 return NULL;
1109         }
1110         return &gtt->ttm;
1111 }
1112
1113 /*
1114  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1115  *
1116  * Map the pages of a ttm_tt object to an address space visible
1117  * to the underlying device.
1118  */
1119 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1120                                   struct ttm_tt *ttm,
1121                                   struct ttm_operation_ctx *ctx)
1122 {
1123         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1124         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1125
1126         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1127         if (gtt && gtt->userptr) {
1128                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1129                 if (!ttm->sg)
1130                         return -ENOMEM;
1131                 return 0;
1132         }
1133
1134         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1135                 return 0;
1136
1137         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1138 }
1139
1140 /*
1141  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1142  *
1143  * Unmaps pages of a ttm_tt object from the device address space and
1144  * unpopulates the page array backing it.
1145  */
1146 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1147                                      struct ttm_tt *ttm)
1148 {
1149         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1150         struct amdgpu_device *adev;
1151
1152         if (gtt && gtt->userptr) {
1153                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1154                 kfree(ttm->sg);
1155                 ttm->sg = NULL;
1156                 return;
1157         }
1158
1159         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1160                 return;
1161
1162         adev = amdgpu_ttm_adev(bdev);
1163         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1164 }
1165
1166 /**
1167  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1168  * task
1169  *
1170  * @bo: The ttm_buffer_object to bind this userptr to
1171  * @addr:  The address in the current tasks VM space to use
1172  * @flags: Requirements of userptr object.
1173  *
1174  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1175  * to current task
1176  */
1177 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1178                               uint64_t addr, uint32_t flags)
1179 {
1180         struct amdgpu_ttm_tt *gtt;
1181
1182         if (!bo->ttm) {
1183                 /* TODO: We want a separate TTM object type for userptrs */
1184                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1185                 if (bo->ttm == NULL)
1186                         return -ENOMEM;
1187         }
1188
1189         /* Set TTM_PAGE_FLAG_SG before populate but after create. */
1190         bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
1191
1192         gtt = (void *)bo->ttm;
1193         gtt->userptr = addr;
1194         gtt->userflags = flags;
1195
1196         if (gtt->usertask)
1197                 put_task_struct(gtt->usertask);
1198         gtt->usertask = current->group_leader;
1199         get_task_struct(gtt->usertask);
1200
1201         return 0;
1202 }
1203
1204 /*
1205  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1206  */
1207 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1208 {
1209         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1210
1211         if (gtt == NULL)
1212                 return NULL;
1213
1214         if (gtt->usertask == NULL)
1215                 return NULL;
1216
1217         return gtt->usertask->mm;
1218 }
1219
1220 /*
1221  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1222  * address range for the current task.
1223  *
1224  */
1225 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1226                                   unsigned long end)
1227 {
1228         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1229         unsigned long size;
1230
1231         if (gtt == NULL || !gtt->userptr)
1232                 return false;
1233
1234         /* Return false if no part of the ttm_tt object lies within
1235          * the range
1236          */
1237         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1238         if (gtt->userptr > end || gtt->userptr + size <= start)
1239                 return false;
1240
1241         return true;
1242 }
1243
1244 /*
1245  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1246  */
1247 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1248 {
1249         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250
1251         if (gtt == NULL || !gtt->userptr)
1252                 return false;
1253
1254         return true;
1255 }
1256
1257 /*
1258  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1259  */
1260 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1261 {
1262         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1263
1264         if (gtt == NULL)
1265                 return false;
1266
1267         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1268 }
1269
1270 /**
1271  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1272  *
1273  * @ttm: The ttm_tt object to compute the flags for
1274  * @mem: The memory registry backing this ttm_tt object
1275  *
1276  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1277  */
1278 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1279 {
1280         uint64_t flags = 0;
1281
1282         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1283                 flags |= AMDGPU_PTE_VALID;
1284
1285         if (mem && (mem->mem_type == TTM_PL_TT ||
1286                     mem->mem_type == AMDGPU_PL_PREEMPT)) {
1287                 flags |= AMDGPU_PTE_SYSTEM;
1288
1289                 if (ttm->caching == ttm_cached)
1290                         flags |= AMDGPU_PTE_SNOOPED;
1291         }
1292
1293         if (mem && mem->mem_type == TTM_PL_VRAM &&
1294                         mem->bus.caching == ttm_cached)
1295                 flags |= AMDGPU_PTE_SNOOPED;
1296
1297         return flags;
1298 }
1299
1300 /**
1301  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1302  *
1303  * @adev: amdgpu_device pointer
1304  * @ttm: The ttm_tt object to compute the flags for
1305  * @mem: The memory registry backing this ttm_tt object
1306  *
1307  * Figure out the flags to use for a VM PTE (Page Table Entry).
1308  */
1309 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1310                                  struct ttm_resource *mem)
1311 {
1312         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1313
1314         flags |= adev->gart.gart_pte_flags;
1315         flags |= AMDGPU_PTE_READABLE;
1316
1317         if (!amdgpu_ttm_tt_is_readonly(ttm))
1318                 flags |= AMDGPU_PTE_WRITEABLE;
1319
1320         return flags;
1321 }
1322
1323 /*
1324  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1325  * object.
1326  *
1327  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1328  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1329  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1330  * used to clean out a memory space.
1331  */
1332 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1333                                             const struct ttm_place *place)
1334 {
1335         unsigned long num_pages = bo->resource->num_pages;
1336         struct amdgpu_res_cursor cursor;
1337         struct dma_resv_list *flist;
1338         struct dma_fence *f;
1339         int i;
1340
1341         /* Swapout? */
1342         if (bo->resource->mem_type == TTM_PL_SYSTEM)
1343                 return true;
1344
1345         if (bo->type == ttm_bo_type_kernel &&
1346             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1347                 return false;
1348
1349         /* If bo is a KFD BO, check if the bo belongs to the current process.
1350          * If true, then return false as any KFD process needs all its BOs to
1351          * be resident to run successfully
1352          */
1353         flist = dma_resv_shared_list(bo->base.resv);
1354         if (flist) {
1355                 for (i = 0; i < flist->shared_count; ++i) {
1356                         f = rcu_dereference_protected(flist->shared[i],
1357                                 dma_resv_held(bo->base.resv));
1358                         if (amdkfd_fence_check_mm(f, current->mm))
1359                                 return false;
1360                 }
1361         }
1362
1363         switch (bo->resource->mem_type) {
1364         case AMDGPU_PL_PREEMPT:
1365                 /* Preemptible BOs don't own system resources managed by the
1366                  * driver (pages, VRAM, GART space). They point to resources
1367                  * owned by someone else (e.g. pageable memory in user mode
1368                  * or a DMABuf). They are used in a preemptible context so we
1369                  * can guarantee no deadlocks and good QoS in case of MMU
1370                  * notifiers or DMABuf move notifiers from the resource owner.
1371                  */
1372                 return false;
1373         case TTM_PL_TT:
1374                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1375                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1376                         return false;
1377                 return true;
1378
1379         case TTM_PL_VRAM:
1380                 /* Check each drm MM node individually */
1381                 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
1382                                  &cursor);
1383                 while (cursor.remaining) {
1384                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1385                             && !(place->lpfn &&
1386                                  place->lpfn <= PFN_DOWN(cursor.start)))
1387                                 return true;
1388
1389                         amdgpu_res_next(&cursor, cursor.size);
1390                 }
1391                 return false;
1392
1393         default:
1394                 break;
1395         }
1396
1397         return ttm_bo_eviction_valuable(bo, place);
1398 }
1399
1400 /**
1401  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1402  *
1403  * @bo:  The buffer object to read/write
1404  * @offset:  Offset into buffer object
1405  * @buf:  Secondary buffer to write/read from
1406  * @len: Length in bytes of access
1407  * @write:  true if writing
1408  *
1409  * This is used to access VRAM that backs a buffer object via MMIO
1410  * access for debugging purposes.
1411  */
1412 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1413                                     unsigned long offset, void *buf, int len,
1414                                     int write)
1415 {
1416         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1417         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1418         struct amdgpu_res_cursor cursor;
1419         unsigned long flags;
1420         uint32_t value = 0;
1421         int ret = 0;
1422
1423         if (bo->resource->mem_type != TTM_PL_VRAM)
1424                 return -EIO;
1425
1426         amdgpu_res_first(bo->resource, offset, len, &cursor);
1427         while (cursor.remaining) {
1428                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1429                 uint64_t bytes = 4 - (cursor.start & 3);
1430                 uint32_t shift = (cursor.start & 3) * 8;
1431                 uint32_t mask = 0xffffffff << shift;
1432
1433                 if (cursor.size < bytes) {
1434                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1435                         bytes = cursor.size;
1436                 }
1437
1438                 if (mask != 0xffffffff) {
1439                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1440                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1441                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1442                         value = RREG32_NO_KIQ(mmMM_DATA);
1443                         if (write) {
1444                                 value &= ~mask;
1445                                 value |= (*(uint32_t *)buf << shift) & mask;
1446                                 WREG32_NO_KIQ(mmMM_DATA, value);
1447                         }
1448                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1449                         if (!write) {
1450                                 value = (value & mask) >> shift;
1451                                 memcpy(buf, &value, bytes);
1452                         }
1453                 } else {
1454                         bytes = cursor.size & ~0x3ULL;
1455                         amdgpu_device_vram_access(adev, cursor.start,
1456                                                   (uint32_t *)buf, bytes,
1457                                                   write);
1458                 }
1459
1460                 ret += bytes;
1461                 buf = (uint8_t *)buf + bytes;
1462                 amdgpu_res_next(&cursor, bytes);
1463         }
1464
1465         return ret;
1466 }
1467
1468 static void
1469 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1470 {
1471         amdgpu_bo_move_notify(bo, false, NULL);
1472 }
1473
1474 static struct ttm_device_funcs amdgpu_bo_driver = {
1475         .ttm_tt_create = &amdgpu_ttm_tt_create,
1476         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1477         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1478         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1479         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1480         .evict_flags = &amdgpu_evict_flags,
1481         .move = &amdgpu_bo_move,
1482         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1483         .release_notify = &amdgpu_bo_release_notify,
1484         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1485         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1486         .access_memory = &amdgpu_ttm_access_memory,
1487         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1488 };
1489
1490 /*
1491  * Firmware Reservation functions
1492  */
1493 /**
1494  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1495  *
1496  * @adev: amdgpu_device pointer
1497  *
1498  * free fw reserved vram if it has been reserved.
1499  */
1500 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1501 {
1502         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1503                 NULL, &adev->mman.fw_vram_usage_va);
1504 }
1505
1506 /**
1507  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1508  *
1509  * @adev: amdgpu_device pointer
1510  *
1511  * create bo vram reservation from fw.
1512  */
1513 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1514 {
1515         uint64_t vram_size = adev->gmc.visible_vram_size;
1516
1517         adev->mman.fw_vram_usage_va = NULL;
1518         adev->mman.fw_vram_usage_reserved_bo = NULL;
1519
1520         if (adev->mman.fw_vram_usage_size == 0 ||
1521             adev->mman.fw_vram_usage_size > vram_size)
1522                 return 0;
1523
1524         return amdgpu_bo_create_kernel_at(adev,
1525                                           adev->mman.fw_vram_usage_start_offset,
1526                                           adev->mman.fw_vram_usage_size,
1527                                           AMDGPU_GEM_DOMAIN_VRAM,
1528                                           &adev->mman.fw_vram_usage_reserved_bo,
1529                                           &adev->mman.fw_vram_usage_va);
1530 }
1531
1532 /*
1533  * Memoy training reservation functions
1534  */
1535
1536 /**
1537  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1538  *
1539  * @adev: amdgpu_device pointer
1540  *
1541  * free memory training reserved vram if it has been reserved.
1542  */
1543 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1544 {
1545         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1546
1547         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1548         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1549         ctx->c2p_bo = NULL;
1550
1551         return 0;
1552 }
1553
1554 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1555 {
1556         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1557
1558         memset(ctx, 0, sizeof(*ctx));
1559
1560         ctx->c2p_train_data_offset =
1561                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1562         ctx->p2c_train_data_offset =
1563                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1564         ctx->train_data_size =
1565                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1566
1567         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1568                         ctx->train_data_size,
1569                         ctx->p2c_train_data_offset,
1570                         ctx->c2p_train_data_offset);
1571 }
1572
1573 /*
1574  * reserve TMR memory at the top of VRAM which holds
1575  * IP Discovery data and is protected by PSP.
1576  */
1577 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1578 {
1579         int ret;
1580         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1581         bool mem_train_support = false;
1582
1583         if (!amdgpu_sriov_vf(adev)) {
1584                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1585                         mem_train_support = true;
1586                 else
1587                         DRM_DEBUG("memory training does not support!\n");
1588         }
1589
1590         /*
1591          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1592          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1593          *
1594          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1595          * discovery data and G6 memory training data respectively
1596          */
1597         adev->mman.discovery_tmr_size =
1598                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1599         if (!adev->mman.discovery_tmr_size)
1600                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1601
1602         if (mem_train_support) {
1603                 /* reserve vram for mem train according to TMR location */
1604                 amdgpu_ttm_training_data_block_init(adev);
1605                 ret = amdgpu_bo_create_kernel_at(adev,
1606                                          ctx->c2p_train_data_offset,
1607                                          ctx->train_data_size,
1608                                          AMDGPU_GEM_DOMAIN_VRAM,
1609                                          &ctx->c2p_bo,
1610                                          NULL);
1611                 if (ret) {
1612                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1613                         amdgpu_ttm_training_reserve_vram_fini(adev);
1614                         return ret;
1615                 }
1616                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1617         }
1618
1619         ret = amdgpu_bo_create_kernel_at(adev,
1620                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1621                                 adev->mman.discovery_tmr_size,
1622                                 AMDGPU_GEM_DOMAIN_VRAM,
1623                                 &adev->mman.discovery_memory,
1624                                 NULL);
1625         if (ret) {
1626                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1627                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1628                 return ret;
1629         }
1630
1631         return 0;
1632 }
1633
1634 /*
1635  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1636  * gtt/vram related fields.
1637  *
1638  * This initializes all of the memory space pools that the TTM layer
1639  * will need such as the GTT space (system memory mapped to the device),
1640  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1641  * can be mapped per VMID.
1642  */
1643 int amdgpu_ttm_init(struct amdgpu_device *adev)
1644 {
1645         uint64_t gtt_size;
1646         int r;
1647         u64 vis_vram_limit;
1648
1649         mutex_init(&adev->mman.gtt_window_lock);
1650
1651         /* No others user of address space so set it to 0 */
1652         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1653                                adev_to_drm(adev)->anon_inode->i_mapping,
1654                                adev_to_drm(adev)->vma_offset_manager,
1655                                adev->need_swiotlb,
1656                                dma_addressing_limited(adev->dev));
1657         if (r) {
1658                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1659                 return r;
1660         }
1661         adev->mman.initialized = true;
1662
1663         /* Initialize VRAM pool with all of VRAM divided into pages */
1664         r = amdgpu_vram_mgr_init(adev);
1665         if (r) {
1666                 DRM_ERROR("Failed initializing VRAM heap.\n");
1667                 return r;
1668         }
1669
1670         /* Reduce size of CPU-visible VRAM if requested */
1671         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1672         if (amdgpu_vis_vram_limit > 0 &&
1673             vis_vram_limit <= adev->gmc.visible_vram_size)
1674                 adev->gmc.visible_vram_size = vis_vram_limit;
1675
1676         /* Change the size here instead of the init above so only lpfn is affected */
1677         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1678 #ifdef CONFIG_64BIT
1679 #ifdef CONFIG_X86
1680         if (adev->gmc.xgmi.connected_to_cpu)
1681                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1682                                 adev->gmc.visible_vram_size);
1683
1684         else
1685 #endif
1686                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1687                                 adev->gmc.visible_vram_size);
1688 #endif
1689
1690         /*
1691          *The reserved vram for firmware must be pinned to the specified
1692          *place on the VRAM, so reserve it early.
1693          */
1694         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1695         if (r) {
1696                 return r;
1697         }
1698
1699         /*
1700          * only NAVI10 and onwards ASIC support for IP discovery.
1701          * If IP discovery enabled, a block of memory should be
1702          * reserved for IP discovey.
1703          */
1704         if (adev->mman.discovery_bin) {
1705                 r = amdgpu_ttm_reserve_tmr(adev);
1706                 if (r)
1707                         return r;
1708         }
1709
1710         /* allocate memory as required for VGA
1711          * This is used for VGA emulation and pre-OS scanout buffers to
1712          * avoid display artifacts while transitioning between pre-OS
1713          * and driver.  */
1714         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1715                                        AMDGPU_GEM_DOMAIN_VRAM,
1716                                        &adev->mman.stolen_vga_memory,
1717                                        NULL);
1718         if (r)
1719                 return r;
1720         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1721                                        adev->mman.stolen_extended_size,
1722                                        AMDGPU_GEM_DOMAIN_VRAM,
1723                                        &adev->mman.stolen_extended_memory,
1724                                        NULL);
1725         if (r)
1726                 return r;
1727         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1728                                        adev->mman.stolen_reserved_size,
1729                                        AMDGPU_GEM_DOMAIN_VRAM,
1730                                        &adev->mman.stolen_reserved_memory,
1731                                        NULL);
1732         if (r)
1733                 return r;
1734
1735         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1736                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1737
1738         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1739          * or whatever the user passed on module init */
1740         if (amdgpu_gtt_size == -1) {
1741                 struct sysinfo si;
1742
1743                 si_meminfo(&si);
1744                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1745                                adev->gmc.mc_vram_size),
1746                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1747         }
1748         else
1749                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1750
1751         /* Initialize GTT memory pool */
1752         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1753         if (r) {
1754                 DRM_ERROR("Failed initializing GTT heap.\n");
1755                 return r;
1756         }
1757         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1758                  (unsigned)(gtt_size / (1024 * 1024)));
1759
1760         /* Initialize preemptible memory pool */
1761         r = amdgpu_preempt_mgr_init(adev);
1762         if (r) {
1763                 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1764                 return r;
1765         }
1766
1767         /* Initialize various on-chip memory pools */
1768         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1769         if (r) {
1770                 DRM_ERROR("Failed initializing GDS heap.\n");
1771                 return r;
1772         }
1773
1774         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1775         if (r) {
1776                 DRM_ERROR("Failed initializing gws heap.\n");
1777                 return r;
1778         }
1779
1780         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1781         if (r) {
1782                 DRM_ERROR("Failed initializing oa heap.\n");
1783                 return r;
1784         }
1785
1786         return 0;
1787 }
1788
1789 /*
1790  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1791  */
1792 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1793 {
1794         if (!adev->mman.initialized)
1795                 return;
1796
1797         amdgpu_ttm_training_reserve_vram_fini(adev);
1798         /* return the stolen vga memory back to VRAM */
1799         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1800         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1801         /* return the IP Discovery TMR memory back to VRAM */
1802         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1803         if (adev->mman.stolen_reserved_size)
1804                 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1805                                       NULL, NULL);
1806         amdgpu_ttm_fw_reserve_vram_fini(adev);
1807
1808         amdgpu_vram_mgr_fini(adev);
1809         amdgpu_gtt_mgr_fini(adev);
1810         amdgpu_preempt_mgr_fini(adev);
1811         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1812         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1813         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1814         ttm_device_fini(&adev->mman.bdev);
1815         adev->mman.initialized = false;
1816         DRM_INFO("amdgpu: ttm finalized\n");
1817 }
1818
1819 /**
1820  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1821  *
1822  * @adev: amdgpu_device pointer
1823  * @enable: true when we can use buffer functions.
1824  *
1825  * Enable/disable use of buffer functions during suspend/resume. This should
1826  * only be called at bootup or when userspace isn't running.
1827  */
1828 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1829 {
1830         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1831         uint64_t size;
1832         int r;
1833
1834         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1835             adev->mman.buffer_funcs_enabled == enable)
1836                 return;
1837
1838         if (enable) {
1839                 struct amdgpu_ring *ring;
1840                 struct drm_gpu_scheduler *sched;
1841
1842                 ring = adev->mman.buffer_funcs_ring;
1843                 sched = &ring->sched;
1844                 r = drm_sched_entity_init(&adev->mman.entity,
1845                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1846                                           1, NULL);
1847                 if (r) {
1848                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1849                                   r);
1850                         return;
1851                 }
1852         } else {
1853                 drm_sched_entity_destroy(&adev->mman.entity);
1854                 dma_fence_put(man->move);
1855                 man->move = NULL;
1856         }
1857
1858         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1859         if (enable)
1860                 size = adev->gmc.real_vram_size;
1861         else
1862                 size = adev->gmc.visible_vram_size;
1863         man->size = size >> PAGE_SHIFT;
1864         adev->mman.buffer_funcs_enabled = enable;
1865 }
1866
1867 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1868                        uint64_t dst_offset, uint32_t byte_count,
1869                        struct dma_resv *resv,
1870                        struct dma_fence **fence, bool direct_submit,
1871                        bool vm_needs_flush, bool tmz)
1872 {
1873         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1874                 AMDGPU_IB_POOL_DELAYED;
1875         struct amdgpu_device *adev = ring->adev;
1876         struct amdgpu_job *job;
1877
1878         uint32_t max_bytes;
1879         unsigned num_loops, num_dw;
1880         unsigned i;
1881         int r;
1882
1883         if (direct_submit && !ring->sched.ready) {
1884                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1885                 return -EINVAL;
1886         }
1887
1888         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1889         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1890         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1891
1892         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1893         if (r)
1894                 return r;
1895
1896         if (vm_needs_flush) {
1897                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1898                                         adev->gmc.pdb0_bo : adev->gart.bo);
1899                 job->vm_needs_flush = true;
1900         }
1901         if (resv) {
1902                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1903                                      AMDGPU_SYNC_ALWAYS,
1904                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1905                 if (r) {
1906                         DRM_ERROR("sync failed (%d).\n", r);
1907                         goto error_free;
1908                 }
1909         }
1910
1911         for (i = 0; i < num_loops; i++) {
1912                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1913
1914                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1915                                         dst_offset, cur_size_in_bytes, tmz);
1916
1917                 src_offset += cur_size_in_bytes;
1918                 dst_offset += cur_size_in_bytes;
1919                 byte_count -= cur_size_in_bytes;
1920         }
1921
1922         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1923         WARN_ON(job->ibs[0].length_dw > num_dw);
1924         if (direct_submit)
1925                 r = amdgpu_job_submit_direct(job, ring, fence);
1926         else
1927                 r = amdgpu_job_submit(job, &adev->mman.entity,
1928                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1929         if (r)
1930                 goto error_free;
1931
1932         return r;
1933
1934 error_free:
1935         amdgpu_job_free(job);
1936         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1937         return r;
1938 }
1939
1940 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1941                        uint32_t src_data,
1942                        struct dma_resv *resv,
1943                        struct dma_fence **fence)
1944 {
1945         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1946         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1947         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1948
1949         struct amdgpu_res_cursor cursor;
1950         unsigned int num_loops, num_dw;
1951         uint64_t num_bytes;
1952
1953         struct amdgpu_job *job;
1954         int r;
1955
1956         if (!adev->mman.buffer_funcs_enabled) {
1957                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1958                 return -EINVAL;
1959         }
1960
1961         if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1962                 DRM_ERROR("Trying to clear preemptible memory.\n");
1963                 return -EINVAL;
1964         }
1965
1966         if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1967                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1968                 if (r)
1969                         return r;
1970         }
1971
1972         num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1973         num_loops = 0;
1974
1975         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1976         while (cursor.remaining) {
1977                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1978                 amdgpu_res_next(&cursor, cursor.size);
1979         }
1980         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1981
1982         /* for IB padding */
1983         num_dw += 64;
1984
1985         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1986                                      &job);
1987         if (r)
1988                 return r;
1989
1990         if (resv) {
1991                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1992                                      AMDGPU_SYNC_ALWAYS,
1993                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1994                 if (r) {
1995                         DRM_ERROR("sync failed (%d).\n", r);
1996                         goto error_free;
1997                 }
1998         }
1999
2000         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2001         while (cursor.remaining) {
2002                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2003                 uint64_t dst_addr = cursor.start;
2004
2005                 dst_addr += amdgpu_ttm_domain_start(adev,
2006                                                     bo->tbo.resource->mem_type);
2007                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2008                                         cur_size);
2009
2010                 amdgpu_res_next(&cursor, cur_size);
2011         }
2012
2013         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2014         WARN_ON(job->ibs[0].length_dw > num_dw);
2015         r = amdgpu_job_submit(job, &adev->mman.entity,
2016                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2017         if (r)
2018                 goto error_free;
2019
2020         return 0;
2021
2022 error_free:
2023         amdgpu_job_free(job);
2024         return r;
2025 }
2026
2027 #if defined(CONFIG_DEBUG_FS)
2028
2029 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2030 {
2031         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2032         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2033                                                             TTM_PL_VRAM);
2034         struct drm_printer p = drm_seq_file_printer(m);
2035
2036         man->func->debug(man, &p);
2037         return 0;
2038 }
2039
2040 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2041 {
2042         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2043
2044         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2045 }
2046
2047 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2048 {
2049         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2050         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2051                                                             TTM_PL_TT);
2052         struct drm_printer p = drm_seq_file_printer(m);
2053
2054         man->func->debug(man, &p);
2055         return 0;
2056 }
2057
2058 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2059 {
2060         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2061         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2062                                                             AMDGPU_PL_GDS);
2063         struct drm_printer p = drm_seq_file_printer(m);
2064
2065         man->func->debug(man, &p);
2066         return 0;
2067 }
2068
2069 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2070 {
2071         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2072         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2073                                                             AMDGPU_PL_GWS);
2074         struct drm_printer p = drm_seq_file_printer(m);
2075
2076         man->func->debug(man, &p);
2077         return 0;
2078 }
2079
2080 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2081 {
2082         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2083         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2084                                                             AMDGPU_PL_OA);
2085         struct drm_printer p = drm_seq_file_printer(m);
2086
2087         man->func->debug(man, &p);
2088         return 0;
2089 }
2090
2091 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2092 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2093 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2094 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2095 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2096 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2097
2098 /*
2099  * amdgpu_ttm_vram_read - Linear read access to VRAM
2100  *
2101  * Accesses VRAM via MMIO for debugging purposes.
2102  */
2103 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2104                                     size_t size, loff_t *pos)
2105 {
2106         struct amdgpu_device *adev = file_inode(f)->i_private;
2107         ssize_t result = 0;
2108
2109         if (size & 0x3 || *pos & 0x3)
2110                 return -EINVAL;
2111
2112         if (*pos >= adev->gmc.mc_vram_size)
2113                 return -ENXIO;
2114
2115         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2116         while (size) {
2117                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2118                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2119
2120                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2121                 if (copy_to_user(buf, value, bytes))
2122                         return -EFAULT;
2123
2124                 result += bytes;
2125                 buf += bytes;
2126                 *pos += bytes;
2127                 size -= bytes;
2128         }
2129
2130         return result;
2131 }
2132
2133 /*
2134  * amdgpu_ttm_vram_write - Linear write access to VRAM
2135  *
2136  * Accesses VRAM via MMIO for debugging purposes.
2137  */
2138 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2139                                     size_t size, loff_t *pos)
2140 {
2141         struct amdgpu_device *adev = file_inode(f)->i_private;
2142         ssize_t result = 0;
2143         int r;
2144
2145         if (size & 0x3 || *pos & 0x3)
2146                 return -EINVAL;
2147
2148         if (*pos >= adev->gmc.mc_vram_size)
2149                 return -ENXIO;
2150
2151         while (size) {
2152                 unsigned long flags;
2153                 uint32_t value;
2154
2155                 if (*pos >= adev->gmc.mc_vram_size)
2156                         return result;
2157
2158                 r = get_user(value, (uint32_t *)buf);
2159                 if (r)
2160                         return r;
2161
2162                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2163                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2164                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2165                 WREG32_NO_KIQ(mmMM_DATA, value);
2166                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2167
2168                 result += 4;
2169                 buf += 4;
2170                 *pos += 4;
2171                 size -= 4;
2172         }
2173
2174         return result;
2175 }
2176
2177 static const struct file_operations amdgpu_ttm_vram_fops = {
2178         .owner = THIS_MODULE,
2179         .read = amdgpu_ttm_vram_read,
2180         .write = amdgpu_ttm_vram_write,
2181         .llseek = default_llseek,
2182 };
2183
2184 /*
2185  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2186  *
2187  * This function is used to read memory that has been mapped to the
2188  * GPU and the known addresses are not physical addresses but instead
2189  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2190  */
2191 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2192                                  size_t size, loff_t *pos)
2193 {
2194         struct amdgpu_device *adev = file_inode(f)->i_private;
2195         struct iommu_domain *dom;
2196         ssize_t result = 0;
2197         int r;
2198
2199         /* retrieve the IOMMU domain if any for this device */
2200         dom = iommu_get_domain_for_dev(adev->dev);
2201
2202         while (size) {
2203                 phys_addr_t addr = *pos & PAGE_MASK;
2204                 loff_t off = *pos & ~PAGE_MASK;
2205                 size_t bytes = PAGE_SIZE - off;
2206                 unsigned long pfn;
2207                 struct page *p;
2208                 void *ptr;
2209
2210                 bytes = bytes < size ? bytes : size;
2211
2212                 /* Translate the bus address to a physical address.  If
2213                  * the domain is NULL it means there is no IOMMU active
2214                  * and the address translation is the identity
2215                  */
2216                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2217
2218                 pfn = addr >> PAGE_SHIFT;
2219                 if (!pfn_valid(pfn))
2220                         return -EPERM;
2221
2222                 p = pfn_to_page(pfn);
2223                 if (p->mapping != adev->mman.bdev.dev_mapping)
2224                         return -EPERM;
2225
2226                 ptr = kmap(p);
2227                 r = copy_to_user(buf, ptr + off, bytes);
2228                 kunmap(p);
2229                 if (r)
2230                         return -EFAULT;
2231
2232                 size -= bytes;
2233                 *pos += bytes;
2234                 result += bytes;
2235         }
2236
2237         return result;
2238 }
2239
2240 /*
2241  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2242  *
2243  * This function is used to write memory that has been mapped to the
2244  * GPU and the known addresses are not physical addresses but instead
2245  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2246  */
2247 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2248                                  size_t size, loff_t *pos)
2249 {
2250         struct amdgpu_device *adev = file_inode(f)->i_private;
2251         struct iommu_domain *dom;
2252         ssize_t result = 0;
2253         int r;
2254
2255         dom = iommu_get_domain_for_dev(adev->dev);
2256
2257         while (size) {
2258                 phys_addr_t addr = *pos & PAGE_MASK;
2259                 loff_t off = *pos & ~PAGE_MASK;
2260                 size_t bytes = PAGE_SIZE - off;
2261                 unsigned long pfn;
2262                 struct page *p;
2263                 void *ptr;
2264
2265                 bytes = bytes < size ? bytes : size;
2266
2267                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2268
2269                 pfn = addr >> PAGE_SHIFT;
2270                 if (!pfn_valid(pfn))
2271                         return -EPERM;
2272
2273                 p = pfn_to_page(pfn);
2274                 if (p->mapping != adev->mman.bdev.dev_mapping)
2275                         return -EPERM;
2276
2277                 ptr = kmap(p);
2278                 r = copy_from_user(ptr + off, buf, bytes);
2279                 kunmap(p);
2280                 if (r)
2281                         return -EFAULT;
2282
2283                 size -= bytes;
2284                 *pos += bytes;
2285                 result += bytes;
2286         }
2287
2288         return result;
2289 }
2290
2291 static const struct file_operations amdgpu_ttm_iomem_fops = {
2292         .owner = THIS_MODULE,
2293         .read = amdgpu_iomem_read,
2294         .write = amdgpu_iomem_write,
2295         .llseek = default_llseek
2296 };
2297
2298 #endif
2299
2300 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2301 {
2302 #if defined(CONFIG_DEBUG_FS)
2303         struct drm_minor *minor = adev_to_drm(adev)->primary;
2304         struct dentry *root = minor->debugfs_root;
2305
2306         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2307                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2308         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2309                             &amdgpu_ttm_iomem_fops);
2310         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2311                             &amdgpu_mm_vram_table_fops);
2312         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2313                             &amdgpu_mm_tt_table_fops);
2314         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2315                             &amdgpu_mm_gds_table_fops);
2316         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2317                             &amdgpu_mm_gws_table_fops);
2318         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2319                             &amdgpu_mm_oa_table_fops);
2320         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2321                             &amdgpu_ttm_page_pool_fops);
2322 #endif
2323 }