1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxk_hard: DRX-K DVB-C/T demodulator driver
5 * Copyright (C) 2010-2011 Digital Devices GmbH
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/i2c.h>
17 #include <linux/hardirq.h>
18 #include <asm/div64.h>
20 #include <media/dvb_frontend.h>
22 #include "drxk_hard.h"
23 #include <media/dvb_math.h>
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
28 enum operation_mode o_mode);
29 static int set_qam_standard(struct drxk_state *state,
30 enum operation_mode o_mode);
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
32 s32 tuner_freq_offset);
33 static int set_dvbt_standard(struct drxk_state *state,
34 enum operation_mode o_mode);
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
37 s32 tuner_freq_offset);
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state)
45 return state->m_operation_mode == OM_DVBT;
48 static bool is_qam(struct drxk_state *state)
50 return state->m_operation_mode == OM_QAM_ITU_A ||
51 state->m_operation_mode == OM_QAM_ITU_B ||
52 state->m_operation_mode == OM_QAM_ITU_C;
57 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
58 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
60 #define DEFAULT_MER_83 165
61 #define DEFAULT_MER_93 250
63 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
64 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
67 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
68 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
71 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
72 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
74 #ifndef DRXK_KI_RAGC_ATV
75 #define DRXK_KI_RAGC_ATV 4
77 #ifndef DRXK_KI_IAGC_ATV
78 #define DRXK_KI_IAGC_ATV 6
80 #ifndef DRXK_KI_DAGC_ATV
81 #define DRXK_KI_DAGC_ATV 7
84 #ifndef DRXK_KI_RAGC_QAM
85 #define DRXK_KI_RAGC_QAM 3
87 #ifndef DRXK_KI_IAGC_QAM
88 #define DRXK_KI_IAGC_QAM 4
90 #ifndef DRXK_KI_DAGC_QAM
91 #define DRXK_KI_DAGC_QAM 7
93 #ifndef DRXK_KI_RAGC_DVBT
94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
96 #ifndef DRXK_KI_IAGC_DVBT
97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
99 #ifndef DRXK_KI_DAGC_DVBT
100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
103 #ifndef DRXK_AGC_DAC_OFFSET
104 #define DRXK_AGC_DAC_OFFSET (0x800)
107 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
108 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
111 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
112 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
115 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
116 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
119 #ifndef DRXK_QAM_SYMBOLRATE_MAX
120 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
123 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
124 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
125 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
126 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
127 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
128 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
129 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
130 #define DRXK_BL_ROM_OFFSET_UCODE 0
132 #define DRXK_BLC_TIMEOUT 100
134 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
135 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
137 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
139 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
140 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
143 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
144 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
145 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
146 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
147 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
149 static unsigned int debug;
150 module_param(debug, int, 0644);
151 MODULE_PARM_DESC(debug, "enable debug messages");
153 #define dprintk(level, fmt, arg...) do { \
154 if (debug >= level) \
155 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
158 static inline u32 Frac28a(u32 a, u32 c)
164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
166 * integer part, only the 4 least significant
167 * bits will be visible in the result
170 /* division using radix 16, 7 nibbles in the result */
171 for (i = 0; i < 7; i++) {
172 Q1 = (Q1 << 4) | (R0 / c);
182 static inline u32 log10times100(u32 value)
184 return (100L * intlog10(value)) >> 24;
187 /***************************************************************************/
188 /* I2C **********************************************************************/
189 /***************************************************************************/
191 static int drxk_i2c_lock(struct drxk_state *state)
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
194 state->drxk_i2c_exclusive_lock = true;
199 static void drxk_i2c_unlock(struct drxk_state *state)
201 if (!state->drxk_i2c_exclusive_lock)
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
205 state->drxk_i2c_exclusive_lock = false;
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
211 if (state->drxk_i2c_exclusive_lock)
212 return __i2c_transfer(state->i2c, msgs, len);
214 return i2c_transfer(state->i2c, msgs, len);
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
219 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
220 .buf = val, .len = 1}
223 return drxk_i2c_transfer(state, msgs, 1);
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
229 struct i2c_msg msg = {
230 .addr = adr, .flags = 0, .buf = data, .len = len };
235 for (i = 0; i < len; i++)
236 pr_cont(" %02x", data[i]);
239 status = drxk_i2c_transfer(state, &msg, 1);
240 if (status >= 0 && status != 1)
244 pr_err("i2c write error at addr 0x%02x\n", adr);
249 static int i2c_read(struct drxk_state *state,
250 u8 adr, u8 *msg, int len, u8 *answ, int alen)
253 struct i2c_msg msgs[2] = {
254 {.addr = adr, .flags = 0,
255 .buf = msg, .len = len},
256 {.addr = adr, .flags = I2C_M_RD,
257 .buf = answ, .len = alen}
260 status = drxk_i2c_transfer(state, msgs, 2);
263 pr_cont(": ERROR!\n");
267 pr_err("i2c read error at addr 0x%02x\n", adr);
272 dprintk(2, ": read from");
273 for (i = 0; i < len; i++)
274 pr_cont(" %02x", msg[i]);
275 pr_cont(", value = ");
276 for (i = 0; i < alen; i++)
277 pr_cont(" %02x", answ[i]);
283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
286 u8 adr = state->demod_address, mm1[4], mm2[2], len;
288 if (state->single_master)
291 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
292 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
293 mm1[1] = ((reg >> 16) & 0xFF);
294 mm1[2] = ((reg >> 24) & 0xFF) | flags;
295 mm1[3] = ((reg >> 7) & 0xFF);
298 mm1[0] = ((reg << 1) & 0xFF);
299 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
302 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
303 status = i2c_read(state, adr, mm1, len, mm2, 2);
307 *data = mm2[0] | (mm2[1] << 8);
312 static int read16(struct drxk_state *state, u32 reg, u16 *data)
314 return read16_flags(state, reg, data, 0);
317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
320 u8 adr = state->demod_address, mm1[4], mm2[4], len;
322 if (state->single_master)
325 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
326 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
327 mm1[1] = ((reg >> 16) & 0xFF);
328 mm1[2] = ((reg >> 24) & 0xFF) | flags;
329 mm1[3] = ((reg >> 7) & 0xFF);
332 mm1[0] = ((reg << 1) & 0xFF);
333 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
336 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
337 status = i2c_read(state, adr, mm1, len, mm2, 4);
341 *data = mm2[0] | (mm2[1] << 8) |
342 (mm2[2] << 16) | (mm2[3] << 24);
347 static int read32(struct drxk_state *state, u32 reg, u32 *data)
349 return read32_flags(state, reg, data, 0);
352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
354 u8 adr = state->demod_address, mm[6], len;
356 if (state->single_master)
358 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
359 mm[0] = (((reg << 1) & 0xFF) | 0x01);
360 mm[1] = ((reg >> 16) & 0xFF);
361 mm[2] = ((reg >> 24) & 0xFF) | flags;
362 mm[3] = ((reg >> 7) & 0xFF);
365 mm[0] = ((reg << 1) & 0xFF);
366 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
369 mm[len] = data & 0xff;
370 mm[len + 1] = (data >> 8) & 0xff;
372 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
373 return i2c_write(state, adr, mm, len + 2);
376 static int write16(struct drxk_state *state, u32 reg, u16 data)
378 return write16_flags(state, reg, data, 0);
381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
383 u8 adr = state->demod_address, mm[8], len;
385 if (state->single_master)
387 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
388 mm[0] = (((reg << 1) & 0xFF) | 0x01);
389 mm[1] = ((reg >> 16) & 0xFF);
390 mm[2] = ((reg >> 24) & 0xFF) | flags;
391 mm[3] = ((reg >> 7) & 0xFF);
394 mm[0] = ((reg << 1) & 0xFF);
395 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
398 mm[len] = data & 0xff;
399 mm[len + 1] = (data >> 8) & 0xff;
400 mm[len + 2] = (data >> 16) & 0xff;
401 mm[len + 3] = (data >> 24) & 0xff;
402 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
404 return i2c_write(state, adr, mm, len + 4);
407 static int write32(struct drxk_state *state, u32 reg, u32 data)
409 return write32_flags(state, reg, data, 0);
412 static int write_block(struct drxk_state *state, u32 address,
413 const int block_size, const u8 p_block[])
415 int status = 0, blk_size = block_size;
418 if (state->single_master)
421 while (blk_size > 0) {
422 int chunk = blk_size > state->m_chunk_size ?
423 state->m_chunk_size : blk_size;
424 u8 *adr_buf = &state->chunk[0];
427 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
428 adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
429 adr_buf[1] = ((address >> 16) & 0xFF);
430 adr_buf[2] = ((address >> 24) & 0xFF);
431 adr_buf[3] = ((address >> 7) & 0xFF);
434 if (chunk == state->m_chunk_size)
437 adr_buf[0] = ((address << 1) & 0xFF);
438 adr_buf[1] = (((address >> 16) & 0x0F) |
439 ((address >> 18) & 0xF0));
442 memcpy(&state->chunk[adr_length], p_block, chunk);
443 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
447 for (i = 0; i < chunk; i++)
448 pr_cont(" %02x", p_block[i]);
451 status = i2c_write(state, state->demod_address,
452 &state->chunk[0], chunk + adr_length);
454 pr_err("%s: i2c write error at addr 0x%02x\n",
459 address += (chunk >> 1);
465 #ifndef DRXK_MAX_RETRIES_POWERUP
466 #define DRXK_MAX_RETRIES_POWERUP 20
469 static int power_up_device(struct drxk_state *state)
477 status = i2c_read1(state, state->demod_address, &data);
481 status = i2c_write(state, state->demod_address,
483 usleep_range(10000, 11000);
487 status = i2c_read1(state, state->demod_address,
489 } while (status < 0 &&
490 (retry_count < DRXK_MAX_RETRIES_POWERUP));
491 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
495 /* Make sure all clk domains are active */
496 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
499 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
502 /* Enable pll lock tests */
503 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
507 state->m_current_power_mode = DRX_POWER_UP;
511 pr_err("Error %d on %s\n", status, __func__);
517 static int init_state(struct drxk_state *state)
520 * FIXME: most (all?) of the values below should be moved into
521 * struct drxk_config, as they are probably board-specific
523 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
524 u32 ul_vsb_if_agc_output_level = 0;
525 u32 ul_vsb_if_agc_min_level = 0;
526 u32 ul_vsb_if_agc_max_level = 0x7FFF;
527 u32 ul_vsb_if_agc_speed = 3;
529 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
530 u32 ul_vsb_rf_agc_output_level = 0;
531 u32 ul_vsb_rf_agc_min_level = 0;
532 u32 ul_vsb_rf_agc_max_level = 0x7FFF;
533 u32 ul_vsb_rf_agc_speed = 3;
534 u32 ul_vsb_rf_agc_top = 9500;
535 u32 ul_vsb_rf_agc_cut_off_current = 4000;
537 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
538 u32 ul_atv_if_agc_output_level = 0;
539 u32 ul_atv_if_agc_min_level = 0;
540 u32 ul_atv_if_agc_max_level = 0;
541 u32 ul_atv_if_agc_speed = 3;
543 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
544 u32 ul_atv_rf_agc_output_level = 0;
545 u32 ul_atv_rf_agc_min_level = 0;
546 u32 ul_atv_rf_agc_max_level = 0;
547 u32 ul_atv_rf_agc_top = 9500;
548 u32 ul_atv_rf_agc_cut_off_current = 4000;
549 u32 ul_atv_rf_agc_speed = 3;
551 u32 ulQual83 = DEFAULT_MER_83;
552 u32 ulQual93 = DEFAULT_MER_93;
554 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
555 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
557 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
558 /* io_pad_cfg_mode output mode is drive always */
559 /* io_pad_cfg_drive is set to power 2 (23 mA) */
560 u32 ul_gpio_cfg = 0x0113;
561 u32 ul_invert_ts_clock = 0;
562 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
563 u32 ul_dvbt_bitrate = 50000000;
564 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
566 u32 ul_insert_rs_byte = 0;
568 u32 ul_rf_mirror = 1;
569 u32 ul_power_down = 0;
573 state->m_has_lna = false;
574 state->m_has_dvbt = false;
575 state->m_has_dvbc = false;
576 state->m_has_atv = false;
577 state->m_has_oob = false;
578 state->m_has_audio = false;
580 if (!state->m_chunk_size)
581 state->m_chunk_size = 124;
583 state->m_osc_clock_freq = 0;
584 state->m_smart_ant_inverted = false;
585 state->m_b_p_down_open_bridge = false;
587 /* real system clock frequency in kHz */
588 state->m_sys_clock_freq = 151875;
589 /* Timing div, 250ns/Psys */
590 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
591 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
592 HI_I2C_DELAY) / 1000;
594 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
595 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
596 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
597 /* port/bridge/power down ctrl */
598 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
600 state->m_b_power_down = (ul_power_down != 0);
602 state->m_drxk_a3_patch_code = false;
604 /* Init AGC and PGA parameters */
606 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
607 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
608 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
609 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
610 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
611 state->m_vsb_pga_cfg = 140;
614 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
615 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
616 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
617 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
618 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
619 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
620 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
621 state->m_vsb_pre_saw_cfg.reference = 0x07;
622 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
624 state->m_Quality83percent = DEFAULT_MER_83;
625 state->m_Quality93percent = DEFAULT_MER_93;
626 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
627 state->m_Quality83percent = ulQual83;
628 state->m_Quality93percent = ulQual93;
632 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
633 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
634 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
635 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
636 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
639 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
640 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
641 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
642 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
643 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
644 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
645 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
646 state->m_atv_pre_saw_cfg.reference = 0x04;
647 state->m_atv_pre_saw_cfg.use_pre_saw = true;
651 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
652 state->m_dvbt_rf_agc_cfg.output_level = 0;
653 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
654 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
655 state->m_dvbt_rf_agc_cfg.top = 0x2100;
656 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
657 state->m_dvbt_rf_agc_cfg.speed = 1;
661 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
662 state->m_dvbt_if_agc_cfg.output_level = 0;
663 state->m_dvbt_if_agc_cfg.min_output_level = 0;
664 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
665 state->m_dvbt_if_agc_cfg.top = 13424;
666 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
667 state->m_dvbt_if_agc_cfg.speed = 3;
668 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
669 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
670 /* state->m_dvbtPgaCfg = 140; */
672 state->m_dvbt_pre_saw_cfg.reference = 4;
673 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
676 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
677 state->m_qam_rf_agc_cfg.output_level = 0;
678 state->m_qam_rf_agc_cfg.min_output_level = 6023;
679 state->m_qam_rf_agc_cfg.max_output_level = 27000;
680 state->m_qam_rf_agc_cfg.top = 0x2380;
681 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
682 state->m_qam_rf_agc_cfg.speed = 3;
685 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
686 state->m_qam_if_agc_cfg.output_level = 0;
687 state->m_qam_if_agc_cfg.min_output_level = 0;
688 state->m_qam_if_agc_cfg.max_output_level = 9000;
689 state->m_qam_if_agc_cfg.top = 0x0511;
690 state->m_qam_if_agc_cfg.cut_off_current = 0;
691 state->m_qam_if_agc_cfg.speed = 3;
692 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
693 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
695 state->m_qam_pga_cfg = 140;
696 state->m_qam_pre_saw_cfg.reference = 4;
697 state->m_qam_pre_saw_cfg.use_pre_saw = false;
699 state->m_operation_mode = OM_NONE;
700 state->m_drxk_state = DRXK_UNINITIALIZED;
702 /* MPEG output configuration */
703 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
704 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
705 state->m_invert_data = false; /* If TRUE; invert DATA signals */
706 state->m_invert_err = false; /* If TRUE; invert ERR signal */
707 state->m_invert_str = false; /* If TRUE; invert STR signals */
708 state->m_invert_val = false; /* If TRUE; invert VAL signals */
709 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
711 /* If TRUE; static MPEG clockrate will be used;
712 otherwise clockrate will adapt to the bitrate of the TS */
714 state->m_dvbt_bitrate = ul_dvbt_bitrate;
715 state->m_dvbc_bitrate = ul_dvbc_bitrate;
717 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
719 /* Maximum bitrate in b/s in case static clockrate is selected */
720 state->m_mpeg_ts_static_bitrate = 19392658;
721 state->m_disable_te_ihandling = false;
723 if (ul_insert_rs_byte)
724 state->m_insert_rs_byte = true;
726 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
727 if (ul_mpeg_lock_time_out < 10000)
728 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
729 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
730 if (ul_demod_lock_time_out < 10000)
731 state->m_demod_lock_time_out = ul_demod_lock_time_out;
734 state->m_constellation = DRX_CONSTELLATION_AUTO;
735 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
736 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
737 state->m_fec_rs_prescale = 1;
739 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
740 state->m_agcfast_clip_ctrl_delay = 0;
742 state->m_gpio_cfg = ul_gpio_cfg;
744 state->m_b_power_down = false;
745 state->m_current_power_mode = DRX_POWER_DOWN;
747 state->m_rfmirror = (ul_rf_mirror == 0);
748 state->m_if_agc_pol = false;
752 static int drxx_open(struct drxk_state *state)
760 /* stop lock indicator process */
761 status = write16(state, SCU_RAM_GPIO__A,
762 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
765 /* Check device id */
766 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
769 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
772 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
775 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
778 status = write16(state, SIO_TOP_COMM_KEY__A, key);
781 pr_err("Error %d on %s\n", status, __func__);
785 static int get_device_capabilities(struct drxk_state *state)
787 u16 sio_pdr_ohw_cfg = 0;
788 u32 sio_top_jtagid_lo = 0;
790 const char *spin = "";
795 /* stop lock indicator process */
796 status = write16(state, SCU_RAM_GPIO__A,
797 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
800 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
803 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
806 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
810 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
812 /* ignore (bypass ?) */
816 state->m_osc_clock_freq = 27000;
820 state->m_osc_clock_freq = 20250;
824 state->m_osc_clock_freq = 20250;
827 pr_err("Clock Frequency is unknown\n");
831 Determine device capabilities
834 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
838 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
841 switch ((sio_top_jtagid_lo >> 29) & 0xF) {
843 state->m_device_spin = DRXK_SPIN_A1;
847 state->m_device_spin = DRXK_SPIN_A2;
851 state->m_device_spin = DRXK_SPIN_A3;
855 state->m_device_spin = DRXK_SPIN_UNKNOWN;
857 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
860 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
862 /* typeId = DRX3913K_TYPE_ID */
863 state->m_has_lna = false;
864 state->m_has_oob = false;
865 state->m_has_atv = false;
866 state->m_has_audio = false;
867 state->m_has_dvbt = true;
868 state->m_has_dvbc = true;
869 state->m_has_sawsw = true;
870 state->m_has_gpio2 = false;
871 state->m_has_gpio1 = false;
872 state->m_has_irqn = false;
875 /* typeId = DRX3915K_TYPE_ID */
876 state->m_has_lna = false;
877 state->m_has_oob = false;
878 state->m_has_atv = true;
879 state->m_has_audio = false;
880 state->m_has_dvbt = true;
881 state->m_has_dvbc = false;
882 state->m_has_sawsw = true;
883 state->m_has_gpio2 = true;
884 state->m_has_gpio1 = true;
885 state->m_has_irqn = false;
888 /* typeId = DRX3916K_TYPE_ID */
889 state->m_has_lna = false;
890 state->m_has_oob = false;
891 state->m_has_atv = true;
892 state->m_has_audio = false;
893 state->m_has_dvbt = true;
894 state->m_has_dvbc = false;
895 state->m_has_sawsw = true;
896 state->m_has_gpio2 = true;
897 state->m_has_gpio1 = true;
898 state->m_has_irqn = false;
901 /* typeId = DRX3918K_TYPE_ID */
902 state->m_has_lna = false;
903 state->m_has_oob = false;
904 state->m_has_atv = true;
905 state->m_has_audio = true;
906 state->m_has_dvbt = true;
907 state->m_has_dvbc = false;
908 state->m_has_sawsw = true;
909 state->m_has_gpio2 = true;
910 state->m_has_gpio1 = true;
911 state->m_has_irqn = false;
914 /* typeId = DRX3921K_TYPE_ID */
915 state->m_has_lna = false;
916 state->m_has_oob = false;
917 state->m_has_atv = true;
918 state->m_has_audio = true;
919 state->m_has_dvbt = true;
920 state->m_has_dvbc = true;
921 state->m_has_sawsw = true;
922 state->m_has_gpio2 = true;
923 state->m_has_gpio1 = true;
924 state->m_has_irqn = false;
927 /* typeId = DRX3923K_TYPE_ID */
928 state->m_has_lna = false;
929 state->m_has_oob = false;
930 state->m_has_atv = true;
931 state->m_has_audio = true;
932 state->m_has_dvbt = true;
933 state->m_has_dvbc = true;
934 state->m_has_sawsw = true;
935 state->m_has_gpio2 = true;
936 state->m_has_gpio1 = true;
937 state->m_has_irqn = false;
940 /* typeId = DRX3925K_TYPE_ID */
941 state->m_has_lna = false;
942 state->m_has_oob = false;
943 state->m_has_atv = true;
944 state->m_has_audio = true;
945 state->m_has_dvbt = true;
946 state->m_has_dvbc = true;
947 state->m_has_sawsw = true;
948 state->m_has_gpio2 = true;
949 state->m_has_gpio1 = true;
950 state->m_has_irqn = false;
953 /* typeId = DRX3926K_TYPE_ID */
954 state->m_has_lna = false;
955 state->m_has_oob = false;
956 state->m_has_atv = true;
957 state->m_has_audio = false;
958 state->m_has_dvbt = true;
959 state->m_has_dvbc = true;
960 state->m_has_sawsw = true;
961 state->m_has_gpio2 = true;
962 state->m_has_gpio1 = true;
963 state->m_has_irqn = false;
966 pr_err("DeviceID 0x%02x not supported\n",
967 ((sio_top_jtagid_lo >> 12) & 0xFF));
972 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
973 ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
974 state->m_osc_clock_freq / 1000,
975 state->m_osc_clock_freq % 1000);
979 pr_err("Error %d on %s\n", status, __func__);
985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
993 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
996 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
997 usleep_range(1000, 2000);
1000 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1001 ((state->m_hi_cfg_ctrl) &
1002 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1003 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1004 if (!powerdown_cmd) {
1005 /* Wait until command rdy */
1006 u32 retry_count = 0;
1010 usleep_range(1000, 2000);
1012 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1014 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1015 && (wait_cmd != 0));
1018 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1022 pr_err("Error %d on %s\n", status, __func__);
1027 static int hi_cfg_command(struct drxk_state *state)
1033 mutex_lock(&state->mutex);
1035 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1036 state->m_hi_cfg_timeout);
1039 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1040 state->m_hi_cfg_ctrl);
1043 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1044 state->m_hi_cfg_wake_up_key);
1047 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1048 state->m_hi_cfg_bridge_delay);
1051 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1052 state->m_hi_cfg_timing_div);
1055 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1056 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1059 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1063 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1065 mutex_unlock(&state->mutex);
1067 pr_err("Error %d on %s\n", status, __func__);
1071 static int init_hi(struct drxk_state *state)
1075 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1076 state->m_hi_cfg_timeout = 0x96FF;
1077 /* port/bridge/power down ctrl */
1078 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1080 return hi_cfg_command(state);
1083 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1086 u16 sio_pdr_mclk_cfg = 0;
1087 u16 sio_pdr_mdx_cfg = 0;
1090 dprintk(1, ": mpeg %s, %s mode\n",
1091 mpeg_enable ? "enable" : "disable",
1092 state->m_enable_parallel ? "parallel" : "serial");
1094 /* stop lock indicator process */
1095 status = write16(state, SCU_RAM_GPIO__A,
1096 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1100 /* MPEG TS pad configuration */
1101 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1106 /* Set MPEG TS pads to inputmode */
1107 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1110 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1113 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1116 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1119 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1122 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1125 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1128 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1131 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1134 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1137 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1140 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1144 /* Enable MPEG output */
1146 ((state->m_ts_data_strength <<
1147 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1148 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1149 SIO_PDR_MCLK_CFG_DRIVE__B) |
1152 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1156 if (state->enable_merr_cfg)
1157 err_cfg = sio_pdr_mdx_cfg;
1159 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1162 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1166 if (state->m_enable_parallel) {
1167 /* parallel -> enable MD1 to MD7 */
1168 status = write16(state, SIO_PDR_MD1_CFG__A,
1172 status = write16(state, SIO_PDR_MD2_CFG__A,
1176 status = write16(state, SIO_PDR_MD3_CFG__A,
1180 status = write16(state, SIO_PDR_MD4_CFG__A,
1184 status = write16(state, SIO_PDR_MD5_CFG__A,
1188 status = write16(state, SIO_PDR_MD6_CFG__A,
1192 status = write16(state, SIO_PDR_MD7_CFG__A,
1197 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1198 SIO_PDR_MD0_CFG_DRIVE__B)
1200 /* serial -> disable MD1 to MD7 */
1201 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1204 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1207 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1210 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1213 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1216 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1219 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1226 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1230 /* Enable MB output over MPEG pads and ctl input */
1231 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1234 /* Write nomagic word to enable pdr reg write */
1235 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1238 pr_err("Error %d on %s\n", status, __func__);
1242 static int mpegts_disable(struct drxk_state *state)
1246 return mpegts_configure_pins(state, false);
1249 static int bl_chain_cmd(struct drxk_state *state,
1250 u16 rom_offset, u16 nr_of_elements, u32 time_out)
1257 mutex_lock(&state->mutex);
1258 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1261 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1264 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1267 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1271 end = jiffies + msecs_to_jiffies(time_out);
1273 usleep_range(1000, 2000);
1274 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1277 } while ((bl_status == 0x1) &&
1278 ((time_is_after_jiffies(end))));
1280 if (bl_status == 0x1) {
1281 pr_err("SIO not ready\n");
1287 pr_err("Error %d on %s\n", status, __func__);
1289 mutex_unlock(&state->mutex);
1294 static int download_microcode(struct drxk_state *state,
1295 const u8 p_mc_image[], u32 length)
1297 const u8 *p_src = p_mc_image;
1307 /* down the drain (we don't care about MAGIC_WORD) */
1309 /* For future reference */
1310 drain = (p_src[0] << 8) | p_src[1];
1312 p_src += sizeof(u16);
1313 offset += sizeof(u16);
1314 n_blocks = (p_src[0] << 8) | p_src[1];
1315 p_src += sizeof(u16);
1316 offset += sizeof(u16);
1318 for (i = 0; i < n_blocks; i += 1) {
1319 address = (p_src[0] << 24) | (p_src[1] << 16) |
1320 (p_src[2] << 8) | p_src[3];
1321 p_src += sizeof(u32);
1322 offset += sizeof(u32);
1324 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1325 p_src += sizeof(u16);
1326 offset += sizeof(u16);
1329 /* For future reference */
1330 flags = (p_src[0] << 8) | p_src[1];
1332 p_src += sizeof(u16);
1333 offset += sizeof(u16);
1336 /* For future reference */
1337 block_crc = (p_src[0] << 8) | p_src[1];
1339 p_src += sizeof(u16);
1340 offset += sizeof(u16);
1342 if (offset + block_size > length) {
1343 pr_err("Firmware is corrupted.\n");
1347 status = write_block(state, address, block_size, p_src);
1349 pr_err("Error %d while loading firmware\n", status);
1352 p_src += block_size;
1353 offset += block_size;
1358 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1362 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1363 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1369 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1370 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1373 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1374 if (status >= 0 && data == desired_status) {
1375 /* tokenring already has correct status */
1378 /* Disable/enable dvbt tokenring bridge */
1379 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1381 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1383 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1384 if ((status >= 0 && data == desired_status)
1385 || time_is_after_jiffies(end))
1387 usleep_range(1000, 2000);
1389 if (data != desired_status) {
1390 pr_err("SIO not ready\n");
1396 static int mpegts_stop(struct drxk_state *state)
1399 u16 fec_oc_snc_mode = 0;
1400 u16 fec_oc_ipr_mode = 0;
1404 /* Graceful shutdown (byte boundaries) */
1405 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1408 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1409 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1413 /* Suppress MCLK during absence of data */
1414 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1417 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1418 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1422 pr_err("Error %d on %s\n", status, __func__);
1427 static int scu_command(struct drxk_state *state,
1428 u16 cmd, u8 parameter_len,
1429 u16 *parameter, u8 result_len, u16 *result)
1431 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1432 #error DRXK register mapping no longer compatible with this routine!
1435 int status = -EINVAL;
1444 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1445 ((result_len > 0) && (result == NULL))) {
1446 pr_err("Error %d on %s\n", status, __func__);
1450 mutex_lock(&state->mutex);
1452 /* assume that the command register is ready
1453 since it is checked afterwards */
1455 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1456 buffer[cnt++] = (parameter[ii] & 0xFF);
1457 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1460 buffer[cnt++] = (cmd & 0xFF);
1461 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1463 write_block(state, SCU_RAM_PARAM_0__A -
1464 (parameter_len - 1), cnt, buffer);
1465 /* Wait until SCU has processed command */
1466 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1468 usleep_range(1000, 2000);
1469 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1472 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1473 if (cur_cmd != DRX_SCU_READY) {
1474 pr_err("SCU not ready\n");
1479 if ((result_len > 0) && (result != NULL)) {
1483 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1484 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1490 /* Check if an error was reported by SCU */
1491 err = (s16)result[0];
1495 /* check for the known error codes */
1497 case SCU_RESULT_UNKCMD:
1498 p = "SCU_RESULT_UNKCMD";
1500 case SCU_RESULT_UNKSTD:
1501 p = "SCU_RESULT_UNKSTD";
1503 case SCU_RESULT_SIZE:
1504 p = "SCU_RESULT_SIZE";
1506 case SCU_RESULT_INVPAR:
1507 p = "SCU_RESULT_INVPAR";
1509 default: /* Other negative values are errors */
1510 sprintf(errname, "ERROR: %d\n", err);
1513 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1514 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1521 pr_err("Error %d on %s\n", status, __func__);
1523 mutex_unlock(&state->mutex);
1527 static int set_iqm_af(struct drxk_state *state, bool active)
1535 status = read16(state, IQM_AF_STDBY__A, &data);
1540 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1541 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1542 | IQM_AF_STDBY_STDBY_PD_STANDBY
1543 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1544 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1546 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1547 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1548 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1549 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1550 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1553 status = write16(state, IQM_AF_STDBY__A, data);
1557 pr_err("Error %d on %s\n", status, __func__);
1561 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1564 u16 sio_cc_pwd_mode = 0;
1568 /* Check arguments */
1574 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1576 case DRXK_POWER_DOWN_OFDM:
1577 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1579 case DRXK_POWER_DOWN_CORE:
1580 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1582 case DRXK_POWER_DOWN_PLL:
1583 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1585 case DRX_POWER_DOWN:
1586 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1589 /* Unknow sleep mode */
1593 /* If already in requested power mode, do nothing */
1594 if (state->m_current_power_mode == *mode)
1597 /* For next steps make sure to start from DRX_POWER_UP mode */
1598 if (state->m_current_power_mode != DRX_POWER_UP) {
1599 status = power_up_device(state);
1602 status = dvbt_enable_ofdm_token_ring(state, true);
1607 if (*mode == DRX_POWER_UP) {
1608 /* Restore analog & pin configuration */
1610 /* Power down to requested mode */
1611 /* Backup some register settings */
1612 /* Set pins with possible pull-ups connected
1613 to them in input mode */
1614 /* Analog power down */
1615 /* ADC power down */
1616 /* Power down device */
1617 /* stop all comm_exec */
1618 /* Stop and power down previous standard */
1619 switch (state->m_operation_mode) {
1621 status = mpegts_stop(state);
1624 status = power_down_dvbt(state, false);
1630 status = mpegts_stop(state);
1633 status = power_down_qam(state);
1640 status = dvbt_enable_ofdm_token_ring(state, false);
1643 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1646 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1650 if (*mode != DRXK_POWER_DOWN_OFDM) {
1651 state->m_hi_cfg_ctrl |=
1652 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1653 status = hi_cfg_command(state);
1658 state->m_current_power_mode = *mode;
1662 pr_err("Error %d on %s\n", status, __func__);
1667 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1669 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1676 status = read16(state, SCU_COMM_EXEC__A, &data);
1679 if (data == SCU_COMM_EXEC_ACTIVE) {
1680 /* Send OFDM stop command */
1681 status = scu_command(state,
1682 SCU_RAM_COMMAND_STANDARD_OFDM
1683 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1684 0, NULL, 1, &cmd_result);
1687 /* Send OFDM reset command */
1688 status = scu_command(state,
1689 SCU_RAM_COMMAND_STANDARD_OFDM
1690 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1691 0, NULL, 1, &cmd_result);
1696 /* Reset datapath for OFDM, processors first */
1697 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1700 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1703 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1708 status = set_iqm_af(state, false);
1712 /* powerdown to OFDM mode */
1713 if (set_power_mode) {
1714 status = ctrl_power_mode(state, &power_mode);
1720 pr_err("Error %d on %s\n", status, __func__);
1724 static int setoperation_mode(struct drxk_state *state,
1725 enum operation_mode o_mode)
1731 Stop and power down previous standard
1732 TODO investigate total power down instead of partial
1733 power down depending on "previous" standard.
1736 /* disable HW lock indicator */
1737 status = write16(state, SCU_RAM_GPIO__A,
1738 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1742 /* Device is already at the required mode */
1743 if (state->m_operation_mode == o_mode)
1746 switch (state->m_operation_mode) {
1747 /* OM_NONE was added for start up */
1751 status = mpegts_stop(state);
1754 status = power_down_dvbt(state, true);
1757 state->m_operation_mode = OM_NONE;
1761 status = mpegts_stop(state);
1764 status = power_down_qam(state);
1767 state->m_operation_mode = OM_NONE;
1776 Power up new standard
1780 dprintk(1, ": DVB-T\n");
1781 state->m_operation_mode = o_mode;
1782 status = set_dvbt_standard(state, o_mode);
1788 dprintk(1, ": DVB-C Annex %c\n",
1789 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1790 state->m_operation_mode = o_mode;
1791 status = set_qam_standard(state, o_mode);
1801 pr_err("Error %d on %s\n", status, __func__);
1805 static int start(struct drxk_state *state, s32 offset_freq,
1806 s32 intermediate_frequency)
1808 int status = -EINVAL;
1811 s32 offsetk_hz = offset_freq / 1000;
1814 if (state->m_drxk_state != DRXK_STOPPED &&
1815 state->m_drxk_state != DRXK_DTV_STARTED)
1818 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1820 if (intermediate_frequency < 0) {
1821 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1822 intermediate_frequency = -intermediate_frequency;
1825 switch (state->m_operation_mode) {
1828 i_freqk_hz = (intermediate_frequency / 1000);
1829 status = set_qam(state, i_freqk_hz, offsetk_hz);
1832 state->m_drxk_state = DRXK_DTV_STARTED;
1835 i_freqk_hz = (intermediate_frequency / 1000);
1836 status = mpegts_stop(state);
1839 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1842 status = dvbt_start(state);
1845 state->m_drxk_state = DRXK_DTV_STARTED;
1852 pr_err("Error %d on %s\n", status, __func__);
1856 static int shut_down(struct drxk_state *state)
1864 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1866 int status = -EINVAL;
1870 if (p_lock_status == NULL)
1873 *p_lock_status = NOT_LOCKED;
1875 /* define the SCU command code */
1876 switch (state->m_operation_mode) {
1880 status = get_qam_lock_status(state, p_lock_status);
1883 status = get_dvbt_lock_status(state, p_lock_status);
1886 pr_debug("Unsupported operation mode %d in %s\n",
1887 state->m_operation_mode, __func__);
1892 pr_err("Error %d on %s\n", status, __func__);
1896 static int mpegts_start(struct drxk_state *state)
1900 u16 fec_oc_snc_mode = 0;
1902 /* Allow OC to sync again */
1903 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1906 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1907 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1910 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1913 pr_err("Error %d on %s\n", status, __func__);
1917 static int mpegts_dto_init(struct drxk_state *state)
1923 /* Rate integration settings */
1924 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1927 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1930 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1933 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1936 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1939 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1942 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1945 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1949 /* Additional configuration */
1950 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1953 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1956 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1959 pr_err("Error %d on %s\n", status, __func__);
1964 static int mpegts_dto_setup(struct drxk_state *state,
1965 enum operation_mode o_mode)
1969 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */
1970 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */
1971 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */
1972 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */
1973 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */
1974 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1975 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */
1976 u16 fec_oc_tmd_mode = 0;
1977 u16 fec_oc_tmd_int_upd_rate = 0;
1978 u32 max_bit_rate = 0;
1979 bool static_clk = false;
1983 /* Check insertion of the Reed-Solomon parity bytes */
1984 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1987 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1990 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1991 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1992 if (state->m_insert_rs_byte) {
1993 /* enable parity symbol forward */
1994 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1995 /* MVAL disable during parity bytes */
1996 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1997 /* TS burst length to 204 */
1998 fec_oc_dto_burst_len = 204;
2001 /* Check serial or parallel output */
2002 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2003 if (!state->m_enable_parallel) {
2004 /* MPEG data output is serial -> set ipr_mode[0] */
2005 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2010 max_bit_rate = state->m_dvbt_bitrate;
2011 fec_oc_tmd_mode = 3;
2012 fec_oc_rcn_ctl_rate = 0xC00000;
2013 static_clk = state->m_dvbt_static_clk;
2017 fec_oc_tmd_mode = 0x0004;
2018 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2019 max_bit_rate = state->m_dvbc_bitrate;
2020 static_clk = state->m_dvbc_static_clk;
2024 } /* switch (standard) */
2028 /* Configure DTO's */
2032 /* Rational DTO for MCLK source (static MCLK rate),
2033 Dynamic DTO for optimal grouping
2034 (avoid intra-packet gaps),
2035 DTO offset enable to sync TS burst with MSTRT */
2036 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2037 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2038 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2039 FEC_OC_FCT_MODE_VIRT_ENA__M);
2041 /* Check user defined bitrate */
2042 bit_rate = max_bit_rate;
2043 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */
2044 bit_rate = 75900000UL;
2046 /* Rational DTO period:
2047 dto_period = (Fsys / bitrate) - 2
2049 result should be floored,
2050 to make sure >= requested bitrate
2052 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2053 * 1000) / bit_rate);
2054 if (fec_oc_dto_period <= 2)
2055 fec_oc_dto_period = 0;
2057 fec_oc_dto_period -= 2;
2058 fec_oc_tmd_int_upd_rate = 8;
2060 /* (commonAttr->static_clk == false) => dynamic mode */
2061 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2062 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2063 fec_oc_tmd_int_upd_rate = 5;
2066 /* Write appropriate registers with requested configuration */
2067 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2070 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2073 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2076 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2079 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2082 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2086 /* Rate integration settings */
2087 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2090 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2091 fec_oc_tmd_int_upd_rate);
2094 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2097 pr_err("Error %d on %s\n", status, __func__);
2101 static int mpegts_configure_polarity(struct drxk_state *state)
2103 u16 fec_oc_reg_ipr_invert = 0;
2105 /* Data mask for the output data byte */
2106 u16 invert_data_mask =
2107 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2108 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2109 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2110 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2114 /* Control selective inversion of output bits */
2115 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2116 if (state->m_invert_data)
2117 fec_oc_reg_ipr_invert |= invert_data_mask;
2118 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2119 if (state->m_invert_err)
2120 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2121 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2122 if (state->m_invert_str)
2123 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2124 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2125 if (state->m_invert_val)
2126 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2127 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2128 if (state->m_invert_clk)
2129 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2131 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2134 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2136 static int set_agc_rf(struct drxk_state *state,
2137 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2139 int status = -EINVAL;
2141 struct s_cfg_agc *p_if_agc_settings;
2145 if (p_agc_cfg == NULL)
2148 switch (p_agc_cfg->ctrl_mode) {
2149 case DRXK_AGC_CTRL_AUTO:
2150 /* Enable RF AGC DAC */
2151 status = read16(state, IQM_AF_STDBY__A, &data);
2154 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2155 status = write16(state, IQM_AF_STDBY__A, data);
2158 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2162 /* Enable SCU RF AGC loop */
2163 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2166 if (state->m_rf_agc_pol)
2167 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2169 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2170 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2174 /* Set speed (using complementary reduction value) */
2175 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2179 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2180 data |= (~(p_agc_cfg->speed <<
2181 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2182 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2184 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2189 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2190 else if (is_qam(state))
2191 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2193 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2194 if (p_if_agc_settings == NULL) {
2199 /* Set TOP, only if IF-AGC is in AUTO mode */
2200 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2201 status = write16(state,
2202 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2208 /* Cut-Off current */
2209 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2210 p_agc_cfg->cut_off_current);
2214 /* Max. output level */
2215 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2216 p_agc_cfg->max_output_level);
2222 case DRXK_AGC_CTRL_USER:
2223 /* Enable RF AGC DAC */
2224 status = read16(state, IQM_AF_STDBY__A, &data);
2227 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2228 status = write16(state, IQM_AF_STDBY__A, data);
2232 /* Disable SCU RF AGC loop */
2233 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2236 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2237 if (state->m_rf_agc_pol)
2238 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2240 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2241 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2245 /* SCU c.o.c. to 0, enabling full control range */
2246 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2250 /* Write value to output pin */
2251 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2252 p_agc_cfg->output_level);
2257 case DRXK_AGC_CTRL_OFF:
2258 /* Disable RF AGC DAC */
2259 status = read16(state, IQM_AF_STDBY__A, &data);
2262 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2263 status = write16(state, IQM_AF_STDBY__A, data);
2267 /* Disable SCU RF AGC loop */
2268 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2271 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2272 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2283 pr_err("Error %d on %s\n", status, __func__);
2287 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2289 static int set_agc_if(struct drxk_state *state,
2290 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2294 struct s_cfg_agc *p_rf_agc_settings;
2298 switch (p_agc_cfg->ctrl_mode) {
2299 case DRXK_AGC_CTRL_AUTO:
2301 /* Enable IF AGC DAC */
2302 status = read16(state, IQM_AF_STDBY__A, &data);
2305 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2306 status = write16(state, IQM_AF_STDBY__A, data);
2310 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2314 /* Enable SCU IF AGC loop */
2315 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2318 if (state->m_if_agc_pol)
2319 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2321 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2322 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2326 /* Set speed (using complementary reduction value) */
2327 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2330 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2331 data |= (~(p_agc_cfg->speed <<
2332 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2333 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2335 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2340 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2342 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2343 if (p_rf_agc_settings == NULL)
2346 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2347 p_rf_agc_settings->top);
2352 case DRXK_AGC_CTRL_USER:
2354 /* Enable IF AGC DAC */
2355 status = read16(state, IQM_AF_STDBY__A, &data);
2358 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2359 status = write16(state, IQM_AF_STDBY__A, data);
2363 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2367 /* Disable SCU IF AGC loop */
2368 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2371 if (state->m_if_agc_pol)
2372 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2374 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2375 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2379 /* Write value to output pin */
2380 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2381 p_agc_cfg->output_level);
2386 case DRXK_AGC_CTRL_OFF:
2388 /* Disable If AGC DAC */
2389 status = read16(state, IQM_AF_STDBY__A, &data);
2392 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2393 status = write16(state, IQM_AF_STDBY__A, data);
2397 /* Disable SCU IF AGC loop */
2398 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2401 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2402 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2406 } /* switch (agcSettingsIf->ctrl_mode) */
2408 /* always set the top to support
2409 configurations without if-loop */
2410 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2413 pr_err("Error %d on %s\n", status, __func__);
2417 static int get_qam_signal_to_noise(struct drxk_state *state,
2418 s32 *p_signal_to_noise)
2421 u16 qam_sl_err_power = 0; /* accum. error between
2422 raw and sliced symbols */
2423 u32 qam_sl_sig_power = 0; /* used for MER, depends of
2425 u32 qam_sl_mer = 0; /* QAM MER */
2429 /* MER calculation */
2431 /* get the register value needed for MER */
2432 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2434 pr_err("Error %d on %s\n", status, __func__);
2438 switch (state->props.modulation) {
2440 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2443 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2446 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2449 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2453 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2457 if (qam_sl_err_power > 0) {
2458 qam_sl_mer = log10times100(qam_sl_sig_power) -
2459 log10times100((u32) qam_sl_err_power);
2461 *p_signal_to_noise = qam_sl_mer;
2466 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2467 s32 *p_signal_to_noise)
2471 u32 eq_reg_td_sqr_err_i = 0;
2472 u32 eq_reg_td_sqr_err_q = 0;
2473 u16 eq_reg_td_sqr_err_exp = 0;
2474 u16 eq_reg_td_tps_pwr_ofs = 0;
2475 u16 eq_reg_td_req_smb_cnt = 0;
2482 u16 transmission_params = 0;
2486 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2487 &eq_reg_td_tps_pwr_ofs);
2490 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2491 &eq_reg_td_req_smb_cnt);
2494 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2495 &eq_reg_td_sqr_err_exp);
2498 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2502 /* Extend SQR_ERR_I operational range */
2503 eq_reg_td_sqr_err_i = (u32) reg_data;
2504 if ((eq_reg_td_sqr_err_exp > 11) &&
2505 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2506 eq_reg_td_sqr_err_i += 0x00010000UL;
2508 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2511 /* Extend SQR_ERR_Q operational range */
2512 eq_reg_td_sqr_err_q = (u32) reg_data;
2513 if ((eq_reg_td_sqr_err_exp > 11) &&
2514 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2515 eq_reg_td_sqr_err_q += 0x00010000UL;
2517 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2518 &transmission_params);
2522 /* Check input data for MER */
2524 /* MER calculation (in 0.1 dB) without math.h */
2525 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2527 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2528 /* No error at all, this must be the HW reset value
2529 * Apparently no first measurement yet
2533 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2534 eq_reg_td_sqr_err_exp;
2535 if ((transmission_params &
2536 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2537 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2542 /* IMER = 100 * log10 (x)
2543 where x = (eq_reg_td_tps_pwr_ofs^2 *
2544 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2547 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2548 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2549 c = 100 * log10 (sqr_err_iq)
2552 /* log(x) x = 9bits * 9bits->18 bits */
2553 a = log10times100(eq_reg_td_tps_pwr_ofs *
2554 eq_reg_td_tps_pwr_ofs);
2555 /* log(x) x = 16bits * 7bits->23 bits */
2556 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2557 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2558 c = log10times100(sqr_err_iq);
2562 *p_signal_to_noise = i_mer;
2566 pr_err("Error %d on %s\n", status, __func__);
2570 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2574 *p_signal_to_noise = 0;
2575 switch (state->m_operation_mode) {
2577 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2580 return get_qam_signal_to_noise(state, p_signal_to_noise);
2588 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2590 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2595 static s32 QE_SN[] = {
2601 108, /* 16-QAM 1/2 */
2602 131, /* 16-QAM 2/3 */
2603 146, /* 16-QAM 3/4 */
2604 156, /* 16-QAM 5/6 */
2605 160, /* 16-QAM 7/8 */
2606 165, /* 64-QAM 1/2 */
2607 187, /* 64-QAM 2/3 */
2608 202, /* 64-QAM 3/4 */
2609 216, /* 64-QAM 5/6 */
2610 225, /* 64-QAM 7/8 */
2616 s32 signal_to_noise = 0;
2617 u16 constellation = 0;
2619 u32 signal_to_noise_rel;
2622 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2625 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2629 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2631 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2635 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2637 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2638 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2640 signal_to_noise_rel = signal_to_noise -
2641 QE_SN[constellation * 5 + code_rate];
2644 if (signal_to_noise_rel < -70)
2646 else if (signal_to_noise_rel < 30)
2647 *p_quality = ((signal_to_noise_rel + 70) *
2650 *p_quality = ber_quality;
2655 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2663 u32 signal_to_noise = 0;
2664 u32 ber_quality = 100;
2665 u32 signal_to_noise_rel = 0;
2667 status = get_qam_signal_to_noise(state, &signal_to_noise);
2671 switch (state->props.modulation) {
2673 signal_to_noise_rel = signal_to_noise - 200;
2676 signal_to_noise_rel = signal_to_noise - 230;
2677 break; /* Not in NorDig */
2679 signal_to_noise_rel = signal_to_noise - 260;
2682 signal_to_noise_rel = signal_to_noise - 290;
2686 signal_to_noise_rel = signal_to_noise - 320;
2690 if (signal_to_noise_rel < -70)
2692 else if (signal_to_noise_rel < 30)
2693 *p_quality = ((signal_to_noise_rel + 70) *
2696 *p_quality = ber_quality;
2702 static int get_quality(struct drxk_state *state, s32 *p_quality)
2706 switch (state->m_operation_mode) {
2708 return get_dvbt_quality(state, p_quality);
2710 return get_dvbc_quality(state, p_quality);
2719 /* Free data ram in SIO HI */
2720 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2721 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2723 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2724 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2725 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2726 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2728 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2729 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2730 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2732 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2734 int status = -EINVAL;
2738 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2740 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2743 if (state->no_i2c_bridge)
2746 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2747 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2750 if (b_enable_bridge) {
2751 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2752 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2756 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2757 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2762 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2766 pr_err("Error %d on %s\n", status, __func__);
2770 static int set_pre_saw(struct drxk_state *state,
2771 struct s_cfg_pre_saw *p_pre_saw_cfg)
2773 int status = -EINVAL;
2777 if ((p_pre_saw_cfg == NULL)
2778 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2781 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2784 pr_err("Error %d on %s\n", status, __func__);
2788 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2789 u16 rom_offset, u16 nr_of_elements, u32 time_out)
2792 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2793 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2799 mutex_lock(&state->mutex);
2800 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2803 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2806 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2809 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2812 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2815 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2819 end = jiffies + msecs_to_jiffies(time_out);
2821 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2824 } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2825 if (bl_status == 0x1) {
2826 pr_err("SIO not ready\n");
2832 pr_err("Error %d on %s\n", status, __func__);
2834 mutex_unlock(&state->mutex);
2839 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2846 /* start measurement */
2847 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2850 status = write16(state, IQM_AF_START_LOCK__A, 1);
2855 status = read16(state, IQM_AF_PHASE0__A, &data);
2859 *count = *count + 1;
2860 status = read16(state, IQM_AF_PHASE1__A, &data);
2864 *count = *count + 1;
2865 status = read16(state, IQM_AF_PHASE2__A, &data);
2869 *count = *count + 1;
2873 pr_err("Error %d on %s\n", status, __func__);
2877 static int adc_synchronization(struct drxk_state *state)
2884 status = adc_sync_measurement(state, &count);
2889 /* Try sampling on a different edge */
2892 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2895 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2896 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2897 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2899 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2901 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2903 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2905 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2908 status = adc_sync_measurement(state, &count);
2917 pr_err("Error %d on %s\n", status, __func__);
2921 static int set_frequency_shifter(struct drxk_state *state,
2922 u16 intermediate_freqk_hz,
2923 s32 tuner_freq_offset, bool is_dtv)
2925 bool select_pos_image = false;
2926 u32 rf_freq_residual = tuner_freq_offset;
2927 u32 fm_frequency_shift = 0;
2928 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2933 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2934 u32 frequency_shift;
2935 bool image_to_select;
2940 Program frequency shifter
2941 No need to account for mirroring on RF
2944 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2945 (state->m_operation_mode == OM_QAM_ITU_C) ||
2946 (state->m_operation_mode == OM_DVBT))
2947 select_pos_image = true;
2949 select_pos_image = false;
2952 /* tuner doesn't mirror */
2953 if_freq_actual = intermediate_freqk_hz +
2954 rf_freq_residual + fm_frequency_shift;
2957 if_freq_actual = intermediate_freqk_hz -
2958 rf_freq_residual - fm_frequency_shift;
2959 if (if_freq_actual > sampling_frequency / 2) {
2961 adc_freq = sampling_frequency - if_freq_actual;
2964 /* adc doesn't mirror */
2965 adc_freq = if_freq_actual;
2969 frequency_shift = adc_freq;
2970 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2971 adc_flip ^ select_pos_image;
2972 state->m_iqm_fs_rate_ofs =
2973 Frac28a((frequency_shift), sampling_frequency);
2975 if (image_to_select)
2976 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2978 /* Program frequency shifter with tuner offset compensation */
2979 /* frequency_shift += tuner_freq_offset; TODO */
2980 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2981 state->m_iqm_fs_rate_ofs);
2983 pr_err("Error %d on %s\n", status, __func__);
2987 static int init_agc(struct drxk_state *state, bool is_dtv)
2990 u16 ingain_tgt_min = 0;
2991 u16 ingain_tgt_max = 0;
2993 u16 clp_sum_min = 0;
2995 u16 sns_sum_min = 0;
2996 u16 sns_sum_max = 0;
2997 u16 clp_sum_max = 0;
2999 u16 ki_innergain_min = 0;
3000 u16 if_iaccu_hi_tgt = 0;
3001 u16 if_iaccu_hi_tgt_min = 0;
3002 u16 if_iaccu_hi_tgt_max = 0;
3004 u16 fast_clp_ctrl_delay = 0;
3005 u16 clp_ctrl_mode = 0;
3010 /* Common settings */
3012 if_iaccu_hi_tgt_min = 2047;
3016 /* AGCInit() not available for DVBT; init done in microcode */
3017 if (!is_qam(state)) {
3018 pr_err("%s: mode %d is not DVB-C\n",
3019 __func__, state->m_operation_mode);
3023 /* FIXME: Analog TV AGC require different settings */
3025 /* Standard specific settings */
3027 clp_dir_to = (u16) -9;
3030 sns_dir_to = (u16) -9;
3031 ki_innergain_min = (u16) -1030;
3032 if_iaccu_hi_tgt_max = 0x2380;
3033 if_iaccu_hi_tgt = 0x2380;
3034 ingain_tgt_min = 0x0511;
3035 ingain_tgt = 0x0511;
3036 ingain_tgt_max = 5119;
3037 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3039 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3040 fast_clp_ctrl_delay);
3044 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3047 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3050 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3053 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3056 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3057 if_iaccu_hi_tgt_min);
3060 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3061 if_iaccu_hi_tgt_max);
3064 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3067 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3070 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3073 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3076 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3079 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3083 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3087 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3091 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3095 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3098 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3101 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3105 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3108 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3111 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3114 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3117 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3120 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3123 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3126 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3129 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3132 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3135 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3138 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3141 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3144 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3147 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3150 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3153 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3156 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3159 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3163 /* Initialize inner-loop KI gain factors */
3164 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3169 data &= ~SCU_RAM_AGC_KI_RF__M;
3170 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3171 data &= ~SCU_RAM_AGC_KI_IF__M;
3172 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3174 status = write16(state, SCU_RAM_AGC_KI__A, data);
3177 pr_err("Error %d on %s\n", status, __func__);
3181 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3186 if (packet_err == NULL)
3187 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3189 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3192 pr_err("Error %d on %s\n", status, __func__);
3196 static int dvbt_sc_command(struct drxk_state *state,
3197 u16 cmd, u16 subcmd,
3198 u16 param0, u16 param1, u16 param2,
3199 u16 param3, u16 param4)
3208 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3210 /* SC is not running */
3216 /* Wait until sc is ready to receive command */
3219 usleep_range(1000, 2000);
3220 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3222 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3223 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3226 /* Write sub-command */
3228 /* All commands using sub-cmd */
3229 case OFDM_SC_RA_RAM_CMD_PROC_START:
3230 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3231 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3232 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3241 /* Write needed parameters and the command */
3244 /* All commands using 5 parameters */
3245 /* All commands using 4 parameters */
3246 /* All commands using 3 parameters */
3247 /* All commands using 2 parameters */
3248 case OFDM_SC_RA_RAM_CMD_PROC_START:
3249 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3250 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3251 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3252 fallthrough; /* All commands using 1 parameters */
3253 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3254 case OFDM_SC_RA_RAM_CMD_USER_IO:
3255 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3256 fallthrough; /* All commands using 0 parameters */
3257 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3258 case OFDM_SC_RA_RAM_CMD_NULL:
3260 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3263 /* Unknown command */
3269 /* Wait until sc is ready processing command */
3272 usleep_range(1000, 2000);
3273 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3275 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3276 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3279 /* Check for illegal cmd */
3280 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3281 if (err_code == 0xFFFF) {
3282 /* illegal command */
3288 /* Retrieve results parameters from SC */
3290 /* All commands yielding 5 results */
3291 /* All commands yielding 4 results */
3292 /* All commands yielding 3 results */
3293 /* All commands yielding 2 results */
3294 /* All commands yielding 1 result */
3295 case OFDM_SC_RA_RAM_CMD_USER_IO:
3296 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3297 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3298 /* All commands yielding 0 results */
3299 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3300 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3301 case OFDM_SC_RA_RAM_CMD_PROC_START:
3302 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3303 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3304 case OFDM_SC_RA_RAM_CMD_NULL:
3307 /* Unknown command */
3310 } /* switch (cmd->cmd) */
3313 pr_err("Error %d on %s\n", status, __func__);
3317 static int power_up_dvbt(struct drxk_state *state)
3319 enum drx_power_mode power_mode = DRX_POWER_UP;
3323 status = ctrl_power_mode(state, &power_mode);
3325 pr_err("Error %d on %s\n", status, __func__);
3329 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3335 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3337 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3339 pr_err("Error %d on %s\n", status, __func__);
3343 #define DEFAULT_FR_THRES_8K 4000
3344 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3351 /* write mask to 1 */
3352 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3353 DEFAULT_FR_THRES_8K);
3355 /* write mask to 0 */
3356 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3359 pr_err("Error %d on %s\n", status, __func__);
3364 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3365 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3371 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3375 switch (echo_thres->fft_mode) {
3376 case DRX_FFTMODE_2K:
3377 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3378 data |= ((echo_thres->threshold <<
3379 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3380 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3382 case DRX_FFTMODE_8K:
3383 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3384 data |= ((echo_thres->threshold <<
3385 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3386 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3392 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3395 pr_err("Error %d on %s\n", status, __func__);
3399 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3400 enum drxk_cfg_dvbt_sqi_speed *speed)
3402 int status = -EINVAL;
3407 case DRXK_DVBT_SQI_SPEED_FAST:
3408 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3409 case DRXK_DVBT_SQI_SPEED_SLOW:
3414 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3418 pr_err("Error %d on %s\n", status, __func__);
3422 /*============================================================================*/
3425 * \brief Activate DVBT specific presets
3426 * \param demod instance of demodulator.
3427 * \return DRXStatus_t.
3429 * Called in DVBTSetStandard
3432 static int dvbt_activate_presets(struct drxk_state *state)
3435 bool setincenable = false;
3436 bool setfrenable = true;
3438 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3439 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3442 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3445 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3448 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3451 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3454 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3455 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3458 pr_err("Error %d on %s\n", status, __func__);
3462 /*============================================================================*/
3465 * \brief Initialize channelswitch-independent settings for DVBT.
3466 * \param demod instance of demodulator.
3467 * \return DRXStatus_t.
3469 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3470 * the DVB-T taps from the drxk_filters.h are used.
3472 static int set_dvbt_standard(struct drxk_state *state,
3473 enum operation_mode o_mode)
3481 power_up_dvbt(state);
3482 /* added antenna switch */
3483 switch_antenna_to_dvbt(state);
3484 /* send OFDM reset command */
3485 status = scu_command(state,
3486 SCU_RAM_COMMAND_STANDARD_OFDM
3487 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3488 0, NULL, 1, &cmd_result);
3492 /* send OFDM setenv command */
3493 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3494 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3495 0, NULL, 1, &cmd_result);
3499 /* reset datapath for OFDM, processors first */
3500 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3503 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3506 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3511 /* synchronize on ofdstate->m_festart */
3512 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3515 /* window size for clipping ADC detection */
3516 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3519 /* window size for for sense pre-SAW detection */
3520 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3523 /* sense threshold for sense pre-SAW detection */
3524 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3527 status = set_iqm_af(state, true);
3531 status = write16(state, IQM_AF_AGC_RF__A, 0);
3535 /* Impulse noise cruncher setup */
3536 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3539 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3542 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3546 status = write16(state, IQM_RC_STRETCH__A, 16);
3549 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3552 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3555 status = write16(state, IQM_CF_SCALE__A, 1600);
3558 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3562 /* virtual clipping threshold for clipping ADC detection */
3563 status = write16(state, IQM_AF_CLP_TH__A, 448);
3566 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3570 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3571 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3575 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3578 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3581 /* enable power measurement interrupt */
3582 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3585 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3589 /* IQM will not be reset from here, sync ADC and update/init AGC */
3590 status = adc_synchronization(state);
3593 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3597 /* Halt SCU to enable safe non-atomic accesses */
3598 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3602 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3605 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3609 /* Set Noise Estimation notch width and enable DC fix */
3610 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3613 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3614 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3618 /* Activate SCU to enable SCU commands */
3619 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3623 if (!state->m_drxk_a3_rom_code) {
3624 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
3625 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3626 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3632 #ifdef COMPILE_FOR_NONRT
3633 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3636 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3642 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3647 #ifdef COMPILE_FOR_NONRT
3648 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3652 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3656 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3660 /* Setup MPEG bus */
3661 status = mpegts_dto_setup(state, OM_DVBT);
3664 /* Set DVBT Presets */
3665 status = dvbt_activate_presets(state);
3671 pr_err("Error %d on %s\n", status, __func__);
3675 /*============================================================================*/
3677 * \brief start dvbt demodulating for channel.
3678 * \param demod instance of demodulator.
3679 * \return DRXStatus_t.
3681 static int dvbt_start(struct drxk_state *state)
3685 /* drxk_ofdm_sc_cmd_t scCmd; */
3688 /* start correct processes to get in lock */
3689 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3690 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3691 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3692 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3697 status = mpegts_start(state);
3700 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3705 pr_err("Error %d on %s\n", status, __func__);
3710 /*============================================================================*/
3713 * \brief Set up dvbt demodulator for channel.
3714 * \param demod instance of demodulator.
3715 * \return DRXStatus_t.
3716 * // original DVBTSetChannel()
3718 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3719 s32 tuner_freq_offset)
3722 u16 transmission_params = 0;
3723 u16 operation_mode = 0;
3724 u32 iqm_rc_rate_ofs = 0;
3729 dprintk(1, "IF =%d, TFO = %d\n",
3730 intermediate_freqk_hz, tuner_freq_offset);
3732 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3733 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3734 0, NULL, 1, &cmd_result);
3738 /* Halt SCU to enable safe non-atomic accesses */
3739 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3743 /* Stop processors */
3744 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3747 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3751 /* Mandatory fix, always stop CP, required to set spl offset back to
3752 hardware default (is set to 0 by ucode during pilot detection */
3753 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3757 /*== Write channel settings to device ================================*/
3760 switch (state->props.transmission_mode) {
3761 case TRANSMISSION_MODE_AUTO:
3763 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3764 fallthrough; /* try first guess DRX_FFTMODE_8K */
3765 case TRANSMISSION_MODE_8K:
3766 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3768 case TRANSMISSION_MODE_2K:
3769 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3774 switch (state->props.guard_interval) {
3776 case GUARD_INTERVAL_AUTO:
3777 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3778 fallthrough; /* try first guess DRX_GUARD_1DIV4 */
3779 case GUARD_INTERVAL_1_4:
3780 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3782 case GUARD_INTERVAL_1_32:
3783 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3785 case GUARD_INTERVAL_1_16:
3786 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3788 case GUARD_INTERVAL_1_8:
3789 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3794 switch (state->props.hierarchy) {
3795 case HIERARCHY_AUTO:
3796 case HIERARCHY_NONE:
3798 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3799 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3800 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3803 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3806 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3809 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3815 switch (state->props.modulation) {
3818 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3819 fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */
3821 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3824 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3827 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3831 /* No hierarchical channels support in BDA */
3832 /* Priority (only for hierarchical channels) */
3833 switch (channel->priority) {
3834 case DRX_PRIORITY_LOW:
3835 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3836 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3837 OFDM_EC_SB_PRIOR_LO);
3839 case DRX_PRIORITY_HIGH:
3840 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3841 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3842 OFDM_EC_SB_PRIOR_HI));
3844 case DRX_PRIORITY_UNKNOWN:
3850 /* Set Priority high */
3851 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3852 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3858 switch (state->props.code_rate_HP) {
3861 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3862 fallthrough; /* try first guess DRX_CODERATE_2DIV3 */
3864 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3867 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3870 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3873 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3876 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3881 * SAW filter selection: normally not necessary, but if wanted
3882 * the application can select a SAW filter via the driver by
3886 /* First determine real bandwidth (Hz) */
3887 /* Also set delay for impulse noise cruncher */
3889 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3890 * changed by SC for fix for some 8K,1/8 guard but is restored by
3891 * InitEC and ResetEC functions
3893 switch (state->props.bandwidth_hz) {
3895 state->props.bandwidth_hz = 8000000;
3898 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3899 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3903 /* cochannel protection for PAL 8 MHz */
3904 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3908 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3912 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3916 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3922 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3923 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3927 /* cochannel protection for PAL 7 MHz */
3928 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3932 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3936 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3940 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3946 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3947 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3951 /* cochannel protection for NTSC 6 MHz */
3952 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3956 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3964 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3974 if (iqm_rc_rate_ofs == 0) {
3975 /* Now compute IQM_RC_RATE_OFS
3976 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3978 ((SysFreq / BandWidth) * (2^21)) - (2^23)
3980 /* (SysFreq / BandWidth) * (2^28) */
3982 * assert (MAX(sysClk)/MIN(bandwidth) < 16)
3983 * => assert(MAX(sysClk) < 16*MIN(bandwidth))
3984 * => assert(109714272 > 48000000) = true
3985 * so Frac 28 can be used
3987 iqm_rc_rate_ofs = Frac28a((u32)
3988 ((state->m_sys_clock_freq *
3989 1000) / 3), bandwidth);
3990 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3991 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3992 iqm_rc_rate_ofs += 0x80L;
3993 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3994 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
3995 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3999 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4000 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4001 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4005 /* Bandwidth setting done */
4008 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4012 status = set_frequency_shifter(state, intermediate_freqk_hz,
4013 tuner_freq_offset, true);
4017 /*== start SC, write channel settings to SC ==========================*/
4019 /* Activate SCU to enable SCU commands */
4020 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4024 /* Enable SC after setting all other parameters */
4025 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4028 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4033 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4034 | SCU_RAM_COMMAND_CMD_DEMOD_START,
4035 0, NULL, 1, &cmd_result);
4039 /* Write SC parameter registers, set all AUTO flags in operation mode */
4040 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4041 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4042 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4043 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4044 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4045 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4046 0, transmission_params, param1, 0, 0, 0);
4050 if (!state->m_drxk_a3_rom_code)
4051 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4054 pr_err("Error %d on %s\n", status, __func__);
4060 /*============================================================================*/
4063 * \brief Retrieve lock status .
4064 * \param demod Pointer to demodulator instance.
4065 * \param lockStat Pointer to lock status structure.
4066 * \return DRXStatus_t.
4069 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4072 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4073 OFDM_SC_RA_RAM_LOCK_FEC__M);
4074 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4075 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4077 u16 sc_ra_ram_lock = 0;
4078 u16 sc_comm_exec = 0;
4082 *p_lock_status = NOT_LOCKED;
4084 /* Check if SC is running */
4085 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4088 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4091 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4095 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4096 *p_lock_status = MPEG_LOCK;
4097 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4098 *p_lock_status = FEC_LOCK;
4099 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4100 *p_lock_status = DEMOD_LOCK;
4101 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4102 *p_lock_status = NEVER_LOCK;
4105 pr_err("Error %d on %s\n", status, __func__);
4110 static int power_up_qam(struct drxk_state *state)
4112 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4116 status = ctrl_power_mode(state, &power_mode);
4118 pr_err("Error %d on %s\n", status, __func__);
4124 /* Power Down QAM */
4125 static int power_down_qam(struct drxk_state *state)
4132 status = read16(state, SCU_COMM_EXEC__A, &data);
4135 if (data == SCU_COMM_EXEC_ACTIVE) {
4140 /* stop all comstate->m_exec */
4141 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4144 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4145 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4146 0, NULL, 1, &cmd_result);
4151 status = set_iqm_af(state, false);
4155 pr_err("Error %d on %s\n", status, __func__);
4160 /*============================================================================*/
4163 * \brief Setup of the QAM Measurement intervals for signal quality
4164 * \param demod instance of demod.
4165 * \param modulation current modulation.
4166 * \return DRXStatus_t.
4169 * Take into account that for certain settings the errorcounters can overflow.
4170 * The implementation does not check this.
4173 static int set_qam_measurement(struct drxk_state *state,
4174 enum e_drxk_constellation modulation,
4177 u32 fec_bits_desired = 0; /* BER accounting period */
4178 u32 fec_rs_period_total = 0; /* Total period */
4179 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
4180 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
4185 fec_rs_prescale = 1;
4186 /* fec_bits_desired = symbol_rate [kHz] *
4192 switch (modulation) {
4193 case DRX_CONSTELLATION_QAM16:
4194 fec_bits_desired = 4 * symbol_rate;
4196 case DRX_CONSTELLATION_QAM32:
4197 fec_bits_desired = 5 * symbol_rate;
4199 case DRX_CONSTELLATION_QAM64:
4200 fec_bits_desired = 6 * symbol_rate;
4202 case DRX_CONSTELLATION_QAM128:
4203 fec_bits_desired = 7 * symbol_rate;
4205 case DRX_CONSTELLATION_QAM256:
4206 fec_bits_desired = 8 * symbol_rate;
4214 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
4215 fec_bits_desired *= 500; /* meas. period [ms] */
4217 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4218 /* fec_rs_period_total = fec_bits_desired / 1632 */
4219 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */
4221 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */
4222 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4223 if (fec_rs_prescale == 0) {
4224 /* Divide by zero (though impossible) */
4230 ((u16) fec_rs_period_total +
4231 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4233 /* write corresponding registers */
4234 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4237 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4241 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4244 pr_err("Error %d on %s\n", status, __func__);
4248 static int set_qam16(struct drxk_state *state)
4253 /* QAM Equalizer Setup */
4255 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4258 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4261 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4264 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4267 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4270 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4273 /* Decision Feedback Equalizer */
4274 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4277 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4280 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4283 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4286 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4289 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4293 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4296 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4299 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4303 /* QAM Slicer Settings */
4304 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4305 DRXK_QAM_SL_SIG_POWER_QAM16);
4309 /* QAM Loop Controller Coeficients */
4310 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4313 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4316 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4319 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4322 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4325 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4328 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4331 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4335 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4338 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4341 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4344 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4347 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4350 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4353 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4356 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4359 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4362 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4365 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4368 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4373 /* QAM State Machine (FSM) Thresholds */
4375 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4378 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4381 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4384 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4387 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4390 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4394 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4397 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4400 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4405 /* QAM FSM Tracking Parameters */
4407 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4410 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4413 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4416 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4419 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4422 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4425 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4431 pr_err("Error %d on %s\n", status, __func__);
4435 /*============================================================================*/
4438 * \brief QAM32 specific setup
4439 * \param demod instance of demod.
4440 * \return DRXStatus_t.
4442 static int set_qam32(struct drxk_state *state)
4448 /* QAM Equalizer Setup */
4450 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4453 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4456 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4459 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4462 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4465 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4469 /* Decision Feedback Equalizer */
4470 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4473 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4476 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4479 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4482 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4485 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4489 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4492 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4495 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4499 /* QAM Slicer Settings */
4501 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4502 DRXK_QAM_SL_SIG_POWER_QAM32);
4507 /* QAM Loop Controller Coeficients */
4509 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4512 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4515 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4518 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4521 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4524 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4527 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4530 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4534 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4537 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4540 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4543 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4546 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4549 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4552 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4555 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4558 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4561 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4564 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4567 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4572 /* QAM State Machine (FSM) Thresholds */
4574 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4577 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4580 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4583 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4586 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4589 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4593 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4596 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4599 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4604 /* QAM FSM Tracking Parameters */
4606 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4609 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4612 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4615 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4618 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4621 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4624 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4627 pr_err("Error %d on %s\n", status, __func__);
4631 /*============================================================================*/
4634 * \brief QAM64 specific setup
4635 * \param demod instance of demod.
4636 * \return DRXStatus_t.
4638 static int set_qam64(struct drxk_state *state)
4643 /* QAM Equalizer Setup */
4645 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4648 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4651 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4654 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4657 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4660 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4664 /* Decision Feedback Equalizer */
4665 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4668 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4671 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4674 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4677 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4680 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4684 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4687 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4690 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4694 /* QAM Slicer Settings */
4695 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4696 DRXK_QAM_SL_SIG_POWER_QAM64);
4701 /* QAM Loop Controller Coeficients */
4703 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4706 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4709 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4712 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4715 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4718 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4721 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4724 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4728 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4731 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4734 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4737 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4740 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4743 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4746 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4749 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4752 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4755 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4758 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4761 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4766 /* QAM State Machine (FSM) Thresholds */
4768 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4771 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4774 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4777 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4780 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4783 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4787 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4790 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4793 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4798 /* QAM FSM Tracking Parameters */
4800 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4803 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4806 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4809 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4812 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4815 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4818 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4821 pr_err("Error %d on %s\n", status, __func__);
4826 /*============================================================================*/
4829 * \brief QAM128 specific setup
4830 * \param demod: instance of demod.
4831 * \return DRXStatus_t.
4833 static int set_qam128(struct drxk_state *state)
4838 /* QAM Equalizer Setup */
4840 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4843 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4846 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4849 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4852 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4855 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4859 /* Decision Feedback Equalizer */
4860 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4863 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4866 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4869 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4872 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4875 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4879 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4882 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4885 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4890 /* QAM Slicer Settings */
4892 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4893 DRXK_QAM_SL_SIG_POWER_QAM128);
4898 /* QAM Loop Controller Coeficients */
4900 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4903 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4906 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4909 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4912 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4915 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4918 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4921 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4925 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4928 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4931 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4934 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4937 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4940 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4943 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4946 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4949 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4952 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4955 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4958 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4963 /* QAM State Machine (FSM) Thresholds */
4965 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4968 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4971 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4974 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4977 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4980 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4984 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4987 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4991 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4995 /* QAM FSM Tracking Parameters */
4997 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5000 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5003 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5006 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5009 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5012 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5015 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5018 pr_err("Error %d on %s\n", status, __func__);
5023 /*============================================================================*/
5026 * \brief QAM256 specific setup
5027 * \param demod: instance of demod.
5028 * \return DRXStatus_t.
5030 static int set_qam256(struct drxk_state *state)
5035 /* QAM Equalizer Setup */
5037 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5040 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5043 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5046 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5049 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5052 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5056 /* Decision Feedback Equalizer */
5057 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5060 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5063 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5066 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5069 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5072 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5076 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5079 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5082 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5086 /* QAM Slicer Settings */
5088 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5089 DRXK_QAM_SL_SIG_POWER_QAM256);
5094 /* QAM Loop Controller Coeficients */
5096 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5099 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5102 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5105 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5108 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5111 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5114 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5117 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5121 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5124 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5127 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5130 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5133 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5136 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5139 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5142 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5145 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5148 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5151 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5154 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5159 /* QAM State Machine (FSM) Thresholds */
5161 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5164 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5167 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5170 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5173 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5176 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5180 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5183 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5186 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5191 /* QAM FSM Tracking Parameters */
5193 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5196 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5199 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5202 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5205 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5208 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5211 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5214 pr_err("Error %d on %s\n", status, __func__);
5219 /*============================================================================*/
5221 * \brief Reset QAM block.
5222 * \param demod: instance of demod.
5223 * \param channel: pointer to channel data.
5224 * \return DRXStatus_t.
5226 static int qam_reset_qam(struct drxk_state *state)
5232 /* Stop QAM comstate->m_exec */
5233 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5237 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5238 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5239 0, NULL, 1, &cmd_result);
5242 pr_err("Error %d on %s\n", status, __func__);
5246 /*============================================================================*/
5249 * \brief Set QAM symbolrate.
5250 * \param demod: instance of demod.
5251 * \param channel: pointer to channel data.
5252 * \return DRXStatus_t.
5254 static int qam_set_symbolrate(struct drxk_state *state)
5256 u32 adc_frequency = 0;
5258 u32 iqm_rc_rate = 0;
5260 u32 lc_symb_rate = 0;
5264 /* Select & calculate correct IQM rate */
5265 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5267 if (state->props.symbol_rate <= 1188750)
5269 else if (state->props.symbol_rate <= 2377500)
5271 else if (state->props.symbol_rate <= 4755000)
5273 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5278 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5280 symb_freq = state->props.symbol_rate * (1 << ratesel);
5281 if (symb_freq == 0) {
5282 /* Divide by zero */
5286 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5287 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5289 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5292 state->m_iqm_rc_rate = iqm_rc_rate;
5294 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15))
5296 symb_freq = state->props.symbol_rate;
5297 if (adc_frequency == 0) {
5298 /* Divide by zero */
5302 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5303 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5305 if (lc_symb_rate > 511)
5307 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5311 pr_err("Error %d on %s\n", status, __func__);
5315 /*============================================================================*/
5318 * \brief Get QAM lock status.
5319 * \param demod: instance of demod.
5320 * \param channel: pointer to channel data.
5321 * \return DRXStatus_t.
5324 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5327 u16 result[2] = { 0, 0 };
5330 *p_lock_status = NOT_LOCKED;
5331 status = scu_command(state,
5332 SCU_RAM_COMMAND_STANDARD_QAM |
5333 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5336 pr_err("Error %d on %s\n", status, __func__);
5338 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5339 /* 0x0000 NOT LOCKED */
5340 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5341 /* 0x4000 DEMOD LOCKED */
5342 *p_lock_status = DEMOD_LOCK;
5343 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5344 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5345 *p_lock_status = MPEG_LOCK;
5347 /* 0xC000 NEVER LOCKED */
5348 /* (system will never be able to lock to the signal) */
5350 * TODO: check this, intermediate & standard specific lock
5351 * states are not taken into account here
5353 *p_lock_status = NEVER_LOCK;
5358 #define QAM_MIRROR__M 0x03
5359 #define QAM_MIRROR_NORMAL 0x00
5360 #define QAM_MIRRORED 0x01
5361 #define QAM_MIRROR_AUTO_ON 0x02
5362 #define QAM_LOCKRANGE__M 0x10
5363 #define QAM_LOCKRANGE_NORMAL 0x10
5365 static int qam_demodulator_command(struct drxk_state *state,
5366 int number_of_parameters)
5370 u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5372 set_param_parameters[0] = state->m_constellation; /* modulation */
5373 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5375 if (number_of_parameters == 2) {
5376 u16 set_env_parameters[1] = { 0 };
5378 if (state->m_operation_mode == OM_QAM_ITU_C)
5379 set_env_parameters[0] = QAM_TOP_ANNEX_C;
5381 set_env_parameters[0] = QAM_TOP_ANNEX_A;
5383 status = scu_command(state,
5384 SCU_RAM_COMMAND_STANDARD_QAM
5385 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5386 1, set_env_parameters, 1, &cmd_result);
5390 status = scu_command(state,
5391 SCU_RAM_COMMAND_STANDARD_QAM
5392 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5393 number_of_parameters, set_param_parameters,
5395 } else if (number_of_parameters == 4) {
5396 if (state->m_operation_mode == OM_QAM_ITU_C)
5397 set_param_parameters[2] = QAM_TOP_ANNEX_C;
5399 set_param_parameters[2] = QAM_TOP_ANNEX_A;
5401 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5402 /* Env parameters */
5403 /* check for LOCKRANGE Extended */
5404 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5406 status = scu_command(state,
5407 SCU_RAM_COMMAND_STANDARD_QAM
5408 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5409 number_of_parameters, set_param_parameters,
5412 pr_warn("Unknown QAM demodulator parameter count %d\n",
5413 number_of_parameters);
5419 pr_warn("Warning %d on %s\n", status, __func__);
5423 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5424 s32 tuner_freq_offset)
5428 int qam_demod_param_count = state->qam_demod_parameter_count;
5432 * STEP 1: reset demodulator
5433 * resets FEC DI and FEC RS
5435 * resets SCU variables
5437 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5440 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5443 status = qam_reset_qam(state);
5448 * STEP 2: configure demodulator
5449 * -set params; resets IQM,QAM,FEC HW; initializes some
5452 status = qam_set_symbolrate(state);
5457 switch (state->props.modulation) {
5459 state->m_constellation = DRX_CONSTELLATION_QAM256;
5463 state->m_constellation = DRX_CONSTELLATION_QAM64;
5466 state->m_constellation = DRX_CONSTELLATION_QAM16;
5469 state->m_constellation = DRX_CONSTELLATION_QAM32;
5472 state->m_constellation = DRX_CONSTELLATION_QAM128;
5481 /* Use the 4-parameter if it's requested or we're probing for
5482 * the correct command. */
5483 if (state->qam_demod_parameter_count == 4
5484 || !state->qam_demod_parameter_count) {
5485 qam_demod_param_count = 4;
5486 status = qam_demodulator_command(state, qam_demod_param_count);
5489 /* Use the 2-parameter command if it was requested or if we're
5490 * probing for the correct command and the 4-parameter command
5492 if (state->qam_demod_parameter_count == 2
5493 || (!state->qam_demod_parameter_count && status < 0)) {
5494 qam_demod_param_count = 2;
5495 status = qam_demodulator_command(state, qam_demod_param_count);
5499 dprintk(1, "Could not set demodulator parameters.\n");
5501 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5502 state->qam_demod_parameter_count,
5503 state->microcode_name);
5505 } else if (!state->qam_demod_parameter_count) {
5507 "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5508 qam_demod_param_count);
5511 * One of our commands was successful. We don't need to
5512 * auto-probe anymore, now that we got the correct command.
5514 state->qam_demod_parameter_count = qam_demod_param_count;
5518 * STEP 3: enable the system in a mode where the ADC provides valid
5519 * signal setup modulation independent registers
5522 status = set_frequency(channel, tuner_freq_offset));
5526 status = set_frequency_shifter(state, intermediate_freqk_hz,
5527 tuner_freq_offset, true);
5531 /* Setup BER measurement */
5532 status = set_qam_measurement(state, state->m_constellation,
5533 state->props.symbol_rate);
5537 /* Reset default values */
5538 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5541 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5545 /* Reset default LC values */
5546 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5549 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5552 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5555 status = write16(state, QAM_LC_MODE__A, 7);
5559 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5562 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5565 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5568 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5571 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5574 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5577 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5580 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5583 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5586 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5589 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5592 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5595 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5598 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5601 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5605 /* Mirroring, QAM-block starting point not inverted */
5606 status = write16(state, QAM_SY_SP_INV__A,
5607 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5611 /* Halt SCU to enable safe non-atomic accesses */
5612 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5616 /* STEP 4: modulation specific setup */
5617 switch (state->props.modulation) {
5619 status = set_qam16(state);
5622 status = set_qam32(state);
5626 status = set_qam64(state);
5629 status = set_qam128(state);
5632 status = set_qam256(state);
5641 /* Activate SCU to enable SCU commands */
5642 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5646 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5647 /* extAttr->currentChannel.modulation = channel->modulation; */
5648 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5649 status = mpegts_dto_setup(state, state->m_operation_mode);
5653 /* start processes */
5654 status = mpegts_start(state);
5657 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5660 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5663 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5667 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5668 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5669 | SCU_RAM_COMMAND_CMD_DEMOD_START,
5670 0, NULL, 1, &cmd_result);
5674 /* update global DRXK data container */
5675 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5679 pr_err("Error %d on %s\n", status, __func__);
5683 static int set_qam_standard(struct drxk_state *state,
5684 enum operation_mode o_mode)
5687 #ifdef DRXK_QAM_TAPS
5688 #define DRXK_QAMA_TAPS_SELECT
5689 #include "drxk_filters.h"
5690 #undef DRXK_QAMA_TAPS_SELECT
5695 /* added antenna switch */
5696 switch_antenna_to_qam(state);
5698 /* Ensure correct power-up mode */
5699 status = power_up_qam(state);
5702 /* Reset QAM block */
5703 status = qam_reset_qam(state);
5709 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5712 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5716 /* Upload IQM Channel Filter settings by
5717 boot loader from ROM table */
5720 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5721 DRXK_BLCC_NR_ELEMENTS_TAPS,
5725 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5726 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5727 DRXK_BLDC_NR_ELEMENTS_TAPS,
5731 status = bl_direct_cmd(state,
5733 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5734 DRXK_BLDC_NR_ELEMENTS_TAPS,
5743 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5746 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5749 status = write16(state, IQM_CF_MIDTAP__A,
5750 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5754 status = write16(state, IQM_RC_STRETCH__A, 21);
5757 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5760 status = write16(state, IQM_AF_CLP_TH__A, 448);
5763 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5766 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5770 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5773 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5776 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5779 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5783 /* IQM Impulse Noise Processing Unit */
5784 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5787 status = write16(state, IQM_CF_DATATH__A, 1000);
5790 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5793 status = write16(state, IQM_CF_DET_LCT__A, 0);
5796 status = write16(state, IQM_CF_WND_LEN__A, 1);
5799 status = write16(state, IQM_CF_PKDTH__A, 1);
5802 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5806 /* turn on IQMAF. Must be done before setAgc**() */
5807 status = set_iqm_af(state, true);
5810 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5814 /* IQM will not be reset from here, sync ADC and update/init AGC */
5815 status = adc_synchronization(state);
5819 /* Set the FSM step period */
5820 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5824 /* Halt SCU to enable safe non-atomic accesses */
5825 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5829 /* No more resets of the IQM, current standard correctly set =>
5830 now AGCs can be configured. */
5832 status = init_agc(state, true);
5835 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5839 /* Configure AGC's */
5840 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5843 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5847 /* Activate SCU to enable SCU commands */
5848 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5851 pr_err("Error %d on %s\n", status, __func__);
5855 static int write_gpio(struct drxk_state *state)
5861 /* stop lock indicator process */
5862 status = write16(state, SCU_RAM_GPIO__A,
5863 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5867 /* Write magic word to enable pdr reg write */
5868 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5872 if (state->m_has_sawsw) {
5873 if (state->uio_mask & 0x0001) { /* UIO-1 */
5874 /* write to io pad configuration register - output mode */
5875 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5880 /* use corresponding bit in io data output registar */
5881 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5884 if ((state->m_gpio & 0x0001) == 0)
5885 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5887 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5888 /* write back to io data output register */
5889 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5893 if (state->uio_mask & 0x0002) { /* UIO-2 */
5894 /* write to io pad configuration register - output mode */
5895 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5900 /* use corresponding bit in io data output registar */
5901 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5904 if ((state->m_gpio & 0x0002) == 0)
5905 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5907 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5908 /* write back to io data output register */
5909 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5913 if (state->uio_mask & 0x0004) { /* UIO-3 */
5914 /* write to io pad configuration register - output mode */
5915 status = write16(state, SIO_PDR_GPIO_CFG__A,
5920 /* use corresponding bit in io data output registar */
5921 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5924 if ((state->m_gpio & 0x0004) == 0)
5925 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5927 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5928 /* write back to io data output register */
5929 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5934 /* Write magic word to disable pdr reg write */
5935 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5938 pr_err("Error %d on %s\n", status, __func__);
5942 static int switch_antenna_to_qam(struct drxk_state *state)
5949 if (!state->antenna_gpio)
5952 gpio_state = state->m_gpio & state->antenna_gpio;
5954 if (state->antenna_dvbt ^ gpio_state) {
5955 /* Antenna is on DVB-T mode. Switch */
5956 if (state->antenna_dvbt)
5957 state->m_gpio &= ~state->antenna_gpio;
5959 state->m_gpio |= state->antenna_gpio;
5960 status = write_gpio(state);
5963 pr_err("Error %d on %s\n", status, __func__);
5967 static int switch_antenna_to_dvbt(struct drxk_state *state)
5974 if (!state->antenna_gpio)
5977 gpio_state = state->m_gpio & state->antenna_gpio;
5979 if (!(state->antenna_dvbt ^ gpio_state)) {
5980 /* Antenna is on DVB-C mode. Switch */
5981 if (state->antenna_dvbt)
5982 state->m_gpio |= state->antenna_gpio;
5984 state->m_gpio &= ~state->antenna_gpio;
5985 status = write_gpio(state);
5988 pr_err("Error %d on %s\n", status, __func__);
5993 static int power_down_device(struct drxk_state *state)
5995 /* Power down to requested mode */
5996 /* Backup some register settings */
5997 /* Set pins with possible pull-ups connected to them in input mode */
5998 /* Analog power down */
5999 /* ADC power down */
6000 /* Power down device */
6004 if (state->m_b_p_down_open_bridge) {
6005 /* Open I2C bridge before power down of DRXK */
6006 status = ConfigureI2CBridge(state, true);
6011 status = dvbt_enable_ofdm_token_ring(state, false);
6015 status = write16(state, SIO_CC_PWD_MODE__A,
6016 SIO_CC_PWD_MODE_LEVEL_CLOCK);
6019 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6022 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6023 status = hi_cfg_command(state);
6026 pr_err("Error %d on %s\n", status, __func__);
6031 static int init_drxk(struct drxk_state *state)
6033 int status = 0, n = 0;
6034 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6038 if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6039 drxk_i2c_lock(state);
6040 status = power_up_device(state);
6043 status = drxx_open(state);
6046 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6047 status = write16(state, SIO_CC_SOFT_RST__A,
6048 SIO_CC_SOFT_RST_OFDM__M
6049 | SIO_CC_SOFT_RST_SYS__M
6050 | SIO_CC_SOFT_RST_OSC__M);
6053 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6057 * TODO is this needed? If yes, how much delay in
6058 * worst case scenario
6060 usleep_range(1000, 2000);
6061 state->m_drxk_a3_patch_code = true;
6062 status = get_device_capabilities(state);
6066 /* Bridge delay, uses oscilator clock */
6067 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6068 /* SDA brdige delay */
6069 state->m_hi_cfg_bridge_delay =
6070 (u16) ((state->m_osc_clock_freq / 1000) *
6071 HI_I2C_BRIDGE_DELAY) / 1000;
6073 if (state->m_hi_cfg_bridge_delay >
6074 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6075 state->m_hi_cfg_bridge_delay =
6076 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6078 /* SCL bridge delay, same as SDA for now */
6079 state->m_hi_cfg_bridge_delay +=
6080 state->m_hi_cfg_bridge_delay <<
6081 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6083 status = init_hi(state);
6086 /* disable various processes */
6088 if (!(state->m_DRXK_A1_ROM_CODE)
6089 && !(state->m_DRXK_A2_ROM_CODE))
6092 status = write16(state, SCU_RAM_GPIO__A,
6093 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6098 /* disable MPEG port */
6099 status = mpegts_disable(state);
6103 /* Stop AUD and SCU */
6104 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6107 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6111 /* enable token-ring bus through OFDM block for possible ucode upload */
6112 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6113 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6117 /* include boot loader section */
6118 status = write16(state, SIO_BL_COMM_EXEC__A,
6119 SIO_BL_COMM_EXEC_ACTIVE);
6122 status = bl_chain_cmd(state, 0, 6, 100);
6127 status = download_microcode(state, state->fw->data,
6133 /* disable token-ring bus through OFDM block for possible ucode upload */
6134 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6135 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6139 /* Run SCU for a little while to initialize microcode version numbers */
6140 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6143 status = drxx_open(state);
6146 /* added for test */
6149 power_mode = DRXK_POWER_DOWN_OFDM;
6150 status = ctrl_power_mode(state, &power_mode);
6154 /* Stamp driver version number in SCU data RAM in BCD code
6155 Done to enable field application engineers to retrieve drxdriver version
6156 via I2C from SCU RAM.
6157 Not using SCU command interface for SCU register access since no
6158 microcode may be present.
6161 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6162 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6163 ((DRXK_VERSION_MAJOR % 10) << 4) +
6164 (DRXK_VERSION_MINOR % 10);
6165 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6170 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6171 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6172 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6173 (DRXK_VERSION_PATCH % 10);
6174 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6179 pr_info("DRXK driver version %d.%d.%d\n",
6180 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6181 DRXK_VERSION_PATCH);
6184 * Dirty fix of default values for ROM/PATCH microcode
6185 * Dirty because this fix makes it impossible to setup
6186 * suitable values before calling DRX_Open. This solution
6187 * requires changes to RF AGC speed to be done via the CTRL
6188 * function after calling DRX_Open
6191 /* m_dvbt_rf_agc_cfg.speed = 3; */
6193 /* Reset driver debug flags to 0 */
6194 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6199 NOTE: No more full FEC resets allowed afterwards!! */
6200 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6203 /* MPEGTS functions are still the same */
6204 status = mpegts_dto_init(state);
6207 status = mpegts_stop(state);
6210 status = mpegts_configure_polarity(state);
6213 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6216 /* added: configure GPIO */
6217 status = write_gpio(state);
6221 state->m_drxk_state = DRXK_STOPPED;
6223 if (state->m_b_power_down) {
6224 status = power_down_device(state);
6227 state->m_drxk_state = DRXK_POWERED_DOWN;
6229 state->m_drxk_state = DRXK_STOPPED;
6231 /* Initialize the supported delivery systems */
6233 if (state->m_has_dvbc) {
6234 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6235 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6236 strlcat(state->frontend.ops.info.name, " DVB-C",
6237 sizeof(state->frontend.ops.info.name));
6239 if (state->m_has_dvbt) {
6240 state->frontend.ops.delsys[n++] = SYS_DVBT;
6241 strlcat(state->frontend.ops.info.name, " DVB-T",
6242 sizeof(state->frontend.ops.info.name));
6244 drxk_i2c_unlock(state);
6248 state->m_drxk_state = DRXK_NO_DEV;
6249 drxk_i2c_unlock(state);
6250 pr_err("Error %d on %s\n", status, __func__);
6256 static void load_firmware_cb(const struct firmware *fw,
6259 struct drxk_state *state = context;
6261 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6263 pr_err("Could not load firmware file %s.\n",
6264 state->microcode_name);
6265 pr_info("Copy %s to your hotplug directory!\n",
6266 state->microcode_name);
6267 state->microcode_name = NULL;
6270 * As firmware is now load asynchronous, it is not possible
6271 * anymore to fail at frontend attach. We might silently
6272 * return here, and hope that the driver won't crash.
6273 * We might also change all DVB callbacks to return -ENODEV
6274 * if the device is not initialized.
6275 * As the DRX-K devices have their own internal firmware,
6276 * let's just hope that it will match a firmware revision
6277 * compatible with this driver and proceed.
6285 static void drxk_release(struct dvb_frontend *fe)
6287 struct drxk_state *state = fe->demodulator_priv;
6290 release_firmware(state->fw);
6295 static int drxk_sleep(struct dvb_frontend *fe)
6297 struct drxk_state *state = fe->demodulator_priv;
6301 if (state->m_drxk_state == DRXK_NO_DEV)
6303 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6310 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6312 struct drxk_state *state = fe->demodulator_priv;
6314 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6316 if (state->m_drxk_state == DRXK_NO_DEV)
6319 return ConfigureI2CBridge(state, enable ? true : false);
6322 static int drxk_set_parameters(struct dvb_frontend *fe)
6324 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6325 u32 delsys = p->delivery_system, old_delsys;
6326 struct drxk_state *state = fe->demodulator_priv;
6331 if (state->m_drxk_state == DRXK_NO_DEV)
6334 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6337 if (!fe->ops.tuner_ops.get_if_frequency) {
6338 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6342 if (fe->ops.i2c_gate_ctrl)
6343 fe->ops.i2c_gate_ctrl(fe, 1);
6344 if (fe->ops.tuner_ops.set_params)
6345 fe->ops.tuner_ops.set_params(fe);
6346 if (fe->ops.i2c_gate_ctrl)
6347 fe->ops.i2c_gate_ctrl(fe, 0);
6349 old_delsys = state->props.delivery_system;
6352 if (old_delsys != delsys) {
6355 case SYS_DVBC_ANNEX_A:
6356 case SYS_DVBC_ANNEX_C:
6357 if (!state->m_has_dvbc)
6359 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6361 if (state->m_itut_annex_c)
6362 setoperation_mode(state, OM_QAM_ITU_C);
6364 setoperation_mode(state, OM_QAM_ITU_A);
6367 if (!state->m_has_dvbt)
6369 setoperation_mode(state, OM_DVBT);
6376 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6377 start(state, 0, IF);
6379 /* After set_frontend, stats aren't available */
6380 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6381 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6382 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6383 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6384 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6385 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6386 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6387 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6389 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6394 static int get_strength(struct drxk_state *state, u64 *strength)
6397 struct s_cfg_agc rf_agc, if_agc;
6403 /* FIXME: those are part of the tuner presets */
6404 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */
6405 u16 tuner_if_gain = 40; /* Default value on az6007 driver */
6409 if (is_dvbt(state)) {
6410 rf_agc = state->m_dvbt_rf_agc_cfg;
6411 if_agc = state->m_dvbt_if_agc_cfg;
6412 } else if (is_qam(state)) {
6413 rf_agc = state->m_qam_rf_agc_cfg;
6414 if_agc = state->m_qam_if_agc_cfg;
6416 rf_agc = state->m_atv_rf_agc_cfg;
6417 if_agc = state->m_atv_if_agc_cfg;
6420 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6421 /* SCU output_level */
6422 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6427 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6431 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6432 rf_agc.output_level = scu_lvl + scu_coc;
6434 rf_agc.output_level = 0xffff;
6436 /* Take RF gain into account */
6437 total_gain += tuner_rf_gain;
6439 /* clip output value */
6440 if (rf_agc.output_level < rf_agc.min_output_level)
6441 rf_agc.output_level = rf_agc.min_output_level;
6442 if (rf_agc.output_level > rf_agc.max_output_level)
6443 rf_agc.output_level = rf_agc.max_output_level;
6445 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6446 if (agc_range > 0) {
6448 ((u32)(tuner_rf_gain)) *
6449 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6454 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6455 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6456 &if_agc.output_level);
6460 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6465 /* Take IF gain into account */
6466 total_gain += (u32) tuner_if_gain;
6468 /* clip output value */
6469 if (if_agc.output_level < if_agc.min_output_level)
6470 if_agc.output_level = if_agc.min_output_level;
6471 if (if_agc.output_level > if_agc.max_output_level)
6472 if_agc.output_level = if_agc.max_output_level;
6474 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6475 if (agc_range > 0) {
6477 ((u32)(tuner_if_gain)) *
6478 ((u32)(if_agc.output_level - if_agc.min_output_level))
6484 * Convert to 0..65535 scale.
6485 * If it can't be measured (AGC is disabled), just show 100%.
6488 *strength = (65535UL * atten / total_gain / 100);
6495 static int drxk_get_stats(struct dvb_frontend *fe)
6497 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6498 struct drxk_state *state = fe->demodulator_priv;
6503 u32 post_bit_err_count;
6504 u32 post_bit_error_scale;
6505 u32 pre_bit_err_count;
6508 u32 pkt_error_count;
6511 if (state->m_drxk_state == DRXK_NO_DEV)
6513 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6517 state->fe_status = 0;
6518 get_lock_status(state, &stat);
6519 if (stat == MPEG_LOCK)
6520 state->fe_status |= 0x1f;
6521 if (stat == FEC_LOCK)
6522 state->fe_status |= 0x0f;
6523 if (stat == DEMOD_LOCK)
6524 state->fe_status |= 0x07;
6527 * Estimate signal strength from AGC
6529 get_strength(state, &c->strength.stat[0].uvalue);
6530 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6533 if (stat >= DEMOD_LOCK) {
6534 get_signal_to_noise(state, &cnr);
6535 c->cnr.stat[0].svalue = cnr * 100;
6536 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6538 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6541 if (stat < FEC_LOCK) {
6542 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6543 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6544 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6545 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6546 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6547 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6553 /* BER measurement is valid if at least FEC lock is achieved */
6556 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6557 * written to set nr of symbols or bits over which to measure
6558 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6561 /* Read registers for post/preViterbi BER calculation */
6562 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6565 pre_bit_err_count = reg16;
6567 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6570 pre_bit_count = reg16;
6572 /* Number of bit-errors */
6573 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6576 post_bit_err_count = reg16;
6578 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6581 post_bit_error_scale = reg16;
6583 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6588 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6591 pkt_error_count = reg16;
6592 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6594 post_bit_err_count *= post_bit_error_scale;
6596 post_bit_count = pkt_count * 204 * 8;
6598 /* Store the results */
6599 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6600 c->block_error.stat[0].uvalue += pkt_error_count;
6601 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6602 c->block_count.stat[0].uvalue += pkt_count;
6604 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6605 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6606 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6607 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6609 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6610 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6611 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6612 c->post_bit_count.stat[0].uvalue += post_bit_count;
6619 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6621 struct drxk_state *state = fe->demodulator_priv;
6626 rc = drxk_get_stats(fe);
6630 *status = state->fe_status;
6635 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6638 struct drxk_state *state = fe->demodulator_priv;
6639 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6643 if (state->m_drxk_state == DRXK_NO_DEV)
6645 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6648 *strength = c->strength.stat[0].uvalue;
6652 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6654 struct drxk_state *state = fe->demodulator_priv;
6659 if (state->m_drxk_state == DRXK_NO_DEV)
6661 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6664 get_signal_to_noise(state, &snr2);
6666 /* No negative SNR, clip to zero */
6669 *snr = snr2 & 0xffff;
6673 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6675 struct drxk_state *state = fe->demodulator_priv;
6680 if (state->m_drxk_state == DRXK_NO_DEV)
6682 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6685 dvbtqam_get_acc_pkt_err(state, &err);
6686 *ucblocks = (u32) err;
6690 static int drxk_get_tune_settings(struct dvb_frontend *fe,
6691 struct dvb_frontend_tune_settings *sets)
6693 struct drxk_state *state = fe->demodulator_priv;
6694 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6698 if (state->m_drxk_state == DRXK_NO_DEV)
6700 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6703 switch (p->delivery_system) {
6704 case SYS_DVBC_ANNEX_A:
6705 case SYS_DVBC_ANNEX_C:
6707 sets->min_delay_ms = 3000;
6708 sets->max_drift = 0;
6709 sets->step_size = 0;
6716 static const struct dvb_frontend_ops drxk_ops = {
6717 /* .delsys will be filled dynamically */
6720 .frequency_min_hz = 47 * MHz,
6721 .frequency_max_hz = 865 * MHz,
6723 .symbol_rate_min = 870000,
6724 .symbol_rate_max = 11700000,
6726 .frequency_stepsize_hz = 166667,
6728 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6729 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6730 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6731 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6732 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6733 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6736 .release = drxk_release,
6737 .sleep = drxk_sleep,
6738 .i2c_gate_ctrl = drxk_gate_ctrl,
6740 .set_frontend = drxk_set_parameters,
6741 .get_tune_settings = drxk_get_tune_settings,
6743 .read_status = drxk_read_status,
6744 .read_signal_strength = drxk_read_signal_strength,
6745 .read_snr = drxk_read_snr,
6746 .read_ucblocks = drxk_read_ucblocks,
6749 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6750 struct i2c_adapter *i2c)
6752 struct dtv_frontend_properties *p;
6753 struct drxk_state *state = NULL;
6754 u8 adr = config->adr;
6758 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6763 state->demod_address = adr;
6764 state->single_master = config->single_master;
6765 state->microcode_name = config->microcode_name;
6766 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6767 state->no_i2c_bridge = config->no_i2c_bridge;
6768 state->antenna_gpio = config->antenna_gpio;
6769 state->antenna_dvbt = config->antenna_dvbt;
6770 state->m_chunk_size = config->chunk_size;
6771 state->enable_merr_cfg = config->enable_merr_cfg;
6773 if (config->dynamic_clk) {
6774 state->m_dvbt_static_clk = false;
6775 state->m_dvbc_static_clk = false;
6777 state->m_dvbt_static_clk = true;
6778 state->m_dvbc_static_clk = true;
6782 if (config->mpeg_out_clk_strength)
6783 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6785 state->m_ts_clockk_strength = 0x06;
6787 if (config->parallel_ts)
6788 state->m_enable_parallel = true;
6790 state->m_enable_parallel = false;
6792 /* NOTE: as more UIO bits will be used, add them to the mask */
6793 state->uio_mask = config->antenna_gpio;
6795 /* Default gpio to DVB-C */
6796 if (!state->antenna_dvbt && state->antenna_gpio)
6797 state->m_gpio |= state->antenna_gpio;
6799 state->m_gpio &= ~state->antenna_gpio;
6801 mutex_init(&state->mutex);
6803 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6804 state->frontend.demodulator_priv = state;
6808 /* Load firmware and initialize DRX-K */
6809 if (state->microcode_name) {
6810 const struct firmware *fw = NULL;
6812 status = request_firmware(&fw, state->microcode_name,
6813 state->i2c->dev.parent);
6816 load_firmware_cb(fw, state);
6817 } else if (init_drxk(state) < 0)
6821 /* Initialize stats */
6822 p = &state->frontend.dtv_property_cache;
6823 p->strength.len = 1;
6825 p->block_error.len = 1;
6826 p->block_count.len = 1;
6827 p->pre_bit_error.len = 1;
6828 p->pre_bit_count.len = 1;
6829 p->post_bit_error.len = 1;
6830 p->post_bit_count.len = 1;
6832 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6833 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6834 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6835 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6836 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6837 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6838 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6839 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6841 pr_info("frontend initialized.\n");
6842 return &state->frontend;
6845 pr_err("not found\n");
6849 EXPORT_SYMBOL(drxk_attach);
6851 MODULE_DESCRIPTION("DRX-K driver");
6852 MODULE_AUTHOR("Ralph Metzler");
6853 MODULE_LICENSE("GPL");