1 // SPDX-License-Identifier: GPL-2.0
5 * Extracted from init.c
7 #include <linux/memblock.h>
8 #include <linux/percpu.h>
9 #include <linux/init.h>
10 #include <linux/string.h>
11 #include <linux/slab.h>
12 #include <linux/cache.h>
15 #include <asm/tlbflush.h>
16 #include <asm/mmu_context.h>
18 #include <asm/initialize_mmu.h>
21 #if defined(CONFIG_HIGHMEM)
22 static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
24 pmd_t *pmd = pmd_off_k(vaddr);
28 n_pages = ALIGN(n_pages, PTRS_PER_PTE);
30 pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
31 __func__, vaddr, n_pages);
33 pte = memblock_alloc_low(n_pages * sizeof(pte_t), PAGE_SIZE);
35 panic("%s: Failed to allocate %lu bytes align=%lx\n",
36 __func__, n_pages * sizeof(pte_t), PAGE_SIZE);
38 for (i = 0; i < n_pages; ++i)
39 pte_clear(NULL, 0, pte + i);
41 for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
42 pte_t *cur_pte = pte + i;
44 BUG_ON(!pmd_none(*pmd));
45 set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
46 BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
47 pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
48 __func__, pmd, cur_pte);
53 static void __init fixedrange_init(void)
55 init_pmd(__fix_to_virt(0), __end_of_fixed_addresses);
59 void __init paging_init(void)
63 pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
69 * Flush the mmu and reset associated register to default values.
73 #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
75 * Writing zeros to the instruction and data TLBCFG special
76 * registers ensure that valid values exist in the register.
78 * For existing PGSZID<w> fields, zero selects the first element
79 * of the page-size array. For nonexistent PGSZID<w> fields,
80 * zero is the best value to write. Also, when changing PGSZID<w>
81 * fields, the corresponding TLB must be flushed.
83 set_itlbcfg_register(0);
84 set_dtlbcfg_register(0);
87 local_flush_tlb_all();
89 /* Set rasid register to a known value. */
91 set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
93 /* Set PTEVADDR special register to the start of the page
94 * table, which is in kernel mappable space (ie. not
95 * statically mapped). This register's value is undefined on
98 set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR);
103 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
105 * Update the IO area mapping in case xtensa_kio_paddr has changed
107 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
108 XCHAL_KIO_CACHED_VADDR + 6);
109 write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
110 XCHAL_KIO_CACHED_VADDR + 6);
111 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
112 XCHAL_KIO_BYPASS_VADDR + 6);
113 write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
114 XCHAL_KIO_BYPASS_VADDR + 6);