arch/x86/events/intel/uncore.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #include <linux/slab.h>
   3 #include <linux/pci.h>
   4 #include <asm/apicdef.h>
   5 #include <linux/io-64-nonatomic-lo-hi.h>
   6
   7 #include <linux/perf_event.h>
   8 #include "../perf_event.h"
   9
  10 #define UNCORE_PMU_NAME_LEN             32
  11 #define UNCORE_PMU_HRTIMER_INTERVAL     (60LL * NSEC_PER_SEC)
  12 #define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
  13
  14 #define UNCORE_FIXED_EVENT              0xff
  15 #define UNCORE_PMC_IDX_MAX_GENERIC      8
  16 #define UNCORE_PMC_IDX_MAX_FIXED        1
  17 #define UNCORE_PMC_IDX_MAX_FREERUNNING  1
  18 #define UNCORE_PMC_IDX_FIXED            UNCORE_PMC_IDX_MAX_GENERIC
  19 #define UNCORE_PMC_IDX_FREERUNNING      (UNCORE_PMC_IDX_FIXED + \
  20                                         UNCORE_PMC_IDX_MAX_FIXED)
  21 #define UNCORE_PMC_IDX_MAX              (UNCORE_PMC_IDX_FREERUNNING + \
  22                                         UNCORE_PMC_IDX_MAX_FREERUNNING)
  23
  24 #define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx)  \
  25                 ((dev << 24) | (func << 16) | (type << 8) | idx)
  26 #define UNCORE_PCI_DEV_DATA(type, idx)  ((type << 8) | idx)
  27 #define UNCORE_PCI_DEV_DEV(data)        ((data >> 24) & 0xff)
  28 #define UNCORE_PCI_DEV_FUNC(data)       ((data >> 16) & 0xff)
  29 #define UNCORE_PCI_DEV_TYPE(data)       ((data >> 8) & 0xff)
  30 #define UNCORE_PCI_DEV_IDX(data)        (data & 0xff)
  31 #define UNCORE_EXTRA_PCI_DEV            0xff
  32 #define UNCORE_EXTRA_PCI_DEV_MAX        4
  33
  34 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
  35
  36 struct pci_extra_dev {
  37         struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
  38 };
  39
  40 struct intel_uncore_ops;
  41 struct intel_uncore_pmu;
  42 struct intel_uncore_box;
  43 struct uncore_event_desc;
  44 struct freerunning_counters;
  45
  46 struct intel_uncore_type {
  47         const char *name;
  48         int num_counters;
  49         int num_boxes;
  50         int perf_ctr_bits;
  51         int fixed_ctr_bits;
  52         int num_freerunning_types;
  53         unsigned perf_ctr;
  54         unsigned event_ctl;
  55         unsigned event_mask;
  56         unsigned event_mask_ext;
  57         unsigned fixed_ctr;
  58         unsigned fixed_ctl;
  59         unsigned box_ctl;
  60         union {
  61                 unsigned msr_offset;
  62                 unsigned mmio_offset;
  63         };
  64         unsigned mmio_map_size;
  65         unsigned num_shared_regs:8;
  66         unsigned single_fixed:1;
  67         unsigned pair_ctr_ctl:1;
  68         unsigned *msr_offsets;
  69         struct event_constraint unconstrainted;
  70         struct event_constraint *constraints;
  71         struct intel_uncore_pmu *pmus;
  72         struct intel_uncore_ops *ops;
  73         struct uncore_event_desc *event_descs;
  74         struct freerunning_counters *freerunning;
  75         const struct attribute_group *attr_groups[4];
  76         const struct attribute_group **attr_update;
  77         struct pmu *pmu; /* for custom pmu ops */
  78         /*
  79          * Uncore PMU would store relevant platform topology configuration here
  80          * to identify which platform component each PMON block of that type is
  81          * supposed to monitor.
  82          */
  83         u64 *topology;
  84         /*
  85          * Optional callbacks for managing mapping of Uncore units to PMONs
  86          */
  87         int (*set_mapping)(struct intel_uncore_type *type);
  88         void (*cleanup_mapping)(struct intel_uncore_type *type);
  89 };
  90
  91 #define pmu_group attr_groups[0]
  92 #define format_group attr_groups[1]
  93 #define events_group attr_groups[2]
  94
  95 struct intel_uncore_ops {
  96         void (*init_box)(struct intel_uncore_box *);
  97         void (*exit_box)(struct intel_uncore_box *);
  98         void (*disable_box)(struct intel_uncore_box *);
  99         void (*enable_box)(struct intel_uncore_box *);
 100         void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
 101         void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
 102         u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
 103         int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
 104         struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
 105                                                    struct perf_event *);
 106         void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
 107 };
 108
 109 struct intel_uncore_pmu {
 110         struct pmu                      pmu;
 111         char                            name[UNCORE_PMU_NAME_LEN];
 112         int                             pmu_idx;
 113         int                             func_id;
 114         bool                            registered;
 115         atomic_t                        activeboxes;
 116         struct intel_uncore_type        *type;
 117         struct intel_uncore_box         **boxes;
 118 };
 119
 120 struct intel_uncore_extra_reg {
 121         raw_spinlock_t lock;
 122         u64 config, config1, config2;
 123         atomic_t ref;
 124 };
 125
 126 struct intel_uncore_box {
 127         int pci_phys_id;
 128         int dieid;      /* Logical die ID */
 129         int n_active;   /* number of active events */
 130         int n_events;
 131         int cpu;        /* cpu to collect events */
 132         unsigned long flags;
 133         atomic_t refcnt;
 134         struct perf_event *events[UNCORE_PMC_IDX_MAX];
 135         struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
 136         struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
 137         unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
 138         u64 tags[UNCORE_PMC_IDX_MAX];
 139         struct pci_dev *pci_dev;
 140         struct intel_uncore_pmu *pmu;
 141         u64 hrtimer_duration; /* hrtimer timeout for this box */
 142         struct hrtimer hrtimer;
 143         struct list_head list;
 144         struct list_head active_list;
 145         void __iomem *io_addr;
 146         struct intel_uncore_extra_reg shared_regs[];
 147 };
 148
 149 /* CFL uncore 8th cbox MSRs */
 150 #define CFL_UNC_CBO_7_PERFEVTSEL0               0xf70
 151 #define CFL_UNC_CBO_7_PER_CTR0                  0xf76
 152
 153 #define UNCORE_BOX_FLAG_INITIATED               0
 154 /* event config registers are 8-byte apart */
 155 #define UNCORE_BOX_FLAG_CTL_OFFS8               1
 156 /* CFL 8th CBOX has different MSR space */
 157 #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS      2
 158
 159 struct uncore_event_desc {
 160         struct kobj_attribute attr;
 161         const char *config;
 162 };
 163
 164 struct freerunning_counters {
 165         unsigned int counter_base;
 166         unsigned int counter_offset;
 167         unsigned int box_offset;
 168         unsigned int num_counters;
 169         unsigned int bits;
 170         unsigned *box_offsets;
 171 };
 172
 173 struct pci2phy_map {
 174         struct list_head list;
 175         int segment;
 176         int pbus_to_physid[256];
 177 };
 178
 179 struct pci2phy_map *__find_pci2phy_map(int segment);
 180 int uncore_pcibus_to_physid(struct pci_bus *bus);
 181
 182 ssize_t uncore_event_show(struct kobject *kobj,
 183                           struct kobj_attribute *attr, char *buf);
 184
 185 static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev)
 186 {
 187         return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu);
 188 }
 189
 190 #define to_device_attribute(n)  container_of(n, struct device_attribute, attr)
 191 #define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr)
 192 #define attr_to_ext_attr(n)     to_dev_ext_attribute(to_device_attribute(n))
 193
 194 extern int __uncore_max_dies;
 195 #define uncore_max_dies()       (__uncore_max_dies)
 196
 197 #define INTEL_UNCORE_EVENT_DESC(_name, _config)                 \
 198 {                                                               \
 199         .attr   = __ATTR(_name, 0444, uncore_event_show, NULL), \
 200         .config = _config,                                      \
 201 }
 202
 203 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)                 \
 204 static ssize_t __uncore_##_var##_show(struct kobject *kobj,             \
 205                                 struct kobj_attribute *attr,            \
 206                                 char *page)                             \
 207 {                                                                       \
 208         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);                     \
 209         return sprintf(page, _format "\n");                             \
 210 }                                                                       \
 211 static struct kobj_attribute format_attr_##_var =                       \
 212         __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
 213
 214 static inline bool uncore_pmc_fixed(int idx)
 215 {
 216         return idx == UNCORE_PMC_IDX_FIXED;
 217 }
 218
 219 static inline bool uncore_pmc_freerunning(int idx)
 220 {
 221         return idx == UNCORE_PMC_IDX_FREERUNNING;
 222 }
 223
 224 static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box,
 225                                                unsigned long offset)
 226 {
 227         if (offset < box->pmu->type->mmio_map_size)
 228                 return true;
 229
 230         pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n",
 231                      offset, box->pmu->type->name);
 232
 233         return false;
 234 }
 235
 236 static inline
 237 unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box)
 238 {
 239         return box->pmu->type->box_ctl +
 240                box->pmu->type->mmio_offset * box->pmu->pmu_idx;
 241 }
 242
 243 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
 244 {
 245         return box->pmu->type->box_ctl;
 246 }
 247
 248 static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
 249 {
 250         return box->pmu->type->fixed_ctl;
 251 }
 252
 253 static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
 254 {
 255         return box->pmu->type->fixed_ctr;
 256 }
 257
 258 static inline
 259 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
 260 {
 261         if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
 262                 return idx * 8 + box->pmu->type->event_ctl;
 263
 264         return idx * 4 + box->pmu->type->event_ctl;
 265 }
 266
 267 static inline
 268 unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
 269 {
 270         return idx * 8 + box->pmu->type->perf_ctr;
 271 }
 272
 273 static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
 274 {
 275         struct intel_uncore_pmu *pmu = box->pmu;
 276         return pmu->type->msr_offsets ?
 277                 pmu->type->msr_offsets[pmu->pmu_idx] :
 278                 pmu->type->msr_offset * pmu->pmu_idx;
 279 }
 280
 281 static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
 282 {
 283         if (!box->pmu->type->box_ctl)
 284                 return 0;
 285         return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
 286 }
 287
 288 static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
 289 {
 290         if (!box->pmu->type->fixed_ctl)
 291                 return 0;
 292         return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
 293 }
 294
 295 static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
 296 {
 297         return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
 298 }
 299
 300
 301 /*
 302  * In the uncore document, there is no event-code assigned to free running
 303  * counters. Some events need to be defined to indicate the free running
 304  * counters. The events are encoded as event-code + umask-code.
 305  *
 306  * The event-code for all free running counters is 0xff, which is the same as
 307  * the fixed counters.
 308  *
 309  * The umask-code is used to distinguish a fixed counter and a free running
 310  * counter, and different types of free running counters.
 311  * - For fixed counters, the umask-code is 0x0X.
 312  *   X indicates the index of the fixed counter, which starts from 0.
 313  * - For free running counters, the umask-code uses the rest of the space.
 314  *   It would bare the format of 0xXY.
 315  *   X stands for the type of free running counters, which starts from 1.
 316  *   Y stands for the index of free running counters of same type, which
 317  *   starts from 0.
 318  *
 319  * For example, there are three types of IIO free running counters on Skylake
 320  * server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters.
 321  * The event-code for all the free running counters is 0xff.
 322  * 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type,
 323  * which umask-code starts from 0x10.
 324  * So 'ioclk' is encoded as event=0xff,umask=0x10
 325  * 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is
 326  * the second type, which umask-code starts from 0x20.
 327  * So 'bw_in_port2' is encoded as event=0xff,umask=0x22
 328  */
 329 static inline unsigned int uncore_freerunning_idx(u64 config)
 330 {
 331         return ((config >> 8) & 0xf);
 332 }
 333
 334 #define UNCORE_FREERUNNING_UMASK_START          0x10
 335
 336 static inline unsigned int uncore_freerunning_type(u64 config)
 337 {
 338         return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf);
 339 }
 340
 341 static inline
 342 unsigned int uncore_freerunning_counter(struct intel_uncore_box *box,
 343                                         struct perf_event *event)
 344 {
 345         unsigned int type = uncore_freerunning_type(event->hw.config);
 346         unsigned int idx = uncore_freerunning_idx(event->hw.config);
 347         struct intel_uncore_pmu *pmu = box->pmu;
 348
 349         return pmu->type->freerunning[type].counter_base +
 350                pmu->type->freerunning[type].counter_offset * idx +
 351                (pmu->type->freerunning[type].box_offsets ?
 352                 pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] :
 353                 pmu->type->freerunning[type].box_offset * pmu->pmu_idx);
 354 }
 355
 356 static inline
 357 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
 358 {
 359         if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
 360                 return CFL_UNC_CBO_7_PERFEVTSEL0 +
 361                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
 362         } else {
 363                 return box->pmu->type->event_ctl +
 364                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
 365                        uncore_msr_box_offset(box);
 366         }
 367 }
 368
 369 static inline
 370 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
 371 {
 372         if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
 373                 return CFL_UNC_CBO_7_PER_CTR0 +
 374                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
 375         } else {
 376                 return box->pmu->type->perf_ctr +
 377                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
 378                        uncore_msr_box_offset(box);
 379         }
 380 }
 381
 382 static inline
 383 unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
 384 {
 385         if (box->pci_dev || box->io_addr)
 386                 return uncore_pci_fixed_ctl(box);
 387         else
 388                 return uncore_msr_fixed_ctl(box);
 389 }
 390
 391 static inline
 392 unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
 393 {
 394         if (box->pci_dev || box->io_addr)
 395                 return uncore_pci_fixed_ctr(box);
 396         else
 397                 return uncore_msr_fixed_ctr(box);
 398 }
 399
 400 static inline
 401 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
 402 {
 403         if (box->pci_dev || box->io_addr)
 404                 return uncore_pci_event_ctl(box, idx);
 405         else
 406                 return uncore_msr_event_ctl(box, idx);
 407 }
 408
 409 static inline
 410 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
 411 {
 412         if (box->pci_dev || box->io_addr)
 413                 return uncore_pci_perf_ctr(box, idx);
 414         else
 415                 return uncore_msr_perf_ctr(box, idx);
 416 }
 417
 418 static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
 419 {
 420         return box->pmu->type->perf_ctr_bits;
 421 }
 422
 423 static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
 424 {
 425         return box->pmu->type->fixed_ctr_bits;
 426 }
 427
 428 static inline
 429 unsigned int uncore_freerunning_bits(struct intel_uncore_box *box,
 430                                      struct perf_event *event)
 431 {
 432         unsigned int type = uncore_freerunning_type(event->hw.config);
 433
 434         return box->pmu->type->freerunning[type].bits;
 435 }
 436
 437 static inline int uncore_num_freerunning(struct intel_uncore_box *box,
 438                                          struct perf_event *event)
 439 {
 440         unsigned int type = uncore_freerunning_type(event->hw.config);
 441
 442         return box->pmu->type->freerunning[type].num_counters;
 443 }
 444
 445 static inline int uncore_num_freerunning_types(struct intel_uncore_box *box,
 446                                                struct perf_event *event)
 447 {
 448         return box->pmu->type->num_freerunning_types;
 449 }
 450
 451 static inline bool check_valid_freerunning_event(struct intel_uncore_box *box,
 452                                                  struct perf_event *event)
 453 {
 454         unsigned int type = uncore_freerunning_type(event->hw.config);
 455         unsigned int idx = uncore_freerunning_idx(event->hw.config);
 456
 457         return (type < uncore_num_freerunning_types(box, event)) &&
 458                (idx < uncore_num_freerunning(box, event));
 459 }
 460
 461 static inline int uncore_num_counters(struct intel_uncore_box *box)
 462 {
 463         return box->pmu->type->num_counters;
 464 }
 465
 466 static inline bool is_freerunning_event(struct perf_event *event)
 467 {
 468         u64 cfg = event->attr.config;
 469
 470         return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) &&
 471                (((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START);
 472 }
 473
 474 /* Check and reject invalid config */
 475 static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box,
 476                                                struct perf_event *event)
 477 {
 478         if (is_freerunning_event(event))
 479                 return 0;
 480
 481         return -EINVAL;
 482 }
 483
 484 static inline void uncore_disable_event(struct intel_uncore_box *box,
 485                                 struct perf_event *event)
 486 {
 487         box->pmu->type->ops->disable_event(box, event);
 488 }
 489
 490 static inline void uncore_enable_event(struct intel_uncore_box *box,
 491                                 struct perf_event *event)
 492 {
 493         box->pmu->type->ops->enable_event(box, event);
 494 }
 495
 496 static inline u64 uncore_read_counter(struct intel_uncore_box *box,
 497                                 struct perf_event *event)
 498 {
 499         return box->pmu->type->ops->read_counter(box, event);
 500 }
 501
 502 static inline void uncore_box_init(struct intel_uncore_box *box)
 503 {
 504         if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
 505                 if (box->pmu->type->ops->init_box)
 506                         box->pmu->type->ops->init_box(box);
 507         }
 508 }
 509
 510 static inline void uncore_box_exit(struct intel_uncore_box *box)
 511 {
 512         if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
 513                 if (box->pmu->type->ops->exit_box)
 514                         box->pmu->type->ops->exit_box(box);
 515         }
 516 }
 517
 518 static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
 519 {
 520         return (box->dieid < 0);
 521 }
 522
 523 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
 524 {
 525         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
 526 }
 527
 528 static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
 529 {
 530         return event->pmu_private;
 531 }
 532
 533 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
 534 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
 535 void uncore_mmio_exit_box(struct intel_uncore_box *box);
 536 u64 uncore_mmio_read_counter(struct intel_uncore_box *box,
 537                              struct perf_event *event);
 538 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
 539 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
 540 void uncore_pmu_event_start(struct perf_event *event, int flags);
 541 void uncore_pmu_event_stop(struct perf_event *event, int flags);
 542 int uncore_pmu_event_add(struct perf_event *event, int flags);
 543 void uncore_pmu_event_del(struct perf_event *event, int flags);
 544 void uncore_pmu_event_read(struct perf_event *event);
 545 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
 546 struct event_constraint *
 547 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
 548 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
 549 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
 550
 551 extern struct intel_uncore_type **uncore_msr_uncores;
 552 extern struct intel_uncore_type **uncore_pci_uncores;
 553 extern struct intel_uncore_type **uncore_mmio_uncores;
 554 extern struct pci_driver *uncore_pci_driver;
 555 extern raw_spinlock_t pci2phy_map_lock;
 556 extern struct list_head pci2phy_map_head;
 557 extern struct pci_extra_dev *uncore_extra_pci_dev;
 558 extern struct event_constraint uncore_constraint_empty;
 559
 560 /* uncore_snb.c */
 561 int snb_uncore_pci_init(void);
 562 int ivb_uncore_pci_init(void);
 563 int hsw_uncore_pci_init(void);
 564 int bdw_uncore_pci_init(void);
 565 int skl_uncore_pci_init(void);
 566 void snb_uncore_cpu_init(void);
 567 void nhm_uncore_cpu_init(void);
 568 void skl_uncore_cpu_init(void);
 569 void icl_uncore_cpu_init(void);
 570 void tgl_uncore_mmio_init(void);
 571 void tgl_l_uncore_mmio_init(void);
 572 int snb_pci2phy_map_init(int devid);
 573
 574 /* uncore_snbep.c */
 575 int snbep_uncore_pci_init(void);
 576 void snbep_uncore_cpu_init(void);
 577 int ivbep_uncore_pci_init(void);
 578 void ivbep_uncore_cpu_init(void);
 579 int hswep_uncore_pci_init(void);
 580 void hswep_uncore_cpu_init(void);
 581 int bdx_uncore_pci_init(void);
 582 void bdx_uncore_cpu_init(void);
 583 int knl_uncore_pci_init(void);
 584 void knl_uncore_cpu_init(void);
 585 int skx_uncore_pci_init(void);
 586 void skx_uncore_cpu_init(void);
 587 int snr_uncore_pci_init(void);
 588 void snr_uncore_cpu_init(void);
 589 void snr_uncore_mmio_init(void);
 590 int icx_uncore_pci_init(void);
 591 void icx_uncore_cpu_init(void);
 592 void icx_uncore_mmio_init(void);
 593
 594 /* uncore_nhmex.c */
 595 void nhmex_uncore_cpu_init(void);