arch/powerpc/perf/power7-pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Performance counter support for POWER7 processors.
   4  *
   5  * Copyright 2009 Paul Mackerras, IBM Corporation.
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/perf_event.h>
   9 #include <linux/string.h>
  10 #include <asm/reg.h>
  11 #include <asm/cputable.h>
  12
  13 /*
  14  * Bits in event code for POWER7
  15  */
  16 #define PM_PMC_SH       16      /* PMC number (1-based) for direct events */
  17 #define PM_PMC_MSK      0xf
  18 #define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
  19 #define PM_UNIT_SH      12      /* TTMMUX number and setting - unit select */
  20 #define PM_UNIT_MSK     0xf
  21 #define PM_COMBINE_SH   11      /* Combined event bit */
  22 #define PM_COMBINE_MSK  1
  23 #define PM_COMBINE_MSKS 0x800
  24 #define PM_L2SEL_SH     8       /* L2 event select */
  25 #define PM_L2SEL_MSK    7
  26 #define PM_PMCSEL_MSK   0xff
  27
  28 /*
  29  * Bits in MMCR1 for POWER7
  30  */
  31 #define MMCR1_TTM0SEL_SH        60
  32 #define MMCR1_TTM1SEL_SH        56
  33 #define MMCR1_TTM2SEL_SH        52
  34 #define MMCR1_TTM3SEL_SH        48
  35 #define MMCR1_TTMSEL_MSK        0xf
  36 #define MMCR1_L2SEL_SH          45
  37 #define MMCR1_L2SEL_MSK         7
  38 #define MMCR1_PMC1_COMBINE_SH   35
  39 #define MMCR1_PMC2_COMBINE_SH   34
  40 #define MMCR1_PMC3_COMBINE_SH   33
  41 #define MMCR1_PMC4_COMBINE_SH   32
  42 #define MMCR1_PMC1SEL_SH        24
  43 #define MMCR1_PMC2SEL_SH        16
  44 #define MMCR1_PMC3SEL_SH        8
  45 #define MMCR1_PMC4SEL_SH        0
  46 #define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
  47 #define MMCR1_PMCSEL_MSK        0xff
  48
  49 /*
  50  * Power7 event codes.
  51  */
  52 #define EVENT(_name, _code) \
  53         _name = _code,
  54
  55 enum {
  56 #include "power7-events-list.h"
  57 };
  58 #undef EVENT
  59
  60 /*
  61  * Layout of constraint bits:
  62  * 6666555555555544444444443333333333222222222211111111110000000000
  63  * 3210987654321098765432109876543210987654321098765432109876543210
  64  *                                              < ><  ><><><><><><>
  65  *                                              L2  NC P6P5P4P3P2P1
  66  *
  67  * L2 - 16-18 - Required L2SEL value (select field)
  68  *
  69  * NC - number of counters
  70  *     15: NC error 0x8000
  71  *     12-14: number of events needing PMC1-4 0x7000
  72  *
  73  * P6
  74  *     11: P6 error 0x800
  75  *     10-11: Count of events needing PMC6
  76  *
  77  * P1..P5
  78  *     0-9: Count of events needing PMC1..PMC5
  79  */
  80
  81 static int power7_get_constraint(u64 event, unsigned long *maskp,
  82                                  unsigned long *valp)
  83 {
  84         int pmc, sh, unit;
  85         unsigned long mask = 0, value = 0;
  86
  87         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
  88         if (pmc) {
  89                 if (pmc > 6)
  90                         return -1;
  91                 sh = (pmc - 1) * 2;
  92                 mask |= 2 << sh;
  93                 value |= 1 << sh;
  94                 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
  95                         return -1;
  96         }
  97         if (pmc < 5) {
  98                 /* need a counter from PMC1-4 set */
  99                 mask  |= 0x8000;
 100                 value |= 0x1000;
 101         }
 102
 103         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 104         if (unit == 6) {
 105                 /* L2SEL must be identical across events */
 106                 int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
 107                 mask  |= 0x7 << 16;
 108                 value |= l2sel << 16;
 109         }
 110
 111         *maskp = mask;
 112         *valp = value;
 113         return 0;
 114 }
 115
 116 #define MAX_ALT 2       /* at most 2 alternatives for any event */
 117
 118 static const unsigned int event_alternatives[][MAX_ALT] = {
 119         { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
 120         { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
 121         { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
 122 };
 123
 124 /*
 125  * Scan the alternatives table for a match and return the
 126  * index into the alternatives table if found, else -1.
 127  */
 128 static int find_alternative(u64 event)
 129 {
 130         int i, j;
 131
 132         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 133                 if (event < event_alternatives[i][0])
 134                         break;
 135                 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 136                         if (event == event_alternatives[i][j])
 137                                 return i;
 138         }
 139         return -1;
 140 }
 141
 142 static s64 find_alternative_decode(u64 event)
 143 {
 144         int pmc, psel;
 145
 146         /* this only handles the 4x decode events */
 147         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 148         psel = event & PM_PMCSEL_MSK;
 149         if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
 150                 return event - (1 << PM_PMC_SH) + 8;
 151         if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
 152                 return event + (1 << PM_PMC_SH) - 8;
 153         return -1;
 154 }
 155
 156 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 157 {
 158         int i, j, nalt = 1;
 159         s64 ae;
 160
 161         alt[0] = event;
 162         nalt = 1;
 163         i = find_alternative(event);
 164         if (i >= 0) {
 165                 for (j = 0; j < MAX_ALT; ++j) {
 166                         ae = event_alternatives[i][j];
 167                         if (ae && ae != event)
 168                                 alt[nalt++] = ae;
 169                 }
 170         } else {
 171                 ae = find_alternative_decode(event);
 172                 if (ae > 0)
 173                         alt[nalt++] = ae;
 174         }
 175
 176         if (flags & PPMU_ONLY_COUNT_RUN) {
 177                 /*
 178                  * We're only counting in RUN state,
 179                  * so PM_CYC is equivalent to PM_RUN_CYC
 180                  * and PM_INST_CMPL === PM_RUN_INST_CMPL.
 181                  * This doesn't include alternatives that don't provide
 182                  * any extra flexibility in assigning PMCs.
 183                  */
 184                 j = nalt;
 185                 for (i = 0; i < nalt; ++i) {
 186                         switch (alt[i]) {
 187                         case 0x1e:      /* PM_CYC */
 188                                 alt[j++] = 0x600f4;     /* PM_RUN_CYC */
 189                                 break;
 190                         case 0x600f4:   /* PM_RUN_CYC */
 191                                 alt[j++] = 0x1e;
 192                                 break;
 193                         case 0x2:       /* PM_PPC_CMPL */
 194                                 alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
 195                                 break;
 196                         case 0x500fa:   /* PM_RUN_INST_CMPL */
 197                                 alt[j++] = 0x2; /* PM_PPC_CMPL */
 198                                 break;
 199                         }
 200                 }
 201                 nalt = j;
 202         }
 203
 204         return nalt;
 205 }
 206
 207 /*
 208  * Returns 1 if event counts things relating to marked instructions
 209  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 210  */
 211 static int power7_marked_instr_event(u64 event)
 212 {
 213         int pmc, psel;
 214         int unit;
 215
 216         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 217         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 218         psel = event & PM_PMCSEL_MSK & ~1;      /* trim off edge/level bit */
 219         if (pmc >= 5)
 220                 return 0;
 221
 222         switch (psel >> 4) {
 223         case 2:
 224                 return pmc == 2 || pmc == 4;
 225         case 3:
 226                 if (psel == 0x3c)
 227                         return pmc == 1;
 228                 if (psel == 0x3e)
 229                         return pmc != 2;
 230                 return 1;
 231         case 4:
 232         case 5:
 233                 return unit == 0xd;
 234         case 6:
 235                 if (psel == 0x64)
 236                         return pmc >= 3;
 237                 break;
 238         case 8:
 239                 return unit == 0xd;
 240         }
 241         return 0;
 242 }
 243
 244 static int power7_compute_mmcr(u64 event[], int n_ev,
 245                                unsigned int hwc[], struct mmcr_regs *mmcr,
 246                                struct perf_event *pevents[])
 247 {
 248         unsigned long mmcr1 = 0;
 249         unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
 250         unsigned int pmc, unit, combine, l2sel, psel;
 251         unsigned int pmc_inuse = 0;
 252         int i;
 253
 254         /* First pass to count resource use */
 255         for (i = 0; i < n_ev; ++i) {
 256                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 257                 if (pmc) {
 258                         if (pmc > 6)
 259                                 return -1;
 260                         if (pmc_inuse & (1 << (pmc - 1)))
 261                                 return -1;
 262                         pmc_inuse |= 1 << (pmc - 1);
 263                 }
 264         }
 265
 266         /* Second pass: assign PMCs, set all MMCR1 fields */
 267         for (i = 0; i < n_ev; ++i) {
 268                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 269                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 270                 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
 271                 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
 272                 psel = event[i] & PM_PMCSEL_MSK;
 273                 if (!pmc) {
 274                         /* Bus event or any-PMC direct event */
 275                         for (pmc = 0; pmc < 4; ++pmc) {
 276                                 if (!(pmc_inuse & (1 << pmc)))
 277                                         break;
 278                         }
 279                         if (pmc >= 4)
 280                                 return -1;
 281                         pmc_inuse |= 1 << pmc;
 282                 } else {
 283                         /* Direct or decoded event */
 284                         --pmc;
 285                 }
 286                 if (pmc <= 3) {
 287                         mmcr1 |= (unsigned long) unit
 288                                 << (MMCR1_TTM0SEL_SH - 4 * pmc);
 289                         mmcr1 |= (unsigned long) combine
 290                                 << (MMCR1_PMC1_COMBINE_SH - pmc);
 291                         mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
 292                         if (unit == 6)  /* L2 events */
 293                                 mmcr1 |= (unsigned long) l2sel
 294                                         << MMCR1_L2SEL_SH;
 295                 }
 296                 if (power7_marked_instr_event(event[i]))
 297                         mmcra |= MMCRA_SAMPLE_ENABLE;
 298                 hwc[i] = pmc;
 299         }
 300
 301         /* Return MMCRx values */
 302         mmcr->mmcr0 = 0;
 303         if (pmc_inuse & 1)
 304                 mmcr->mmcr0 = MMCR0_PMC1CE;
 305         if (pmc_inuse & 0x3e)
 306                 mmcr->mmcr0 |= MMCR0_PMCjCE;
 307         mmcr->mmcr1 = mmcr1;
 308         mmcr->mmcra = mmcra;
 309         return 0;
 310 }
 311
 312 static void power7_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
 313 {
 314         if (pmc <= 3)
 315                 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
 316 }
 317
 318 static int power7_generic_events[] = {
 319         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 320         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_GCT_NOSLOT_CYC,
 321         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 322         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 323         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 324         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 325         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
 326         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED,
 327 };
 328
 329 #define C(x)    PERF_COUNT_HW_CACHE_##x
 330
 331 /*
 332  * Table of generalized cache-related events.
 333  * 0 means not supported, -1 means nonsensical, other values
 334  * are event codes.
 335  */
 336 static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 337         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 338                 [C(OP_READ)] = {        0xc880,         0x400f0 },
 339                 [C(OP_WRITE)] = {       0,              0x300f0 },
 340                 [C(OP_PREFETCH)] = {    0xd8b8,         0       },
 341         },
 342         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 343                 [C(OP_READ)] = {        0,              0x200fc },
 344                 [C(OP_WRITE)] = {       -1,             -1      },
 345                 [C(OP_PREFETCH)] = {    0x408a,         0       },
 346         },
 347         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 348                 [C(OP_READ)] = {        0x16080,        0x26080 },
 349                 [C(OP_WRITE)] = {       0x16082,        0x26082 },
 350                 [C(OP_PREFETCH)] = {    0,              0       },
 351         },
 352         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 353                 [C(OP_READ)] = {        0,              0x300fc },
 354                 [C(OP_WRITE)] = {       -1,             -1      },
 355                 [C(OP_PREFETCH)] = {    -1,             -1      },
 356         },
 357         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 358                 [C(OP_READ)] = {        0,              0x400fc },
 359                 [C(OP_WRITE)] = {       -1,             -1      },
 360                 [C(OP_PREFETCH)] = {    -1,             -1      },
 361         },
 362         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 363                 [C(OP_READ)] = {        0x10068,        0x400f6 },
 364                 [C(OP_WRITE)] = {       -1,             -1      },
 365                 [C(OP_PREFETCH)] = {    -1,             -1      },
 366         },
 367         [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 368                 [C(OP_READ)] = {        -1,             -1      },
 369                 [C(OP_WRITE)] = {       -1,             -1      },
 370                 [C(OP_PREFETCH)] = {    -1,             -1      },
 371         },
 372 };
 373
 374
 375 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
 376 GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_GCT_NOSLOT_CYC);
 377 GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
 378 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
 379 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
 380 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1);
 381 GENERIC_EVENT_ATTR(branch-instructions,         PM_BRU_FIN);
 382 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED);
 383
 384 #define EVENT(_name, _code)     POWER_EVENT_ATTR(_name, _name);
 385 #include "power7-events-list.h"
 386 #undef EVENT
 387
 388 #define EVENT(_name, _code)     POWER_EVENT_PTR(_name),
 389
 390 static struct attribute *power7_events_attr[] = {
 391         GENERIC_EVENT_PTR(PM_CYC),
 392         GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
 393         GENERIC_EVENT_PTR(PM_CMPLU_STALL),
 394         GENERIC_EVENT_PTR(PM_INST_CMPL),
 395         GENERIC_EVENT_PTR(PM_LD_REF_L1),
 396         GENERIC_EVENT_PTR(PM_LD_MISS_L1),
 397         GENERIC_EVENT_PTR(PM_BRU_FIN),
 398         GENERIC_EVENT_PTR(PM_BR_MPRED),
 399
 400         #include "power7-events-list.h"
 401         #undef EVENT
 402         NULL
 403 };
 404
 405 static struct attribute_group power7_pmu_events_group = {
 406         .name = "events",
 407         .attrs = power7_events_attr,
 408 };
 409
 410 PMU_FORMAT_ATTR(event, "config:0-19");
 411
 412 static struct attribute *power7_pmu_format_attr[] = {
 413         &format_attr_event.attr,
 414         NULL,
 415 };
 416
 417 static struct attribute_group power7_pmu_format_group = {
 418         .name = "format",
 419         .attrs = power7_pmu_format_attr,
 420 };
 421
 422 static const struct attribute_group *power7_pmu_attr_groups[] = {
 423         &power7_pmu_format_group,
 424         &power7_pmu_events_group,
 425         NULL,
 426 };
 427
 428 static struct power_pmu power7_pmu = {
 429         .name                   = "POWER7",
 430         .n_counter              = 6,
 431         .max_alternatives       = MAX_ALT + 1,
 432         .add_fields             = 0x1555ul,
 433         .test_adder             = 0x3000ul,
 434         .compute_mmcr           = power7_compute_mmcr,
 435         .get_constraint         = power7_get_constraint,
 436         .get_alternatives       = power7_get_alternatives,
 437         .disable_pmc            = power7_disable_pmc,
 438         .flags                  = PPMU_ALT_SIPR,
 439         .attr_groups            = power7_pmu_attr_groups,
 440         .n_generic              = ARRAY_SIZE(power7_generic_events),
 441         .generic_events         = power7_generic_events,
 442         .cache_events           = &power7_cache_events,
 443 };
 444
 445 int init_power7_pmu(void)
 446 {
 447         if (!cur_cpu_spec->oprofile_cpu_type ||
 448             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
 449                 return -ENODEV;
 450
 451         if (pvr_version_is(PVR_POWER7p))
 452                 power7_pmu.flags |= PPMU_SIAR_VALID;
 453
 454         return register_power_pmu(&power7_pmu);
 455 }