arch/powerpc/perf/power10-events-list.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Performance counter support for POWER10 processors.
   4  *
   5  * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
   6  * Copyright 2020 Athira Rajeev, IBM Corporation.
   7  */
   8
   9 /*
  10  * Power10 event codes.
  11  */
  12 EVENT(PM_RUN_CYC,                               0x600f4);
  13 EVENT(PM_DISP_STALL_CYC,                        0x100f8);
  14 EVENT(PM_EXEC_STALL,                            0x30008);
  15 EVENT(PM_RUN_INST_CMPL,                         0x500fa);
  16 EVENT(PM_BR_CMPL,                               0x4d05e);
  17 EVENT(PM_BR_MPRED_CMPL,                         0x400f6);
  18
  19 /* All L1 D cache load references counted at finish, gated by reject */
  20 EVENT(PM_LD_REF_L1,                             0x100fc);
  21 /* Load Missed L1 */
  22 EVENT(PM_LD_MISS_L1,                            0x3e054);
  23 /* Store Missed L1 */
  24 EVENT(PM_ST_MISS_L1,                            0x300f0);
  25 /* L1 cache data prefetches */
  26 EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS,           0x1002c);
  27 /* Demand iCache Miss */
  28 EVENT(PM_L1_ICACHE_MISS,                        0x200fc);
  29 /* Instruction fetches from L1 */
  30 EVENT(PM_INST_FROM_L1,                          0x04080);
  31 /* Instruction Demand sectors wriittent into IL1 */
  32 EVENT(PM_INST_FROM_L1MISS,                      0x03f00000001c040);
  33 /* Instruction prefetch written into IL1 */
  34 EVENT(PM_IC_PREF_REQ,                           0x040a0);
  35 /* The data cache was reloaded from local core's L3 due to a demand load */
  36 EVENT(PM_DATA_FROM_L3,                          0x01340000001c040);
  37 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
  38 EVENT(PM_DATA_FROM_L3MISS,                      0x300fe);
  39 /* Data PTEG reload */
  40 EVENT(PM_DTLB_MISS,                             0x300fc);
  41 /* ITLB Reloaded */
  42 EVENT(PM_ITLB_MISS,                             0x400fc);
  43
  44 EVENT(PM_RUN_CYC_ALT,                           0x0001e);
  45 EVENT(PM_RUN_INST_CMPL_ALT,                     0x00002);
  46
  47 /*
  48  * Memory Access Events
  49  *
  50  * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
  51  * To enable capturing of memory profiling, these MMCRA bits
  52  * needs to be programmed and corresponding raw event format
  53  * encoding.
  54  *
  55  * MMCRA bits encoding needed are
  56  *     SM (Sampling Mode)
  57  *     EM (Eligibility for Random Sampling)
  58  *     TECE (Threshold Event Counter Event)
  59  *     TS (Threshold Start Event)
  60  *     TE (Threshold End Event)
  61  *
  62  * Corresponding Raw Encoding bits:
  63  *     sample [EM,SM]
  64  *     thresh_sel (TECE)
  65  *     thresh start (TS)
  66  *     thresh end (TE)
  67  */
  68
  69 EVENT(MEM_LOADS,                                0x34340401e0);
  70 EVENT(MEM_STORES,                               0x343c0401e0);