arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public [email protected] mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_44xx.h"
  25 #include "cm2_44xx.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28
  29 /* Base offset for all OMAP4 interrupts external to MPUSS */
  30 #define OMAP44XX_IRQ_GIC_START  32
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'dmm' class
  38  * instance(s): dmm
  39  */
  40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  41         .name   = "dmm",
  42 };
  43
  44 /* dmm */
  45 static struct omap_hwmod omap44xx_dmm_hwmod = {
  46         .name           = "dmm",
  47         .class          = &omap44xx_dmm_hwmod_class,
  48         .clkdm_name     = "l3_emif_clkdm",
  49         .prcm = {
  50                 .omap4 = {
  51                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  52                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  53                 },
  54         },
  55 };
  56
  57 /*
  58  * 'l3' class
  59  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  60  */
  61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  62         .name   = "l3",
  63 };
  64
  65 /* l3_instr */
  66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  67         .name           = "l3_instr",
  68         .class          = &omap44xx_l3_hwmod_class,
  69         .clkdm_name     = "l3_instr_clkdm",
  70         .prcm = {
  71                 .omap4 = {
  72                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  73                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  74                         .modulemode   = MODULEMODE_HWCTRL,
  75                 },
  76         },
  77 };
  78
  79 /* l3_main_1 */
  80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  81         .name           = "l3_main_1",
  82         .class          = &omap44xx_l3_hwmod_class,
  83         .clkdm_name     = "l3_1_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  88                 },
  89         },
  90 };
  91
  92 /* l3_main_2 */
  93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  94         .name           = "l3_main_2",
  95         .class          = &omap44xx_l3_hwmod_class,
  96         .clkdm_name     = "l3_2_clkdm",
  97         .prcm = {
  98                 .omap4 = {
  99                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 100                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 101                 },
 102         },
 103 };
 104
 105 /* l3_main_3 */
 106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 107         .name           = "l3_main_3",
 108         .class          = &omap44xx_l3_hwmod_class,
 109         .clkdm_name     = "l3_instr_clkdm",
 110         .prcm = {
 111                 .omap4 = {
 112                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 113                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 114                         .modulemode   = MODULEMODE_HWCTRL,
 115                 },
 116         },
 117 };
 118
 119 /*
 120  * 'l4' class
 121  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 122  */
 123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 124         .name   = "l4",
 125 };
 126
 127 /* l4_abe */
 128 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 129         .name           = "l4_abe",
 130         .class          = &omap44xx_l4_hwmod_class,
 131         .clkdm_name     = "abe_clkdm",
 132         .prcm = {
 133                 .omap4 = {
 134                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 135                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 136                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 137                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 138                 },
 139         },
 140 };
 141
 142 /* l4_cfg */
 143 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 144         .name           = "l4_cfg",
 145         .class          = &omap44xx_l4_hwmod_class,
 146         .clkdm_name     = "l4_cfg_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 150                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per */
 156 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 157         .name           = "l4_per",
 158         .class          = &omap44xx_l4_hwmod_class,
 159         .clkdm_name     = "l4_per_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 163                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 164                 },
 165         },
 166 };
 167
 168 /* l4_wkup */
 169 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 170         .name           = "l4_wkup",
 171         .class          = &omap44xx_l4_hwmod_class,
 172         .clkdm_name     = "l4_wkup_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /*
 182  * 'mpu_bus' class
 183  * instance(s): mpu_private
 184  */
 185 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 186         .name   = "mpu_bus",
 187 };
 188
 189 /* mpu_private */
 190 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 191         .name           = "mpu_private",
 192         .class          = &omap44xx_mpu_bus_hwmod_class,
 193         .clkdm_name     = "mpuss_clkdm",
 194         .prcm = {
 195                 .omap4 = {
 196                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 197                 },
 198         },
 199 };
 200
 201 /*
 202  * 'ocp_wp_noc' class
 203  * instance(s): ocp_wp_noc
 204  */
 205 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 206         .name   = "ocp_wp_noc",
 207 };
 208
 209 /* ocp_wp_noc */
 210 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 211         .name           = "ocp_wp_noc",
 212         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 213         .clkdm_name     = "l3_instr_clkdm",
 214         .prcm = {
 215                 .omap4 = {
 216                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 217                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 218                         .modulemode   = MODULEMODE_HWCTRL,
 219                 },
 220         },
 221 };
 222
 223 /*
 224  * Modules omap_hwmod structures
 225  *
 226  * The following IPs are excluded for the moment because:
 227  * - They do not need an explicit SW control using omap_hwmod API.
 228  * - They still need to be validated with the driver
 229  *   properly adapted to omap_hwmod / omap_device
 230  *
 231  * usim
 232  */
 233
 234 /*
 235  * 'ctrl_module' class
 236  * attila core control module + core pad control module + wkup pad control
 237  * module + attila wkup control module
 238  */
 239
 240 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 241         .rev_offs       = 0x0000,
 242         .sysc_offs      = 0x0010,
 243         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 245                            SIDLE_SMART_WKUP),
 246         .sysc_fields    = &omap_hwmod_sysc_type2,
 247 };
 248
 249 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 250         .name   = "ctrl_module",
 251         .sysc   = &omap44xx_ctrl_module_sysc,
 252 };
 253
 254 /* ctrl_module_core */
 255 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 256         .name           = "ctrl_module_core",
 257         .class          = &omap44xx_ctrl_module_hwmod_class,
 258         .clkdm_name     = "l4_cfg_clkdm",
 259         .prcm = {
 260                 .omap4 = {
 261                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 262                 },
 263         },
 264 };
 265
 266 /* ctrl_module_pad_core */
 267 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 268         .name           = "ctrl_module_pad_core",
 269         .class          = &omap44xx_ctrl_module_hwmod_class,
 270         .clkdm_name     = "l4_cfg_clkdm",
 271         .prcm = {
 272                 .omap4 = {
 273                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 274                 },
 275         },
 276 };
 277
 278 /* ctrl_module_wkup */
 279 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 280         .name           = "ctrl_module_wkup",
 281         .class          = &omap44xx_ctrl_module_hwmod_class,
 282         .clkdm_name     = "l4_wkup_clkdm",
 283         .prcm = {
 284                 .omap4 = {
 285                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 286                 },
 287         },
 288 };
 289
 290 /* ctrl_module_pad_wkup */
 291 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 292         .name           = "ctrl_module_pad_wkup",
 293         .class          = &omap44xx_ctrl_module_hwmod_class,
 294         .clkdm_name     = "l4_wkup_clkdm",
 295         .prcm = {
 296                 .omap4 = {
 297                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 298                 },
 299         },
 300 };
 301
 302 /*
 303  * 'debugss' class
 304  * debug and emulation sub system
 305  */
 306
 307 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 308         .name   = "debugss",
 309 };
 310
 311 /* debugss */
 312 static struct omap_hwmod omap44xx_debugss_hwmod = {
 313         .name           = "debugss",
 314         .class          = &omap44xx_debugss_hwmod_class,
 315         .clkdm_name     = "emu_sys_clkdm",
 316         .main_clk       = "trace_clk_div_ck",
 317         .prcm = {
 318                 .omap4 = {
 319                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 320                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 321                 },
 322         },
 323 };
 324
 325 /*
 326  * 'emif' class
 327  * external memory interface no1
 328  */
 329
 330 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 331         .rev_offs       = 0x0000,
 332 };
 333
 334 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 335         .name   = "emif",
 336         .sysc   = &omap44xx_emif_sysc,
 337 };
 338
 339 /* emif1 */
 340 static struct omap_hwmod omap44xx_emif1_hwmod = {
 341         .name           = "emif1",
 342         .class          = &omap44xx_emif_hwmod_class,
 343         .clkdm_name     = "l3_emif_clkdm",
 344         .flags          = HWMOD_INIT_NO_IDLE,
 345         .main_clk       = "ddrphy_ck",
 346         .prcm = {
 347                 .omap4 = {
 348                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 349                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 350                         .modulemode   = MODULEMODE_HWCTRL,
 351                 },
 352         },
 353 };
 354
 355 /* emif2 */
 356 static struct omap_hwmod omap44xx_emif2_hwmod = {
 357         .name           = "emif2",
 358         .class          = &omap44xx_emif_hwmod_class,
 359         .clkdm_name     = "l3_emif_clkdm",
 360         .flags          = HWMOD_INIT_NO_IDLE,
 361         .main_clk       = "ddrphy_ck",
 362         .prcm = {
 363                 .omap4 = {
 364                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 365                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 366                         .modulemode   = MODULEMODE_HWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /*
 372  * 'gpmc' class
 373  * general purpose memory controller
 374  */
 375
 376 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
 377         .rev_offs       = 0x0000,
 378         .sysc_offs      = 0x0010,
 379         .syss_offs      = 0x0014,
 380         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 381                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 382         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 383         .sysc_fields    = &omap_hwmod_sysc_type1,
 384 };
 385
 386 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 387         .name   = "gpmc",
 388         .sysc   = &omap44xx_gpmc_sysc,
 389 };
 390
 391 /* gpmc */
 392 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 393         .name           = "gpmc",
 394         .class          = &omap44xx_gpmc_hwmod_class,
 395         .clkdm_name     = "l3_2_clkdm",
 396         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 397         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 398         .prcm = {
 399                 .omap4 = {
 400                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
 401                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
 402                         .modulemode   = MODULEMODE_HWCTRL,
 403                 },
 404         },
 405 };
 406
 407 /*
 408  * 'iss' class
 409  * external images sensor pixel data processor
 410  */
 411
 412 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
 413         .rev_offs       = 0x0000,
 414         .sysc_offs      = 0x0010,
 415         /*
 416          * ISS needs 100 OCP clk cycles delay after a softreset before
 417          * accessing sysconfig again.
 418          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 419          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 420          *
 421          * TODO: Indicate errata when available.
 422          */
 423         .srst_udelay    = 2,
 424         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 425                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 426         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 427                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 428                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 429         .sysc_fields    = &omap_hwmod_sysc_type2,
 430 };
 431
 432 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 433         .name   = "iss",
 434         .sysc   = &omap44xx_iss_sysc,
 435 };
 436
 437 /* iss */
 438 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 439         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 440 };
 441
 442 static struct omap_hwmod omap44xx_iss_hwmod = {
 443         .name           = "iss",
 444         .class          = &omap44xx_iss_hwmod_class,
 445         .clkdm_name     = "iss_clkdm",
 446         .main_clk       = "ducati_clk_mux_ck",
 447         .prcm = {
 448                 .omap4 = {
 449                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
 450                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
 451                         .modulemode   = MODULEMODE_SWCTRL,
 452                 },
 453         },
 454         .opt_clks       = iss_opt_clks,
 455         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
 456 };
 457
 458 /*
 459  * 'iva' class
 460  * multi-standard video encoder/decoder hardware accelerator
 461  */
 462
 463 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 464         .name   = "iva",
 465 };
 466
 467 /* iva */
 468 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
 469         { .name = "seq0", .rst_shift = 0 },
 470         { .name = "seq1", .rst_shift = 1 },
 471         { .name = "logic", .rst_shift = 2 },
 472 };
 473
 474 static struct omap_hwmod omap44xx_iva_hwmod = {
 475         .name           = "iva",
 476         .class          = &omap44xx_iva_hwmod_class,
 477         .clkdm_name     = "ivahd_clkdm",
 478         .rst_lines      = omap44xx_iva_resets,
 479         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
 480         .main_clk       = "dpll_iva_m5x2_ck",
 481         .prcm = {
 482                 .omap4 = {
 483                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
 484                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 485                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
 486                         .modulemode   = MODULEMODE_HWCTRL,
 487                 },
 488         },
 489 };
 490
 491 /*
 492  * 'mpu' class
 493  * mpu sub-system
 494  */
 495
 496 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 497         .name   = "mpu",
 498 };
 499
 500 /* mpu */
 501 static struct omap_hwmod omap44xx_mpu_hwmod = {
 502         .name           = "mpu",
 503         .class          = &omap44xx_mpu_hwmod_class,
 504         .clkdm_name     = "mpuss_clkdm",
 505         .flags          = HWMOD_INIT_NO_IDLE,
 506         .main_clk       = "dpll_mpu_m2_ck",
 507         .prcm = {
 508                 .omap4 = {
 509                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
 510                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
 511                 },
 512         },
 513 };
 514
 515 /*
 516  * 'ocmc_ram' class
 517  * top-level core on-chip ram
 518  */
 519
 520 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
 521         .name   = "ocmc_ram",
 522 };
 523
 524 /* ocmc_ram */
 525 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
 526         .name           = "ocmc_ram",
 527         .class          = &omap44xx_ocmc_ram_hwmod_class,
 528         .clkdm_name     = "l3_2_clkdm",
 529         .prcm = {
 530                 .omap4 = {
 531                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
 532                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
 533                 },
 534         },
 535 };
 536
 537
 538 /*
 539  * 'prcm' class
 540  * power and reset manager (part of the prcm infrastructure) + clock manager 2
 541  * + clock manager 1 (in always on power domain) + local prm in mpu
 542  */
 543
 544 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
 545         .name   = "prcm",
 546 };
 547
 548 /* prcm_mpu */
 549 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 550         .name           = "prcm_mpu",
 551         .class          = &omap44xx_prcm_hwmod_class,
 552         .clkdm_name     = "l4_wkup_clkdm",
 553         .flags          = HWMOD_NO_IDLEST,
 554         .prcm = {
 555                 .omap4 = {
 556                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 557                 },
 558         },
 559 };
 560
 561 /* cm_core_aon */
 562 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
 563         .name           = "cm_core_aon",
 564         .class          = &omap44xx_prcm_hwmod_class,
 565         .flags          = HWMOD_NO_IDLEST,
 566         .prcm = {
 567                 .omap4 = {
 568                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 569                 },
 570         },
 571 };
 572
 573 /* cm_core */
 574 static struct omap_hwmod omap44xx_cm_core_hwmod = {
 575         .name           = "cm_core",
 576         .class          = &omap44xx_prcm_hwmod_class,
 577         .flags          = HWMOD_NO_IDLEST,
 578         .prcm = {
 579                 .omap4 = {
 580                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 581                 },
 582         },
 583 };
 584
 585 /* prm */
 586 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 587         { .name = "rst_global_warm_sw", .rst_shift = 0 },
 588         { .name = "rst_global_cold_sw", .rst_shift = 1 },
 589 };
 590
 591 static struct omap_hwmod omap44xx_prm_hwmod = {
 592         .name           = "prm",
 593         .class          = &omap44xx_prcm_hwmod_class,
 594         .rst_lines      = omap44xx_prm_resets,
 595         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 596 };
 597
 598 /*
 599  * 'scrm' class
 600  * system clock and reset manager
 601  */
 602
 603 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
 604         .name   = "scrm",
 605 };
 606
 607 /* scrm */
 608 static struct omap_hwmod omap44xx_scrm_hwmod = {
 609         .name           = "scrm",
 610         .class          = &omap44xx_scrm_hwmod_class,
 611         .clkdm_name     = "l4_wkup_clkdm",
 612         .prcm = {
 613                 .omap4 = {
 614                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 615                 },
 616         },
 617 };
 618
 619 /*
 620  * 'sl2if' class
 621  * shared level 2 memory interface
 622  */
 623
 624 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
 625         .name   = "sl2if",
 626 };
 627
 628 /* sl2if */
 629 static struct omap_hwmod omap44xx_sl2if_hwmod = {
 630         .name           = "sl2if",
 631         .class          = &omap44xx_sl2if_hwmod_class,
 632         .clkdm_name     = "ivahd_clkdm",
 633         .prcm = {
 634                 .omap4 = {
 635                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
 636                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
 637                         .modulemode   = MODULEMODE_HWCTRL,
 638                 },
 639         },
 640 };
 641
 642 /*
 643  * interfaces
 644  */
 645
 646 /* l3_main_1 -> dmm */
 647 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 648         .master         = &omap44xx_l3_main_1_hwmod,
 649         .slave          = &omap44xx_dmm_hwmod,
 650         .clk            = "l3_div_ck",
 651         .user           = OCP_USER_SDMA,
 652 };
 653
 654 /* mpu -> dmm */
 655 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 656         .master         = &omap44xx_mpu_hwmod,
 657         .slave          = &omap44xx_dmm_hwmod,
 658         .clk            = "l3_div_ck",
 659         .user           = OCP_USER_MPU,
 660 };
 661
 662 /* iva -> l3_instr */
 663 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 664         .master         = &omap44xx_iva_hwmod,
 665         .slave          = &omap44xx_l3_instr_hwmod,
 666         .clk            = "l3_div_ck",
 667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 668 };
 669
 670 /* l3_main_3 -> l3_instr */
 671 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 672         .master         = &omap44xx_l3_main_3_hwmod,
 673         .slave          = &omap44xx_l3_instr_hwmod,
 674         .clk            = "l3_div_ck",
 675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 676 };
 677
 678 /* ocp_wp_noc -> l3_instr */
 679 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
 680         .master         = &omap44xx_ocp_wp_noc_hwmod,
 681         .slave          = &omap44xx_l3_instr_hwmod,
 682         .clk            = "l3_div_ck",
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* l3_main_2 -> l3_main_1 */
 687 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 688         .master         = &omap44xx_l3_main_2_hwmod,
 689         .slave          = &omap44xx_l3_main_1_hwmod,
 690         .clk            = "l3_div_ck",
 691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 692 };
 693
 694 /* l4_cfg -> l3_main_1 */
 695 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 696         .master         = &omap44xx_l4_cfg_hwmod,
 697         .slave          = &omap44xx_l3_main_1_hwmod,
 698         .clk            = "l4_div_ck",
 699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 700 };
 701
 702 /* mpu -> l3_main_1 */
 703 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 704         .master         = &omap44xx_mpu_hwmod,
 705         .slave          = &omap44xx_l3_main_1_hwmod,
 706         .clk            = "l3_div_ck",
 707         .user           = OCP_USER_MPU,
 708 };
 709
 710 /* debugss -> l3_main_2 */
 711 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
 712         .master         = &omap44xx_debugss_hwmod,
 713         .slave          = &omap44xx_l3_main_2_hwmod,
 714         .clk            = "dbgclk_mux_ck",
 715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 716 };
 717
 718 /* iss -> l3_main_2 */
 719 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 720         .master         = &omap44xx_iss_hwmod,
 721         .slave          = &omap44xx_l3_main_2_hwmod,
 722         .clk            = "l3_div_ck",
 723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 724 };
 725
 726 /* iva -> l3_main_2 */
 727 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 728         .master         = &omap44xx_iva_hwmod,
 729         .slave          = &omap44xx_l3_main_2_hwmod,
 730         .clk            = "l3_div_ck",
 731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 732 };
 733
 734 /* l3_main_1 -> l3_main_2 */
 735 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 736         .master         = &omap44xx_l3_main_1_hwmod,
 737         .slave          = &omap44xx_l3_main_2_hwmod,
 738         .clk            = "l3_div_ck",
 739         .user           = OCP_USER_MPU,
 740 };
 741
 742 /* l4_cfg -> l3_main_2 */
 743 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 744         .master         = &omap44xx_l4_cfg_hwmod,
 745         .slave          = &omap44xx_l3_main_2_hwmod,
 746         .clk            = "l4_div_ck",
 747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 748 };
 749
 750 /* l3_main_1 -> l3_main_3 */
 751 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 752         .master         = &omap44xx_l3_main_1_hwmod,
 753         .slave          = &omap44xx_l3_main_3_hwmod,
 754         .clk            = "l3_div_ck",
 755         .user           = OCP_USER_MPU,
 756 };
 757
 758 /* l3_main_2 -> l3_main_3 */
 759 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 760         .master         = &omap44xx_l3_main_2_hwmod,
 761         .slave          = &omap44xx_l3_main_3_hwmod,
 762         .clk            = "l3_div_ck",
 763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 764 };
 765
 766 /* l4_cfg -> l3_main_3 */
 767 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 768         .master         = &omap44xx_l4_cfg_hwmod,
 769         .slave          = &omap44xx_l3_main_3_hwmod,
 770         .clk            = "l4_div_ck",
 771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 772 };
 773
 774 /* l3_main_1 -> l4_abe */
 775 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 776         .master         = &omap44xx_l3_main_1_hwmod,
 777         .slave          = &omap44xx_l4_abe_hwmod,
 778         .clk            = "l3_div_ck",
 779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 780 };
 781
 782 /* mpu -> l4_abe */
 783 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 784         .master         = &omap44xx_mpu_hwmod,
 785         .slave          = &omap44xx_l4_abe_hwmod,
 786         .clk            = "ocp_abe_iclk",
 787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 788 };
 789
 790 /* l3_main_1 -> l4_cfg */
 791 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 792         .master         = &omap44xx_l3_main_1_hwmod,
 793         .slave          = &omap44xx_l4_cfg_hwmod,
 794         .clk            = "l3_div_ck",
 795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 796 };
 797
 798 /* l3_main_2 -> l4_per */
 799 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 800         .master         = &omap44xx_l3_main_2_hwmod,
 801         .slave          = &omap44xx_l4_per_hwmod,
 802         .clk            = "l3_div_ck",
 803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 804 };
 805
 806 /* l4_cfg -> l4_wkup */
 807 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 808         .master         = &omap44xx_l4_cfg_hwmod,
 809         .slave          = &omap44xx_l4_wkup_hwmod,
 810         .clk            = "l4_div_ck",
 811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 812 };
 813
 814 /* mpu -> mpu_private */
 815 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 816         .master         = &omap44xx_mpu_hwmod,
 817         .slave          = &omap44xx_mpu_private_hwmod,
 818         .clk            = "l3_div_ck",
 819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 820 };
 821
 822 /* l4_cfg -> ocp_wp_noc */
 823 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
 824         .master         = &omap44xx_l4_cfg_hwmod,
 825         .slave          = &omap44xx_ocp_wp_noc_hwmod,
 826         .clk            = "l4_div_ck",
 827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 828 };
 829
 830 /* l4_cfg -> ctrl_module_core */
 831 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
 832         .master         = &omap44xx_l4_cfg_hwmod,
 833         .slave          = &omap44xx_ctrl_module_core_hwmod,
 834         .clk            = "l4_div_ck",
 835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 836 };
 837
 838 /* l4_cfg -> ctrl_module_pad_core */
 839 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
 840         .master         = &omap44xx_l4_cfg_hwmod,
 841         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
 842         .clk            = "l4_div_ck",
 843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 844 };
 845
 846 /* l4_wkup -> ctrl_module_wkup */
 847 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
 848         .master         = &omap44xx_l4_wkup_hwmod,
 849         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
 850         .clk            = "l4_wkup_clk_mux_ck",
 851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 852 };
 853
 854 /* l4_wkup -> ctrl_module_pad_wkup */
 855 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
 856         .master         = &omap44xx_l4_wkup_hwmod,
 857         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
 858         .clk            = "l4_wkup_clk_mux_ck",
 859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 860 };
 861
 862 /* l3_instr -> debugss */
 863 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
 864         .master         = &omap44xx_l3_instr_hwmod,
 865         .slave          = &omap44xx_debugss_hwmod,
 866         .clk            = "l3_div_ck",
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 /* l3_main_2 -> gpmc */
 871 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
 872         .master         = &omap44xx_l3_main_2_hwmod,
 873         .slave          = &omap44xx_gpmc_hwmod,
 874         .clk            = "l3_div_ck",
 875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 876 };
 877
 878 /* l3_main_2 -> iss */
 879 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
 880         .master         = &omap44xx_l3_main_2_hwmod,
 881         .slave          = &omap44xx_iss_hwmod,
 882         .clk            = "l3_div_ck",
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* iva -> sl2if */
 887 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
 888         .master         = &omap44xx_iva_hwmod,
 889         .slave          = &omap44xx_sl2if_hwmod,
 890         .clk            = "dpll_iva_m5x2_ck",
 891         .user           = OCP_USER_IVA,
 892 };
 893
 894 /* l3_main_2 -> iva */
 895 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
 896         .master         = &omap44xx_l3_main_2_hwmod,
 897         .slave          = &omap44xx_iva_hwmod,
 898         .clk            = "l3_div_ck",
 899         .user           = OCP_USER_MPU,
 900 };
 901
 902 /* l3_main_2 -> ocmc_ram */
 903 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
 904         .master         = &omap44xx_l3_main_2_hwmod,
 905         .slave          = &omap44xx_ocmc_ram_hwmod,
 906         .clk            = "l3_div_ck",
 907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 908 };
 909
 910 /* mpu_private -> prcm_mpu */
 911 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
 912         .master         = &omap44xx_mpu_private_hwmod,
 913         .slave          = &omap44xx_prcm_mpu_hwmod,
 914         .clk            = "l3_div_ck",
 915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 916 };
 917
 918 /* l4_wkup -> cm_core_aon */
 919 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
 920         .master         = &omap44xx_l4_wkup_hwmod,
 921         .slave          = &omap44xx_cm_core_aon_hwmod,
 922         .clk            = "l4_wkup_clk_mux_ck",
 923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 924 };
 925
 926 /* l4_cfg -> cm_core */
 927 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
 928         .master         = &omap44xx_l4_cfg_hwmod,
 929         .slave          = &omap44xx_cm_core_hwmod,
 930         .clk            = "l4_div_ck",
 931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 932 };
 933
 934 /* l4_wkup -> prm */
 935 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
 936         .master         = &omap44xx_l4_wkup_hwmod,
 937         .slave          = &omap44xx_prm_hwmod,
 938         .clk            = "l4_wkup_clk_mux_ck",
 939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 940 };
 941
 942 /* l4_wkup -> scrm */
 943 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 944         .master         = &omap44xx_l4_wkup_hwmod,
 945         .slave          = &omap44xx_scrm_hwmod,
 946         .clk            = "l4_wkup_clk_mux_ck",
 947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 948 };
 949
 950 /* l3_main_2 -> sl2if */
 951 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
 952         .master         = &omap44xx_l3_main_2_hwmod,
 953         .slave          = &omap44xx_sl2if_hwmod,
 954         .clk            = "l3_div_ck",
 955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 956 };
 957
 958 /* mpu -> emif1 */
 959 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
 960         .master         = &omap44xx_mpu_hwmod,
 961         .slave          = &omap44xx_emif1_hwmod,
 962         .clk            = "l3_div_ck",
 963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 964 };
 965
 966 /* mpu -> emif2 */
 967 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
 968         .master         = &omap44xx_mpu_hwmod,
 969         .slave          = &omap44xx_emif2_hwmod,
 970         .clk            = "l3_div_ck",
 971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 972 };
 973
 974 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 975         &omap44xx_l3_main_1__dmm,
 976         &omap44xx_mpu__dmm,
 977         &omap44xx_iva__l3_instr,
 978         &omap44xx_l3_main_3__l3_instr,
 979         &omap44xx_ocp_wp_noc__l3_instr,
 980         &omap44xx_l3_main_2__l3_main_1,
 981         &omap44xx_l4_cfg__l3_main_1,
 982         &omap44xx_mpu__l3_main_1,
 983         &omap44xx_debugss__l3_main_2,
 984         &omap44xx_iss__l3_main_2,
 985         &omap44xx_iva__l3_main_2,
 986         &omap44xx_l3_main_1__l3_main_2,
 987         &omap44xx_l4_cfg__l3_main_2,
 988         &omap44xx_l3_main_1__l3_main_3,
 989         &omap44xx_l3_main_2__l3_main_3,
 990         &omap44xx_l4_cfg__l3_main_3,
 991         &omap44xx_l3_main_1__l4_abe,
 992         &omap44xx_mpu__l4_abe,
 993         &omap44xx_l3_main_1__l4_cfg,
 994         &omap44xx_l3_main_2__l4_per,
 995         &omap44xx_l4_cfg__l4_wkup,
 996         &omap44xx_mpu__mpu_private,
 997         &omap44xx_l4_cfg__ocp_wp_noc,
 998         &omap44xx_l4_cfg__ctrl_module_core,
 999         &omap44xx_l4_cfg__ctrl_module_pad_core,
1000         &omap44xx_l4_wkup__ctrl_module_wkup,
1001         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
1002         &omap44xx_l3_instr__debugss,
1003         &omap44xx_l3_main_2__gpmc,
1004         &omap44xx_l3_main_2__iss,
1005         /* &omap44xx_iva__sl2if, */
1006         &omap44xx_l3_main_2__iva,
1007         &omap44xx_l3_main_2__ocmc_ram,
1008         &omap44xx_mpu_private__prcm_mpu,
1009         &omap44xx_l4_wkup__cm_core_aon,
1010         &omap44xx_l4_cfg__cm_core,
1011         &omap44xx_l4_wkup__prm,
1012         &omap44xx_l4_wkup__scrm,
1013         /* &omap44xx_l3_main_2__sl2if, */
1014         &omap44xx_mpu__emif1,
1015         &omap44xx_mpu__emif2,
1016         NULL,
1017 };
1018
1019 int __init omap44xx_hwmod_init(void)
1020 {
1021         omap_hwmod_init();
1022         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
1023 }
1024