drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
 130                                                struct drm_file *filp,
 131                                                struct amdgpu_ctx *ctx,
 132                                                struct amdgpu_ib *ibs,
 133                                                uint32_t num_ibs)
 134 {
 135         struct amdgpu_cs_parser *parser;
 136         int i;
 137
 138         parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL);
 139         if (!parser)
 140                 return NULL;
 141
 142         parser->adev = adev;
 143         parser->filp = filp;
 144         parser->ctx = ctx;
 145         parser->ibs = ibs;
 146         parser->num_ibs = num_ibs;
 147         for (i = 0; i < num_ibs; i++)
 148                 ibs[i].ctx = ctx;
 149
 150         return parser;
 151 }
 152
 153 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 154 {
 155         union drm_amdgpu_cs *cs = data;
 156         uint64_t *chunk_array_user;
 157         uint64_t *chunk_array = NULL;
 158         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 159         unsigned size, i;
 160         int r = 0;
 161
 162         if (!cs->in.num_chunks)
 163                 goto out;
 164
 165         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 166         if (!p->ctx) {
 167                 r = -EINVAL;
 168                 goto out;
 169         }
 170         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 171
 172         /* get chunks */
 173         INIT_LIST_HEAD(&p->validated);
 174         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 175         if (chunk_array == NULL) {
 176                 r = -ENOMEM;
 177                 goto out;
 178         }
 179
 180         chunk_array_user = (uint64_t __user *)(cs->in.chunks);
 181         if (copy_from_user(chunk_array, chunk_array_user,
 182                            sizeof(uint64_t)*cs->in.num_chunks)) {
 183                 r = -EFAULT;
 184                 goto out;
 185         }
 186
 187         p->nchunks = cs->in.num_chunks;
 188         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 189                             GFP_KERNEL);
 190         if (p->chunks == NULL) {
 191                 r = -ENOMEM;
 192                 goto out;
 193         }
 194
 195         for (i = 0; i < p->nchunks; i++) {
 196                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 197                 struct drm_amdgpu_cs_chunk user_chunk;
 198                 uint32_t __user *cdata;
 199
 200                 chunk_ptr = (void __user *)chunk_array[i];
 201                 if (copy_from_user(&user_chunk, chunk_ptr,
 202                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 203                         r = -EFAULT;
 204                         goto out;
 205                 }
 206                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 207                 p->chunks[i].length_dw = user_chunk.length_dw;
 208
 209                 size = p->chunks[i].length_dw;
 210                 cdata = (void __user *)user_chunk.chunk_data;
 211                 p->chunks[i].user_ptr = cdata;
 212
 213                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 214                 if (p->chunks[i].kdata == NULL) {
 215                         r = -ENOMEM;
 216                         goto out;
 217                 }
 218                 size *= sizeof(uint32_t);
 219                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 220                         r = -EFAULT;
 221                         goto out;
 222                 }
 223
 224                 switch (p->chunks[i].chunk_id) {
 225                 case AMDGPU_CHUNK_ID_IB:
 226                         p->num_ibs++;
 227                         break;
 228
 229                 case AMDGPU_CHUNK_ID_FENCE:
 230                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 231                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 232                                 uint32_t handle;
 233                                 struct drm_gem_object *gobj;
 234                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 235
 236                                 fence_data = (void *)p->chunks[i].kdata;
 237                                 handle = fence_data->handle;
 238                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 239                                                              p->filp, handle);
 240                                 if (gobj == NULL) {
 241                                         r = -EINVAL;
 242                                         goto out;
 243                                 }
 244
 245                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 246                                 p->uf.offset = fence_data->offset;
 247                         } else {
 248                                 r = -EINVAL;
 249                                 goto out;
 250                         }
 251                         break;
 252
 253                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 254                         break;
 255
 256                 default:
 257                         r = -EINVAL;
 258                         goto out;
 259                 }
 260         }
 261
 262
 263         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 264         if (!p->ibs)
 265                 r = -ENOMEM;
 266
 267 out:
 268         kfree(chunk_array);
 269         return r;
 270 }
 271
 272 /* Returns how many bytes TTM can move per IB.
 273  */
 274 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 275 {
 276         u64 real_vram_size = adev->mc.real_vram_size;
 277         u64 vram_usage = atomic64_read(&adev->vram_usage);
 278
 279         /* This function is based on the current VRAM usage.
 280          *
 281          * - If all of VRAM is free, allow relocating the number of bytes that
 282          *   is equal to 1/4 of the size of VRAM for this IB.
 283
 284          * - If more than one half of VRAM is occupied, only allow relocating
 285          *   1 MB of data for this IB.
 286          *
 287          * - From 0 to one half of used VRAM, the threshold decreases
 288          *   linearly.
 289          *         __________________
 290          * 1/4 of -|\               |
 291          * VRAM    | \              |
 292          *         |  \             |
 293          *         |   \            |
 294          *         |    \           |
 295          *         |     \          |
 296          *         |      \         |
 297          *         |       \________|1 MB
 298          *         |----------------|
 299          *    VRAM 0 %             100 %
 300          *         used            used
 301          *
 302          * Note: It's a threshold, not a limit. The threshold must be crossed
 303          * for buffer relocations to stop, so any buffer of an arbitrary size
 304          * can be moved as long as the threshold isn't crossed before
 305          * the relocation takes place. We don't want to disable buffer
 306          * relocations completely.
 307          *
 308          * The idea is that buffers should be placed in VRAM at creation time
 309          * and TTM should only do a minimum number of relocations during
 310          * command submission. In practice, you need to submit at least
 311          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 312          *
 313          * Also, things can get pretty crazy under memory pressure and actual
 314          * VRAM usage can change a lot, so playing safe even at 50% does
 315          * consistently increase performance.
 316          */
 317
 318         u64 half_vram = real_vram_size >> 1;
 319         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 320         u64 bytes_moved_threshold = half_free_vram >> 1;
 321         return max(bytes_moved_threshold, 1024*1024ull);
 322 }
 323
 324 int amdgpu_cs_list_validate(struct amdgpu_device *adev,
 325                             struct amdgpu_vm *vm,
 326                             struct list_head *validated)
 327 {
 328         struct amdgpu_bo_list_entry *lobj;
 329         struct amdgpu_bo *bo;
 330         u64 bytes_moved = 0, initial_bytes_moved;
 331         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 332         int r;
 333
 334         list_for_each_entry(lobj, validated, tv.head) {
 335                 bo = lobj->robj;
 336                 if (!bo->pin_count) {
 337                         u32 domain = lobj->prefered_domains;
 338                         u32 current_domain =
 339                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 340
 341                         /* Check if this buffer will be moved and don't move it
 342                          * if we have moved too many buffers for this IB already.
 343                          *
 344                          * Note that this allows moving at least one buffer of
 345                          * any size, because it doesn't take the current "bo"
 346                          * into account. We don't want to disallow buffer moves
 347                          * completely.
 348                          */
 349                         if ((lobj->allowed_domains & current_domain) != 0 &&
 350                             (domain & current_domain) == 0 && /* will be moved */
 351                             bytes_moved > bytes_moved_threshold) {
 352                                 /* don't move it */
 353                                 domain = current_domain;
 354                         }
 355
 356                 retry:
 357                         amdgpu_ttm_placement_from_domain(bo, domain);
 358                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 359                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 360                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 361                                        initial_bytes_moved;
 362
 363                         if (unlikely(r)) {
 364                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 365                                         domain = lobj->allowed_domains;
 366                                         goto retry;
 367                                 }
 368                                 return r;
 369                         }
 370                 }
 371                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 372         }
 373         return 0;
 374 }
 375
 376 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 377 {
 378         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 379         struct amdgpu_cs_buckets buckets;
 380         struct list_head duplicates;
 381         bool need_mmap_lock = false;
 382         int i, r;
 383
 384         if (p->bo_list) {
 385                 need_mmap_lock = p->bo_list->has_userptr;
 386                 amdgpu_cs_buckets_init(&buckets);
 387                 for (i = 0; i < p->bo_list->num_entries; i++)
 388                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 389                                                                   p->bo_list->array[i].priority);
 390
 391                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 392         }
 393
 394         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 395                                       &p->validated);
 396
 397         if (need_mmap_lock)
 398                 down_read(&current->mm->mmap_sem);
 399
 400         INIT_LIST_HEAD(&duplicates);
 401         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 402         if (unlikely(r != 0))
 403                 goto error_reserve;
 404
 405         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
 406         if (r)
 407                 goto error_validate;
 408
 409         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
 410
 411 error_validate:
 412         if (r)
 413                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 414
 415 error_reserve:
 416         if (need_mmap_lock)
 417                 up_read(&current->mm->mmap_sem);
 418
 419         return r;
 420 }
 421
 422 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 423 {
 424         struct amdgpu_bo_list_entry *e;
 425         int r;
 426
 427         list_for_each_entry(e, &p->validated, tv.head) {
 428                 struct reservation_object *resv = e->robj->tbo.resv;
 429                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 430
 431                 if (r)
 432                         return r;
 433         }
 434         return 0;
 435 }
 436
 437 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 438                                   struct list_head *b)
 439 {
 440         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 441         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 442
 443         /* Sort A before B if A is smaller. */
 444         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 445 }
 446
 447 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
 448 {
 449         if (!error) {
 450                 /* Sort the buffer list from the smallest to largest buffer,
 451                  * which affects the order of buffers in the LRU list.
 452                  * This assures that the smallest buffers are added first
 453                  * to the LRU list, so they are likely to be later evicted
 454                  * first, instead of large buffers whose eviction is more
 455                  * expensive.
 456                  *
 457                  * This slightly lowers the number of bytes moved by TTM
 458                  * per frame under memory pressure.
 459                  */
 460                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 461
 462                 ttm_eu_fence_buffer_objects(&parser->ticket,
 463                                 &parser->validated,
 464                                 &parser->ibs[parser->num_ibs-1].fence->base);
 465         } else if (backoff) {
 466                 ttm_eu_backoff_reservation(&parser->ticket,
 467                                            &parser->validated);
 468         }
 469 }
 470
 471 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
 472 {
 473         unsigned i;
 474         if (parser->ctx)
 475                 amdgpu_ctx_put(parser->ctx);
 476         if (parser->bo_list)
 477                 amdgpu_bo_list_put(parser->bo_list);
 478
 479         drm_free_large(parser->vm_bos);
 480         for (i = 0; i < parser->nchunks; i++)
 481                 drm_free_large(parser->chunks[i].kdata);
 482         kfree(parser->chunks);
 483         if (!amdgpu_enable_scheduler)
 484         {
 485                 if (parser->ibs)
 486                         for (i = 0; i < parser->num_ibs; i++)
 487                                 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 488                 kfree(parser->ibs);
 489                 if (parser->uf.bo)
 490                         drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 491         }
 492
 493         kfree(parser);
 494 }
 495
 496 /**
 497  * cs_parser_fini() - clean parser states
 498  * @parser:     parser structure holding parsing context.
 499  * @error:      error number
 500  *
 501  * If error is set than unvalidate buffer, otherwise just free memory
 502  * used by parsing context.
 503  **/
 504 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 505 {
 506        amdgpu_cs_parser_fini_early(parser, error, backoff);
 507        amdgpu_cs_parser_fini_late(parser);
 508 }
 509
 510 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 511                                    struct amdgpu_vm *vm)
 512 {
 513         struct amdgpu_device *adev = p->adev;
 514         struct amdgpu_bo_va *bo_va;
 515         struct amdgpu_bo *bo;
 516         int i, r;
 517
 518         r = amdgpu_vm_update_page_directory(adev, vm);
 519         if (r)
 520                 return r;
 521
 522         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
 523         if (r)
 524                 return r;
 525
 526         r = amdgpu_vm_clear_freed(adev, vm);
 527         if (r)
 528                 return r;
 529
 530         if (p->bo_list) {
 531                 for (i = 0; i < p->bo_list->num_entries; i++) {
 532                         struct fence *f;
 533
 534                         /* ignore duplicates */
 535                         bo = p->bo_list->array[i].robj;
 536                         if (!bo)
 537                                 continue;
 538
 539                         bo_va = p->bo_list->array[i].bo_va;
 540                         if (bo_va == NULL)
 541                                 continue;
 542
 543                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 544                         if (r)
 545                                 return r;
 546
 547                         f = bo_va->last_pt_update;
 548                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 549                         if (r)
 550                                 return r;
 551                 }
 552         }
 553
 554         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 555 }
 556
 557 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 558                                  struct amdgpu_cs_parser *parser)
 559 {
 560         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 561         struct amdgpu_vm *vm = &fpriv->vm;
 562         struct amdgpu_ring *ring;
 563         int i, r;
 564
 565         if (parser->num_ibs == 0)
 566                 return 0;
 567
 568         /* Only for UVD/VCE VM emulation */
 569         for (i = 0; i < parser->num_ibs; i++) {
 570                 ring = parser->ibs[i].ring;
 571                 if (ring->funcs->parse_cs) {
 572                         r = amdgpu_ring_parse_cs(ring, parser, i);
 573                         if (r)
 574                                 return r;
 575                 }
 576         }
 577
 578         mutex_lock(&vm->mutex);
 579         r = amdgpu_bo_vm_update_pte(parser, vm);
 580         if (r) {
 581                 goto out;
 582         }
 583         amdgpu_cs_sync_rings(parser);
 584         if (!amdgpu_enable_scheduler)
 585                 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 586                                        parser->filp);
 587
 588 out:
 589         mutex_unlock(&vm->mutex);
 590         return r;
 591 }
 592
 593 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 594 {
 595         if (r == -EDEADLK) {
 596                 r = amdgpu_gpu_reset(adev);
 597                 if (!r)
 598                         r = -EAGAIN;
 599         }
 600         return r;
 601 }
 602
 603 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 604                              struct amdgpu_cs_parser *parser)
 605 {
 606         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 607         struct amdgpu_vm *vm = &fpriv->vm;
 608         int i, j;
 609         int r;
 610
 611         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 612                 struct amdgpu_cs_chunk *chunk;
 613                 struct amdgpu_ib *ib;
 614                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 615                 struct amdgpu_ring *ring;
 616
 617                 chunk = &parser->chunks[i];
 618                 ib = &parser->ibs[j];
 619                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 620
 621                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 622                         continue;
 623
 624                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 625                                        chunk_ib->ip_instance, chunk_ib->ring,
 626                                        &ring);
 627                 if (r)
 628                         return r;
 629
 630                 if (ring->funcs->parse_cs) {
 631                         struct amdgpu_bo_va_mapping *m;
 632                         struct amdgpu_bo *aobj = NULL;
 633                         uint64_t offset;
 634                         uint8_t *kptr;
 635
 636                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 637                                                    &aobj);
 638                         if (!aobj) {
 639                                 DRM_ERROR("IB va_start is invalid\n");
 640                                 return -EINVAL;
 641                         }
 642
 643                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 644                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 645                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 646                                 return -EINVAL;
 647                         }
 648
 649                         /* the IB should be reserved at this point */
 650                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 651                         if (r) {
 652                                 return r;
 653                         }
 654
 655                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 656                         kptr += chunk_ib->va_start - offset;
 657
 658                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 659                         if (r) {
 660                                 DRM_ERROR("Failed to get ib !\n");
 661                                 return r;
 662                         }
 663
 664                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 665                         amdgpu_bo_kunmap(aobj);
 666                 } else {
 667                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 668                         if (r) {
 669                                 DRM_ERROR("Failed to get ib !\n");
 670                                 return r;
 671                         }
 672
 673                         ib->gpu_addr = chunk_ib->va_start;
 674                 }
 675
 676                 ib->length_dw = chunk_ib->ib_bytes / 4;
 677                 ib->flags = chunk_ib->flags;
 678                 ib->ctx = parser->ctx;
 679                 j++;
 680         }
 681
 682         if (!parser->num_ibs)
 683                 return 0;
 684
 685         /* add GDS resources to first IB */
 686         if (parser->bo_list) {
 687                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 688                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 689                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 690                 struct amdgpu_ib *ib = &parser->ibs[0];
 691
 692                 if (gds) {
 693                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 694                         ib->gds_size = amdgpu_bo_size(gds);
 695                 }
 696                 if (gws) {
 697                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 698                         ib->gws_size = amdgpu_bo_size(gws);
 699                 }
 700                 if (oa) {
 701                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 702                         ib->oa_size = amdgpu_bo_size(oa);
 703                 }
 704         }
 705         /* wrap the last IB with user fence */
 706         if (parser->uf.bo) {
 707                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 708
 709                 /* UVD & VCE fw doesn't support user fences */
 710                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 711                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 712                         return -EINVAL;
 713
 714                 ib->user = &parser->uf;
 715         }
 716
 717         return 0;
 718 }
 719
 720 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 721                                   struct amdgpu_cs_parser *p)
 722 {
 723         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 724         struct amdgpu_ib *ib;
 725         int i, j, r;
 726
 727         if (!p->num_ibs)
 728                 return 0;
 729
 730         /* Add dependencies to first IB */
 731         ib = &p->ibs[0];
 732         for (i = 0; i < p->nchunks; ++i) {
 733                 struct drm_amdgpu_cs_chunk_dep *deps;
 734                 struct amdgpu_cs_chunk *chunk;
 735                 unsigned num_deps;
 736
 737                 chunk = &p->chunks[i];
 738
 739                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 740                         continue;
 741
 742                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 743                 num_deps = chunk->length_dw * 4 /
 744                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 745
 746                 for (j = 0; j < num_deps; ++j) {
 747                         struct amdgpu_ring *ring;
 748                         struct amdgpu_ctx *ctx;
 749                         struct fence *fence;
 750
 751                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 752                                                deps[j].ip_instance,
 753                                                deps[j].ring, &ring);
 754                         if (r)
 755                                 return r;
 756
 757                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 758                         if (ctx == NULL)
 759                                 return -EINVAL;
 760
 761                         fence = amdgpu_ctx_get_fence(ctx, ring,
 762                                                      deps[j].handle);
 763                         if (IS_ERR(fence)) {
 764                                 r = PTR_ERR(fence);
 765                                 amdgpu_ctx_put(ctx);
 766                                 return r;
 767
 768                         } else if (fence) {
 769                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 770                                 fence_put(fence);
 771                                 amdgpu_ctx_put(ctx);
 772                                 if (r)
 773                                         return r;
 774                         }
 775                 }
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int amdgpu_cs_free_job(struct amdgpu_job *job)
 782 {
 783         int i;
 784         if (job->ibs)
 785                 for (i = 0; i < job->num_ibs; i++)
 786                         amdgpu_ib_free(job->adev, &job->ibs[i]);
 787         kfree(job->ibs);
 788         if (job->uf.bo)
 789                 drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base);
 790         return 0;
 791 }
 792
 793 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 794 {
 795         struct amdgpu_device *adev = dev->dev_private;
 796         union drm_amdgpu_cs *cs = data;
 797         struct amdgpu_cs_parser *parser;
 798         bool reserved_buffers = false;
 799         int i, r;
 800
 801         down_read(&adev->exclusive_lock);
 802         if (!adev->accel_working) {
 803                 up_read(&adev->exclusive_lock);
 804                 return -EBUSY;
 805         }
 806
 807         parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
 808         if (!parser)
 809                 return -ENOMEM;
 810         r = amdgpu_cs_parser_init(parser, data);
 811         if (r) {
 812                 DRM_ERROR("Failed to initialize parser !\n");
 813                 amdgpu_cs_parser_fini(parser, r, false);
 814                 up_read(&adev->exclusive_lock);
 815                 r = amdgpu_cs_handle_lockup(adev, r);
 816                 return r;
 817         }
 818
 819         r = amdgpu_cs_parser_relocs(parser);
 820         if (r == -ENOMEM)
 821                 DRM_ERROR("Not enough memory for command submission!\n");
 822         else if (r && r != -ERESTARTSYS)
 823                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 824         else if (!r) {
 825                 reserved_buffers = true;
 826                 r = amdgpu_cs_ib_fill(adev, parser);
 827         }
 828
 829         if (!r) {
 830                 r = amdgpu_cs_dependencies(adev, parser);
 831                 if (r)
 832                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 833         }
 834
 835         if (r)
 836                 goto out;
 837
 838         for (i = 0; i < parser->num_ibs; i++)
 839                 trace_amdgpu_cs(parser, i);
 840
 841         r = amdgpu_cs_ib_vm_chunk(adev, parser);
 842         if (r)
 843                 goto out;
 844
 845         if (amdgpu_enable_scheduler && parser->num_ibs) {
 846                 struct amdgpu_job *job;
 847                 struct amdgpu_ring * ring =  parser->ibs->ring;
 848                 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
 849                 if (!job)
 850                         return -ENOMEM;
 851                 job->base.sched = &ring->sched;
 852                 job->base.s_entity = &parser->ctx->rings[ring->idx].entity;
 853                 job->adev = parser->adev;
 854                 job->ibs = parser->ibs;
 855                 job->num_ibs = parser->num_ibs;
 856                 job->base.owner = parser->filp;
 857                 mutex_init(&job->job_lock);
 858                 if (job->ibs[job->num_ibs - 1].user) {
 859                         memcpy(&job->uf,  &parser->uf,
 860                                sizeof(struct amdgpu_user_fence));
 861                         job->ibs[job->num_ibs - 1].user = &job->uf;
 862                 }
 863
 864                 job->free_job = amdgpu_cs_free_job;
 865                 mutex_lock(&job->job_lock);
 866                 r = amd_sched_entity_push_job(&job->base);
 867                 if (r) {
 868                         mutex_unlock(&job->job_lock);
 869                         amdgpu_cs_free_job(job);
 870                         kfree(job);
 871                         goto out;
 872                 }
 873                 cs->out.handle =
 874                         amdgpu_ctx_add_fence(parser->ctx, ring,
 875                                              &job->base.s_fence->base);
 876                 parser->ibs[parser->num_ibs - 1].sequence = cs->out.handle;
 877
 878                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 879                 ttm_eu_fence_buffer_objects(&parser->ticket,
 880                                 &parser->validated,
 881                                 &job->base.s_fence->base);
 882
 883                 mutex_unlock(&job->job_lock);
 884                 amdgpu_cs_parser_fini_late(parser);
 885                 up_read(&adev->exclusive_lock);
 886                 return 0;
 887         }
 888
 889         cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
 890 out:
 891         amdgpu_cs_parser_fini(parser, r, reserved_buffers);
 892         up_read(&adev->exclusive_lock);
 893         r = amdgpu_cs_handle_lockup(adev, r);
 894         return r;
 895 }
 896
 897 /**
 898  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 899  *
 900  * @dev: drm device
 901  * @data: data from userspace
 902  * @filp: file private
 903  *
 904  * Wait for the command submission identified by handle to finish.
 905  */
 906 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 907                          struct drm_file *filp)
 908 {
 909         union drm_amdgpu_wait_cs *wait = data;
 910         struct amdgpu_device *adev = dev->dev_private;
 911         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 912         struct amdgpu_ring *ring = NULL;
 913         struct amdgpu_ctx *ctx;
 914         struct fence *fence;
 915         long r;
 916
 917         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 918                                wait->in.ring, &ring);
 919         if (r)
 920                 return r;
 921
 922         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 923         if (ctx == NULL)
 924                 return -EINVAL;
 925
 926         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 927         if (IS_ERR(fence))
 928                 r = PTR_ERR(fence);
 929         else if (fence) {
 930                 r = fence_wait_timeout(fence, true, timeout);
 931                 fence_put(fence);
 932         } else
 933                 r = 1;
 934
 935         amdgpu_ctx_put(ctx);
 936         if (r < 0)
 937                 return r;
 938
 939         memset(wait, 0, sizeof(*wait));
 940         wait->out.status = (r == 0);
 941
 942         return 0;
 943 }
 944
 945 /**
 946  * amdgpu_cs_find_bo_va - find bo_va for VM address
 947  *
 948  * @parser: command submission parser context
 949  * @addr: VM address
 950  * @bo: resulting BO of the mapping found
 951  *
 952  * Search the buffer objects in the command submission context for a certain
 953  * virtual memory address. Returns allocation structure when found, NULL
 954  * otherwise.
 955  */
 956 struct amdgpu_bo_va_mapping *
 957 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 958                        uint64_t addr, struct amdgpu_bo **bo)
 959 {
 960         struct amdgpu_bo_list_entry *reloc;
 961         struct amdgpu_bo_va_mapping *mapping;
 962
 963         addr /= AMDGPU_GPU_PAGE_SIZE;
 964
 965         list_for_each_entry(reloc, &parser->validated, tv.head) {
 966                 if (!reloc->bo_va)
 967                         continue;
 968
 969                 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
 970                         if (mapping->it.start > addr ||
 971                             addr > mapping->it.last)
 972                                 continue;
 973
 974                         *bo = reloc->bo_va->bo;
 975                         return mapping;
 976                 }
 977
 978                 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
 979                         if (mapping->it.start > addr ||
 980                             addr > mapping->it.last)
 981                                 continue;
 982
 983                         *bo = reloc->bo_va->bo;
 984                         return mapping;
 985                 }
 986         }
 987
 988         return NULL;
 989 }