drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v2_0.h"
  26
  27 #include "mmhub/mmhub_2_0_0_offset.h"
  28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  29 #include "mmhub/mmhub_2_0_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
  35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX             0
  36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid                       0x0070
  37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX              0
  38
  39 static const char *mmhub_client_ids_navi1x[][2] = {
  40         [3][0] = "DCEDMC",
  41         [4][0] = "DCEVGA",
  42         [5][0] = "MP0",
  43         [6][0] = "MP1",
  44         [13][0] = "VMC",
  45         [14][0] = "HDP",
  46         [15][0] = "OSS",
  47         [16][0] = "VCNU",
  48         [17][0] = "JPEG",
  49         [18][0] = "VCN",
  50         [3][1] = "DCEDMC",
  51         [4][1] = "DCEXFC",
  52         [5][1] = "DCEVGA",
  53         [6][1] = "DCEDWB",
  54         [7][1] = "MP0",
  55         [8][1] = "MP1",
  56         [9][1] = "DBGU1",
  57         [10][1] = "DBGU0",
  58         [11][1] = "XDP",
  59         [14][1] = "HDP",
  60         [15][1] = "OSS",
  61         [16][1] = "VCNU",
  62         [17][1] = "JPEG",
  63         [18][1] = "VCN",
  64 };
  65
  66 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
  67         [3][0] = "DCEDMC",
  68         [4][0] = "DCEVGA",
  69         [5][0] = "MP0",
  70         [6][0] = "MP1",
  71         [8][0] = "VMC",
  72         [9][0] = "VCNU0",
  73         [10][0] = "JPEG",
  74         [12][0] = "VCNU1",
  75         [13][0] = "VCN1",
  76         [14][0] = "HDP",
  77         [15][0] = "OSS",
  78         [32+11][0] = "VCN0",
  79         [0][1] = "DBGU0",
  80         [1][1] = "DBGU1",
  81         [2][1] = "DCEDWB",
  82         [3][1] = "DCEDMC",
  83         [4][1] = "DCEVGA",
  84         [5][1] = "MP0",
  85         [6][1] = "MP1",
  86         [7][1] = "XDP",
  87         [9][1] = "VCNU0",
  88         [10][1] = "JPEG",
  89         [11][1] = "VCN0",
  90         [12][1] = "VCNU1",
  91         [13][1] = "VCN1",
  92         [14][1] = "HDP",
  93         [15][1] = "OSS",
  94 };
  95
  96 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
  97                                               uint32_t flush_type)
  98 {
  99         u32 req = 0;
 100
 101         /* invalidate using legacy mode on vmid*/
 102         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 103                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 104         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 105         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 106         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 107         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 108         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 109         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 110         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 111                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 112
 113         return req;
 114 }
 115
 116 static void
 117 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
 118                                              uint32_t status)
 119 {
 120         uint32_t cid, rw;
 121         const char *mmhub_cid = NULL;
 122
 123         cid = REG_GET_FIELD(status,
 124                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
 125         rw = REG_GET_FIELD(status,
 126                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
 127
 128         dev_err(adev->dev,
 129                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 130                 status);
 131         switch (adev->asic_type) {
 132         case CHIP_NAVI10:
 133         case CHIP_NAVI12:
 134         case CHIP_NAVI14:
 135                 mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
 136                 break;
 137         case CHIP_SIENNA_CICHLID:
 138         case CHIP_NAVY_FLOUNDER:
 139         case CHIP_DIMGREY_CAVEFISH:
 140                 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
 141                 break;
 142         default:
 143                 mmhub_cid = NULL;
 144                 break;
 145         }
 146         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 147                 mmhub_cid ? mmhub_cid : "unknown", cid);
 148         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 149                 REG_GET_FIELD(status,
 150                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 151         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 152                 REG_GET_FIELD(status,
 153                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 154         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 155                 REG_GET_FIELD(status,
 156                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 157         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 158                 REG_GET_FIELD(status,
 159                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 160         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 161 }
 162
 163 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 164                                 uint64_t page_table_base)
 165 {
 166         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 167
 168         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 169                             hub->ctx_addr_distance * vmid,
 170                             lower_32_bits(page_table_base));
 171
 172         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 173                             hub->ctx_addr_distance * vmid,
 174                             upper_32_bits(page_table_base));
 175 }
 176
 177 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 178 {
 179         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 180
 181         mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 182
 183         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 184                      (u32)(adev->gmc.gart_start >> 12));
 185         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 186                      (u32)(adev->gmc.gart_start >> 44));
 187
 188         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 189                      (u32)(adev->gmc.gart_end >> 12));
 190         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 191                      (u32)(adev->gmc.gart_end >> 44));
 192 }
 193
 194 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 195 {
 196         uint64_t value;
 197         uint32_t tmp;
 198
 199         /* Program the AGP BAR */
 200         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
 201         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 202         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 203
 204         if (!amdgpu_sriov_vf(adev)) {
 205                 /* Program the system aperture low logical page number. */
 206                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 207                              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 208                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 209                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 210         }
 211
 212         /* Set default page address. */
 213         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 214                 adev->vm_manager.vram_base_offset;
 215         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 216                      (u32)(value >> 12));
 217         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 218                      (u32)(value >> 44));
 219
 220         /* Program "protection fault". */
 221         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 222                      (u32)(adev->dummy_page_addr >> 12));
 223         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 224                      (u32)((u64)adev->dummy_page_addr >> 44));
 225
 226         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
 227         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 228                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 229         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 230 }
 231
 232 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
 233 {
 234         uint32_t tmp;
 235
 236         /* Setup TLB control */
 237         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 238
 239         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 240         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 241         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 242                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 243         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 244                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 245         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 246         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 247                             MTYPE, MTYPE_UC); /* UC, uncached */
 248
 249         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 250 }
 251
 252 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 253 {
 254         uint32_t tmp;
 255
 256         /* These registers are not accessible to VF-SRIOV.
 257          * The PF will program them instead.
 258          */
 259         if (amdgpu_sriov_vf(adev))
 260                 return;
 261
 262         /* Setup L2 cache */
 263         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 264         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 265         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 266         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 267                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 268         /* XXX for emulation, Refer to closed source code.*/
 269         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 270                             0);
 271         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 272         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 273         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 274         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 275
 276         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
 277         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 278         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 279         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 280
 281         tmp = mmMMVM_L2_CNTL3_DEFAULT;
 282         if (adev->gmc.translate_further) {
 283                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 284                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 285                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 286         } else {
 287                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 288                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 289                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 290         }
 291         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 292
 293         tmp = mmMMVM_L2_CNTL4_DEFAULT;
 294         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 295         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 296         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
 297
 298         tmp = mmMMVM_L2_CNTL5_DEFAULT;
 299         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 300         WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
 301 }
 302
 303 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 304 {
 305         uint32_t tmp;
 306
 307         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 308         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 309         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 310         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 311                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 312         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 313 }
 314
 315 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 316 {
 317         /* These registers are not accessible to VF-SRIOV.
 318          * The PF will program them instead.
 319          */
 320         if (amdgpu_sriov_vf(adev))
 321                 return;
 322
 323         WREG32_SOC15(MMHUB, 0,
 324                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 325                      0xFFFFFFFF);
 326         WREG32_SOC15(MMHUB, 0,
 327                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 328                      0x0000000F);
 329
 330         WREG32_SOC15(MMHUB, 0,
 331                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 332         WREG32_SOC15(MMHUB, 0,
 333                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 334
 335         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 336                      0);
 337         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 338                      0);
 339 }
 340
 341 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 342 {
 343         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 344         int i;
 345         uint32_t tmp;
 346
 347         for (i = 0; i <= 14; i++) {
 348                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
 349                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 350                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 351                                     adev->vm_manager.num_level);
 352                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 353                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 354                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 355                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 356                                     1);
 357                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 358                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 359                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 360                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 361                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 362                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 363                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 364                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 365                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 366                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 367                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 368                                     PAGE_TABLE_BLOCK_SIZE,
 369                                     adev->vm_manager.block_size - 9);
 370                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 371                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 372                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 373                                     !adev->gmc.noretry);
 374                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
 375                                     i * hub->ctx_distance, tmp);
 376                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 377                                     i * hub->ctx_addr_distance, 0);
 378                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 379                                     i * hub->ctx_addr_distance, 0);
 380                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 381                                     i * hub->ctx_addr_distance,
 382                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 383                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 384                                     i * hub->ctx_addr_distance,
 385                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 386         }
 387 }
 388
 389 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 390 {
 391         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 392         unsigned i;
 393
 394         for (i = 0; i < 18; ++i) {
 395                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 396                                     i * hub->eng_addr_distance, 0xffffffff);
 397                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 398                                     i * hub->eng_addr_distance, 0x1f);
 399         }
 400 }
 401
 402 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
 403 {
 404         /* GART Enable. */
 405         mmhub_v2_0_init_gart_aperture_regs(adev);
 406         mmhub_v2_0_init_system_aperture_regs(adev);
 407         mmhub_v2_0_init_tlb_regs(adev);
 408         mmhub_v2_0_init_cache_regs(adev);
 409
 410         mmhub_v2_0_enable_system_domain(adev);
 411         mmhub_v2_0_disable_identity_aperture(adev);
 412         mmhub_v2_0_setup_vmid_config(adev);
 413         mmhub_v2_0_program_invalidation(adev);
 414
 415         return 0;
 416 }
 417
 418 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
 419 {
 420         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 421         u32 tmp;
 422         u32 i;
 423
 424         /* Disable all tables */
 425         for (i = 0; i < AMDGPU_NUM_VMID; i++)
 426                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
 427                                     i * hub->ctx_distance, 0);
 428
 429         /* Setup TLB control */
 430         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 431         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 432         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 433                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 434         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 435
 436         /* Setup L2 cache */
 437         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 438         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 439         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 440         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
 441 }
 442
 443 /**
 444  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 445  *
 446  * @adev: amdgpu_device pointer
 447  * @value: true redirects VM faults to the default page
 448  */
 449 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 450 {
 451         u32 tmp;
 452
 453         /* These registers are not accessible to VF-SRIOV.
 454          * The PF will program them instead.
 455          */
 456         if (amdgpu_sriov_vf(adev))
 457                 return;
 458
 459         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 460         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 461                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 462         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 463                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 464         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 465                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 466         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 467                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 468         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 469                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 470                             value);
 471         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 472                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 473         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 474                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 475         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 476                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 477         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 478                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 479         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 480                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 481         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 482                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 483         if (!value) {
 484                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 485                                 CRASH_ON_NO_RETRY_FAULT, 1);
 486                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 487                                 CRASH_ON_RETRY_FAULT, 1);
 488         }
 489         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 490 }
 491
 492 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
 493         .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
 494         .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
 495 };
 496
 497 static void mmhub_v2_0_init(struct amdgpu_device *adev)
 498 {
 499         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 500
 501         hub->ctx0_ptb_addr_lo32 =
 502                 SOC15_REG_OFFSET(MMHUB, 0,
 503                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 504         hub->ctx0_ptb_addr_hi32 =
 505                 SOC15_REG_OFFSET(MMHUB, 0,
 506                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 507         hub->vm_inv_eng0_sem =
 508                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
 509         hub->vm_inv_eng0_req =
 510                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
 511         hub->vm_inv_eng0_ack =
 512                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
 513         hub->vm_context0_cntl =
 514                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 515         hub->vm_l2_pro_fault_status =
 516                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
 517         hub->vm_l2_pro_fault_cntl =
 518                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 519
 520         hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
 521         hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 522                 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 523         hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
 524                 mmMMVM_INVALIDATE_ENG0_REQ;
 525         hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 526                 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 527
 528         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 529                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 530                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 531                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 532                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 533                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 534                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 535
 536         hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
 537 }
 538
 539 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 540                                                         bool enable)
 541 {
 542         uint32_t def, data, def1, data1;
 543
 544         switch (adev->asic_type) {
 545         case CHIP_SIENNA_CICHLID:
 546         case CHIP_NAVY_FLOUNDER:
 547         case CHIP_DIMGREY_CAVEFISH:
 548                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 549                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 550                 break;
 551         default:
 552                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 553                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 554                 break;
 555         }
 556
 557         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 558                 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 559
 560                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 561                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 562                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 563                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 564                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 565                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 566
 567         } else {
 568                 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
 569
 570                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 571                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 572                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 573                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 574                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 575                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 576         }
 577
 578         switch (adev->asic_type) {
 579         case CHIP_SIENNA_CICHLID:
 580         case CHIP_NAVY_FLOUNDER:
 581         case CHIP_DIMGREY_CAVEFISH:
 582                 if (def != data)
 583                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 584                 if (def1 != data1)
 585                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
 586                 break;
 587         default:
 588                 if (def != data)
 589                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 590                 if (def1 != data1)
 591                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 592                 break;
 593         }
 594 }
 595
 596 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 597                                                        bool enable)
 598 {
 599         uint32_t def, data;
 600
 601         switch (adev->asic_type) {
 602         case CHIP_SIENNA_CICHLID:
 603         case CHIP_NAVY_FLOUNDER:
 604         case CHIP_DIMGREY_CAVEFISH:
 605                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 606                 break;
 607         default:
 608                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 609                 break;
 610         }
 611
 612         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 613                 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 614         else
 615                 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 616
 617         if (def != data) {
 618                 switch (adev->asic_type) {
 619                 case CHIP_SIENNA_CICHLID:
 620                 case CHIP_NAVY_FLOUNDER:
 621                 case CHIP_DIMGREY_CAVEFISH:
 622                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 623                         break;
 624                 default:
 625                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 626                         break;
 627                 }
 628         }
 629 }
 630
 631 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 632                                enum amd_clockgating_state state)
 633 {
 634         if (amdgpu_sriov_vf(adev))
 635                 return 0;
 636
 637         switch (adev->asic_type) {
 638         case CHIP_NAVI10:
 639         case CHIP_NAVI14:
 640         case CHIP_NAVI12:
 641         case CHIP_SIENNA_CICHLID:
 642         case CHIP_NAVY_FLOUNDER:
 643         case CHIP_DIMGREY_CAVEFISH:
 644                 mmhub_v2_0_update_medium_grain_clock_gating(adev,
 645                                 state == AMD_CG_STATE_GATE);
 646                 mmhub_v2_0_update_medium_grain_light_sleep(adev,
 647                                 state == AMD_CG_STATE_GATE);
 648                 break;
 649         default:
 650                 break;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 657 {
 658         int data, data1;
 659
 660         if (amdgpu_sriov_vf(adev))
 661                 *flags = 0;
 662
 663         switch (adev->asic_type) {
 664         case CHIP_SIENNA_CICHLID:
 665         case CHIP_NAVY_FLOUNDER:
 666         case CHIP_DIMGREY_CAVEFISH:
 667                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 668                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 669                 break;
 670         default:
 671                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 672                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 673                 break;
 674         }
 675
 676         /* AMD_CG_SUPPORT_MC_MGCG */
 677         if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
 678             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 679                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 680                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 681                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 682                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 683                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 684                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 685
 686         /* AMD_CG_SUPPORT_MC_LS */
 687         if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 688                 *flags |= AMD_CG_SUPPORT_MC_LS;
 689 }
 690
 691 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
 692         .init = mmhub_v2_0_init,
 693         .gart_enable = mmhub_v2_0_gart_enable,
 694         .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
 695         .gart_disable = mmhub_v2_0_gart_disable,
 696         .set_clockgating = mmhub_v2_0_set_clockgating,
 697         .get_clockgating = mmhub_v2_0_get_clockgating,
 698         .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
 699 };