drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <[email protected]>
  21  *          Alex Deucher <[email protected]>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  34
  35 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  36 {
  37         if (adev->pm.dpm_enabled) {
  38                 mutex_lock(&adev->pm.mutex);
  39                 if (power_supply_is_system_supplied() > 0)
  40                         adev->pm.dpm.ac_power = true;
  41                 else
  42                         adev->pm.dpm.ac_power = false;
  43                 if (adev->pm.funcs->enable_bapm)
  44                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  45                 mutex_unlock(&adev->pm.mutex);
  46         }
  47 }
  48
  49 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  50                                     struct device_attribute *attr,
  51                                     char *buf)
  52 {
  53         struct drm_device *ddev = dev_get_drvdata(dev);
  54         struct amdgpu_device *adev = ddev->dev_private;
  55         enum amdgpu_pm_state_type pm = adev->pm.dpm.user_state;
  56
  57         return snprintf(buf, PAGE_SIZE, "%s\n",
  58                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  59                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  60 }
  61
  62 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  63                                     struct device_attribute *attr,
  64                                     const char *buf,
  65                                     size_t count)
  66 {
  67         struct drm_device *ddev = dev_get_drvdata(dev);
  68         struct amdgpu_device *adev = ddev->dev_private;
  69
  70         mutex_lock(&adev->pm.mutex);
  71         if (strncmp("battery", buf, strlen("battery")) == 0)
  72                 adev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
  73         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
  74                 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
  75         else if (strncmp("performance", buf, strlen("performance")) == 0)
  76                 adev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
  77         else {
  78                 mutex_unlock(&adev->pm.mutex);
  79                 count = -EINVAL;
  80                 goto fail;
  81         }
  82         mutex_unlock(&adev->pm.mutex);
  83
  84         /* Can't set dpm state when the card is off */
  85         if (!(adev->flags & AMD_IS_PX) ||
  86             (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
  87                 amdgpu_pm_compute_clocks(adev);
  88 fail:
  89         return count;
  90 }
  91
  92 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
  93                                                        struct device_attribute *attr,
  94                                                        char *buf)
  95 {
  96         struct drm_device *ddev = dev_get_drvdata(dev);
  97         struct amdgpu_device *adev = ddev->dev_private;
  98         enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
  99
 100         return snprintf(buf, PAGE_SIZE, "%s\n",
 101                         (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 102                         (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 103 }
 104
 105 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 106                                                        struct device_attribute *attr,
 107                                                        const char *buf,
 108                                                        size_t count)
 109 {
 110         struct drm_device *ddev = dev_get_drvdata(dev);
 111         struct amdgpu_device *adev = ddev->dev_private;
 112         enum amdgpu_dpm_forced_level level;
 113         int ret = 0;
 114
 115         mutex_lock(&adev->pm.mutex);
 116         if (strncmp("low", buf, strlen("low")) == 0) {
 117                 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
 118         } else if (strncmp("high", buf, strlen("high")) == 0) {
 119                 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
 120         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 121                 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
 122         } else {
 123                 count = -EINVAL;
 124                 goto fail;
 125         }
 126         if (adev->pm.funcs->force_performance_level) {
 127                 if (adev->pm.dpm.thermal_active) {
 128                         count = -EINVAL;
 129                         goto fail;
 130                 }
 131                 ret = amdgpu_dpm_force_performance_level(adev, level);
 132                 if (ret)
 133                         count = -EINVAL;
 134         }
 135 fail:
 136         mutex_unlock(&adev->pm.mutex);
 137
 138         return count;
 139 }
 140
 141 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 142 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 143                    amdgpu_get_dpm_forced_performance_level,
 144                    amdgpu_set_dpm_forced_performance_level);
 145
 146 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 147                                       struct device_attribute *attr,
 148                                       char *buf)
 149 {
 150         struct amdgpu_device *adev = dev_get_drvdata(dev);
 151         int temp;
 152
 153         if (adev->pm.funcs->get_temperature)
 154                 temp = amdgpu_dpm_get_temperature(adev);
 155         else
 156                 temp = 0;
 157
 158         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 159 }
 160
 161 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 162                                              struct device_attribute *attr,
 163                                              char *buf)
 164 {
 165         struct amdgpu_device *adev = dev_get_drvdata(dev);
 166         int hyst = to_sensor_dev_attr(attr)->index;
 167         int temp;
 168
 169         if (hyst)
 170                 temp = adev->pm.dpm.thermal.min_temp;
 171         else
 172                 temp = adev->pm.dpm.thermal.max_temp;
 173
 174         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 175 }
 176
 177 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 178                                             struct device_attribute *attr,
 179                                             char *buf)
 180 {
 181         struct amdgpu_device *adev = dev_get_drvdata(dev);
 182         u32 pwm_mode = 0;
 183
 184         if (adev->pm.funcs->get_fan_control_mode)
 185                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 186
 187         /* never 0 (full-speed), fuse or smc-controlled always */
 188         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 189 }
 190
 191 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 192                                             struct device_attribute *attr,
 193                                             const char *buf,
 194                                             size_t count)
 195 {
 196         struct amdgpu_device *adev = dev_get_drvdata(dev);
 197         int err;
 198         int value;
 199
 200         if(!adev->pm.funcs->set_fan_control_mode)
 201                 return -EINVAL;
 202
 203         err = kstrtoint(buf, 10, &value);
 204         if (err)
 205                 return err;
 206
 207         switch (value) {
 208         case 1: /* manual, percent-based */
 209                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 210                 break;
 211         default: /* disable */
 212                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 213                 break;
 214         }
 215
 216         return count;
 217 }
 218
 219 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 220                                          struct device_attribute *attr,
 221                                          char *buf)
 222 {
 223         return sprintf(buf, "%i\n", 0);
 224 }
 225
 226 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 227                                          struct device_attribute *attr,
 228                                          char *buf)
 229 {
 230         return sprintf(buf, "%i\n", 255);
 231 }
 232
 233 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 234                                      struct device_attribute *attr,
 235                                      const char *buf, size_t count)
 236 {
 237         struct amdgpu_device *adev = dev_get_drvdata(dev);
 238         int err;
 239         u32 value;
 240
 241         err = kstrtou32(buf, 10, &value);
 242         if (err)
 243                 return err;
 244
 245         value = (value * 100) / 255;
 246
 247         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 248         if (err)
 249                 return err;
 250
 251         return count;
 252 }
 253
 254 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 255                                      struct device_attribute *attr,
 256                                      char *buf)
 257 {
 258         struct amdgpu_device *adev = dev_get_drvdata(dev);
 259         int err;
 260         u32 speed;
 261
 262         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 263         if (err)
 264                 return err;
 265
 266         speed = (speed * 255) / 100;
 267
 268         return sprintf(buf, "%i\n", speed);
 269 }
 270
 271 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 272 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 273 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 274 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 275 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 276 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 277 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 278
 279 static struct attribute *hwmon_attributes[] = {
 280         &sensor_dev_attr_temp1_input.dev_attr.attr,
 281         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 282         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 283         &sensor_dev_attr_pwm1.dev_attr.attr,
 284         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 285         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 286         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 287         NULL
 288 };
 289
 290 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 291                                         struct attribute *attr, int index)
 292 {
 293         struct device *dev = container_of(kobj, struct device, kobj);
 294         struct amdgpu_device *adev = dev_get_drvdata(dev);
 295         umode_t effective_mode = attr->mode;
 296
 297         /* Skip attributes if DPM is not enabled */
 298         if (!adev->pm.dpm_enabled &&
 299             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 300              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 301              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 302              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 303              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 304              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 305                 return 0;
 306
 307         /* Skip fan attributes if fan is not present */
 308         if (adev->pm.no_fan &&
 309             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 310              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 311              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 312              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 313                 return 0;
 314
 315         /* mask fan attributes if we have no bindings for this asic to expose */
 316         if ((!adev->pm.funcs->get_fan_speed_percent &&
 317              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 318             (!adev->pm.funcs->get_fan_control_mode &&
 319              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 320                 effective_mode &= ~S_IRUGO;
 321
 322         if ((!adev->pm.funcs->set_fan_speed_percent &&
 323              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 324             (!adev->pm.funcs->set_fan_control_mode &&
 325              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 326                 effective_mode &= ~S_IWUSR;
 327
 328         /* hide max/min values if we can't both query and manage the fan */
 329         if ((!adev->pm.funcs->set_fan_speed_percent &&
 330              !adev->pm.funcs->get_fan_speed_percent) &&
 331             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 332              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 333                 return 0;
 334
 335         return effective_mode;
 336 }
 337
 338 static const struct attribute_group hwmon_attrgroup = {
 339         .attrs = hwmon_attributes,
 340         .is_visible = hwmon_attributes_visible,
 341 };
 342
 343 static const struct attribute_group *hwmon_groups[] = {
 344         &hwmon_attrgroup,
 345         NULL
 346 };
 347
 348 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 349 {
 350         struct amdgpu_device *adev =
 351                 container_of(work, struct amdgpu_device,
 352                              pm.dpm.thermal.work);
 353         /* switch to the thermal state */
 354         enum amdgpu_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 355
 356         if (!adev->pm.dpm_enabled)
 357                 return;
 358
 359         if (adev->pm.funcs->get_temperature) {
 360                 int temp = amdgpu_dpm_get_temperature(adev);
 361
 362                 if (temp < adev->pm.dpm.thermal.min_temp)
 363                         /* switch back the user state */
 364                         dpm_state = adev->pm.dpm.user_state;
 365         } else {
 366                 if (adev->pm.dpm.thermal.high_to_low)
 367                         /* switch back the user state */
 368                         dpm_state = adev->pm.dpm.user_state;
 369         }
 370         mutex_lock(&adev->pm.mutex);
 371         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 372                 adev->pm.dpm.thermal_active = true;
 373         else
 374                 adev->pm.dpm.thermal_active = false;
 375         adev->pm.dpm.state = dpm_state;
 376         mutex_unlock(&adev->pm.mutex);
 377
 378         amdgpu_pm_compute_clocks(adev);
 379 }
 380
 381 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 382                                                      enum amdgpu_pm_state_type dpm_state)
 383 {
 384         int i;
 385         struct amdgpu_ps *ps;
 386         u32 ui_class;
 387         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 388                 true : false;
 389
 390         /* check if the vblank period is too short to adjust the mclk */
 391         if (single_display && adev->pm.funcs->vblank_too_short) {
 392                 if (amdgpu_dpm_vblank_too_short(adev))
 393                         single_display = false;
 394         }
 395
 396         /* certain older asics have a separare 3D performance state,
 397          * so try that first if the user selected performance
 398          */
 399         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 400                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 401         /* balanced states don't exist at the moment */
 402         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 403                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 404
 405 restart_search:
 406         /* Pick the best power state based on current conditions */
 407         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 408                 ps = &adev->pm.dpm.ps[i];
 409                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 410                 switch (dpm_state) {
 411                 /* user states */
 412                 case POWER_STATE_TYPE_BATTERY:
 413                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 414                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 415                                         if (single_display)
 416                                                 return ps;
 417                                 } else
 418                                         return ps;
 419                         }
 420                         break;
 421                 case POWER_STATE_TYPE_BALANCED:
 422                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 423                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 424                                         if (single_display)
 425                                                 return ps;
 426                                 } else
 427                                         return ps;
 428                         }
 429                         break;
 430                 case POWER_STATE_TYPE_PERFORMANCE:
 431                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 432                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 433                                         if (single_display)
 434                                                 return ps;
 435                                 } else
 436                                         return ps;
 437                         }
 438                         break;
 439                 /* internal states */
 440                 case POWER_STATE_TYPE_INTERNAL_UVD:
 441                         if (adev->pm.dpm.uvd_ps)
 442                                 return adev->pm.dpm.uvd_ps;
 443                         else
 444                                 break;
 445                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 446                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 447                                 return ps;
 448                         break;
 449                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 450                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 451                                 return ps;
 452                         break;
 453                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 454                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 455                                 return ps;
 456                         break;
 457                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 458                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 459                                 return ps;
 460                         break;
 461                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 462                         return adev->pm.dpm.boot_ps;
 463                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 464                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 465                                 return ps;
 466                         break;
 467                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 468                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 469                                 return ps;
 470                         break;
 471                 case POWER_STATE_TYPE_INTERNAL_ULV:
 472                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 473                                 return ps;
 474                         break;
 475                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 476                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 477                                 return ps;
 478                         break;
 479                 default:
 480                         break;
 481                 }
 482         }
 483         /* use a fallback state if we didn't match */
 484         switch (dpm_state) {
 485         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 486                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 487                 goto restart_search;
 488         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 489         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 490         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 491                 if (adev->pm.dpm.uvd_ps) {
 492                         return adev->pm.dpm.uvd_ps;
 493                 } else {
 494                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 495                         goto restart_search;
 496                 }
 497         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 498                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 499                 goto restart_search;
 500         case POWER_STATE_TYPE_INTERNAL_ACPI:
 501                 dpm_state = POWER_STATE_TYPE_BATTERY;
 502                 goto restart_search;
 503         case POWER_STATE_TYPE_BATTERY:
 504         case POWER_STATE_TYPE_BALANCED:
 505         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 506                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 507                 goto restart_search;
 508         default:
 509                 break;
 510         }
 511
 512         return NULL;
 513 }
 514
 515 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 516 {
 517         int i;
 518         struct amdgpu_ps *ps;
 519         enum amdgpu_pm_state_type dpm_state;
 520         int ret;
 521
 522         /* if dpm init failed */
 523         if (!adev->pm.dpm_enabled)
 524                 return;
 525
 526         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
 527                 /* add other state override checks here */
 528                 if ((!adev->pm.dpm.thermal_active) &&
 529                     (!adev->pm.dpm.uvd_active))
 530                         adev->pm.dpm.state = adev->pm.dpm.user_state;
 531         }
 532         dpm_state = adev->pm.dpm.state;
 533
 534         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
 535         if (ps)
 536                 adev->pm.dpm.requested_ps = ps;
 537         else
 538                 return;
 539
 540         /* no need to reprogram if nothing changed unless we are on BTC+ */
 541         if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
 542                 /* vce just modifies an existing state so force a change */
 543                 if (ps->vce_active != adev->pm.dpm.vce_active)
 544                         goto force;
 545                 if (adev->flags & AMD_IS_APU) {
 546                         /* for APUs if the num crtcs changed but state is the same,
 547                          * all we need to do is update the display configuration.
 548                          */
 549                         if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
 550                                 /* update display watermarks based on new power state */
 551                                 amdgpu_display_bandwidth_update(adev);
 552                                 /* update displays */
 553                                 amdgpu_dpm_display_configuration_changed(adev);
 554                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 555                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 556                         }
 557                         return;
 558                 } else {
 559                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 560                          * nothing to do, if the num crtcs is > 1 and state is the same,
 561                          * update display configuration.
 562                          */
 563                         if (adev->pm.dpm.new_active_crtcs ==
 564                             adev->pm.dpm.current_active_crtcs) {
 565                                 return;
 566                         } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
 567                                    (adev->pm.dpm.new_active_crtc_count > 1)) {
 568                                 /* update display watermarks based on new power state */
 569                                 amdgpu_display_bandwidth_update(adev);
 570                                 /* update displays */
 571                                 amdgpu_dpm_display_configuration_changed(adev);
 572                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 573                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 574                                 return;
 575                         }
 576                 }
 577         }
 578
 579 force:
 580         if (amdgpu_dpm == 1) {
 581                 printk("switching from power state:\n");
 582                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
 583                 printk("switching to power state:\n");
 584                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
 585         }
 586
 587         mutex_lock(&adev->ring_lock);
 588
 589         /* update whether vce is active */
 590         ps->vce_active = adev->pm.dpm.vce_active;
 591
 592         ret = amdgpu_dpm_pre_set_power_state(adev);
 593         if (ret)
 594                 goto done;
 595
 596         /* update display watermarks based on new power state */
 597         amdgpu_display_bandwidth_update(adev);
 598         /* update displays */
 599         amdgpu_dpm_display_configuration_changed(adev);
 600
 601         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 602         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 603
 604         /* wait for the rings to drain */
 605         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 606                 struct amdgpu_ring *ring = adev->rings[i];
 607                 if (ring && ring->ready)
 608                         amdgpu_fence_wait_empty(ring);
 609         }
 610
 611         /* program the new power state */
 612         amdgpu_dpm_set_power_state(adev);
 613
 614         /* update current power state */
 615         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
 616
 617         amdgpu_dpm_post_set_power_state(adev);
 618
 619         if (adev->pm.funcs->force_performance_level) {
 620                 if (adev->pm.dpm.thermal_active) {
 621                         enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
 622                         /* force low perf level for thermal */
 623                         amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
 624                         /* save the user's level */
 625                         adev->pm.dpm.forced_level = level;
 626                 } else {
 627                         /* otherwise, user selected level */
 628                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
 629                 }
 630         }
 631
 632 done:
 633         mutex_unlock(&adev->ring_lock);
 634 }
 635
 636 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 637 {
 638         if (adev->pm.funcs->powergate_uvd) {
 639                 mutex_lock(&adev->pm.mutex);
 640                 /* enable/disable UVD */
 641                 amdgpu_dpm_powergate_uvd(adev, !enable);
 642                 mutex_unlock(&adev->pm.mutex);
 643         } else {
 644                 if (enable) {
 645                         mutex_lock(&adev->pm.mutex);
 646                         adev->pm.dpm.uvd_active = true;
 647                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
 648                         mutex_unlock(&adev->pm.mutex);
 649                 } else {
 650                         mutex_lock(&adev->pm.mutex);
 651                         adev->pm.dpm.uvd_active = false;
 652                         mutex_unlock(&adev->pm.mutex);
 653                 }
 654
 655                 amdgpu_pm_compute_clocks(adev);
 656         }
 657 }
 658
 659 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 660 {
 661         if (adev->pm.funcs->powergate_vce) {
 662                 mutex_lock(&adev->pm.mutex);
 663                 /* enable/disable VCE */
 664                 amdgpu_dpm_powergate_vce(adev, !enable);
 665
 666                 mutex_unlock(&adev->pm.mutex);
 667         } else {
 668                 if (enable) {
 669                         mutex_lock(&adev->pm.mutex);
 670                         adev->pm.dpm.vce_active = true;
 671                         /* XXX select vce level based on ring/task */
 672                         adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
 673                         mutex_unlock(&adev->pm.mutex);
 674                 } else {
 675                         mutex_lock(&adev->pm.mutex);
 676                         adev->pm.dpm.vce_active = false;
 677                         mutex_unlock(&adev->pm.mutex);
 678                 }
 679
 680                 amdgpu_pm_compute_clocks(adev);
 681         }
 682 }
 683
 684 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
 685 {
 686         int i;
 687
 688         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 689                 printk("== power state %d ==\n", i);
 690                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
 691         }
 692 }
 693
 694 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 695 {
 696         int ret;
 697
 698         if (adev->pm.funcs->get_temperature == NULL)
 699                 return 0;
 700         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
 701                                                                    DRIVER_NAME, adev,
 702                                                                    hwmon_groups);
 703         if (IS_ERR(adev->pm.int_hwmon_dev)) {
 704                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
 705                 dev_err(adev->dev,
 706                         "Unable to register hwmon device: %d\n", ret);
 707                 return ret;
 708         }
 709
 710         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
 711         if (ret) {
 712                 DRM_ERROR("failed to create device file for dpm state\n");
 713                 return ret;
 714         }
 715         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
 716         if (ret) {
 717                 DRM_ERROR("failed to create device file for dpm state\n");
 718                 return ret;
 719         }
 720         ret = amdgpu_debugfs_pm_init(adev);
 721         if (ret) {
 722                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
 723                 return ret;
 724         }
 725
 726         return 0;
 727 }
 728
 729 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 730 {
 731         if (adev->pm.int_hwmon_dev)
 732                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
 733         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
 734         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
 735 }
 736
 737 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
 738 {
 739         struct drm_device *ddev = adev->ddev;
 740         struct drm_crtc *crtc;
 741         struct amdgpu_crtc *amdgpu_crtc;
 742
 743         if (!adev->pm.dpm_enabled)
 744                 return;
 745
 746         mutex_lock(&adev->pm.mutex);
 747
 748         /* update active crtc counts */
 749         adev->pm.dpm.new_active_crtcs = 0;
 750         adev->pm.dpm.new_active_crtc_count = 0;
 751         if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
 752                 list_for_each_entry(crtc,
 753                                     &ddev->mode_config.crtc_list, head) {
 754                         amdgpu_crtc = to_amdgpu_crtc(crtc);
 755                         if (crtc->enabled) {
 756                                 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
 757                                 adev->pm.dpm.new_active_crtc_count++;
 758                         }
 759                 }
 760         }
 761
 762         /* update battery/ac status */
 763         if (power_supply_is_system_supplied() > 0)
 764                 adev->pm.dpm.ac_power = true;
 765         else
 766                 adev->pm.dpm.ac_power = false;
 767
 768         amdgpu_dpm_change_power_state_locked(adev);
 769
 770         mutex_unlock(&adev->pm.mutex);
 771
 772 }
 773
 774 /*
 775  * Debugfs info
 776  */
 777 #if defined(CONFIG_DEBUG_FS)
 778
 779 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
 780 {
 781         struct drm_info_node *node = (struct drm_info_node *) m->private;
 782         struct drm_device *dev = node->minor->dev;
 783         struct amdgpu_device *adev = dev->dev_private;
 784
 785         if (adev->pm.dpm_enabled) {
 786                 mutex_lock(&adev->pm.mutex);
 787                 if (adev->pm.funcs->debugfs_print_current_performance_level)
 788                         amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
 789                 else
 790                         seq_printf(m, "Debugfs support not implemented for this asic\n");
 791                 mutex_unlock(&adev->pm.mutex);
 792         }
 793
 794         return 0;
 795 }
 796
 797 static struct drm_info_list amdgpu_pm_info_list[] = {
 798         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
 799 };
 800 #endif
 801
 802 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
 803 {
 804 #if defined(CONFIG_DEBUG_FS)
 805         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
 806 #else
 807         return 0;
 808 #endif
 809 }