drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v3_0_3.h"
  26
  27 #include "gc/gc_11_0_3_offset.h"
  28 #include "gc/gc_11_0_3_sh_mask.h"
  29 #include "navi10_enum.h"
  30 #include "soc15_common.h"
  31
  32 #define regGCVM_L2_CNTL3_DEFAULT                0x80100007
  33 #define regGCVM_L2_CNTL4_DEFAULT                0x000000c1
  34 #define regGCVM_L2_CNTL5_DEFAULT                0x00003fe0
  35
  36 static const char *gfxhub_client_ids[] = {
  37         "CB/DB",
  38         "Reserved",
  39         "GE1",
  40         "GE2",
  41         "CPF",
  42         "CPC",
  43         "CPG",
  44         "RLC",
  45         "TCP",
  46         "SQC (inst)",
  47         "SQC (data)",
  48         "SQG",
  49         "Reserved",
  50         "SDMA0",
  51         "SDMA1",
  52         "GCR",
  53         "SDMA2",
  54         "SDMA3",
  55 };
  56
  57 static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid,
  58                                                uint32_t flush_type)
  59 {
  60         u32 req = 0;
  61
  62         /* invalidate using legacy mode on vmid*/
  63         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  64                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  65         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  66         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  67         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  68         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  69         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  70         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  71         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  72                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  73
  74         return req;
  75 }
  76
  77 static void
  78 gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
  79                                              uint32_t status)
  80 {
  81         u32 cid = REG_GET_FIELD(status,
  82                                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
  83
  84         dev_err(adev->dev,
  85                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
  86                 status);
  87         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
  88                 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
  89                 cid);
  90         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
  91                 REG_GET_FIELD(status,
  92                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
  93         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
  94                 REG_GET_FIELD(status,
  95                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
  96         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
  97                 REG_GET_FIELD(status,
  98                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
  99         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 100                 REG_GET_FIELD(status,
 101                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 102         dev_err(adev->dev, "\t RW: 0x%lx\n",
 103                 REG_GET_FIELD(status,
 104                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
 105 }
 106
 107 static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev)
 108 {
 109         u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
 110
 111         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 112         base <<= 24;
 113
 114         return base;
 115 }
 116
 117 static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev)
 118 {
 119         return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
 120 }
 121
 122 static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 123                                 uint64_t page_table_base)
 124 {
 125         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 126
 127         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 128                             hub->ctx_addr_distance * vmid,
 129                             lower_32_bits(page_table_base));
 130
 131         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 132                             hub->ctx_addr_distance * vmid,
 133                             upper_32_bits(page_table_base));
 134 }
 135
 136 static void gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev)
 137 {
 138         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 139
 140         gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base);
 141
 142         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 143                      (u32)(adev->gmc.gart_start >> 12));
 144         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 145                      (u32)(adev->gmc.gart_start >> 44));
 146
 147         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 148                      (u32)(adev->gmc.gart_end >> 12));
 149         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 150                      (u32)(adev->gmc.gart_end >> 44));
 151 }
 152
 153 static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
 154 {
 155         uint64_t value;
 156
 157         if (amdgpu_sriov_vf(adev))
 158                 return;
 159
 160         /* Disable AGP. */
 161         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
 162         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 163         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 164
 165         /* Program the system aperture low logical page number. */
 166         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 167                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 168         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 169                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 170
 171         /* Set default page address. */
 172         value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
 173                 + adev->vm_manager.vram_base_offset;
 174         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 175                      (u32)(value >> 12));
 176         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 177                      (u32)(value >> 44));
 178
 179         /* Program "protection fault". */
 180         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 181                      (u32)(adev->dummy_page_addr >> 12));
 182         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 183                      (u32)((u64)adev->dummy_page_addr >> 44));
 184
 185         WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 186                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 187 }
 188
 189
 190 static void gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device *adev)
 191 {
 192         uint32_t tmp;
 193
 194         /* Setup TLB control */
 195         tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
 196
 197         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 198         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 199         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 200                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 201         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 202                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 203         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 204         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 205                             MTYPE, MTYPE_UC); /* UC, uncached */
 206
 207         WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
 208 }
 209
 210 static void gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device *adev)
 211 {
 212         uint32_t tmp;
 213
 214         /* These registers are not accessible to VF-SRIOV.
 215          * The PF will program them instead.
 216          */
 217         if (amdgpu_sriov_vf(adev))
 218                 return;
 219
 220         /* Setup L2 cache */
 221         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
 222         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 223         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 224         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 225                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 226         /* XXX for emulation, Refer to closed source code.*/
 227         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 228                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 229         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 230         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 231         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 232         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
 233
 234         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
 235         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 236         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 237         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
 238
 239         tmp = regGCVM_L2_CNTL3_DEFAULT;
 240         if (adev->gmc.translate_further) {
 241                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 242                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 243                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 244         } else {
 245                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 246                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 247                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 248         }
 249         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
 250
 251         tmp = regGCVM_L2_CNTL4_DEFAULT;
 252         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 253         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 254         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
 255
 256         tmp = regGCVM_L2_CNTL5_DEFAULT;
 257         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 258         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
 259 }
 260
 261 static void gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device *adev)
 262 {
 263         uint32_t tmp;
 264
 265         tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
 266         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 267         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 268         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 269                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 270         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
 271 }
 272
 273 static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev)
 274 {
 275         /* These registers are not accessible to VF-SRIOV.
 276          * The PF will program them instead.
 277          */
 278         if (amdgpu_sriov_vf(adev))
 279                 return;
 280
 281         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 282                      0xFFFFFFFF);
 283         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 284                      0x0000000F);
 285
 286         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 287                      0);
 288         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 289                      0);
 290
 291         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 292         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 293
 294 }
 295
 296 static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
 297 {
 298         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 299         int i;
 300         uint32_t tmp;
 301
 302         for (i = 0; i <= 14; i++) {
 303                 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
 304                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 305                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 306                                     adev->vm_manager.num_level);
 307                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 308                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 309                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 310                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 311                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 312                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 313                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 314                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 315                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 316                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 317                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 318                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 319                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 320                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 321                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 322                                 PAGE_TABLE_BLOCK_SIZE,
 323                                 adev->vm_manager.block_size - 9);
 324                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 325                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 326                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 327                                     !amdgpu_noretry);
 328                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
 329                                     i * hub->ctx_distance, tmp);
 330                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 331                                     i * hub->ctx_addr_distance, 0);
 332                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 333                                     i * hub->ctx_addr_distance, 0);
 334                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 335                                     i * hub->ctx_addr_distance,
 336                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 337                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 338                                     i * hub->ctx_addr_distance,
 339                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 340         }
 341
 342         hub->vm_cntx_cntl = tmp;
 343 }
 344
 345 static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev)
 346 {
 347         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 348         unsigned i;
 349
 350         for (i = 0 ; i < 18; ++i) {
 351                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 352                                     i * hub->eng_addr_distance, 0xffffffff);
 353                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 354                                     i * hub->eng_addr_distance, 0x1f);
 355         }
 356 }
 357
 358 static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev)
 359 {
 360         /* GART Enable. */
 361         gfxhub_v3_0_3_init_gart_aperture_regs(adev);
 362         gfxhub_v3_0_3_init_system_aperture_regs(adev);
 363         gfxhub_v3_0_3_init_tlb_regs(adev);
 364         gfxhub_v3_0_3_init_cache_regs(adev);
 365
 366         gfxhub_v3_0_3_enable_system_domain(adev);
 367         gfxhub_v3_0_3_disable_identity_aperture(adev);
 368         gfxhub_v3_0_3_setup_vmid_config(adev);
 369         gfxhub_v3_0_3_program_invalidation(adev);
 370
 371         return 0;
 372 }
 373
 374 static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev)
 375 {
 376         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 377         u32 tmp;
 378         u32 i;
 379
 380         /* Disable all tables */
 381         for (i = 0; i < 16; i++)
 382                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
 383                                     i * hub->ctx_distance, 0);
 384
 385         /* Setup TLB control */
 386         tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
 387         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 388         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 389                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 390         WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
 391
 392         /* Setup L2 cache */
 393         WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 394         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
 395 }
 396
 397 /**
 398  * gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling
 399  *
 400  * @adev: amdgpu_device pointer
 401  * @value: true redirects VM faults to the default page
 402  */
 403 static void gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev,
 404                                           bool value)
 405 {
 406         u32 tmp;
 407
 408         /* These registers are not accessible to VF-SRIOV.
 409          * The PF will program them instead.
 410          */
 411         if (amdgpu_sriov_vf(adev))
 412                 return;
 413
 414         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
 415         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 416                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 417         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 418                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 419         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 420                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 421         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 422                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 423         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 424                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 425                             value);
 426         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 427                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 428         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 429                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 430         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 431                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 432         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 433                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 434         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 435                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 436         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 437                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 438         if (!value) {
 439                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 440                                 CRASH_ON_NO_RETRY_FAULT, 1);
 441                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 442                                 CRASH_ON_RETRY_FAULT, 1);
 443         }
 444         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 445 }
 446
 447 static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = {
 448         .print_l2_protection_fault_status = gfxhub_v3_0_3_print_l2_protection_fault_status,
 449         .get_invalidate_req = gfxhub_v3_0_3_get_invalidate_req,
 450 };
 451
 452 static void gfxhub_v3_0_3_init(struct amdgpu_device *adev)
 453 {
 454         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 455
 456         hub->ctx0_ptb_addr_lo32 =
 457                 SOC15_REG_OFFSET(GC, 0,
 458                                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 459         hub->ctx0_ptb_addr_hi32 =
 460                 SOC15_REG_OFFSET(GC, 0,
 461                                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 462         hub->vm_inv_eng0_sem =
 463                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
 464         hub->vm_inv_eng0_req =
 465                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
 466         hub->vm_inv_eng0_ack =
 467                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
 468         hub->vm_context0_cntl =
 469                 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
 470         hub->vm_l2_pro_fault_status =
 471                 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
 472         hub->vm_l2_pro_fault_cntl =
 473                 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
 474
 475         hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
 476         hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 477                 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 478         hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
 479                 regGCVM_INVALIDATE_ENG0_REQ;
 480         hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 481                 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 482
 483         hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 484                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 485                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 486                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 487                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 488                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 489                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 490
 491         hub->vmhub_funcs = &gfxhub_v3_0_3_vmhub_funcs;
 492 }
 493
 494 const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs = {
 495         .get_fb_location = gfxhub_v3_0_3_get_fb_location,
 496         .get_mc_fb_offset = gfxhub_v3_0_3_get_mc_fb_offset,
 497         .setup_vm_pt_regs = gfxhub_v3_0_3_setup_vm_pt_regs,
 498         .gart_enable = gfxhub_v3_0_3_gart_enable,
 499         .gart_disable = gfxhub_v3_0_3_gart_disable,
 500         .set_fault_enable_default = gfxhub_v3_0_3_set_fault_enable_default,
 501         .init = gfxhub_v3_0_3_init,
 502 };