drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  54 {
  55         struct amdgpu_mman *mman;
  56         struct amdgpu_device *adev;
  57
  58         mman = container_of(bdev, struct amdgpu_mman, bdev);
  59         adev = container_of(mman, struct amdgpu_device, mman);
  60         return adev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         struct amdgpu_ring *ring;
  81         struct amd_sched_rq *rq;
  82         int r;
  83
  84         adev->mman.mem_global_referenced = false;
  85         global_ref = &adev->mman.mem_global_ref;
  86         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  87         global_ref->size = sizeof(struct ttm_mem_global);
  88         global_ref->init = &amdgpu_ttm_mem_global_init;
  89         global_ref->release = &amdgpu_ttm_mem_global_release;
  90         r = drm_global_item_ref(global_ref);
  91         if (r != 0) {
  92                 DRM_ERROR("Failed setting up TTM memory accounting "
  93                           "subsystem.\n");
  94                 return r;
  95         }
  96
  97         adev->mman.bo_global_ref.mem_glob =
  98                 adev->mman.mem_global_ref.object;
  99         global_ref = &adev->mman.bo_global_ref.ref;
 100         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 101         global_ref->size = sizeof(struct ttm_bo_global);
 102         global_ref->init = &ttm_bo_global_init;
 103         global_ref->release = &ttm_bo_global_release;
 104         r = drm_global_item_ref(global_ref);
 105         if (r != 0) {
 106                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 107                 drm_global_item_unref(&adev->mman.mem_global_ref);
 108                 return r;
 109         }
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs);
 115         if (r != 0) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 drm_global_item_unref(&adev->mman.mem_global_ref);
 118                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 119                 return r;
 120         }
 121
 122         adev->mman.mem_global_referenced = true;
 123
 124         return 0;
 125 }
 126
 127 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 128 {
 129         if (adev->mman.mem_global_referenced) {
 130                 amd_sched_entity_fini(adev->mman.entity.sched,
 131                                       &adev->mman.entity);
 132                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 133                 drm_global_item_unref(&adev->mman.mem_global_ref);
 134                 adev->mman.mem_global_referenced = false;
 135         }
 136 }
 137
 138 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 139 {
 140         return 0;
 141 }
 142
 143 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 144                                 struct ttm_mem_type_manager *man)
 145 {
 146         struct amdgpu_device *adev;
 147
 148         adev = amdgpu_get_adev(bdev);
 149
 150         switch (type) {
 151         case TTM_PL_SYSTEM:
 152                 /* System memory */
 153                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 break;
 157         case TTM_PL_TT:
 158                 man->func = &ttm_bo_manager_func;
 159                 man->gpu_offset = adev->mc.gtt_start;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 163                 break;
 164         case TTM_PL_VRAM:
 165                 /* "On-card" video ram */
 166                 man->func = &ttm_bo_manager_func;
 167                 man->gpu_offset = adev->mc.vram_start;
 168                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 169                              TTM_MEMTYPE_FLAG_MAPPABLE;
 170                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 171                 man->default_caching = TTM_PL_FLAG_WC;
 172                 break;
 173         case AMDGPU_PL_GDS:
 174         case AMDGPU_PL_GWS:
 175         case AMDGPU_PL_OA:
 176                 /* On-chip GDS memory*/
 177                 man->func = &ttm_bo_manager_func;
 178                 man->gpu_offset = 0;
 179                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 180                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 181                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 182                 break;
 183         default:
 184                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 185                 return -EINVAL;
 186         }
 187         return 0;
 188 }
 189
 190 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 191                                 struct ttm_placement *placement)
 192 {
 193         struct amdgpu_bo *rbo;
 194         static struct ttm_place placements = {
 195                 .fpfn = 0,
 196                 .lpfn = 0,
 197                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 198         };
 199
 200         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 201                 placement->placement = &placements;
 202                 placement->busy_placement = &placements;
 203                 placement->num_placement = 1;
 204                 placement->num_busy_placement = 1;
 205                 return;
 206         }
 207         rbo = container_of(bo, struct amdgpu_bo, tbo);
 208         switch (bo->mem.mem_type) {
 209         case TTM_PL_VRAM:
 210                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 211                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 212                 else
 213                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 214                 break;
 215         case TTM_PL_TT:
 216         default:
 217                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 218         }
 219         *placement = rbo->placement;
 220 }
 221
 222 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 223 {
 224         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 225
 226         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 227 }
 228
 229 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 230                              struct ttm_mem_reg *new_mem)
 231 {
 232         struct ttm_mem_reg *old_mem = &bo->mem;
 233
 234         BUG_ON(old_mem->mm_node != NULL);
 235         *old_mem = *new_mem;
 236         new_mem->mm_node = NULL;
 237 }
 238
 239 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 240                         bool evict, bool no_wait_gpu,
 241                         struct ttm_mem_reg *new_mem,
 242                         struct ttm_mem_reg *old_mem)
 243 {
 244         struct amdgpu_device *adev;
 245         struct amdgpu_ring *ring;
 246         uint64_t old_start, new_start;
 247         struct fence *fence;
 248         int r;
 249
 250         adev = amdgpu_get_adev(bo->bdev);
 251         ring = adev->mman.buffer_funcs_ring;
 252         old_start = old_mem->start << PAGE_SHIFT;
 253         new_start = new_mem->start << PAGE_SHIFT;
 254
 255         switch (old_mem->mem_type) {
 256         case TTM_PL_VRAM:
 257                 old_start += adev->mc.vram_start;
 258                 break;
 259         case TTM_PL_TT:
 260                 old_start += adev->mc.gtt_start;
 261                 break;
 262         default:
 263                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 264                 return -EINVAL;
 265         }
 266         switch (new_mem->mem_type) {
 267         case TTM_PL_VRAM:
 268                 new_start += adev->mc.vram_start;
 269                 break;
 270         case TTM_PL_TT:
 271                 new_start += adev->mc.gtt_start;
 272                 break;
 273         default:
 274                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 275                 return -EINVAL;
 276         }
 277         if (!ring->ready) {
 278                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 279                 return -EINVAL;
 280         }
 281
 282         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 283
 284         r = amdgpu_copy_buffer(ring, old_start, new_start,
 285                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 286                                bo->resv, &fence);
 287         /* FIXME: handle copy error */
 288         r = ttm_bo_move_accel_cleanup(bo, fence,
 289                                       evict, no_wait_gpu, new_mem);
 290         fence_put(fence);
 291         return r;
 292 }
 293
 294 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 295                                 bool evict, bool interruptible,
 296                                 bool no_wait_gpu,
 297                                 struct ttm_mem_reg *new_mem)
 298 {
 299         struct amdgpu_device *adev;
 300         struct ttm_mem_reg *old_mem = &bo->mem;
 301         struct ttm_mem_reg tmp_mem;
 302         struct ttm_place placements;
 303         struct ttm_placement placement;
 304         int r;
 305
 306         adev = amdgpu_get_adev(bo->bdev);
 307         tmp_mem = *new_mem;
 308         tmp_mem.mm_node = NULL;
 309         placement.num_placement = 1;
 310         placement.placement = &placements;
 311         placement.num_busy_placement = 1;
 312         placement.busy_placement = &placements;
 313         placements.fpfn = 0;
 314         placements.lpfn = 0;
 315         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 316         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 317                              interruptible, no_wait_gpu);
 318         if (unlikely(r)) {
 319                 return r;
 320         }
 321
 322         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 323         if (unlikely(r)) {
 324                 goto out_cleanup;
 325         }
 326
 327         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 328         if (unlikely(r)) {
 329                 goto out_cleanup;
 330         }
 331         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 332         if (unlikely(r)) {
 333                 goto out_cleanup;
 334         }
 335         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 336 out_cleanup:
 337         ttm_bo_mem_put(bo, &tmp_mem);
 338         return r;
 339 }
 340
 341 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 342                                 bool evict, bool interruptible,
 343                                 bool no_wait_gpu,
 344                                 struct ttm_mem_reg *new_mem)
 345 {
 346         struct amdgpu_device *adev;
 347         struct ttm_mem_reg *old_mem = &bo->mem;
 348         struct ttm_mem_reg tmp_mem;
 349         struct ttm_placement placement;
 350         struct ttm_place placements;
 351         int r;
 352
 353         adev = amdgpu_get_adev(bo->bdev);
 354         tmp_mem = *new_mem;
 355         tmp_mem.mm_node = NULL;
 356         placement.num_placement = 1;
 357         placement.placement = &placements;
 358         placement.num_busy_placement = 1;
 359         placement.busy_placement = &placements;
 360         placements.fpfn = 0;
 361         placements.lpfn = 0;
 362         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 363         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 364                              interruptible, no_wait_gpu);
 365         if (unlikely(r)) {
 366                 return r;
 367         }
 368         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 369         if (unlikely(r)) {
 370                 goto out_cleanup;
 371         }
 372         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 373         if (unlikely(r)) {
 374                 goto out_cleanup;
 375         }
 376 out_cleanup:
 377         ttm_bo_mem_put(bo, &tmp_mem);
 378         return r;
 379 }
 380
 381 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 382                         bool evict, bool interruptible,
 383                         bool no_wait_gpu,
 384                         struct ttm_mem_reg *new_mem)
 385 {
 386         struct amdgpu_device *adev;
 387         struct ttm_mem_reg *old_mem = &bo->mem;
 388         int r;
 389
 390         adev = amdgpu_get_adev(bo->bdev);
 391         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 392                 amdgpu_move_null(bo, new_mem);
 393                 return 0;
 394         }
 395         if ((old_mem->mem_type == TTM_PL_TT &&
 396              new_mem->mem_type == TTM_PL_SYSTEM) ||
 397             (old_mem->mem_type == TTM_PL_SYSTEM &&
 398              new_mem->mem_type == TTM_PL_TT)) {
 399                 /* bind is enough */
 400                 amdgpu_move_null(bo, new_mem);
 401                 return 0;
 402         }
 403         if (adev->mman.buffer_funcs == NULL ||
 404             adev->mman.buffer_funcs_ring == NULL ||
 405             !adev->mman.buffer_funcs_ring->ready) {
 406                 /* use memcpy */
 407                 goto memcpy;
 408         }
 409
 410         if (old_mem->mem_type == TTM_PL_VRAM &&
 411             new_mem->mem_type == TTM_PL_SYSTEM) {
 412                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 413                                         no_wait_gpu, new_mem);
 414         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 415                    new_mem->mem_type == TTM_PL_VRAM) {
 416                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 417                                             no_wait_gpu, new_mem);
 418         } else {
 419                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 420         }
 421
 422         if (r) {
 423 memcpy:
 424                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 425                 if (r) {
 426                         return r;
 427                 }
 428         }
 429
 430         /* update statistics */
 431         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 432         return 0;
 433 }
 434
 435 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 436 {
 437         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 438         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 439
 440         mem->bus.addr = NULL;
 441         mem->bus.offset = 0;
 442         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 443         mem->bus.base = 0;
 444         mem->bus.is_iomem = false;
 445         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 446                 return -EINVAL;
 447         switch (mem->mem_type) {
 448         case TTM_PL_SYSTEM:
 449                 /* system memory */
 450                 return 0;
 451         case TTM_PL_TT:
 452                 break;
 453         case TTM_PL_VRAM:
 454                 mem->bus.offset = mem->start << PAGE_SHIFT;
 455                 /* check if it's visible */
 456                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 457                         return -EINVAL;
 458                 mem->bus.base = adev->mc.aper_base;
 459                 mem->bus.is_iomem = true;
 460 #ifdef __alpha__
 461                 /*
 462                  * Alpha: use bus.addr to hold the ioremap() return,
 463                  * so we can modify bus.base below.
 464                  */
 465                 if (mem->placement & TTM_PL_FLAG_WC)
 466                         mem->bus.addr =
 467                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 468                                            mem->bus.size);
 469                 else
 470                         mem->bus.addr =
 471                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 472                                                 mem->bus.size);
 473
 474                 /*
 475                  * Alpha: Use just the bus offset plus
 476                  * the hose/domain memory base for bus.base.
 477                  * It then can be used to build PTEs for VRAM
 478                  * access, as done in ttm_bo_vm_fault().
 479                  */
 480                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 481                         adev->ddev->hose->dense_mem_base;
 482 #endif
 483                 break;
 484         default:
 485                 return -EINVAL;
 486         }
 487         return 0;
 488 }
 489
 490 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 491 {
 492 }
 493
 494 /*
 495  * TTM backend functions.
 496  */
 497 struct amdgpu_ttm_tt {
 498         struct ttm_dma_tt               ttm;
 499         struct amdgpu_device            *adev;
 500         u64                             offset;
 501         uint64_t                        userptr;
 502         struct mm_struct                *usermm;
 503         uint32_t                        userflags;
 504 };
 505
 506 /* prepare the sg table with the user pages */
 507 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 508 {
 509         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 510         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 511         unsigned pinned = 0, nents;
 512         int r;
 513
 514         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 515         enum dma_data_direction direction = write ?
 516                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 517
 518         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 519                 /* check that we only pin down anonymous memory
 520                    to prevent problems with writeback */
 521                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 522                 struct vm_area_struct *vma;
 523
 524                 vma = find_vma(gtt->usermm, gtt->userptr);
 525                 if (!vma || vma->vm_file || vma->vm_end < end)
 526                         return -EPERM;
 527         }
 528
 529         do {
 530                 unsigned num_pages = ttm->num_pages - pinned;
 531                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 532                 struct page **pages = ttm->pages + pinned;
 533
 534                 r = get_user_pages(current, current->mm, userptr, num_pages,
 535                                    write, 0, pages, NULL);
 536                 if (r < 0)
 537                         goto release_pages;
 538
 539                 pinned += r;
 540
 541         } while (pinned < ttm->num_pages);
 542
 543         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 544                                       ttm->num_pages << PAGE_SHIFT,
 545                                       GFP_KERNEL);
 546         if (r)
 547                 goto release_sg;
 548
 549         r = -ENOMEM;
 550         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 551         if (nents != ttm->sg->nents)
 552                 goto release_sg;
 553
 554         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 555                                          gtt->ttm.dma_address, ttm->num_pages);
 556
 557         return 0;
 558
 559 release_sg:
 560         kfree(ttm->sg);
 561
 562 release_pages:
 563         release_pages(ttm->pages, pinned, 0);
 564         return r;
 565 }
 566
 567 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 568 {
 569         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 570         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 571         struct sg_page_iter sg_iter;
 572
 573         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 574         enum dma_data_direction direction = write ?
 575                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 576
 577         /* double check that we don't free the table twice */
 578         if (!ttm->sg->sgl)
 579                 return;
 580
 581         /* free the sg table and pages again */
 582         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 583
 584         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 585                 struct page *page = sg_page_iter_page(&sg_iter);
 586                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 587                         set_page_dirty(page);
 588
 589                 mark_page_accessed(page);
 590                 page_cache_release(page);
 591         }
 592
 593         sg_free_table(ttm->sg);
 594 }
 595
 596 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 597                                    struct ttm_mem_reg *bo_mem)
 598 {
 599         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 600         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 601         int r;
 602
 603         if (gtt->userptr) {
 604                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 605                 if (r) {
 606                         DRM_ERROR("failed to pin userptr\n");
 607                         return r;
 608                 }
 609         }
 610         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 611         if (!ttm->num_pages) {
 612                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 613                      ttm->num_pages, bo_mem, ttm);
 614         }
 615
 616         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 617             bo_mem->mem_type == AMDGPU_PL_GWS ||
 618             bo_mem->mem_type == AMDGPU_PL_OA)
 619                 return -EINVAL;
 620
 621         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 622                 ttm->pages, gtt->ttm.dma_address, flags);
 623
 624         if (r) {
 625                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 626                           ttm->num_pages, (unsigned)gtt->offset);
 627                 return r;
 628         }
 629         return 0;
 630 }
 631
 632 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 633 {
 634         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 635
 636         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 637         if (gtt->adev->gart.ready)
 638                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 639
 640         if (gtt->userptr)
 641                 amdgpu_ttm_tt_unpin_userptr(ttm);
 642
 643         return 0;
 644 }
 645
 646 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 647 {
 648         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 649
 650         ttm_dma_tt_fini(&gtt->ttm);
 651         kfree(gtt);
 652 }
 653
 654 static struct ttm_backend_func amdgpu_backend_func = {
 655         .bind = &amdgpu_ttm_backend_bind,
 656         .unbind = &amdgpu_ttm_backend_unbind,
 657         .destroy = &amdgpu_ttm_backend_destroy,
 658 };
 659
 660 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 661                                     unsigned long size, uint32_t page_flags,
 662                                     struct page *dummy_read_page)
 663 {
 664         struct amdgpu_device *adev;
 665         struct amdgpu_ttm_tt *gtt;
 666
 667         adev = amdgpu_get_adev(bdev);
 668
 669         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 670         if (gtt == NULL) {
 671                 return NULL;
 672         }
 673         gtt->ttm.ttm.func = &amdgpu_backend_func;
 674         gtt->adev = adev;
 675         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 676                 kfree(gtt);
 677                 return NULL;
 678         }
 679         return &gtt->ttm.ttm;
 680 }
 681
 682 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 683 {
 684         struct amdgpu_device *adev;
 685         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 686         unsigned i;
 687         int r;
 688         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 689
 690         if (ttm->state != tt_unpopulated)
 691                 return 0;
 692
 693         if (gtt && gtt->userptr) {
 694                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 695                 if (!ttm->sg)
 696                         return -ENOMEM;
 697
 698                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 699                 ttm->state = tt_unbound;
 700                 return 0;
 701         }
 702
 703         if (slave && ttm->sg) {
 704                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 705                                                  gtt->ttm.dma_address, ttm->num_pages);
 706                 ttm->state = tt_unbound;
 707                 return 0;
 708         }
 709
 710         adev = amdgpu_get_adev(ttm->bdev);
 711
 712 #ifdef CONFIG_SWIOTLB
 713         if (swiotlb_nr_tbl()) {
 714                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 715         }
 716 #endif
 717
 718         r = ttm_pool_populate(ttm);
 719         if (r) {
 720                 return r;
 721         }
 722
 723         for (i = 0; i < ttm->num_pages; i++) {
 724                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 725                                                        0, PAGE_SIZE,
 726                                                        PCI_DMA_BIDIRECTIONAL);
 727                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 728                         while (i--) {
 729                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 730                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 731                                 gtt->ttm.dma_address[i] = 0;
 732                         }
 733                         ttm_pool_unpopulate(ttm);
 734                         return -EFAULT;
 735                 }
 736         }
 737         return 0;
 738 }
 739
 740 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 741 {
 742         struct amdgpu_device *adev;
 743         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 744         unsigned i;
 745         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 746
 747         if (gtt && gtt->userptr) {
 748                 kfree(ttm->sg);
 749                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 750                 return;
 751         }
 752
 753         if (slave)
 754                 return;
 755
 756         adev = amdgpu_get_adev(ttm->bdev);
 757
 758 #ifdef CONFIG_SWIOTLB
 759         if (swiotlb_nr_tbl()) {
 760                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 761                 return;
 762         }
 763 #endif
 764
 765         for (i = 0; i < ttm->num_pages; i++) {
 766                 if (gtt->ttm.dma_address[i]) {
 767                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 768                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 769                 }
 770         }
 771
 772         ttm_pool_unpopulate(ttm);
 773 }
 774
 775 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 776                               uint32_t flags)
 777 {
 778         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 779
 780         if (gtt == NULL)
 781                 return -EINVAL;
 782
 783         gtt->userptr = addr;
 784         gtt->usermm = current->mm;
 785         gtt->userflags = flags;
 786         return 0;
 787 }
 788
 789 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 790 {
 791         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 792
 793         if (gtt == NULL)
 794                 return NULL;
 795
 796         return gtt->usermm;
 797 }
 798
 799 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 800                                   unsigned long end)
 801 {
 802         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 803         unsigned long size;
 804
 805         if (gtt == NULL)
 806                 return false;
 807
 808         if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
 809                 return false;
 810
 811         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 812         if (gtt->userptr > end || gtt->userptr + size <= start)
 813                 return false;
 814
 815         return true;
 816 }
 817
 818 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 819 {
 820         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 821
 822         if (gtt == NULL)
 823                 return false;
 824
 825         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 826 }
 827
 828 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 829                                  struct ttm_mem_reg *mem)
 830 {
 831         uint32_t flags = 0;
 832
 833         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 834                 flags |= AMDGPU_PTE_VALID;
 835
 836         if (mem && mem->mem_type == TTM_PL_TT) {
 837                 flags |= AMDGPU_PTE_SYSTEM;
 838
 839                 if (ttm->caching_state == tt_cached)
 840                         flags |= AMDGPU_PTE_SNOOPED;
 841         }
 842
 843         if (adev->asic_type >= CHIP_TONGA)
 844                 flags |= AMDGPU_PTE_EXECUTABLE;
 845
 846         flags |= AMDGPU_PTE_READABLE;
 847
 848         if (!amdgpu_ttm_tt_is_readonly(ttm))
 849                 flags |= AMDGPU_PTE_WRITEABLE;
 850
 851         return flags;
 852 }
 853
 854 static struct ttm_bo_driver amdgpu_bo_driver = {
 855         .ttm_tt_create = &amdgpu_ttm_tt_create,
 856         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 857         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 858         .invalidate_caches = &amdgpu_invalidate_caches,
 859         .init_mem_type = &amdgpu_init_mem_type,
 860         .evict_flags = &amdgpu_evict_flags,
 861         .move = &amdgpu_bo_move,
 862         .verify_access = &amdgpu_verify_access,
 863         .move_notify = &amdgpu_bo_move_notify,
 864         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 865         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 866         .io_mem_free = &amdgpu_ttm_io_mem_free,
 867 };
 868
 869 int amdgpu_ttm_init(struct amdgpu_device *adev)
 870 {
 871         int r;
 872
 873         r = amdgpu_ttm_global_init(adev);
 874         if (r) {
 875                 return r;
 876         }
 877         /* No others user of address space so set it to 0 */
 878         r = ttm_bo_device_init(&adev->mman.bdev,
 879                                adev->mman.bo_global_ref.ref.object,
 880                                &amdgpu_bo_driver,
 881                                adev->ddev->anon_inode->i_mapping,
 882                                DRM_FILE_PAGE_OFFSET,
 883                                adev->need_dma32);
 884         if (r) {
 885                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 886                 return r;
 887         }
 888         adev->mman.initialized = true;
 889         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
 890                                 adev->mc.real_vram_size >> PAGE_SHIFT);
 891         if (r) {
 892                 DRM_ERROR("Failed initializing VRAM heap.\n");
 893                 return r;
 894         }
 895         /* Change the size here instead of the init above so only lpfn is affected */
 896         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 897
 898         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
 899                              AMDGPU_GEM_DOMAIN_VRAM,
 900                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 901                              NULL, NULL, &adev->stollen_vga_memory);
 902         if (r) {
 903                 return r;
 904         }
 905         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 906         if (r)
 907                 return r;
 908         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
 909         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 910         if (r) {
 911                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 912                 return r;
 913         }
 914         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 915                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
 916         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
 917                                 adev->mc.gtt_size >> PAGE_SHIFT);
 918         if (r) {
 919                 DRM_ERROR("Failed initializing GTT heap.\n");
 920                 return r;
 921         }
 922         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
 923                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
 924
 925         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
 926         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
 927         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
 928         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
 929         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
 930         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
 931         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
 932         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
 933         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
 934         /* GDS Memory */
 935         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
 936                                 adev->gds.mem.total_size >> PAGE_SHIFT);
 937         if (r) {
 938                 DRM_ERROR("Failed initializing GDS heap.\n");
 939                 return r;
 940         }
 941
 942         /* GWS */
 943         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
 944                                 adev->gds.gws.total_size >> PAGE_SHIFT);
 945         if (r) {
 946                 DRM_ERROR("Failed initializing gws heap.\n");
 947                 return r;
 948         }
 949
 950         /* OA */
 951         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
 952                                 adev->gds.oa.total_size >> PAGE_SHIFT);
 953         if (r) {
 954                 DRM_ERROR("Failed initializing oa heap.\n");
 955                 return r;
 956         }
 957
 958         r = amdgpu_ttm_debugfs_init(adev);
 959         if (r) {
 960                 DRM_ERROR("Failed to init debugfs\n");
 961                 return r;
 962         }
 963         return 0;
 964 }
 965
 966 void amdgpu_ttm_fini(struct amdgpu_device *adev)
 967 {
 968         int r;
 969
 970         if (!adev->mman.initialized)
 971                 return;
 972         amdgpu_ttm_debugfs_fini(adev);
 973         if (adev->stollen_vga_memory) {
 974                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 975                 if (r == 0) {
 976                         amdgpu_bo_unpin(adev->stollen_vga_memory);
 977                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 978                 }
 979                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 980         }
 981         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
 982         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
 983         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
 984         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
 985         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
 986         ttm_bo_device_release(&adev->mman.bdev);
 987         amdgpu_gart_fini(adev);
 988         amdgpu_ttm_global_fini(adev);
 989         adev->mman.initialized = false;
 990         DRM_INFO("amdgpu: ttm finalized\n");
 991 }
 992
 993 /* this should only be called at bootup or when userspace
 994  * isn't running */
 995 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
 996 {
 997         struct ttm_mem_type_manager *man;
 998
 999         if (!adev->mman.initialized)
1000                 return;
1001
1002         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1003         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1004         man->size = size >> PAGE_SHIFT;
1005 }
1006
1007 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1008 {
1009         struct drm_file *file_priv;
1010         struct amdgpu_device *adev;
1011
1012         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1013                 return -EINVAL;
1014
1015         file_priv = filp->private_data;
1016         adev = file_priv->minor->dev->dev_private;
1017         if (adev == NULL)
1018                 return -EINVAL;
1019
1020         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1021 }
1022
1023 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1024                        uint64_t src_offset,
1025                        uint64_t dst_offset,
1026                        uint32_t byte_count,
1027                        struct reservation_object *resv,
1028                        struct fence **fence)
1029 {
1030         struct amdgpu_device *adev = ring->adev;
1031         struct amdgpu_job *job;
1032
1033         uint32_t max_bytes;
1034         unsigned num_loops, num_dw;
1035         unsigned i;
1036         int r;
1037
1038         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1039         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1040         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1041
1042         /* for IB padding */
1043         while (num_dw & 0x7)
1044                 num_dw++;
1045
1046         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1047         if (r)
1048                 return r;
1049
1050         if (resv) {
1051                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1052                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1053                 if (r) {
1054                         DRM_ERROR("sync failed (%d).\n", r);
1055                         goto error_free;
1056                 }
1057         }
1058
1059         for (i = 0; i < num_loops; i++) {
1060                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1061
1062                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1063                                         dst_offset, cur_size_in_bytes);
1064
1065                 src_offset += cur_size_in_bytes;
1066                 dst_offset += cur_size_in_bytes;
1067                 byte_count -= cur_size_in_bytes;
1068         }
1069
1070         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1071         WARN_ON(job->ibs[0].length_dw > num_dw);
1072         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1073                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1074         if (r)
1075                 goto error_free;
1076
1077         return 0;
1078
1079 error_free:
1080         amdgpu_job_free(job);
1081         return r;
1082 }
1083
1084 #if defined(CONFIG_DEBUG_FS)
1085
1086 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1087 {
1088         struct drm_info_node *node = (struct drm_info_node *)m->private;
1089         unsigned ttm_pl = *(int *)node->info_ent->data;
1090         struct drm_device *dev = node->minor->dev;
1091         struct amdgpu_device *adev = dev->dev_private;
1092         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1093         int ret;
1094         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1095
1096         spin_lock(&glob->lru_lock);
1097         ret = drm_mm_dump_table(m, mm);
1098         spin_unlock(&glob->lru_lock);
1099         if (ttm_pl == TTM_PL_VRAM)
1100                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1101                            adev->mman.bdev.man[ttm_pl].size,
1102                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1103                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1104         return ret;
1105 }
1106
1107 static int ttm_pl_vram = TTM_PL_VRAM;
1108 static int ttm_pl_tt = TTM_PL_TT;
1109
1110 static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1111         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1112         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1113         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1114 #ifdef CONFIG_SWIOTLB
1115         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1116 #endif
1117 };
1118
1119 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1120                                     size_t size, loff_t *pos)
1121 {
1122         struct amdgpu_device *adev = f->f_inode->i_private;
1123         ssize_t result = 0;
1124         int r;
1125
1126         if (size & 0x3 || *pos & 0x3)
1127                 return -EINVAL;
1128
1129         while (size) {
1130                 unsigned long flags;
1131                 uint32_t value;
1132
1133                 if (*pos >= adev->mc.mc_vram_size)
1134                         return result;
1135
1136                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1137                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1138                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1139                 value = RREG32(mmMM_DATA);
1140                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1141
1142                 r = put_user(value, (uint32_t *)buf);
1143                 if (r)
1144                         return r;
1145
1146                 result += 4;
1147                 buf += 4;
1148                 *pos += 4;
1149                 size -= 4;
1150         }
1151
1152         return result;
1153 }
1154
1155 static const struct file_operations amdgpu_ttm_vram_fops = {
1156         .owner = THIS_MODULE,
1157         .read = amdgpu_ttm_vram_read,
1158         .llseek = default_llseek
1159 };
1160
1161 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1162                                    size_t size, loff_t *pos)
1163 {
1164         struct amdgpu_device *adev = f->f_inode->i_private;
1165         ssize_t result = 0;
1166         int r;
1167
1168         while (size) {
1169                 loff_t p = *pos / PAGE_SIZE;
1170                 unsigned off = *pos & ~PAGE_MASK;
1171                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1172                 struct page *page;
1173                 void *ptr;
1174
1175                 if (p >= adev->gart.num_cpu_pages)
1176                         return result;
1177
1178                 page = adev->gart.pages[p];
1179                 if (page) {
1180                         ptr = kmap(page);
1181                         ptr += off;
1182
1183                         r = copy_to_user(buf, ptr, cur_size);
1184                         kunmap(adev->gart.pages[p]);
1185                 } else
1186                         r = clear_user(buf, cur_size);
1187
1188                 if (r)
1189                         return -EFAULT;
1190
1191                 result += cur_size;
1192                 buf += cur_size;
1193                 *pos += cur_size;
1194                 size -= cur_size;
1195         }
1196
1197         return result;
1198 }
1199
1200 static const struct file_operations amdgpu_ttm_gtt_fops = {
1201         .owner = THIS_MODULE,
1202         .read = amdgpu_ttm_gtt_read,
1203         .llseek = default_llseek
1204 };
1205
1206 #endif
1207
1208 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1209 {
1210 #if defined(CONFIG_DEBUG_FS)
1211         unsigned count;
1212
1213         struct drm_minor *minor = adev->ddev->primary;
1214         struct dentry *ent, *root = minor->debugfs_root;
1215
1216         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1217                                   adev, &amdgpu_ttm_vram_fops);
1218         if (IS_ERR(ent))
1219                 return PTR_ERR(ent);
1220         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1221         adev->mman.vram = ent;
1222
1223         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1224                                   adev, &amdgpu_ttm_gtt_fops);
1225         if (IS_ERR(ent))
1226                 return PTR_ERR(ent);
1227         i_size_write(ent->d_inode, adev->mc.gtt_size);
1228         adev->mman.gtt = ent;
1229
1230         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1231
1232 #ifdef CONFIG_SWIOTLB
1233         if (!swiotlb_nr_tbl())
1234                 --count;
1235 #endif
1236
1237         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1238 #else
1239
1240         return 0;
1241 #endif
1242 }
1243
1244 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1245 {
1246 #if defined(CONFIG_DEBUG_FS)
1247
1248         debugfs_remove(adev->mman.vram);
1249         adev->mman.vram = NULL;
1250
1251         debugfs_remove(adev->mman.gtt);
1252         adev->mman.gtt = NULL;
1253 #endif
1254 }