drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_cs.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_hw_ip.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v4_0.h"
  34 #include "vcn_v4_0.h"
  35
  36 #include "vcn/vcn_4_0_0_offset.h"
  37 #include "vcn/vcn_4_0_0_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #include <drm/drm_drv.h>
  41
  42 #define mmUVD_DPG_LMA_CTL                                                       regUVD_DPG_LMA_CTL
  43 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                              regUVD_DPG_LMA_CTL_BASE_IDX
  44 #define mmUVD_DPG_LMA_DATA                                                      regUVD_DPG_LMA_DATA
  45 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                             regUVD_DPG_LMA_DATA_BASE_IDX
  46
  47 #define VCN_VID_SOC_ADDRESS_2_0                                                 0x1fb00
  48 #define VCN1_VID_SOC_ADDRESS_3_0                                                0x48300
  49
  50 #define VCN_HARVEST_MMSCH                                                               0
  51
  52 #define RDECODE_MSG_CREATE                                                      0x00000000
  53 #define RDECODE_MESSAGE_CREATE                                                  0x00000001
  54
  55 static int amdgpu_ih_clientid_vcns[] = {
  56         SOC15_IH_CLIENTID_VCN,
  57         SOC15_IH_CLIENTID_VCN1
  58 };
  59
  60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
  61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
  62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  63 static int vcn_v4_0_set_powergating_state(void *handle,
  64         enum amd_powergating_state state);
  65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
  66         int inst_idx, struct dpg_pause_state *new_state);
  67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
  68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  69
  70 /**
  71  * vcn_v4_0_early_init - set function pointers and load microcode
  72  *
  73  * @handle: amdgpu_device pointer
  74  *
  75  * Set ring and irq function pointers
  76  * Load microcode from filesystem
  77  */
  78 static int vcn_v4_0_early_init(void *handle)
  79 {
  80         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  81         int i;
  82
  83         if (amdgpu_sriov_vf(adev)) {
  84                 adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
  85                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  86                         if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
  87                                 adev->vcn.harvest_config |= 1 << i;
  88                                 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
  89                         }
  90                 }
  91         }
  92
  93         /* re-use enc ring as unified ring */
  94         adev->vcn.num_enc_rings = 1;
  95
  96         vcn_v4_0_set_unified_ring_funcs(adev);
  97         vcn_v4_0_set_irq_funcs(adev);
  98         vcn_v4_0_set_ras_funcs(adev);
  99
 100         return amdgpu_vcn_early_init(adev);
 101 }
 102
 103 /**
 104  * vcn_v4_0_sw_init - sw init for VCN block
 105  *
 106  * @handle: amdgpu_device pointer
 107  *
 108  * Load firmware and sw initialization
 109  */
 110 static int vcn_v4_0_sw_init(void *handle)
 111 {
 112         struct amdgpu_ring *ring;
 113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 114         int i, r;
 115
 116         r = amdgpu_vcn_sw_init(adev);
 117         if (r)
 118                 return r;
 119
 120         amdgpu_vcn_setup_ucode(adev);
 121
 122         r = amdgpu_vcn_resume(adev);
 123         if (r)
 124                 return r;
 125
 126         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 127                 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 128
 129                 if (adev->vcn.harvest_config & (1 << i))
 130                         continue;
 131
 132                 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
 133                 if (i == 0)
 134                         atomic_set(&adev->vcn.inst[i].sched_score, 1);
 135                 else
 136                         atomic_set(&adev->vcn.inst[i].sched_score, 0);
 137
 138                 /* VCN UNIFIED TRAP */
 139                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 140                                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 141                 if (r)
 142                         return r;
 143
 144                 /* VCN POISON TRAP */
 145                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 146                                 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
 147                 if (r)
 148                         return r;
 149
 150                 ring = &adev->vcn.inst[i].ring_enc[0];
 151                 ring->use_doorbell = true;
 152                 if (amdgpu_sriov_vf(adev))
 153                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
 154                 else
 155                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 156                 ring->vm_hub = AMDGPU_MMHUB0(0);
 157                 sprintf(ring->name, "vcn_unified_%d", i);
 158
 159                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 160                                                 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 161                 if (r)
 162                         return r;
 163
 164                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 165                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 166                 fw_shared->sq.is_enabled = 1;
 167
 168                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
 169                 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
 170                         AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
 171
 172                 if (amdgpu_sriov_vf(adev))
 173                         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
 174
 175                 if (amdgpu_vcnfw_log)
 176                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 177         }
 178
 179         if (amdgpu_sriov_vf(adev)) {
 180                 r = amdgpu_virt_alloc_mm_table(adev);
 181                 if (r)
 182                         return r;
 183         }
 184
 185         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 186                 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
 187
 188         r = amdgpu_vcn_ras_sw_init(adev);
 189         if (r)
 190                 return r;
 191
 192         return 0;
 193 }
 194
 195 /**
 196  * vcn_v4_0_sw_fini - sw fini for VCN block
 197  *
 198  * @handle: amdgpu_device pointer
 199  *
 200  * VCN suspend and free up sw allocation
 201  */
 202 static int vcn_v4_0_sw_fini(void *handle)
 203 {
 204         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 205         int i, r, idx;
 206
 207         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 208                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 209                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 210
 211                         if (adev->vcn.harvest_config & (1 << i))
 212                                 continue;
 213
 214                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 215                         fw_shared->present_flag_0 = 0;
 216                         fw_shared->sq.is_enabled = 0;
 217                 }
 218
 219                 drm_dev_exit(idx);
 220         }
 221
 222         if (amdgpu_sriov_vf(adev))
 223                 amdgpu_virt_free_mm_table(adev);
 224
 225         r = amdgpu_vcn_suspend(adev);
 226         if (r)
 227                 return r;
 228
 229         r = amdgpu_vcn_sw_fini(adev);
 230
 231         return r;
 232 }
 233
 234 /**
 235  * vcn_v4_0_hw_init - start and test VCN block
 236  *
 237  * @handle: amdgpu_device pointer
 238  *
 239  * Initialize the hardware, boot up the VCPU and do some testing
 240  */
 241 static int vcn_v4_0_hw_init(void *handle)
 242 {
 243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 244         struct amdgpu_ring *ring;
 245         int i, r;
 246
 247         if (amdgpu_sriov_vf(adev)) {
 248                 r = vcn_v4_0_start_sriov(adev);
 249                 if (r)
 250                         goto done;
 251
 252                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 253                         if (adev->vcn.harvest_config & (1 << i))
 254                                 continue;
 255
 256                         ring = &adev->vcn.inst[i].ring_enc[0];
 257                         ring->wptr = 0;
 258                         ring->wptr_old = 0;
 259                         vcn_v4_0_unified_ring_set_wptr(ring);
 260                         ring->sched.ready = true;
 261
 262                 }
 263         } else {
 264                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 265                         if (adev->vcn.harvest_config & (1 << i))
 266                                 continue;
 267
 268                         ring = &adev->vcn.inst[i].ring_enc[0];
 269
 270                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 271                                         ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 272
 273                         r = amdgpu_ring_test_helper(ring);
 274                         if (r)
 275                                 goto done;
 276
 277                 }
 278         }
 279
 280 done:
 281         if (!r)
 282                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 283                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 284
 285         return r;
 286 }
 287
 288 /**
 289  * vcn_v4_0_hw_fini - stop the hardware block
 290  *
 291  * @handle: amdgpu_device pointer
 292  *
 293  * Stop the VCN block, mark ring as not ready any more
 294  */
 295 static int vcn_v4_0_hw_fini(void *handle)
 296 {
 297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 298         int i;
 299
 300         cancel_delayed_work_sync(&adev->vcn.idle_work);
 301
 302         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 303                 if (adev->vcn.harvest_config & (1 << i))
 304                         continue;
 305                 if (!amdgpu_sriov_vf(adev)) {
 306                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 307                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 308                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
 309                         vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 310                         }
 311                 }
 312                 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 313                         amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
 314         }
 315
 316         return 0;
 317 }
 318
 319 /**
 320  * vcn_v4_0_suspend - suspend VCN block
 321  *
 322  * @handle: amdgpu_device pointer
 323  *
 324  * HW fini and suspend VCN block
 325  */
 326 static int vcn_v4_0_suspend(void *handle)
 327 {
 328         int r;
 329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 330
 331         r = vcn_v4_0_hw_fini(adev);
 332         if (r)
 333                 return r;
 334
 335         r = amdgpu_vcn_suspend(adev);
 336
 337         return r;
 338 }
 339
 340 /**
 341  * vcn_v4_0_resume - resume VCN block
 342  *
 343  * @handle: amdgpu_device pointer
 344  *
 345  * Resume firmware and hw init VCN block
 346  */
 347 static int vcn_v4_0_resume(void *handle)
 348 {
 349         int r;
 350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 351
 352         r = amdgpu_vcn_resume(adev);
 353         if (r)
 354                 return r;
 355
 356         r = vcn_v4_0_hw_init(adev);
 357
 358         return r;
 359 }
 360
 361 /**
 362  * vcn_v4_0_mc_resume - memory controller programming
 363  *
 364  * @adev: amdgpu_device pointer
 365  * @inst: instance number
 366  *
 367  * Let the VCN memory controller know it's offsets
 368  */
 369 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
 370 {
 371         uint32_t offset, size;
 372         const struct common_firmware_header *hdr;
 373
 374         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 375         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 376
 377         /* cache window 0: fw */
 378         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 379                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 380                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 381                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 382                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 383                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 384                 offset = 0;
 385         } else {
 386                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 387                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 388                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 389                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 390                 offset = size;
 391                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 392         }
 393         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
 394
 395         /* cache window 1: stack */
 396         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 397                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 398         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 399                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 400         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 401         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 402
 403         /* cache window 2: context */
 404         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 405                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 406         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 407                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 408         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 409         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 410
 411         /* non-cache window */
 412         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 413                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 414         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 415                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 416         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 417         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
 418                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 419 }
 420
 421 /**
 422  * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
 423  *
 424  * @adev: amdgpu_device pointer
 425  * @inst_idx: instance number index
 426  * @indirect: indirectly write sram
 427  *
 428  * Let the VCN memory controller know it's offsets with dpg mode
 429  */
 430 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 431 {
 432         uint32_t offset, size;
 433         const struct common_firmware_header *hdr;
 434         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 435         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 436
 437         /* cache window 0: fw */
 438         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 439                 if (!indirect) {
 440                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 441                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 442                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 443                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 444                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 445                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 446                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 447                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 448                 } else {
 449                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 450                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 451                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 452                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 453                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 454                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 455                 }
 456                 offset = 0;
 457         } else {
 458                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 459                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 460                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 461                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 462                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 463                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 464                 offset = size;
 465                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 466                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 467                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 468         }
 469
 470         if (!indirect)
 471                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 472                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 473         else
 474                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 475                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 476
 477         /* cache window 1: stack */
 478         if (!indirect) {
 479                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 480                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 481                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 482                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 483                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 484                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 485                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 486                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 487         } else {
 488                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 489                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 490                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 491                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 492                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 493                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 494         }
 495         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 496                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 497
 498         /* cache window 2: context */
 499         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 500                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 501                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 502         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 503                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 504                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 505         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 506                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 507         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 508                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 509
 510         /* non-cache window */
 511         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 512                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 513                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 514         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 515                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 516                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 517         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 518                         VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 519         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 520                         VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
 521                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 522
 523         /* VCN global tiling registers */
 524         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 525                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 526 }
 527
 528 /**
 529  * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
 530  *
 531  * @adev: amdgpu_device pointer
 532  * @inst: instance number
 533  *
 534  * Disable static power gating for VCN block
 535  */
 536 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 537 {
 538         uint32_t data = 0;
 539
 540         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 541                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 542                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 543                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 544                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 545                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 546                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 547                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 548                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 549                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 550                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 551                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 552                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 553                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 554                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 555
 556                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 557                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
 558                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 559         } else {
 560                 uint32_t value;
 561
 562                 value = (inst) ? 0x2200800 : 0;
 563                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 564                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 565                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 566                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 567                         | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 568                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 569                         | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 570                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 571                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 572                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 573                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 574                         | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 575                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 576                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 577
 578                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 579                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value,  0x3F3FFFFF);
 580         }
 581
 582         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 583         data &= ~0x103;
 584         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 585                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 586                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 587
 588         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 589
 590         return;
 591 }
 592
 593 /**
 594  * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
 595  *
 596  * @adev: amdgpu_device pointer
 597  * @inst: instance number
 598  *
 599  * Enable static power gating for VCN block
 600  */
 601 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 602 {
 603         uint32_t data;
 604
 605         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 606                 /* Before power off, this indicator has to be turned on */
 607                 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 608                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 609                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 610                 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 611
 612                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 613                         | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 614                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 615                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 616                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 617                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 618                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 619                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 620                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 621                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 622                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 623                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 624                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 625                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 626                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 627
 628                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 629                         | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
 630                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 631                         | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
 632                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 633                         | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
 634                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 635                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 636                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 637                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 638                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 639                         | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
 640                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 641                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 642                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 643         }
 644
 645         return;
 646 }
 647
 648 /**
 649  * vcn_v4_0_disable_clock_gating - disable VCN clock gating
 650  *
 651  * @adev: amdgpu_device pointer
 652  * @inst: instance number
 653  *
 654  * Disable clock gating for VCN block
 655  */
 656 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 657 {
 658         uint32_t data;
 659
 660         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 661                 return;
 662
 663         /* VCN disable CGC */
 664         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 665         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 666         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 667         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 668         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 669
 670         data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
 671         data &= ~(UVD_CGC_GATE__SYS_MASK
 672                 | UVD_CGC_GATE__UDEC_MASK
 673                 | UVD_CGC_GATE__MPEG2_MASK
 674                 | UVD_CGC_GATE__REGS_MASK
 675                 | UVD_CGC_GATE__RBC_MASK
 676                 | UVD_CGC_GATE__LMI_MC_MASK
 677                 | UVD_CGC_GATE__LMI_UMC_MASK
 678                 | UVD_CGC_GATE__IDCT_MASK
 679                 | UVD_CGC_GATE__MPRD_MASK
 680                 | UVD_CGC_GATE__MPC_MASK
 681                 | UVD_CGC_GATE__LBSI_MASK
 682                 | UVD_CGC_GATE__LRBBM_MASK
 683                 | UVD_CGC_GATE__UDEC_RE_MASK
 684                 | UVD_CGC_GATE__UDEC_CM_MASK
 685                 | UVD_CGC_GATE__UDEC_IT_MASK
 686                 | UVD_CGC_GATE__UDEC_DB_MASK
 687                 | UVD_CGC_GATE__UDEC_MP_MASK
 688                 | UVD_CGC_GATE__WCB_MASK
 689                 | UVD_CGC_GATE__VCPU_MASK
 690                 | UVD_CGC_GATE__MMSCH_MASK);
 691
 692         WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
 693         SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);
 694
 695         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 696         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 697                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 698                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 699                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 700                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 701                 | UVD_CGC_CTRL__SYS_MODE_MASK
 702                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 703                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 704                 | UVD_CGC_CTRL__REGS_MODE_MASK
 705                 | UVD_CGC_CTRL__RBC_MODE_MASK
 706                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 707                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 708                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 709                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 710                 | UVD_CGC_CTRL__MPC_MODE_MASK
 711                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 712                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 713                 | UVD_CGC_CTRL__WCB_MODE_MASK
 714                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 715                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 716         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 717
 718         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
 719         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 720                 | UVD_SUVD_CGC_GATE__SIT_MASK
 721                 | UVD_SUVD_CGC_GATE__SMP_MASK
 722                 | UVD_SUVD_CGC_GATE__SCM_MASK
 723                 | UVD_SUVD_CGC_GATE__SDB_MASK
 724                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 725                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 726                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 727                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 728                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 729                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 730                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 731                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 732                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 733                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 734                 | UVD_SUVD_CGC_GATE__ENT_MASK
 735                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 736                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 737                 | UVD_SUVD_CGC_GATE__SITE_MASK
 738                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 739                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 740                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 741                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 742                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 743         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
 744
 745         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 746         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 747                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 748                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 749                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 750                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 751                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 752                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 753                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 754                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 755                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 756         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 757 }
 758
 759 /**
 760  * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 761  *
 762  * @adev: amdgpu_device pointer
 763  * @sram_sel: sram select
 764  * @inst_idx: instance number index
 765  * @indirect: indirectly write sram
 766  *
 767  * Disable clock gating for VCN block with dpg mode
 768  */
 769 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 770       int inst_idx, uint8_t indirect)
 771 {
 772         uint32_t reg_data = 0;
 773
 774         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 775                 return;
 776
 777         /* enable sw clock gating control */
 778         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 779         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 780         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 781         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 782                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 783                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 784                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 785                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 786                  UVD_CGC_CTRL__SYS_MODE_MASK |
 787                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 788                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 789                  UVD_CGC_CTRL__REGS_MODE_MASK |
 790                  UVD_CGC_CTRL__RBC_MODE_MASK |
 791                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 792                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 793                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 794                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 795                  UVD_CGC_CTRL__MPC_MODE_MASK |
 796                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 797                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 798                  UVD_CGC_CTRL__WCB_MODE_MASK |
 799                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 800         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 801                 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 802
 803         /* turn off clock gating */
 804         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 805                 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
 806
 807         /* turn on SUVD clock gating */
 808         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 809                 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 810
 811         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 812         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 813                 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 814 }
 815
 816 /**
 817  * vcn_v4_0_enable_clock_gating - enable VCN clock gating
 818  *
 819  * @adev: amdgpu_device pointer
 820  * @inst: instance number
 821  *
 822  * Enable clock gating for VCN block
 823  */
 824 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 825 {
 826         uint32_t data;
 827
 828         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 829                 return;
 830
 831         /* enable VCN CGC */
 832         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 833         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 834         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 835         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 836         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 837
 838         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 839         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 840                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 841                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 842                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 843                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 844                 | UVD_CGC_CTRL__SYS_MODE_MASK
 845                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 846                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 847                 | UVD_CGC_CTRL__REGS_MODE_MASK
 848                 | UVD_CGC_CTRL__RBC_MODE_MASK
 849                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 850                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 851                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 852                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 853                 | UVD_CGC_CTRL__MPC_MODE_MASK
 854                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 855                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 856                 | UVD_CGC_CTRL__WCB_MODE_MASK
 857                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 858                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 859         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 860
 861         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 862         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 863                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 864                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 865                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 866                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 867                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 868                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 869                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 870                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 871                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 872         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 873
 874         return;
 875 }
 876
 877 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
 878                                 bool indirect)
 879 {
 880         uint32_t tmp;
 881
 882         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 883                 return;
 884
 885         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
 886               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
 887               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
 888               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
 889         WREG32_SOC15_DPG_MODE(inst_idx,
 890                               SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
 891                               tmp, 0, indirect);
 892
 893         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 894         WREG32_SOC15_DPG_MODE(inst_idx,
 895                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
 896                               tmp, 0, indirect);
 897 }
 898
 899 /**
 900  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
 901  *
 902  * @adev: amdgpu_device pointer
 903  * @inst_idx: instance number index
 904  * @indirect: indirectly write sram
 905  *
 906  * Start VCN block with dpg mode
 907  */
 908 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 909 {
 910         volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 911         struct amdgpu_ring *ring;
 912         uint32_t tmp;
 913
 914         /* disable register anti-hang mechanism */
 915         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
 916                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 917         /* enable dynamic power gating mode */
 918         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
 919         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 920         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 921         WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
 922
 923         if (indirect)
 924                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 925
 926         /* enable clock gating */
 927         vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 928
 929         /* enable VCPU clock */
 930         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 931         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 932         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 933                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 934
 935         /* disable master interupt */
 936         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 937                 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
 938
 939         /* setup regUVD_LMI_CTRL */
 940         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 941                 UVD_LMI_CTRL__REQ_MODE_MASK |
 942                 UVD_LMI_CTRL__CRC_RESET_MASK |
 943                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 944                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 945                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 946                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 947                 0x00100000L);
 948         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 949                 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
 950
 951         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 952                 VCN, inst_idx, regUVD_MPC_CNTL),
 953                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 954
 955         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 956                 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
 957                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 958                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 959                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 960                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 961
 962         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 963                 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
 964                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 965                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 966                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 967                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 968
 969         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 970                 VCN, inst_idx, regUVD_MPC_SET_MUX),
 971                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 972                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 973                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 974
 975         vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
 976
 977         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 978         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 979         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 980                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 981
 982         /* enable LMI MC and UMC channels */
 983         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 984         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 985                 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 986
 987         vcn_v4_0_enable_ras(adev, inst_idx, indirect);
 988
 989         /* enable master interrupt */
 990         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 991                 VCN, inst_idx, regUVD_MASTINT_EN),
 992                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 993
 994
 995         if (indirect)
 996                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
 997                         (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 998                                 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 999
1000         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1001
1002         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
1003         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1004         WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1005
1006         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1007         tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1008         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1009         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1010         WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1011         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1012
1013         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1014         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1015         ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1016
1017         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1018         tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1019         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1020         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1021
1022         WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1023                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1024                         VCN_RB1_DB_CTRL__EN_MASK);
1025
1026         return 0;
1027 }
1028
1029
1030 /**
1031  * vcn_v4_0_start - VCN start
1032  *
1033  * @adev: amdgpu_device pointer
1034  *
1035  * Start VCN block
1036  */
1037 static int vcn_v4_0_start(struct amdgpu_device *adev)
1038 {
1039         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1040         struct amdgpu_ring *ring;
1041         uint32_t tmp;
1042         int i, j, k, r;
1043
1044         if (adev->pm.dpm_enabled)
1045                 amdgpu_dpm_enable_uvd(adev, true);
1046
1047         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1048                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1049
1050                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1051                         r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1052                         continue;
1053                 }
1054
1055                 /* disable VCN power gating */
1056                 vcn_v4_0_disable_static_power_gating(adev, i);
1057
1058                 /* set VCN status busy */
1059                 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1060                 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1061
1062                 /*SW clock gating */
1063                 vcn_v4_0_disable_clock_gating(adev, i);
1064
1065                 /* enable VCPU clock */
1066                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1067                                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1068
1069                 /* disable master interrupt */
1070                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1071                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1072
1073                 /* enable LMI MC and UMC channels */
1074                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1075                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1076
1077                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1078                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1079                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1080                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1081
1082                 /* setup regUVD_LMI_CTRL */
1083                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1084                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1085                                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1086                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1087                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1088                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1089
1090                 /* setup regUVD_MPC_CNTL */
1091                 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1092                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1093                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1094                 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1095
1096                 /* setup UVD_MPC_SET_MUXA0 */
1097                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1098                                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1099                                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1100                                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1101                                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1102
1103                 /* setup UVD_MPC_SET_MUXB0 */
1104                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1105                                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1106                                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1107                                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1108                                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1109
1110                 /* setup UVD_MPC_SET_MUX */
1111                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1112                                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1113                                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1114                                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1115
1116                 vcn_v4_0_mc_resume(adev, i);
1117
1118                 /* VCN global tiling registers */
1119                 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1120                                 adev->gfx.config.gb_addr_config);
1121
1122                 /* unblock VCPU register access */
1123                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1124                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1125
1126                 /* release VCPU reset to boot */
1127                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1128                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1129
1130                 for (j = 0; j < 10; ++j) {
1131                         uint32_t status;
1132
1133                         for (k = 0; k < 100; ++k) {
1134                                 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1135                                 if (status & 2)
1136                                         break;
1137                                 mdelay(10);
1138                                 if (amdgpu_emu_mode==1)
1139                                         msleep(1);
1140                         }
1141
1142                         if (amdgpu_emu_mode==1) {
1143                                 r = -1;
1144                                 if (status & 2) {
1145                                         r = 0;
1146                                         break;
1147                                 }
1148                         } else {
1149                                 r = 0;
1150                                 if (status & 2)
1151                                         break;
1152
1153                                 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1154                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1155                                                         UVD_VCPU_CNTL__BLK_RST_MASK,
1156                                                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1157                                 mdelay(10);
1158                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1159                                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1160
1161                                 mdelay(10);
1162                                 r = -1;
1163                         }
1164                 }
1165
1166                 if (r) {
1167                         dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1168                         return r;
1169                 }
1170
1171                 /* enable master interrupt */
1172                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1173                                 UVD_MASTINT_EN__VCPU_EN_MASK,
1174                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1175
1176                 /* clear the busy bit of VCN_STATUS */
1177                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1178                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1179
1180                 ring = &adev->vcn.inst[i].ring_enc[0];
1181                 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1182                                 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1183                                 VCN_RB1_DB_CTRL__EN_MASK);
1184
1185                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1186                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1187                 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1188
1189                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1190                 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1191                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1192                 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1193                 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1194                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1195
1196                 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1197                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1198                 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1199
1200                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1201                 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1202                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1203                 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1210 {
1211         int i;
1212         struct amdgpu_ring *ring_enc;
1213         uint64_t cache_addr;
1214         uint64_t rb_enc_addr;
1215         uint64_t ctx_addr;
1216         uint32_t param, resp, expected;
1217         uint32_t offset, cache_size;
1218         uint32_t tmp, timeout;
1219
1220         struct amdgpu_mm_table *table = &adev->virt.mm_table;
1221         uint32_t *table_loc;
1222         uint32_t table_size;
1223         uint32_t size, size_dw;
1224         uint32_t init_status;
1225         uint32_t enabled_vcn;
1226
1227         struct mmsch_v4_0_cmd_direct_write
1228                 direct_wt = { {0} };
1229         struct mmsch_v4_0_cmd_direct_read_modify_write
1230                 direct_rd_mod_wt = { {0} };
1231         struct mmsch_v4_0_cmd_end end = { {0} };
1232         struct mmsch_v4_0_init_header header;
1233
1234         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1235         volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1236
1237         direct_wt.cmd_header.command_type =
1238                 MMSCH_COMMAND__DIRECT_REG_WRITE;
1239         direct_rd_mod_wt.cmd_header.command_type =
1240                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1241         end.cmd_header.command_type =
1242                 MMSCH_COMMAND__END;
1243
1244         header.version = MMSCH_VERSION;
1245         header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1246         for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
1247                 header.inst[i].init_status = 0;
1248                 header.inst[i].table_offset = 0;
1249                 header.inst[i].table_size = 0;
1250         }
1251
1252         table_loc = (uint32_t *)table->cpu_addr;
1253         table_loc += header.total_size;
1254         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1255                 if (adev->vcn.harvest_config & (1 << i))
1256                         continue;
1257
1258                 table_size = 0;
1259
1260                 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1261                         regUVD_STATUS),
1262                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1263
1264                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1265
1266                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1267                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1268                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1269                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1270                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1271                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1272                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1273                         offset = 0;
1274                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1275                                 regUVD_VCPU_CACHE_OFFSET0),
1276                                 0);
1277                 } else {
1278                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1279                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1280                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1281                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1282                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1283                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1284                         offset = cache_size;
1285                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1286                                 regUVD_VCPU_CACHE_OFFSET0),
1287                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1288                 }
1289
1290                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1291                         regUVD_VCPU_CACHE_SIZE0),
1292                         cache_size);
1293
1294                 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1295                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1296                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1297                         lower_32_bits(cache_addr));
1298                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1299                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1300                         upper_32_bits(cache_addr));
1301                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1302                         regUVD_VCPU_CACHE_OFFSET1),
1303                         0);
1304                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1305                         regUVD_VCPU_CACHE_SIZE1),
1306                         AMDGPU_VCN_STACK_SIZE);
1307
1308                 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1309                         AMDGPU_VCN_STACK_SIZE;
1310                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1311                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1312                         lower_32_bits(cache_addr));
1313                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1314                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1315                         upper_32_bits(cache_addr));
1316                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1317                         regUVD_VCPU_CACHE_OFFSET2),
1318                         0);
1319                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1320                         regUVD_VCPU_CACHE_SIZE2),
1321                         AMDGPU_VCN_CONTEXT_SIZE);
1322
1323                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1324                 rb_setup = &fw_shared->rb_setup;
1325
1326                 ring_enc = &adev->vcn.inst[i].ring_enc[0];
1327                 ring_enc->wptr = 0;
1328                 rb_enc_addr = ring_enc->gpu_addr;
1329
1330                 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1331                 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1332                 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1333                 rb_setup->rb_size = ring_enc->ring_size / 4;
1334                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1335
1336                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1337                         regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1338                         lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1339                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1340                         regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1341                         upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1342                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1343                         regUVD_VCPU_NONCACHE_SIZE0),
1344                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1345
1346                 /* add end packet */
1347                 MMSCH_V4_0_INSERT_END();
1348
1349                 /* refine header */
1350                 header.inst[i].init_status = 0;
1351                 header.inst[i].table_offset = header.total_size;
1352                 header.inst[i].table_size = table_size;
1353                 header.total_size += table_size;
1354         }
1355
1356         /* Update init table header in memory */
1357         size = sizeof(struct mmsch_v4_0_init_header);
1358         table_loc = (uint32_t *)table->cpu_addr;
1359         memcpy((void *)table_loc, &header, size);
1360
1361         /* message MMSCH (in VCN[0]) to initialize this client
1362          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1363          * of memory descriptor location
1364          */
1365         ctx_addr = table->gpu_addr;
1366         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1367         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1368
1369         /* 2, update vmid of descriptor */
1370         tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1371         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1372         /* use domain0 for MM scheduler */
1373         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1374         WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1375
1376         /* 3, notify mmsch about the size of this descriptor */
1377         size = header.total_size;
1378         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1379
1380         /* 4, set resp to zero */
1381         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1382
1383         /* 5, kick off the initialization and wait until
1384          * MMSCH_VF_MAILBOX_RESP becomes non-zero
1385          */
1386         param = 0x00000001;
1387         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1388         tmp = 0;
1389         timeout = 1000;
1390         resp = 0;
1391         expected = MMSCH_VF_MAILBOX_RESP__OK;
1392         while (resp != expected) {
1393                 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1394                 if (resp != 0)
1395                         break;
1396
1397                 udelay(10);
1398                 tmp = tmp + 10;
1399                 if (tmp >= timeout) {
1400                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1401                                 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1402                                 "(expected=0x%08x, readback=0x%08x)\n",
1403                                 tmp, expected, resp);
1404                         return -EBUSY;
1405                 }
1406         }
1407         enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1408         init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1409         if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1410         && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1411                 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1412                         "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1413
1414         return 0;
1415 }
1416
1417 /**
1418  * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1419  *
1420  * @adev: amdgpu_device pointer
1421  * @inst_idx: instance number index
1422  *
1423  * Stop VCN block with dpg mode
1424  */
1425 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1426 {
1427         struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1428         uint32_t tmp;
1429
1430         vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
1431         /* Wait for power status to be 1 */
1432         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1433                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1434
1435         /* wait for read ptr to be equal to write ptr */
1436         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1437         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1438
1439         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1440                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1441
1442         /* disable dynamic power gating mode */
1443         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1444                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1445 }
1446
1447 /**
1448  * vcn_v4_0_stop - VCN stop
1449  *
1450  * @adev: amdgpu_device pointer
1451  *
1452  * Stop VCN block
1453  */
1454 static int vcn_v4_0_stop(struct amdgpu_device *adev)
1455 {
1456         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1457         uint32_t tmp;
1458         int i, r = 0;
1459
1460         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1461                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1462                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1463
1464                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1465                         vcn_v4_0_stop_dpg_mode(adev, i);
1466                         continue;
1467                 }
1468
1469                 /* wait for vcn idle */
1470                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1471                 if (r)
1472                         return r;
1473
1474                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1475                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1476                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1477                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1478                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1479                 if (r)
1480                         return r;
1481
1482                 /* disable LMI UMC channel */
1483                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1484                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1485                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1486                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1487                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1488                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1489                 if (r)
1490                         return r;
1491
1492                 /* block VCPU register access */
1493                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1494                                 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1495                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1496
1497                 /* reset VCPU */
1498                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1499                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1500                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1501
1502                 /* disable VCPU clock */
1503                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1504                                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1505
1506                 /* apply soft reset */
1507                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1508                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1509                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1510                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1511                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1512                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1513
1514                 /* clear status */
1515                 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1516
1517                 /* apply HW clock gating */
1518                 vcn_v4_0_enable_clock_gating(adev, i);
1519
1520                 /* enable VCN power gating */
1521                 vcn_v4_0_enable_static_power_gating(adev, i);
1522         }
1523
1524         if (adev->pm.dpm_enabled)
1525                 amdgpu_dpm_enable_uvd(adev, false);
1526
1527         return 0;
1528 }
1529
1530 /**
1531  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1532  *
1533  * @adev: amdgpu_device pointer
1534  * @inst_idx: instance number index
1535  * @new_state: pause state
1536  *
1537  * Pause dpg mode for VCN block
1538  */
1539 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1540       struct dpg_pause_state *new_state)
1541 {
1542         uint32_t reg_data = 0;
1543         int ret_code;
1544
1545         /* pause/unpause if state is changed */
1546         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1547                 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1548                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1549                 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1550                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1551
1552                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1553                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1554                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1555
1556                         if (!ret_code) {
1557                                 /* pause DPG */
1558                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1559                                 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1560
1561                                 /* wait for ACK */
1562                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1563                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1564                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1565
1566                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1567                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1568                         }
1569                 } else {
1570                         /* unpause dpg, no need to wait */
1571                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1572                         WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1573                 }
1574                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1575         }
1576
1577         return 0;
1578 }
1579
1580 /**
1581  * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1582  *
1583  * @ring: amdgpu_ring pointer
1584  *
1585  * Returns the current hardware unified read pointer
1586  */
1587 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1588 {
1589         struct amdgpu_device *adev = ring->adev;
1590
1591         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1592                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1593
1594         return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1595 }
1596
1597 /**
1598  * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1599  *
1600  * @ring: amdgpu_ring pointer
1601  *
1602  * Returns the current hardware unified write pointer
1603  */
1604 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1605 {
1606         struct amdgpu_device *adev = ring->adev;
1607
1608         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1609                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1610
1611         if (ring->use_doorbell)
1612                 return *ring->wptr_cpu_addr;
1613         else
1614                 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1615 }
1616
1617 /**
1618  * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1619  *
1620  * @ring: amdgpu_ring pointer
1621  *
1622  * Commits the enc write pointer to the hardware
1623  */
1624 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1625 {
1626         struct amdgpu_device *adev = ring->adev;
1627
1628         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1629                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1630
1631         if (ring->use_doorbell) {
1632                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1633                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1634         } else {
1635                 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1636         }
1637 }
1638
1639 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1640                                 struct amdgpu_job *job)
1641 {
1642         struct drm_gpu_scheduler **scheds;
1643
1644         /* The create msg must be in the first IB submitted */
1645         if (atomic_read(&job->base.entity->fence_seq))
1646                 return -EINVAL;
1647
1648         /* if VCN0 is harvested, we can't support AV1 */
1649         if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1650                 return -EINVAL;
1651
1652         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1653                 [AMDGPU_RING_PRIO_0].sched;
1654         drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1655         return 0;
1656 }
1657
1658 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1659                             uint64_t addr)
1660 {
1661         struct ttm_operation_ctx ctx = { false, false };
1662         struct amdgpu_bo_va_mapping *map;
1663         uint32_t *msg, num_buffers;
1664         struct amdgpu_bo *bo;
1665         uint64_t start, end;
1666         unsigned int i;
1667         void *ptr;
1668         int r;
1669
1670         addr &= AMDGPU_GMC_HOLE_MASK;
1671         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1672         if (r) {
1673                 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1674                 return r;
1675         }
1676
1677         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1678         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1679         if (addr & 0x7) {
1680                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1681                 return -EINVAL;
1682         }
1683
1684         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1685         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1686         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1687         if (r) {
1688                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1689                 return r;
1690         }
1691
1692         r = amdgpu_bo_kmap(bo, &ptr);
1693         if (r) {
1694                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1695                 return r;
1696         }
1697
1698         msg = ptr + addr - start;
1699
1700         /* Check length */
1701         if (msg[1] > end - addr) {
1702                 r = -EINVAL;
1703                 goto out;
1704         }
1705
1706         if (msg[3] != RDECODE_MSG_CREATE)
1707                 goto out;
1708
1709         num_buffers = msg[2];
1710         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1711                 uint32_t offset, size, *create;
1712
1713                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1714                         continue;
1715
1716                 offset = msg[1];
1717                 size = msg[2];
1718
1719                 if (offset + size > end) {
1720                         r = -EINVAL;
1721                         goto out;
1722                 }
1723
1724                 create = ptr + addr + offset - start;
1725
1726                 /* H264, HEVC and VP9 can run on any instance */
1727                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1728                         continue;
1729
1730                 r = vcn_v4_0_limit_sched(p, job);
1731                 if (r)
1732                         goto out;
1733         }
1734
1735 out:
1736         amdgpu_bo_kunmap(bo);
1737         return r;
1738 }
1739
1740 #define RADEON_VCN_ENGINE_TYPE_ENCODE                   (0x00000002)
1741 #define RADEON_VCN_ENGINE_TYPE_DECODE                   (0x00000003)
1742
1743 #define RADEON_VCN_ENGINE_INFO                          (0x30000001)
1744 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET               16
1745
1746 #define RENCODE_ENCODE_STANDARD_AV1                     2
1747 #define RENCODE_IB_PARAM_SESSION_INIT                   0x00000003
1748 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET        64
1749
1750 /* return the offset in ib if id is found, -1 otherwise
1751  * to speed up the searching we only search upto max_offset
1752  */
1753 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1754 {
1755         int i;
1756
1757         for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1758                 if (ib->ptr[i + 1] == id)
1759                         return i;
1760         }
1761         return -1;
1762 }
1763
1764 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1765                                            struct amdgpu_job *job,
1766                                            struct amdgpu_ib *ib)
1767 {
1768         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1769         struct amdgpu_vcn_decode_buffer *decode_buffer;
1770         uint64_t addr;
1771         uint32_t val;
1772         int idx;
1773
1774         /* The first instance can decode anything */
1775         if (!ring->me)
1776                 return 0;
1777
1778         /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1779         idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1780                         RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1781         if (idx < 0) /* engine info is missing */
1782                 return 0;
1783
1784         val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1785         if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1786                 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1787
1788                 if (!(decode_buffer->valid_buf_flag  & 0x1))
1789                         return 0;
1790
1791                 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1792                         decode_buffer->msg_buffer_address_lo;
1793                 return vcn_v4_0_dec_msg(p, job, addr);
1794         } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1795                 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1796                         RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1797                 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1798                         return vcn_v4_0_limit_sched(p, job);
1799         }
1800         return 0;
1801 }
1802
1803 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1804         .type = AMDGPU_RING_TYPE_VCN_ENC,
1805         .align_mask = 0x3f,
1806         .nop = VCN_ENC_CMD_NO_OP,
1807         .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1808         .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1809         .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1810         .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
1811         .emit_frame_size =
1812                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1813                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1814                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1815                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1816                 1, /* vcn_v2_0_enc_ring_insert_end */
1817         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1818         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1819         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1820         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1821         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1822         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1823         .insert_nop = amdgpu_ring_insert_nop,
1824         .insert_end = vcn_v2_0_enc_ring_insert_end,
1825         .pad_ib = amdgpu_ring_generic_pad_ib,
1826         .begin_use = amdgpu_vcn_ring_begin_use,
1827         .end_use = amdgpu_vcn_ring_end_use,
1828         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1829         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1830         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1831 };
1832
1833 /**
1834  * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
1835  *
1836  * @adev: amdgpu_device pointer
1837  *
1838  * Set unified ring functions
1839  */
1840 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
1841 {
1842         int i;
1843
1844         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1845                 if (adev->vcn.harvest_config & (1 << i))
1846                         continue;
1847
1848                 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs;
1849                 adev->vcn.inst[i].ring_enc[0].me = i;
1850
1851                 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
1852         }
1853 }
1854
1855 /**
1856  * vcn_v4_0_is_idle - check VCN block is idle
1857  *
1858  * @handle: amdgpu_device pointer
1859  *
1860  * Check whether VCN block is idle
1861  */
1862 static bool vcn_v4_0_is_idle(void *handle)
1863 {
1864         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1865         int i, ret = 1;
1866
1867         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1868                 if (adev->vcn.harvest_config & (1 << i))
1869                         continue;
1870
1871                 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1872         }
1873
1874         return ret;
1875 }
1876
1877 /**
1878  * vcn_v4_0_wait_for_idle - wait for VCN block idle
1879  *
1880  * @handle: amdgpu_device pointer
1881  *
1882  * Wait for VCN block idle
1883  */
1884 static int vcn_v4_0_wait_for_idle(void *handle)
1885 {
1886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1887         int i, ret = 0;
1888
1889         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1890                 if (adev->vcn.harvest_config & (1 << i))
1891                         continue;
1892
1893                 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1894                         UVD_STATUS__IDLE);
1895                 if (ret)
1896                         return ret;
1897         }
1898
1899         return ret;
1900 }
1901
1902 /**
1903  * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
1904  *
1905  * @handle: amdgpu_device pointer
1906  * @state: clock gating state
1907  *
1908  * Set VCN block clockgating state
1909  */
1910 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1911 {
1912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1913         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1914         int i;
1915
1916         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1917                 if (adev->vcn.harvest_config & (1 << i))
1918                         continue;
1919
1920                 if (enable) {
1921                         if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1922                                 return -EBUSY;
1923                         vcn_v4_0_enable_clock_gating(adev, i);
1924                 } else {
1925                         vcn_v4_0_disable_clock_gating(adev, i);
1926                 }
1927         }
1928
1929         return 0;
1930 }
1931
1932 /**
1933  * vcn_v4_0_set_powergating_state - set VCN block powergating state
1934  *
1935  * @handle: amdgpu_device pointer
1936  * @state: power gating state
1937  *
1938  * Set VCN block powergating state
1939  */
1940 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
1941 {
1942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1943         int ret;
1944
1945         /* for SRIOV, guest should not control VCN Power-gating
1946          * MMSCH FW should control Power-gating and clock-gating
1947          * guest should avoid touching CGC and PG
1948          */
1949         if (amdgpu_sriov_vf(adev)) {
1950                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1951                 return 0;
1952         }
1953
1954         if(state == adev->vcn.cur_state)
1955                 return 0;
1956
1957         if (state == AMD_PG_STATE_GATE)
1958                 ret = vcn_v4_0_stop(adev);
1959         else
1960                 ret = vcn_v4_0_start(adev);
1961
1962         if(!ret)
1963                 adev->vcn.cur_state = state;
1964
1965         return ret;
1966 }
1967
1968 /**
1969  * vcn_v4_0_set_interrupt_state - set VCN block interrupt state
1970  *
1971  * @adev: amdgpu_device pointer
1972  * @source: interrupt sources
1973  * @type: interrupt types
1974  * @state: interrupt states
1975  *
1976  * Set VCN block interrupt state
1977  */
1978 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1979       unsigned type, enum amdgpu_interrupt_state state)
1980 {
1981         return 0;
1982 }
1983
1984 /**
1985  * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state
1986  *
1987  * @adev: amdgpu_device pointer
1988  * @source: interrupt sources
1989  * @type: interrupt types
1990  * @state: interrupt states
1991  *
1992  * Set VCN block RAS interrupt state
1993  */
1994 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
1995         struct amdgpu_irq_src *source,
1996         unsigned int type,
1997         enum amdgpu_interrupt_state state)
1998 {
1999         return 0;
2000 }
2001
2002 /**
2003  * vcn_v4_0_process_interrupt - process VCN block interrupt
2004  *
2005  * @adev: amdgpu_device pointer
2006  * @source: interrupt sources
2007  * @entry: interrupt entry from clients and sources
2008  *
2009  * Process VCN block interrupt
2010  */
2011 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
2012       struct amdgpu_iv_entry *entry)
2013 {
2014         uint32_t ip_instance;
2015
2016         switch (entry->client_id) {
2017         case SOC15_IH_CLIENTID_VCN:
2018                 ip_instance = 0;
2019                 break;
2020         case SOC15_IH_CLIENTID_VCN1:
2021                 ip_instance = 1;
2022                 break;
2023         default:
2024                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2025                 return 0;
2026         }
2027
2028         DRM_DEBUG("IH: VCN TRAP\n");
2029
2030         switch (entry->src_id) {
2031         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2032                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2033                 break;
2034         default:
2035                 DRM_ERROR("Unhandled interrupt: %d %d\n",
2036                           entry->src_id, entry->src_data[0]);
2037                 break;
2038         }
2039
2040         return 0;
2041 }
2042
2043 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
2044         .set = vcn_v4_0_set_interrupt_state,
2045         .process = vcn_v4_0_process_interrupt,
2046 };
2047
2048 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
2049         .set = vcn_v4_0_set_ras_interrupt_state,
2050         .process = amdgpu_vcn_process_poison_irq,
2051 };
2052
2053 /**
2054  * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
2055  *
2056  * @adev: amdgpu_device pointer
2057  *
2058  * Set VCN block interrupt irq functions
2059  */
2060 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2061 {
2062         int i;
2063
2064         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2065                 if (adev->vcn.harvest_config & (1 << i))
2066                         continue;
2067
2068                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2069                 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
2070
2071                 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
2072                 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
2073         }
2074 }
2075
2076 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
2077         .name = "vcn_v4_0",
2078         .early_init = vcn_v4_0_early_init,
2079         .late_init = NULL,
2080         .sw_init = vcn_v4_0_sw_init,
2081         .sw_fini = vcn_v4_0_sw_fini,
2082         .hw_init = vcn_v4_0_hw_init,
2083         .hw_fini = vcn_v4_0_hw_fini,
2084         .suspend = vcn_v4_0_suspend,
2085         .resume = vcn_v4_0_resume,
2086         .is_idle = vcn_v4_0_is_idle,
2087         .wait_for_idle = vcn_v4_0_wait_for_idle,
2088         .check_soft_reset = NULL,
2089         .pre_soft_reset = NULL,
2090         .soft_reset = NULL,
2091         .post_soft_reset = NULL,
2092         .set_clockgating_state = vcn_v4_0_set_clockgating_state,
2093         .set_powergating_state = vcn_v4_0_set_powergating_state,
2094 };
2095
2096 const struct amdgpu_ip_block_version vcn_v4_0_ip_block =
2097 {
2098         .type = AMD_IP_BLOCK_TYPE_VCN,
2099         .major = 4,
2100         .minor = 0,
2101         .rev = 0,
2102         .funcs = &vcn_v4_0_ip_funcs,
2103 };
2104
2105 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2106                         uint32_t instance, uint32_t sub_block)
2107 {
2108         uint32_t poison_stat = 0, reg_value = 0;
2109
2110         switch (sub_block) {
2111         case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2112                 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2113                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2114                 break;
2115         default:
2116                 break;
2117         }
2118
2119         if (poison_stat)
2120                 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2121                         instance, sub_block);
2122
2123         return poison_stat;
2124 }
2125
2126 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2127 {
2128         uint32_t inst, sub;
2129         uint32_t poison_stat = 0;
2130
2131         for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2132                 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2133                         poison_stat +=
2134                                 vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2135
2136         return !!poison_stat;
2137 }
2138
2139 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2140         .query_poison_status = vcn_v4_0_query_ras_poison_status,
2141 };
2142
2143 static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2144         .ras_block = {
2145                 .hw_ops = &vcn_v4_0_ras_hw_ops,
2146                 .ras_late_init = amdgpu_vcn_ras_late_init,
2147         },
2148 };
2149
2150 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2151 {
2152         switch (adev->ip_versions[VCN_HWIP][0]) {
2153         case IP_VERSION(4, 0, 0):
2154                 adev->vcn.ras = &vcn_v4_0_ras;
2155                 break;
2156         default:
2157                 break;
2158         }
2159 }