drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/module.h>
  30 #include <linux/pagemap.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-buf.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_gem_ttm_helper.h>
  37 #include <drm/ttm/ttm_tt.h>
  38
  39 #include "amdgpu.h"
  40 #include "amdgpu_display.h"
  41 #include "amdgpu_dma_buf.h"
  42 #include "amdgpu_hmm.h"
  43 #include "amdgpu_xgmi.h"
  44
  45 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
  46
  47 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
  48 {
  49         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
  50         struct drm_device *ddev = bo->base.dev;
  51         vm_fault_t ret;
  52         int idx;
  53
  54         ret = ttm_bo_vm_reserve(bo, vmf);
  55         if (ret)
  56                 return ret;
  57
  58         if (drm_dev_enter(ddev, &idx)) {
  59                 ret = amdgpu_bo_fault_reserve_notify(bo);
  60                 if (ret) {
  61                         drm_dev_exit(idx);
  62                         goto unlock;
  63                 }
  64
  65                 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
  66                                                TTM_BO_VM_NUM_PREFAULT);
  67
  68                 drm_dev_exit(idx);
  69         } else {
  70                 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
  71         }
  72         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
  73                 return ret;
  74
  75 unlock:
  76         dma_resv_unlock(bo->base.resv);
  77         return ret;
  78 }
  79
  80 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
  81         .fault = amdgpu_gem_fault,
  82         .open = ttm_bo_vm_open,
  83         .close = ttm_bo_vm_close,
  84         .access = ttm_bo_vm_access
  85 };
  86
  87 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  88 {
  89         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  90
  91         if (robj) {
  92                 amdgpu_hmm_unregister(robj);
  93                 amdgpu_bo_unref(&robj);
  94         }
  95 }
  96
  97 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  98                              int alignment, u32 initial_domain,
  99                              u64 flags, enum ttm_bo_type type,
 100                              struct dma_resv *resv,
 101                              struct drm_gem_object **obj, int8_t xcp_id_plus1)
 102 {
 103         struct amdgpu_bo *bo;
 104         struct amdgpu_bo_user *ubo;
 105         struct amdgpu_bo_param bp;
 106         int r;
 107
 108         memset(&bp, 0, sizeof(bp));
 109         *obj = NULL;
 110
 111         bp.size = size;
 112         bp.byte_align = alignment;
 113         bp.type = type;
 114         bp.resv = resv;
 115         bp.preferred_domain = initial_domain;
 116         bp.flags = flags;
 117         bp.domain = initial_domain;
 118         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 119         bp.xcp_id_plus1 = xcp_id_plus1;
 120
 121         r = amdgpu_bo_create_user(adev, &bp, &ubo);
 122         if (r)
 123                 return r;
 124
 125         bo = &ubo->bo;
 126         *obj = &bo->tbo.base;
 127         (*obj)->funcs = &amdgpu_gem_object_funcs;
 128
 129         return 0;
 130 }
 131
 132 void amdgpu_gem_force_release(struct amdgpu_device *adev)
 133 {
 134         struct drm_device *ddev = adev_to_drm(adev);
 135         struct drm_file *file;
 136
 137         mutex_lock(&ddev->filelist_mutex);
 138
 139         list_for_each_entry(file, &ddev->filelist, lhead) {
 140                 struct drm_gem_object *gobj;
 141                 int handle;
 142
 143                 WARN_ONCE(1, "Still active user space clients!\n");
 144                 spin_lock(&file->table_lock);
 145                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 146                         WARN_ONCE(1, "And also active allocations!\n");
 147                         drm_gem_object_put(gobj);
 148                 }
 149                 idr_destroy(&file->object_idr);
 150                 spin_unlock(&file->table_lock);
 151         }
 152
 153         mutex_unlock(&ddev->filelist_mutex);
 154 }
 155
 156 /*
 157  * Call from drm_gem_handle_create which appear in both new and open ioctl
 158  * case.
 159  */
 160 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
 161                                   struct drm_file *file_priv)
 162 {
 163         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 164         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 165         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 166         struct amdgpu_vm *vm = &fpriv->vm;
 167         struct amdgpu_bo_va *bo_va;
 168         struct mm_struct *mm;
 169         int r;
 170
 171         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 172         if (mm && mm != current->mm)
 173                 return -EPERM;
 174
 175         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 176             abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
 177                 return -EPERM;
 178
 179         r = amdgpu_bo_reserve(abo, false);
 180         if (r)
 181                 return r;
 182
 183         bo_va = amdgpu_vm_bo_find(vm, abo);
 184         if (!bo_va) {
 185                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 186         } else {
 187                 ++bo_va->ref_count;
 188         }
 189         amdgpu_bo_unreserve(abo);
 190         return 0;
 191 }
 192
 193 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
 194                                     struct drm_file *file_priv)
 195 {
 196         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 197         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 198         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 199         struct amdgpu_vm *vm = &fpriv->vm;
 200
 201         struct amdgpu_bo_list_entry vm_pd;
 202         struct list_head list, duplicates;
 203         struct dma_fence *fence = NULL;
 204         struct ttm_validate_buffer tv;
 205         struct ww_acquire_ctx ticket;
 206         struct amdgpu_bo_va *bo_va;
 207         long r;
 208
 209         INIT_LIST_HEAD(&list);
 210         INIT_LIST_HEAD(&duplicates);
 211
 212         tv.bo = &bo->tbo;
 213         tv.num_shared = 2;
 214         list_add(&tv.head, &list);
 215
 216         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 217
 218         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 219         if (r) {
 220                 dev_err(adev->dev, "leaking bo va because "
 221                         "we fail to reserve bo (%ld)\n", r);
 222                 return;
 223         }
 224         bo_va = amdgpu_vm_bo_find(vm, bo);
 225         if (!bo_va || --bo_va->ref_count)
 226                 goto out_unlock;
 227
 228         amdgpu_vm_bo_del(adev, bo_va);
 229         if (!amdgpu_vm_ready(vm))
 230                 goto out_unlock;
 231
 232         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 233         if (r || !fence)
 234                 goto out_unlock;
 235
 236         amdgpu_bo_fence(bo, fence, true);
 237         dma_fence_put(fence);
 238
 239 out_unlock:
 240         if (unlikely(r < 0))
 241                 dev_err(adev->dev, "failed to clear page "
 242                         "tables on GEM object close (%ld)\n", r);
 243         ttm_eu_backoff_reservation(&ticket, &list);
 244 }
 245
 246 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 247 {
 248         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 249
 250         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 251                 return -EPERM;
 252         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 253                 return -EPERM;
 254
 255         /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
 256          * for debugger access to invisible VRAM. Should have used MAP_SHARED
 257          * instead. Clearing VM_MAYWRITE prevents the mapping from ever
 258          * becoming writable and makes is_cow_mapping(vm_flags) false.
 259          */
 260         if (is_cow_mapping(vma->vm_flags) &&
 261             !(vma->vm_flags & VM_ACCESS_FLAGS))
 262                 vm_flags_clear(vma, VM_MAYWRITE);
 263
 264         return drm_gem_ttm_mmap(obj, vma);
 265 }
 266
 267 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 268         .free = amdgpu_gem_object_free,
 269         .open = amdgpu_gem_object_open,
 270         .close = amdgpu_gem_object_close,
 271         .export = amdgpu_gem_prime_export,
 272         .vmap = drm_gem_ttm_vmap,
 273         .vunmap = drm_gem_ttm_vunmap,
 274         .mmap = amdgpu_gem_object_mmap,
 275         .vm_ops = &amdgpu_gem_vm_ops,
 276 };
 277
 278 /*
 279  * GEM ioctls.
 280  */
 281 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 282                             struct drm_file *filp)
 283 {
 284         struct amdgpu_device *adev = drm_to_adev(dev);
 285         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 286         struct amdgpu_vm *vm = &fpriv->vm;
 287         union drm_amdgpu_gem_create *args = data;
 288         uint64_t flags = args->in.domain_flags;
 289         uint64_t size = args->in.bo_size;
 290         struct dma_resv *resv = NULL;
 291         struct drm_gem_object *gobj;
 292         uint32_t handle, initial_domain;
 293         int r;
 294
 295         /* reject invalid gem flags */
 296         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 297                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 298                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 299                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 300                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 301                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
 302                       AMDGPU_GEM_CREATE_ENCRYPTED |
 303                       AMDGPU_GEM_CREATE_DISCARDABLE))
 304                 return -EINVAL;
 305
 306         /* reject invalid gem domains */
 307         if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
 308                 return -EINVAL;
 309
 310         if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
 311                 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
 312                 return -EINVAL;
 313         }
 314
 315         /* create a gem object to contain this object in */
 316         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 317             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 318                 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 319                         /* if gds bo is created from user space, it must be
 320                          * passed to bo list
 321                          */
 322                         DRM_ERROR("GDS bo cannot be per-vm-bo\n");
 323                         return -EINVAL;
 324                 }
 325                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 326         }
 327
 328         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 329                 r = amdgpu_bo_reserve(vm->root.bo, false);
 330                 if (r)
 331                         return r;
 332
 333                 resv = vm->root.bo->tbo.base.resv;
 334         }
 335
 336         initial_domain = (u32)(0xffffffff & args->in.domains);
 337 retry:
 338         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 339                                      initial_domain,
 340                                      flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
 341         if (r && r != -ERESTARTSYS) {
 342                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 343                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 344                         goto retry;
 345                 }
 346
 347                 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
 348                         initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
 349                         goto retry;
 350                 }
 351                 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
 352                                 size, initial_domain, args->in.alignment, r);
 353         }
 354
 355         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 356                 if (!r) {
 357                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 358
 359                         abo->parent = amdgpu_bo_ref(vm->root.bo);
 360                 }
 361                 amdgpu_bo_unreserve(vm->root.bo);
 362         }
 363         if (r)
 364                 return r;
 365
 366         r = drm_gem_handle_create(filp, gobj, &handle);
 367         /* drop reference from allocate - handle holds it now */
 368         drm_gem_object_put(gobj);
 369         if (r)
 370                 return r;
 371
 372         memset(args, 0, sizeof(*args));
 373         args->out.handle = handle;
 374         return 0;
 375 }
 376
 377 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 378                              struct drm_file *filp)
 379 {
 380         struct ttm_operation_ctx ctx = { true, false };
 381         struct amdgpu_device *adev = drm_to_adev(dev);
 382         struct drm_amdgpu_gem_userptr *args = data;
 383         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 384         struct drm_gem_object *gobj;
 385         struct hmm_range *range;
 386         struct amdgpu_bo *bo;
 387         uint32_t handle;
 388         int r;
 389
 390         args->addr = untagged_addr(args->addr);
 391
 392         if (offset_in_page(args->addr | args->size))
 393                 return -EINVAL;
 394
 395         /* reject unknown flag values */
 396         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 397             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 398             AMDGPU_GEM_USERPTR_REGISTER))
 399                 return -EINVAL;
 400
 401         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 402              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 403
 404                 /* if we want to write to it we must install a MMU notifier */
 405                 return -EACCES;
 406         }
 407
 408         /* create a gem object to contain this object in */
 409         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 410                                      0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 411         if (r)
 412                 return r;
 413
 414         bo = gem_to_amdgpu_bo(gobj);
 415         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 416         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 417         r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
 418         if (r)
 419                 goto release_object;
 420
 421         r = amdgpu_hmm_register(bo, args->addr);
 422         if (r)
 423                 goto release_object;
 424
 425         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 426                 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
 427                                                  &range);
 428                 if (r)
 429                         goto release_object;
 430
 431                 r = amdgpu_bo_reserve(bo, true);
 432                 if (r)
 433                         goto user_pages_done;
 434
 435                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 436                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 437                 amdgpu_bo_unreserve(bo);
 438                 if (r)
 439                         goto user_pages_done;
 440         }
 441
 442         r = drm_gem_handle_create(filp, gobj, &handle);
 443         if (r)
 444                 goto user_pages_done;
 445
 446         args->handle = handle;
 447
 448 user_pages_done:
 449         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
 450                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
 451
 452 release_object:
 453         drm_gem_object_put(gobj);
 454
 455         return r;
 456 }
 457
 458 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 459                           struct drm_device *dev,
 460                           uint32_t handle, uint64_t *offset_p)
 461 {
 462         struct drm_gem_object *gobj;
 463         struct amdgpu_bo *robj;
 464
 465         gobj = drm_gem_object_lookup(filp, handle);
 466         if (gobj == NULL) {
 467                 return -ENOENT;
 468         }
 469         robj = gem_to_amdgpu_bo(gobj);
 470         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 471             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 472                 drm_gem_object_put(gobj);
 473                 return -EPERM;
 474         }
 475         *offset_p = amdgpu_bo_mmap_offset(robj);
 476         drm_gem_object_put(gobj);
 477         return 0;
 478 }
 479
 480 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 481                           struct drm_file *filp)
 482 {
 483         union drm_amdgpu_gem_mmap *args = data;
 484         uint32_t handle = args->in.handle;
 485         memset(args, 0, sizeof(*args));
 486         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 487 }
 488
 489 /**
 490  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 491  *
 492  * @timeout_ns: timeout in ns
 493  *
 494  * Calculate the timeout in jiffies from an absolute timeout in ns.
 495  */
 496 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 497 {
 498         unsigned long timeout_jiffies;
 499         ktime_t timeout;
 500
 501         /* clamp timeout if it's to large */
 502         if (((int64_t)timeout_ns) < 0)
 503                 return MAX_SCHEDULE_TIMEOUT;
 504
 505         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 506         if (ktime_to_ns(timeout) < 0)
 507                 return 0;
 508
 509         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 510         /*  clamp timeout to avoid unsigned-> signed overflow */
 511         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 512                 return MAX_SCHEDULE_TIMEOUT - 1;
 513
 514         return timeout_jiffies;
 515 }
 516
 517 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 518                               struct drm_file *filp)
 519 {
 520         union drm_amdgpu_gem_wait_idle *args = data;
 521         struct drm_gem_object *gobj;
 522         struct amdgpu_bo *robj;
 523         uint32_t handle = args->in.handle;
 524         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 525         int r = 0;
 526         long ret;
 527
 528         gobj = drm_gem_object_lookup(filp, handle);
 529         if (gobj == NULL) {
 530                 return -ENOENT;
 531         }
 532         robj = gem_to_amdgpu_bo(gobj);
 533         ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
 534                                     true, timeout);
 535
 536         /* ret == 0 means not signaled,
 537          * ret > 0 means signaled
 538          * ret < 0 means interrupted before timeout
 539          */
 540         if (ret >= 0) {
 541                 memset(args, 0, sizeof(*args));
 542                 args->out.status = (ret == 0);
 543         } else
 544                 r = ret;
 545
 546         drm_gem_object_put(gobj);
 547         return r;
 548 }
 549
 550 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 551                                 struct drm_file *filp)
 552 {
 553         struct drm_amdgpu_gem_metadata *args = data;
 554         struct drm_gem_object *gobj;
 555         struct amdgpu_bo *robj;
 556         int r = -1;
 557
 558         DRM_DEBUG("%d \n", args->handle);
 559         gobj = drm_gem_object_lookup(filp, args->handle);
 560         if (gobj == NULL)
 561                 return -ENOENT;
 562         robj = gem_to_amdgpu_bo(gobj);
 563
 564         r = amdgpu_bo_reserve(robj, false);
 565         if (unlikely(r != 0))
 566                 goto out;
 567
 568         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 569                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 570                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 571                                            sizeof(args->data.data),
 572                                            &args->data.data_size_bytes,
 573                                            &args->data.flags);
 574         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 575                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 576                         r = -EINVAL;
 577                         goto unreserve;
 578                 }
 579                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 580                 if (!r)
 581                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 582                                                    args->data.data_size_bytes,
 583                                                    args->data.flags);
 584         }
 585
 586 unreserve:
 587         amdgpu_bo_unreserve(robj);
 588 out:
 589         drm_gem_object_put(gobj);
 590         return r;
 591 }
 592
 593 /**
 594  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 595  *
 596  * @adev: amdgpu_device pointer
 597  * @vm: vm to update
 598  * @bo_va: bo_va to update
 599  * @operation: map, unmap or clear
 600  *
 601  * Update the bo_va directly after setting its address. Errors are not
 602  * vital here, so they are not reported back to userspace.
 603  */
 604 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 605                                     struct amdgpu_vm *vm,
 606                                     struct amdgpu_bo_va *bo_va,
 607                                     uint32_t operation)
 608 {
 609         int r;
 610
 611         if (!amdgpu_vm_ready(vm))
 612                 return;
 613
 614         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 615         if (r)
 616                 goto error;
 617
 618         if (operation == AMDGPU_VA_OP_MAP ||
 619             operation == AMDGPU_VA_OP_REPLACE) {
 620                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 621                 if (r)
 622                         goto error;
 623         }
 624
 625         r = amdgpu_vm_update_pdes(adev, vm, false);
 626
 627 error:
 628         if (r && r != -ERESTARTSYS)
 629                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 630 }
 631
 632 /**
 633  * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
 634  *
 635  * @adev: amdgpu_device pointer
 636  * @flags: GEM UAPI flags
 637  *
 638  * Returns the GEM UAPI flags mapped into hardware for the ASIC.
 639  */
 640 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
 641 {
 642         uint64_t pte_flag = 0;
 643
 644         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 645                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 646         if (flags & AMDGPU_VM_PAGE_READABLE)
 647                 pte_flag |= AMDGPU_PTE_READABLE;
 648         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 649                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 650         if (flags & AMDGPU_VM_PAGE_PRT)
 651                 pte_flag |= AMDGPU_PTE_PRT;
 652         if (flags & AMDGPU_VM_PAGE_NOALLOC)
 653                 pte_flag |= AMDGPU_PTE_NOALLOC;
 654
 655         if (adev->gmc.gmc_funcs->map_mtype)
 656                 pte_flag |= amdgpu_gmc_map_mtype(adev,
 657                                                  flags & AMDGPU_VM_MTYPE_MASK);
 658
 659         return pte_flag;
 660 }
 661
 662 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 663                           struct drm_file *filp)
 664 {
 665         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 666                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 667                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
 668                 AMDGPU_VM_PAGE_NOALLOC;
 669         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 670                 AMDGPU_VM_PAGE_PRT;
 671
 672         struct drm_amdgpu_gem_va *args = data;
 673         struct drm_gem_object *gobj;
 674         struct amdgpu_device *adev = drm_to_adev(dev);
 675         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 676         struct amdgpu_bo *abo;
 677         struct amdgpu_bo_va *bo_va;
 678         struct amdgpu_bo_list_entry vm_pd;
 679         struct ttm_validate_buffer tv;
 680         struct ww_acquire_ctx ticket;
 681         struct list_head list, duplicates;
 682         uint64_t va_flags;
 683         uint64_t vm_size;
 684         int r = 0;
 685
 686         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 687                 dev_dbg(dev->dev,
 688                         "va_address 0x%LX is in reserved area 0x%LX\n",
 689                         args->va_address, AMDGPU_VA_RESERVED_SIZE);
 690                 return -EINVAL;
 691         }
 692
 693         if (args->va_address >= AMDGPU_GMC_HOLE_START &&
 694             args->va_address < AMDGPU_GMC_HOLE_END) {
 695                 dev_dbg(dev->dev,
 696                         "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
 697                         args->va_address, AMDGPU_GMC_HOLE_START,
 698                         AMDGPU_GMC_HOLE_END);
 699                 return -EINVAL;
 700         }
 701
 702         args->va_address &= AMDGPU_GMC_HOLE_MASK;
 703
 704         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 705         vm_size -= AMDGPU_VA_RESERVED_SIZE;
 706         if (args->va_address + args->map_size > vm_size) {
 707                 dev_dbg(dev->dev,
 708                         "va_address 0x%llx is in top reserved area 0x%llx\n",
 709                         args->va_address + args->map_size, vm_size);
 710                 return -EINVAL;
 711         }
 712
 713         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 714                 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
 715                         args->flags);
 716                 return -EINVAL;
 717         }
 718
 719         switch (args->operation) {
 720         case AMDGPU_VA_OP_MAP:
 721         case AMDGPU_VA_OP_UNMAP:
 722         case AMDGPU_VA_OP_CLEAR:
 723         case AMDGPU_VA_OP_REPLACE:
 724                 break;
 725         default:
 726                 dev_dbg(dev->dev, "unsupported operation %d\n",
 727                         args->operation);
 728                 return -EINVAL;
 729         }
 730
 731         INIT_LIST_HEAD(&list);
 732         INIT_LIST_HEAD(&duplicates);
 733         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 734             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 735                 gobj = drm_gem_object_lookup(filp, args->handle);
 736                 if (gobj == NULL)
 737                         return -ENOENT;
 738                 abo = gem_to_amdgpu_bo(gobj);
 739                 tv.bo = &abo->tbo;
 740                 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 741                         tv.num_shared = 1;
 742                 else
 743                         tv.num_shared = 0;
 744                 list_add(&tv.head, &list);
 745         } else {
 746                 gobj = NULL;
 747                 abo = NULL;
 748         }
 749
 750         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 751
 752         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 753         if (r)
 754                 goto error_unref;
 755
 756         if (abo) {
 757                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 758                 if (!bo_va) {
 759                         r = -ENOENT;
 760                         goto error_backoff;
 761                 }
 762         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 763                 bo_va = fpriv->prt_va;
 764         } else {
 765                 bo_va = NULL;
 766         }
 767
 768         switch (args->operation) {
 769         case AMDGPU_VA_OP_MAP:
 770                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 771                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 772                                      args->offset_in_bo, args->map_size,
 773                                      va_flags);
 774                 break;
 775         case AMDGPU_VA_OP_UNMAP:
 776                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 777                 break;
 778
 779         case AMDGPU_VA_OP_CLEAR:
 780                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 781                                                 args->va_address,
 782                                                 args->map_size);
 783                 break;
 784         case AMDGPU_VA_OP_REPLACE:
 785                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 786                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 787                                              args->offset_in_bo, args->map_size,
 788                                              va_flags);
 789                 break;
 790         default:
 791                 break;
 792         }
 793         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 794                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
 795                                         args->operation);
 796
 797 error_backoff:
 798         ttm_eu_backoff_reservation(&ticket, &list);
 799
 800 error_unref:
 801         drm_gem_object_put(gobj);
 802         return r;
 803 }
 804
 805 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 806                         struct drm_file *filp)
 807 {
 808         struct amdgpu_device *adev = drm_to_adev(dev);
 809         struct drm_amdgpu_gem_op *args = data;
 810         struct drm_gem_object *gobj;
 811         struct amdgpu_vm_bo_base *base;
 812         struct amdgpu_bo *robj;
 813         int r;
 814
 815         gobj = drm_gem_object_lookup(filp, args->handle);
 816         if (gobj == NULL) {
 817                 return -ENOENT;
 818         }
 819         robj = gem_to_amdgpu_bo(gobj);
 820
 821         r = amdgpu_bo_reserve(robj, false);
 822         if (unlikely(r))
 823                 goto out;
 824
 825         switch (args->op) {
 826         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 827                 struct drm_amdgpu_gem_create_in info;
 828                 void __user *out = u64_to_user_ptr(args->value);
 829
 830                 info.bo_size = robj->tbo.base.size;
 831                 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
 832                 info.domains = robj->preferred_domains;
 833                 info.domain_flags = robj->flags;
 834                 amdgpu_bo_unreserve(robj);
 835                 if (copy_to_user(out, &info, sizeof(info)))
 836                         r = -EFAULT;
 837                 break;
 838         }
 839         case AMDGPU_GEM_OP_SET_PLACEMENT:
 840                 if (robj->tbo.base.import_attach &&
 841                     args->value & AMDGPU_GEM_DOMAIN_VRAM) {
 842                         r = -EINVAL;
 843                         amdgpu_bo_unreserve(robj);
 844                         break;
 845                 }
 846                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 847                         r = -EPERM;
 848                         amdgpu_bo_unreserve(robj);
 849                         break;
 850                 }
 851                 for (base = robj->vm_bo; base; base = base->next)
 852                         if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
 853                                 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
 854                                 r = -EINVAL;
 855                                 amdgpu_bo_unreserve(robj);
 856                                 goto out;
 857                         }
 858
 859
 860                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 861                                                         AMDGPU_GEM_DOMAIN_GTT |
 862                                                         AMDGPU_GEM_DOMAIN_CPU);
 863                 robj->allowed_domains = robj->preferred_domains;
 864                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 865                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 866
 867                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 868                         amdgpu_vm_bo_invalidate(adev, robj, true);
 869
 870                 amdgpu_bo_unreserve(robj);
 871                 break;
 872         default:
 873                 amdgpu_bo_unreserve(robj);
 874                 r = -EINVAL;
 875         }
 876
 877 out:
 878         drm_gem_object_put(gobj);
 879         return r;
 880 }
 881
 882 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 883                                   int width,
 884                                   int cpp,
 885                                   bool tiled)
 886 {
 887         int aligned = width;
 888         int pitch_mask = 0;
 889
 890         switch (cpp) {
 891         case 1:
 892                 pitch_mask = 255;
 893                 break;
 894         case 2:
 895                 pitch_mask = 127;
 896                 break;
 897         case 3:
 898         case 4:
 899                 pitch_mask = 63;
 900                 break;
 901         }
 902
 903         aligned += pitch_mask;
 904         aligned &= ~pitch_mask;
 905         return aligned * cpp;
 906 }
 907
 908 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 909                             struct drm_device *dev,
 910                             struct drm_mode_create_dumb *args)
 911 {
 912         struct amdgpu_device *adev = drm_to_adev(dev);
 913         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 914         struct drm_gem_object *gobj;
 915         uint32_t handle;
 916         u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 917                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 918                     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 919         u32 domain;
 920         int r;
 921
 922         /*
 923          * The buffer returned from this function should be cleared, but
 924          * it can only be done if the ring is enabled or we'll fail to
 925          * create the buffer.
 926          */
 927         if (adev->mman.buffer_funcs_enabled)
 928                 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
 929
 930         args->pitch = amdgpu_gem_align_pitch(adev, args->width,
 931                                              DIV_ROUND_UP(args->bpp, 8), 0);
 932         args->size = (u64)args->pitch * args->height;
 933         args->size = ALIGN(args->size, PAGE_SIZE);
 934         domain = amdgpu_bo_get_preferred_domain(adev,
 935                                 amdgpu_display_supported_domains(adev, flags));
 936         r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
 937                                      ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 938         if (r)
 939                 return -ENOMEM;
 940
 941         r = drm_gem_handle_create(file_priv, gobj, &handle);
 942         /* drop reference from allocate - handle holds it now */
 943         drm_gem_object_put(gobj);
 944         if (r) {
 945                 return r;
 946         }
 947         args->handle = handle;
 948         return 0;
 949 }
 950
 951 #if defined(CONFIG_DEBUG_FS)
 952 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
 953 {
 954         struct amdgpu_device *adev = m->private;
 955         struct drm_device *dev = adev_to_drm(adev);
 956         struct drm_file *file;
 957         int r;
 958
 959         r = mutex_lock_interruptible(&dev->filelist_mutex);
 960         if (r)
 961                 return r;
 962
 963         list_for_each_entry(file, &dev->filelist, lhead) {
 964                 struct task_struct *task;
 965                 struct drm_gem_object *gobj;
 966                 int id;
 967
 968                 /*
 969                  * Although we have a valid reference on file->pid, that does
 970                  * not guarantee that the task_struct who called get_pid() is
 971                  * still alive (e.g. get_pid(current) => fork() => exit()).
 972                  * Therefore, we need to protect this ->comm access using RCU.
 973                  */
 974                 rcu_read_lock();
 975                 task = pid_task(file->pid, PIDTYPE_TGID);
 976                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 977                            task ? task->comm : "<unknown>");
 978                 rcu_read_unlock();
 979
 980                 spin_lock(&file->table_lock);
 981                 idr_for_each_entry(&file->object_idr, gobj, id) {
 982                         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 983
 984                         amdgpu_bo_print_info(id, bo, m);
 985                 }
 986                 spin_unlock(&file->table_lock);
 987         }
 988
 989         mutex_unlock(&dev->filelist_mutex);
 990         return 0;
 991 }
 992
 993 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
 994
 995 #endif
 996
 997 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
 998 {
 999 #if defined(CONFIG_DEBUG_FS)
1000         struct drm_minor *minor = adev_to_drm(adev)->primary;
1001         struct dentry *root = minor->debugfs_root;
1002
1003         debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1004                             &amdgpu_debugfs_gem_info_fops);
1005 #endif
1006 }