1 // SPDX-License-Identifier: GPL-2.0
3 * Intel INT0002 "Virtual GPIO" driver
7 * Loosely based on android x86 kernel code which is:
9 * Copyright (c) 2014, Intel Corporation.
13 * Some peripherals on Bay Trail and Cherry Trail platforms signal a Power
14 * Management Event (PME) to the Power Management Controller (PMC) to wakeup
15 * the system. When this happens software needs to clear the PME bus 0 status
16 * bit in the GPE0a_STS register to avoid an IRQ storm on IRQ 9.
18 * This is modelled in ACPI through the INT0002 ACPI device, which is
19 * called a "Virtual GPIO controller" in ACPI because it defines the event
20 * handler to call when the PME triggers through _AEI and _L02 / _E02
21 * methods as would be done for a real GPIO interrupt in ACPI. Note this
22 * is a hack to define an AML event handler for the PME while using existing
23 * ACPI mechanisms, this is not a real GPIO at all.
25 * This driver will bind to the INT0002 device, and register as a GPIO
26 * controller, letting gpiolib-acpi.c call the _L02 handler as it would
27 * for a real GPIO controller.
30 #include <linux/acpi.h>
31 #include <linux/bitmap.h>
32 #include <linux/gpio/driver.h>
33 #include <linux/interrupt.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39 #include <linux/suspend.h>
41 #include <asm/cpu_device_id.h>
42 #include <asm/intel-family.h>
44 #define DRV_NAME "INT0002 Virtual GPIO"
46 /* For some reason the virtual GPIO pin tied to the GPE is numbered pin 2 */
47 #define GPE0A_PME_B0_VIRT_GPIO_PIN 2
49 #define GPE0A_PME_B0_STS_BIT BIT(13)
50 #define GPE0A_PME_B0_EN_BIT BIT(13)
51 #define GPE0A_STS_PORT 0x420
52 #define GPE0A_EN_PORT 0x428
55 * As this is not a real GPIO at all, but just a hack to model an event in
56 * ACPI the get / set functions are dummy functions.
59 static int int0002_gpio_get(struct gpio_chip *chip, unsigned int offset)
64 static void int0002_gpio_set(struct gpio_chip *chip, unsigned int offset,
69 static int int0002_gpio_direction_output(struct gpio_chip *chip,
70 unsigned int offset, int value)
75 static void int0002_irq_ack(struct irq_data *data)
77 outl(GPE0A_PME_B0_STS_BIT, GPE0A_STS_PORT);
80 static void int0002_irq_unmask(struct irq_data *data)
84 gpe_en_reg = inl(GPE0A_EN_PORT);
85 gpe_en_reg |= GPE0A_PME_B0_EN_BIT;
86 outl(gpe_en_reg, GPE0A_EN_PORT);
89 static void int0002_irq_mask(struct irq_data *data)
93 gpe_en_reg = inl(GPE0A_EN_PORT);
94 gpe_en_reg &= ~GPE0A_PME_B0_EN_BIT;
95 outl(gpe_en_reg, GPE0A_EN_PORT);
98 static int int0002_irq_set_wake(struct irq_data *data, unsigned int on)
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
101 struct platform_device *pdev = to_platform_device(chip->parent);
102 int irq = platform_get_irq(pdev, 0);
104 /* Propagate to parent irq */
106 enable_irq_wake(irq);
108 disable_irq_wake(irq);
113 static irqreturn_t int0002_irq(int irq, void *data)
115 struct gpio_chip *chip = data;
118 gpe_sts_reg = inl(GPE0A_STS_PORT);
119 if (!(gpe_sts_reg & GPE0A_PME_B0_STS_BIT))
122 generic_handle_irq(irq_find_mapping(chip->irq.domain,
123 GPE0A_PME_B0_VIRT_GPIO_PIN));
125 pm_wakeup_hard_event(chip->parent);
130 static struct irq_chip int0002_byt_irqchip = {
132 .irq_ack = int0002_irq_ack,
133 .irq_mask = int0002_irq_mask,
134 .irq_unmask = int0002_irq_unmask,
135 .irq_set_wake = int0002_irq_set_wake,
138 static struct irq_chip int0002_cht_irqchip = {
140 .irq_ack = int0002_irq_ack,
141 .irq_mask = int0002_irq_mask,
142 .irq_unmask = int0002_irq_unmask,
144 * No set_wake, on CHT the IRQ is typically shared with the ACPI SCI
145 * and we don't want to mess with the ACPI SCI irq settings.
147 .flags = IRQCHIP_SKIP_SET_WAKE,
150 static const struct x86_cpu_id int0002_cpu_ids[] = {
151 INTEL_CPU_FAM6(ATOM_SILVERMONT, int0002_byt_irqchip), /* Valleyview, Bay Trail */
152 INTEL_CPU_FAM6(ATOM_AIRMONT, int0002_cht_irqchip), /* Braswell, Cherry Trail */
156 static void int0002_init_irq_valid_mask(struct gpio_chip *chip,
157 unsigned long *valid_mask,
160 bitmap_clear(valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);
163 static int int0002_probe(struct platform_device *pdev)
165 struct device *dev = &pdev->dev;
166 const struct x86_cpu_id *cpu_id;
167 struct irq_chip *irq_chip;
168 struct gpio_chip *chip;
171 /* Menlow has a different INT0002 device? <sigh> */
172 cpu_id = x86_match_cpu(int0002_cpu_ids);
176 irq = platform_get_irq(pdev, 0);
180 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
184 chip->label = DRV_NAME;
186 chip->owner = THIS_MODULE;
187 chip->get = int0002_gpio_get;
188 chip->set = int0002_gpio_set;
189 chip->direction_input = int0002_gpio_get;
190 chip->direction_output = int0002_gpio_direction_output;
192 chip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1;
193 chip->irq.init_valid_mask = int0002_init_irq_valid_mask;
195 ret = devm_gpiochip_add_data(&pdev->dev, chip, NULL);
197 dev_err(dev, "Error adding gpio chip: %d\n", ret);
202 * We manually request the irq here instead of passing a flow-handler
203 * to gpiochip_set_chained_irqchip, because the irq is shared.
205 ret = devm_request_irq(dev, irq, int0002_irq,
206 IRQF_SHARED, "INT0002", chip);
208 dev_err(dev, "Error requesting IRQ %d: %d\n", irq, ret);
212 irq_chip = (struct irq_chip *)cpu_id->driver_data;
214 ret = gpiochip_irqchip_add(chip, irq_chip, 0, handle_edge_irq,
217 dev_err(dev, "Error adding irqchip: %d\n", ret);
221 gpiochip_set_chained_irqchip(chip, irq_chip, irq, NULL);
223 device_init_wakeup(dev, true);
227 static int int0002_remove(struct platform_device *pdev)
229 device_init_wakeup(&pdev->dev, false);
233 static const struct acpi_device_id int0002_acpi_ids[] = {
237 MODULE_DEVICE_TABLE(acpi, int0002_acpi_ids);
239 static struct platform_driver int0002_driver = {
242 .acpi_match_table = int0002_acpi_ids,
244 .probe = int0002_probe,
245 .remove = int0002_remove,
248 module_platform_driver(int0002_driver);
251 MODULE_DESCRIPTION("Intel INT0002 Virtual GPIO driver");
252 MODULE_LICENSE("GPL v2");