drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "amdgpu_atombios.h"
  44
  45 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  46 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  47 static int gmc_v7_0_wait_for_idle(void *handle);
  48
  49 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  50 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  52
  53 static const u32 golden_settings_iceland_a11[] =
  54 {
  55         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  59 };
  60
  61 static const u32 iceland_mgcg_cgcg_init[] =
  62 {
  63         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  64 };
  65
  66 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  67 {
  68         switch (adev->asic_type) {
  69         case CHIP_TOPAZ:
  70                 amdgpu_device_program_register_sequence(adev,
  71                                                         iceland_mgcg_cgcg_init,
  72                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
  73                 amdgpu_device_program_register_sequence(adev,
  74                                                         golden_settings_iceland_a11,
  75                                                         ARRAY_SIZE(golden_settings_iceland_a11));
  76                 break;
  77         default:
  78                 break;
  79         }
  80 }
  81
  82 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  83 {
  84         u32 blackout;
  85
  86         gmc_v7_0_wait_for_idle((void *)adev);
  87
  88         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  89         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  90                 /* Block CPU access */
  91                 WREG32(mmBIF_FB_EN, 0);
  92                 /* blackout the MC */
  93                 blackout = REG_SET_FIELD(blackout,
  94                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  95                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  96         }
  97         /* wait for the MC to settle */
  98         udelay(100);
  99 }
 100
 101 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 102 {
 103         u32 tmp;
 104
 105         /* unblackout the MC */
 106         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 107         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 108         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 109         /* allow CPU access */
 110         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 111         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 112         WREG32(mmBIF_FB_EN, tmp);
 113 }
 114
 115 /**
 116  * gmc_v7_0_init_microcode - load ucode images from disk
 117  *
 118  * @adev: amdgpu_device pointer
 119  *
 120  * Use the firmware interface to load the ucode images into
 121  * the driver (not loaded into hw).
 122  * Returns 0 on success, error on failure.
 123  */
 124 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 125 {
 126         const char *chip_name;
 127         char fw_name[30];
 128         int err;
 129
 130         DRM_DEBUG("\n");
 131
 132         switch (adev->asic_type) {
 133         case CHIP_BONAIRE:
 134                 chip_name = "bonaire";
 135                 break;
 136         case CHIP_HAWAII:
 137                 chip_name = "hawaii";
 138                 break;
 139         case CHIP_TOPAZ:
 140                 chip_name = "topaz";
 141                 break;
 142         case CHIP_KAVERI:
 143         case CHIP_KABINI:
 144         case CHIP_MULLINS:
 145                 return 0;
 146         default: BUG();
 147         }
 148
 149         if (adev->asic_type == CHIP_TOPAZ)
 150                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 151         else
 152                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 153
 154         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 155         if (err)
 156                 goto out;
 157         err = amdgpu_ucode_validate(adev->mc.fw);
 158
 159 out:
 160         if (err) {
 161                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 162                 release_firmware(adev->mc.fw);
 163                 adev->mc.fw = NULL;
 164         }
 165         return err;
 166 }
 167
 168 /**
 169  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 170  *
 171  * @adev: amdgpu_device pointer
 172  *
 173  * Load the GDDR MC ucode into the hw (CIK).
 174  * Returns 0 on success, error on failure.
 175  */
 176 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 177 {
 178         const struct mc_firmware_header_v1_0 *hdr;
 179         const __le32 *fw_data = NULL;
 180         const __le32 *io_mc_regs = NULL;
 181         u32 running;
 182         int i, ucode_size, regs_size;
 183
 184         if (!adev->mc.fw)
 185                 return -EINVAL;
 186
 187         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 188         amdgpu_ucode_print_mc_hdr(&hdr->header);
 189
 190         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 191         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 192         io_mc_regs = (const __le32 *)
 193                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 194         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 195         fw_data = (const __le32 *)
 196                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 197
 198         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 199
 200         if (running == 0) {
 201                 /* reset the engine and set to writable */
 202                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 203                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 204
 205                 /* load mc io regs */
 206                 for (i = 0; i < regs_size; i++) {
 207                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 208                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 209                 }
 210                 /* load the MC ucode */
 211                 for (i = 0; i < ucode_size; i++)
 212                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 213
 214                 /* put the engine back into the active state */
 215                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 216                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 217                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 218
 219                 /* wait for training to complete */
 220                 for (i = 0; i < adev->usec_timeout; i++) {
 221                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 222                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 223                                 break;
 224                         udelay(1);
 225                 }
 226                 for (i = 0; i < adev->usec_timeout; i++) {
 227                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 228                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 229                                 break;
 230                         udelay(1);
 231                 }
 232         }
 233
 234         return 0;
 235 }
 236
 237 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 238                                        struct amdgpu_mc *mc)
 239 {
 240         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 241         base <<= 24;
 242
 243         amdgpu_device_vram_location(adev, &adev->mc, base);
 244         amdgpu_device_gart_location(adev, mc);
 245 }
 246
 247 /**
 248  * gmc_v7_0_mc_program - program the GPU memory controller
 249  *
 250  * @adev: amdgpu_device pointer
 251  *
 252  * Set the location of vram, gart, and AGP in the GPU's
 253  * physical address space (CIK).
 254  */
 255 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 256 {
 257         u32 tmp;
 258         int i, j;
 259
 260         /* Initialize HDP */
 261         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 262                 WREG32((0xb05 + j), 0x00000000);
 263                 WREG32((0xb06 + j), 0x00000000);
 264                 WREG32((0xb07 + j), 0x00000000);
 265                 WREG32((0xb08 + j), 0x00000000);
 266                 WREG32((0xb09 + j), 0x00000000);
 267         }
 268         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 269
 270         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 271                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 272         }
 273         if (adev->mode_info.num_crtc) {
 274                 /* Lockout access through VGA aperture*/
 275                 tmp = RREG32(mmVGA_HDP_CONTROL);
 276                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 277                 WREG32(mmVGA_HDP_CONTROL, tmp);
 278
 279                 /* disable VGA render */
 280                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 281                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 282                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 283         }
 284         /* Update configuration */
 285         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 286                adev->mc.vram_start >> 12);
 287         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 288                adev->mc.vram_end >> 12);
 289         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 290                adev->vram_scratch.gpu_addr >> 12);
 291         WREG32(mmMC_VM_AGP_BASE, 0);
 292         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 293         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 294         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 295                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 296         }
 297
 298         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 299
 300         tmp = RREG32(mmHDP_MISC_CNTL);
 301         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 302         WREG32(mmHDP_MISC_CNTL, tmp);
 303
 304         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 305         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 306 }
 307
 308 /**
 309  * gmc_v7_0_mc_init - initialize the memory controller driver params
 310  *
 311  * @adev: amdgpu_device pointer
 312  *
 313  * Look up the amount of vram, vram width, and decide how to place
 314  * vram and gart within the GPU's physical address space (CIK).
 315  * Returns 0 for success.
 316  */
 317 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 318 {
 319         int r;
 320
 321         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 322         if (!adev->mc.vram_width) {
 323                 u32 tmp;
 324                 int chansize, numchan;
 325
 326                 /* Get VRAM informations */
 327                 tmp = RREG32(mmMC_ARB_RAMCFG);
 328                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 329                         chansize = 64;
 330                 } else {
 331                         chansize = 32;
 332                 }
 333                 tmp = RREG32(mmMC_SHARED_CHMAP);
 334                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 335                 case 0:
 336                 default:
 337                         numchan = 1;
 338                         break;
 339                 case 1:
 340                         numchan = 2;
 341                         break;
 342                 case 2:
 343                         numchan = 4;
 344                         break;
 345                 case 3:
 346                         numchan = 8;
 347                         break;
 348                 case 4:
 349                         numchan = 3;
 350                         break;
 351                 case 5:
 352                         numchan = 6;
 353                         break;
 354                 case 6:
 355                         numchan = 10;
 356                         break;
 357                 case 7:
 358                         numchan = 12;
 359                         break;
 360                 case 8:
 361                         numchan = 16;
 362                         break;
 363                 }
 364                 adev->mc.vram_width = numchan * chansize;
 365         }
 366         /* size in MB on si */
 367         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 368         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 369
 370         if (!(adev->flags & AMD_IS_APU)) {
 371                 r = amdgpu_device_resize_fb_bar(adev);
 372                 if (r)
 373                         return r;
 374         }
 375         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 376         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 377
 378 #ifdef CONFIG_X86_64
 379         if (adev->flags & AMD_IS_APU) {
 380                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 381                 adev->mc.aper_size = adev->mc.real_vram_size;
 382         }
 383 #endif
 384
 385         /* In case the PCI BAR is larger than the actual amount of vram */
 386         adev->mc.visible_vram_size = adev->mc.aper_size;
 387         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 388                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 389
 390         /* set the gart size */
 391         if (amdgpu_gart_size == -1) {
 392                 switch (adev->asic_type) {
 393                 case CHIP_TOPAZ:     /* no MM engines */
 394                 default:
 395                         adev->mc.gart_size = 256ULL << 20;
 396                         break;
 397 #ifdef CONFIG_DRM_AMDGPU_CIK
 398                 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
 399                 case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
 400                 case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
 401                 case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
 402                 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
 403                         adev->mc.gart_size = 1024ULL << 20;
 404                         break;
 405 #endif
 406                 }
 407         } else {
 408                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 409         }
 410
 411         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 412
 413         return 0;
 414 }
 415
 416 /*
 417  * GART
 418  * VMID 0 is the physical GPU addresses as used by the kernel.
 419  * VMIDs 1-15 are used for userspace clients and are handled
 420  * by the amdgpu vm/hsa code.
 421  */
 422
 423 /**
 424  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 425  *
 426  * @adev: amdgpu_device pointer
 427  * @vmid: vm instance to flush
 428  *
 429  * Flush the TLB for the requested page table (CIK).
 430  */
 431 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 432                                         uint32_t vmid)
 433 {
 434         /* flush hdp cache */
 435         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 436
 437         /* bits 0-15 are the VM contexts0-15 */
 438         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 439 }
 440
 441 /**
 442  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 443  *
 444  * @adev: amdgpu_device pointer
 445  * @cpu_pt_addr: cpu address of the page table
 446  * @gpu_page_idx: entry in the page table to update
 447  * @addr: dst addr to write into pte/pde
 448  * @flags: access flags
 449  *
 450  * Update the page tables using the CPU.
 451  */
 452 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 453                                      void *cpu_pt_addr,
 454                                      uint32_t gpu_page_idx,
 455                                      uint64_t addr,
 456                                      uint64_t flags)
 457 {
 458         void __iomem *ptr = (void *)cpu_pt_addr;
 459         uint64_t value;
 460
 461         value = addr & 0xFFFFFFFFFFFFF000ULL;
 462         value |= flags;
 463         writeq(value, ptr + (gpu_page_idx * 8));
 464
 465         return 0;
 466 }
 467
 468 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 469                                           uint32_t flags)
 470 {
 471         uint64_t pte_flag = 0;
 472
 473         if (flags & AMDGPU_VM_PAGE_READABLE)
 474                 pte_flag |= AMDGPU_PTE_READABLE;
 475         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 476                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 477         if (flags & AMDGPU_VM_PAGE_PRT)
 478                 pte_flag |= AMDGPU_PTE_PRT;
 479
 480         return pte_flag;
 481 }
 482
 483 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
 484                                 uint64_t *addr, uint64_t *flags)
 485 {
 486         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 487 }
 488
 489 /**
 490  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 491  *
 492  * @adev: amdgpu_device pointer
 493  * @value: true redirects VM faults to the default page
 494  */
 495 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 496                                               bool value)
 497 {
 498         u32 tmp;
 499
 500         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 501         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 502                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 503         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 504                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 505         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 506                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 507         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 508                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 509         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 510                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 511         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 512                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 513         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 514 }
 515
 516 /**
 517  * gmc_v7_0_set_prt - set PRT VM fault
 518  *
 519  * @adev: amdgpu_device pointer
 520  * @enable: enable/disable VM fault handling for PRT
 521  */
 522 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 523 {
 524         uint32_t tmp;
 525
 526         if (enable && !adev->mc.prt_warning) {
 527                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 528                 adev->mc.prt_warning = true;
 529         }
 530
 531         tmp = RREG32(mmVM_PRT_CNTL);
 532         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 533                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 534         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 535                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 536         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 537                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 538         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 539                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 540         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 541                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 542         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 543                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 544         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 545                             MASK_PDE0_FAULT, enable);
 546         WREG32(mmVM_PRT_CNTL, tmp);
 547
 548         if (enable) {
 549                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 550                 uint32_t high = adev->vm_manager.max_pfn;
 551
 552                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 553                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 554                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 555                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 556                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 557                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 558                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 559                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 560         } else {
 561                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 562                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 563                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 564                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 565                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 566                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 567                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 568                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 569         }
 570 }
 571
 572 /**
 573  * gmc_v7_0_gart_enable - gart enable
 574  *
 575  * @adev: amdgpu_device pointer
 576  *
 577  * This sets up the TLBs, programs the page tables for VMID0,
 578  * sets up the hw for VMIDs 1-15 which are allocated on
 579  * demand, and sets up the global locations for the LDS, GDS,
 580  * and GPUVM for FSA64 clients (CIK).
 581  * Returns 0 for success, errors for failure.
 582  */
 583 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 584 {
 585         int r, i;
 586         u32 tmp, field;
 587
 588         if (adev->gart.robj == NULL) {
 589                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 590                 return -EINVAL;
 591         }
 592         r = amdgpu_gart_table_vram_pin(adev);
 593         if (r)
 594                 return r;
 595         /* Setup TLB control */
 596         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 597         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 598         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 599         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 600         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 601         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 602         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 603         /* Setup L2 cache */
 604         tmp = RREG32(mmVM_L2_CNTL);
 605         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 606         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 607         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 608         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 609         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 610         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 611         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 612         WREG32(mmVM_L2_CNTL, tmp);
 613         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 614         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 615         WREG32(mmVM_L2_CNTL2, tmp);
 616
 617         field = adev->vm_manager.fragment_size;
 618         tmp = RREG32(mmVM_L2_CNTL3);
 619         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 620         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 621         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 622         WREG32(mmVM_L2_CNTL3, tmp);
 623         /* setup context0 */
 624         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 625         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 626         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 627         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 628                         (u32)(adev->dummy_page.addr >> 12));
 629         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 630         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 631         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 632         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 633         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 634         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 635
 636         WREG32(0x575, 0);
 637         WREG32(0x576, 0);
 638         WREG32(0x577, 0);
 639
 640         /* empty context1-15 */
 641         /* FIXME start with 4G, once using 2 level pt switch to full
 642          * vm size space
 643          */
 644         /* set vm size, must be a multiple of 4 */
 645         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 646         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 647         for (i = 1; i < 16; i++) {
 648                 if (i < 8)
 649                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 650                                adev->gart.table_addr >> 12);
 651                 else
 652                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 653                                adev->gart.table_addr >> 12);
 654         }
 655
 656         /* enable context1-15 */
 657         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 658                (u32)(adev->dummy_page.addr >> 12));
 659         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 660         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 661         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 662         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 663         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 664                             adev->vm_manager.block_size - 9);
 665         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 666         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 667                 gmc_v7_0_set_fault_enable_default(adev, false);
 668         else
 669                 gmc_v7_0_set_fault_enable_default(adev, true);
 670
 671         if (adev->asic_type == CHIP_KAVERI) {
 672                 tmp = RREG32(mmCHUB_CONTROL);
 673                 tmp &= ~BYPASS_VM;
 674                 WREG32(mmCHUB_CONTROL, tmp);
 675         }
 676
 677         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 678         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 679                  (unsigned)(adev->mc.gart_size >> 20),
 680                  (unsigned long long)adev->gart.table_addr);
 681         adev->gart.ready = true;
 682         return 0;
 683 }
 684
 685 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 686 {
 687         int r;
 688
 689         if (adev->gart.robj) {
 690                 WARN(1, "R600 PCIE GART already initialized\n");
 691                 return 0;
 692         }
 693         /* Initialize common gart structure */
 694         r = amdgpu_gart_init(adev);
 695         if (r)
 696                 return r;
 697         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 698         adev->gart.gart_pte_flags = 0;
 699         return amdgpu_gart_table_vram_alloc(adev);
 700 }
 701
 702 /**
 703  * gmc_v7_0_gart_disable - gart disable
 704  *
 705  * @adev: amdgpu_device pointer
 706  *
 707  * This disables all VM page table (CIK).
 708  */
 709 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 710 {
 711         u32 tmp;
 712
 713         /* Disable all tables */
 714         WREG32(mmVM_CONTEXT0_CNTL, 0);
 715         WREG32(mmVM_CONTEXT1_CNTL, 0);
 716         /* Setup TLB control */
 717         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 718         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 719         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 720         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 721         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 722         /* Setup L2 cache */
 723         tmp = RREG32(mmVM_L2_CNTL);
 724         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 725         WREG32(mmVM_L2_CNTL, tmp);
 726         WREG32(mmVM_L2_CNTL2, 0);
 727         amdgpu_gart_table_vram_unpin(adev);
 728 }
 729
 730 /**
 731  * gmc_v7_0_gart_fini - vm fini callback
 732  *
 733  * @adev: amdgpu_device pointer
 734  *
 735  * Tears down the driver GART/VM setup (CIK).
 736  */
 737 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 738 {
 739         amdgpu_gart_table_vram_free(adev);
 740         amdgpu_gart_fini(adev);
 741 }
 742
 743 /**
 744  * gmc_v7_0_vm_decode_fault - print human readable fault info
 745  *
 746  * @adev: amdgpu_device pointer
 747  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 748  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 749  *
 750  * Print human readable fault information (CIK).
 751  */
 752 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 753                                      u32 status, u32 addr, u32 mc_client)
 754 {
 755         u32 mc_id;
 756         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 757         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 758                                         PROTECTIONS);
 759         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 760                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 761
 762         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 763                               MEMORY_CLIENT_ID);
 764
 765         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 766                protections, vmid, addr,
 767                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 768                              MEMORY_CLIENT_RW) ?
 769                "write" : "read", block, mc_client, mc_id);
 770 }
 771
 772
 773 static const u32 mc_cg_registers[] = {
 774         mmMC_HUB_MISC_HUB_CG,
 775         mmMC_HUB_MISC_SIP_CG,
 776         mmMC_HUB_MISC_VM_CG,
 777         mmMC_XPB_CLK_GAT,
 778         mmATC_MISC_CG,
 779         mmMC_CITF_MISC_WR_CG,
 780         mmMC_CITF_MISC_RD_CG,
 781         mmMC_CITF_MISC_VM_CG,
 782         mmVM_L2_CG,
 783 };
 784
 785 static const u32 mc_cg_ls_en[] = {
 786         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 787         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 788         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 789         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 790         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 791         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 792         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 793         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 794         VM_L2_CG__MEM_LS_ENABLE_MASK,
 795 };
 796
 797 static const u32 mc_cg_en[] = {
 798         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 799         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 800         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 801         MC_XPB_CLK_GAT__ENABLE_MASK,
 802         ATC_MISC_CG__ENABLE_MASK,
 803         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 804         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 805         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 806         VM_L2_CG__ENABLE_MASK,
 807 };
 808
 809 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 810                                   bool enable)
 811 {
 812         int i;
 813         u32 orig, data;
 814
 815         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 816                 orig = data = RREG32(mc_cg_registers[i]);
 817                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 818                         data |= mc_cg_ls_en[i];
 819                 else
 820                         data &= ~mc_cg_ls_en[i];
 821                 if (data != orig)
 822                         WREG32(mc_cg_registers[i], data);
 823         }
 824 }
 825
 826 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 827                                     bool enable)
 828 {
 829         int i;
 830         u32 orig, data;
 831
 832         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 833                 orig = data = RREG32(mc_cg_registers[i]);
 834                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 835                         data |= mc_cg_en[i];
 836                 else
 837                         data &= ~mc_cg_en[i];
 838                 if (data != orig)
 839                         WREG32(mc_cg_registers[i], data);
 840         }
 841 }
 842
 843 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 844                                      bool enable)
 845 {
 846         u32 orig, data;
 847
 848         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 849
 850         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 851                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 852                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 853                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 854                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 855         } else {
 856                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 857                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 858                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 859                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 860         }
 861
 862         if (orig != data)
 863                 WREG32_PCIE(ixPCIE_CNTL2, data);
 864 }
 865
 866 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 867                                      bool enable)
 868 {
 869         u32 orig, data;
 870
 871         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 872
 873         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 874                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 875         else
 876                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 877
 878         if (orig != data)
 879                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 880 }
 881
 882 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 883                                    bool enable)
 884 {
 885         u32 orig, data;
 886
 887         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 888
 889         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 890                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 891         else
 892                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 893
 894         if (orig != data)
 895                 WREG32(mmHDP_MEM_POWER_LS, data);
 896 }
 897
 898 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 899 {
 900         switch (mc_seq_vram_type) {
 901         case MC_SEQ_MISC0__MT__GDDR1:
 902                 return AMDGPU_VRAM_TYPE_GDDR1;
 903         case MC_SEQ_MISC0__MT__DDR2:
 904                 return AMDGPU_VRAM_TYPE_DDR2;
 905         case MC_SEQ_MISC0__MT__GDDR3:
 906                 return AMDGPU_VRAM_TYPE_GDDR3;
 907         case MC_SEQ_MISC0__MT__GDDR4:
 908                 return AMDGPU_VRAM_TYPE_GDDR4;
 909         case MC_SEQ_MISC0__MT__GDDR5:
 910                 return AMDGPU_VRAM_TYPE_GDDR5;
 911         case MC_SEQ_MISC0__MT__HBM:
 912                 return AMDGPU_VRAM_TYPE_HBM;
 913         case MC_SEQ_MISC0__MT__DDR3:
 914                 return AMDGPU_VRAM_TYPE_DDR3;
 915         default:
 916                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 917         }
 918 }
 919
 920 static int gmc_v7_0_early_init(void *handle)
 921 {
 922         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 923
 924         gmc_v7_0_set_gart_funcs(adev);
 925         gmc_v7_0_set_irq_funcs(adev);
 926
 927         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 928         adev->mc.shared_aperture_end =
 929                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 930         adev->mc.private_aperture_start =
 931                 adev->mc.shared_aperture_end + 1;
 932         adev->mc.private_aperture_end =
 933                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 934
 935         return 0;
 936 }
 937
 938 static int gmc_v7_0_late_init(void *handle)
 939 {
 940         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 941
 942         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 943                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 944         else
 945                 return 0;
 946 }
 947
 948 static int gmc_v7_0_sw_init(void *handle)
 949 {
 950         int r;
 951         int dma_bits;
 952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 953
 954         if (adev->flags & AMD_IS_APU) {
 955                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 956         } else {
 957                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 958                 tmp &= MC_SEQ_MISC0__MT__MASK;
 959                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 960         }
 961
 962         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 963         if (r)
 964                 return r;
 965
 966         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 967         if (r)
 968                 return r;
 969
 970         /* Adjust VM size here.
 971          * Currently set to 4GB ((1 << 20) 4k pages).
 972          * Max GPUVM size for cayman and SI is 40 bits.
 973          */
 974         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 975
 976         /* Set the internal MC address mask
 977          * This is the max address of the GPU's
 978          * internal address space.
 979          */
 980         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 981
 982         adev->mc.stolen_size = 256 * 1024;
 983
 984         /* set DMA mask + need_dma32 flags.
 985          * PCIE - can handle 40-bits.
 986          * IGP - can handle 40-bits
 987          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 988          */
 989         adev->need_dma32 = false;
 990         dma_bits = adev->need_dma32 ? 32 : 40;
 991         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 992         if (r) {
 993                 adev->need_dma32 = true;
 994                 dma_bits = 32;
 995                 pr_warn("amdgpu: No suitable DMA available\n");
 996         }
 997         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 998         if (r) {
 999                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1000                 pr_warn("amdgpu: No coherent DMA available\n");
1001         }
1002
1003         r = gmc_v7_0_init_microcode(adev);
1004         if (r) {
1005                 DRM_ERROR("Failed to load mc firmware!\n");
1006                 return r;
1007         }
1008
1009         r = gmc_v7_0_mc_init(adev);
1010         if (r)
1011                 return r;
1012
1013         /* Memory manager */
1014         r = amdgpu_bo_init(adev);
1015         if (r)
1016                 return r;
1017
1018         r = gmc_v7_0_gart_init(adev);
1019         if (r)
1020                 return r;
1021
1022         /*
1023          * number of VMs
1024          * VMID 0 is reserved for System
1025          * amdgpu graphics/compute will use VMIDs 1-7
1026          * amdkfd will use VMIDs 8-15
1027          */
1028         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1029         amdgpu_vm_manager_init(adev);
1030
1031         /* base offset of vram pages */
1032         if (adev->flags & AMD_IS_APU) {
1033                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1034
1035                 tmp <<= 22;
1036                 adev->vm_manager.vram_base_offset = tmp;
1037         } else {
1038                 adev->vm_manager.vram_base_offset = 0;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int gmc_v7_0_sw_fini(void *handle)
1045 {
1046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047
1048         amdgpu_gem_force_release(adev);
1049         amdgpu_vm_manager_fini(adev);
1050         gmc_v7_0_gart_fini(adev);
1051         amdgpu_bo_fini(adev);
1052         release_firmware(adev->mc.fw);
1053         adev->mc.fw = NULL;
1054
1055         return 0;
1056 }
1057
1058 static int gmc_v7_0_hw_init(void *handle)
1059 {
1060         int r;
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         gmc_v7_0_init_golden_registers(adev);
1064
1065         gmc_v7_0_mc_program(adev);
1066
1067         if (!(adev->flags & AMD_IS_APU)) {
1068                 r = gmc_v7_0_mc_load_microcode(adev);
1069                 if (r) {
1070                         DRM_ERROR("Failed to load MC firmware!\n");
1071                         return r;
1072                 }
1073         }
1074
1075         r = gmc_v7_0_gart_enable(adev);
1076         if (r)
1077                 return r;
1078
1079         return r;
1080 }
1081
1082 static int gmc_v7_0_hw_fini(void *handle)
1083 {
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1087         gmc_v7_0_gart_disable(adev);
1088
1089         return 0;
1090 }
1091
1092 static int gmc_v7_0_suspend(void *handle)
1093 {
1094         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096         gmc_v7_0_hw_fini(adev);
1097
1098         return 0;
1099 }
1100
1101 static int gmc_v7_0_resume(void *handle)
1102 {
1103         int r;
1104         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1105
1106         r = gmc_v7_0_hw_init(adev);
1107         if (r)
1108                 return r;
1109
1110         amdgpu_vmid_reset_all(adev);
1111
1112         return 0;
1113 }
1114
1115 static bool gmc_v7_0_is_idle(void *handle)
1116 {
1117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118         u32 tmp = RREG32(mmSRBM_STATUS);
1119
1120         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1121                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1122                 return false;
1123
1124         return true;
1125 }
1126
1127 static int gmc_v7_0_wait_for_idle(void *handle)
1128 {
1129         unsigned i;
1130         u32 tmp;
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133         for (i = 0; i < adev->usec_timeout; i++) {
1134                 /* read MC_STATUS */
1135                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1136                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1137                                                SRBM_STATUS__MCC_BUSY_MASK |
1138                                                SRBM_STATUS__MCD_BUSY_MASK |
1139                                                SRBM_STATUS__VMC_BUSY_MASK);
1140                 if (!tmp)
1141                         return 0;
1142                 udelay(1);
1143         }
1144         return -ETIMEDOUT;
1145
1146 }
1147
1148 static int gmc_v7_0_soft_reset(void *handle)
1149 {
1150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151         u32 srbm_soft_reset = 0;
1152         u32 tmp = RREG32(mmSRBM_STATUS);
1153
1154         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1155                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1156                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1157
1158         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1159                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1160                 if (!(adev->flags & AMD_IS_APU))
1161                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1162                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1163         }
1164
1165         if (srbm_soft_reset) {
1166                 gmc_v7_0_mc_stop(adev);
1167                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1168                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1169                 }
1170
1171
1172                 tmp = RREG32(mmSRBM_SOFT_RESET);
1173                 tmp |= srbm_soft_reset;
1174                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1175                 WREG32(mmSRBM_SOFT_RESET, tmp);
1176                 tmp = RREG32(mmSRBM_SOFT_RESET);
1177
1178                 udelay(50);
1179
1180                 tmp &= ~srbm_soft_reset;
1181                 WREG32(mmSRBM_SOFT_RESET, tmp);
1182                 tmp = RREG32(mmSRBM_SOFT_RESET);
1183
1184                 /* Wait a little for things to settle down */
1185                 udelay(50);
1186
1187                 gmc_v7_0_mc_resume(adev);
1188                 udelay(50);
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1195                                              struct amdgpu_irq_src *src,
1196                                              unsigned type,
1197                                              enum amdgpu_interrupt_state state)
1198 {
1199         u32 tmp;
1200         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1201                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1202                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1203                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1204                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1205                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1206
1207         switch (state) {
1208         case AMDGPU_IRQ_STATE_DISABLE:
1209                 /* system context */
1210                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1211                 tmp &= ~bits;
1212                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1213                 /* VMs */
1214                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1215                 tmp &= ~bits;
1216                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1217                 break;
1218         case AMDGPU_IRQ_STATE_ENABLE:
1219                 /* system context */
1220                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1221                 tmp |= bits;
1222                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1223                 /* VMs */
1224                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1225                 tmp |= bits;
1226                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1227                 break;
1228         default:
1229                 break;
1230         }
1231
1232         return 0;
1233 }
1234
1235 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1236                                       struct amdgpu_irq_src *source,
1237                                       struct amdgpu_iv_entry *entry)
1238 {
1239         u32 addr, status, mc_client;
1240
1241         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1242         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1243         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1244         /* reset addr and status */
1245         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1246
1247         if (!addr && !status)
1248                 return 0;
1249
1250         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1251                 gmc_v7_0_set_fault_enable_default(adev, false);
1252
1253         if (printk_ratelimit()) {
1254                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1255                         entry->src_id, entry->src_data[0]);
1256                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1257                         addr);
1258                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1259                         status);
1260                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int gmc_v7_0_set_clockgating_state(void *handle,
1267                                           enum amd_clockgating_state state)
1268 {
1269         bool gate = false;
1270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272         if (state == AMD_CG_STATE_GATE)
1273                 gate = true;
1274
1275         if (!(adev->flags & AMD_IS_APU)) {
1276                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1277                 gmc_v7_0_enable_mc_ls(adev, gate);
1278         }
1279         gmc_v7_0_enable_bif_mgls(adev, gate);
1280         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1281         gmc_v7_0_enable_hdp_ls(adev, gate);
1282
1283         return 0;
1284 }
1285
1286 static int gmc_v7_0_set_powergating_state(void *handle,
1287                                           enum amd_powergating_state state)
1288 {
1289         return 0;
1290 }
1291
1292 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1293         .name = "gmc_v7_0",
1294         .early_init = gmc_v7_0_early_init,
1295         .late_init = gmc_v7_0_late_init,
1296         .sw_init = gmc_v7_0_sw_init,
1297         .sw_fini = gmc_v7_0_sw_fini,
1298         .hw_init = gmc_v7_0_hw_init,
1299         .hw_fini = gmc_v7_0_hw_fini,
1300         .suspend = gmc_v7_0_suspend,
1301         .resume = gmc_v7_0_resume,
1302         .is_idle = gmc_v7_0_is_idle,
1303         .wait_for_idle = gmc_v7_0_wait_for_idle,
1304         .soft_reset = gmc_v7_0_soft_reset,
1305         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1306         .set_powergating_state = gmc_v7_0_set_powergating_state,
1307 };
1308
1309 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1310         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1311         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1312         .set_prt = gmc_v7_0_set_prt,
1313         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1314         .get_vm_pde = gmc_v7_0_get_vm_pde
1315 };
1316
1317 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1318         .set = gmc_v7_0_vm_fault_interrupt_state,
1319         .process = gmc_v7_0_process_interrupt,
1320 };
1321
1322 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1323 {
1324         if (adev->gart.gart_funcs == NULL)
1325                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1326 }
1327
1328 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1329 {
1330         adev->mc.vm_fault.num_types = 1;
1331         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1332 }
1333
1334 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1335 {
1336         .type = AMD_IP_BLOCK_TYPE_GMC,
1337         .major = 7,
1338         .minor = 0,
1339         .rev = 0,
1340         .funcs = &gmc_v7_0_ip_funcs,
1341 };
1342
1343 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1344 {
1345         .type = AMD_IP_BLOCK_TYPE_GMC,
1346         .major = 7,
1347         .minor = 4,
1348         .rev = 0,
1349         .funcs = &gmc_v7_0_ip_funcs,
1350 };