drivers/staging/rts5208/spi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Realtek PCI-Express card reader
   4  *
   5  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   6  *
   7  * Author:
   8  *   Wei WANG ([email protected])
   9  *   Micky Ching ([email protected])
  10  */
  11
  12 #include <linux/blkdev.h>
  13 #include <linux/kthread.h>
  14 #include <linux/sched.h>
  15
  16 #include "rtsx.h"
  17 #include "spi.h"
  18
  19 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
  20 {
  21         struct spi_info *spi = &chip->spi;
  22
  23         spi->err_code = err_code;
  24 }
  25
  26 static int spi_init(struct rtsx_chip *chip)
  27 {
  28         int retval;
  29
  30         retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
  31                                      CS_POLARITY_LOW | DTO_MSB_FIRST
  32                                      | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
  33         if (retval)
  34                 return retval;
  35         retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
  36                                      SAMPLE_DELAY_HALF);
  37         if (retval)
  38                 return retval;
  39
  40         return STATUS_SUCCESS;
  41 }
  42
  43 static int spi_set_init_para(struct rtsx_chip *chip)
  44 {
  45         struct spi_info *spi = &chip->spi;
  46         int retval;
  47
  48         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
  49                                      (u8)(spi->clk_div >> 8));
  50         if (retval)
  51                 return retval;
  52         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
  53                                      (u8)(spi->clk_div));
  54         if (retval)
  55                 return retval;
  56
  57         retval = switch_clock(chip, spi->spi_clock);
  58         if (retval != STATUS_SUCCESS)
  59                 return STATUS_FAIL;
  60
  61         retval = select_card(chip, SPI_CARD);
  62         if (retval != STATUS_SUCCESS)
  63                 return STATUS_FAIL;
  64
  65         retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
  66                                      SPI_CLK_EN);
  67         if (retval)
  68                 return retval;
  69         retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
  70                                      SPI_OUTPUT_EN);
  71         if (retval)
  72                 return retval;
  73
  74         wait_timeout(10);
  75
  76         retval = spi_init(chip);
  77         if (retval != STATUS_SUCCESS)
  78                 return STATUS_FAIL;
  79
  80         return STATUS_SUCCESS;
  81 }
  82
  83 static int sf_polling_status(struct rtsx_chip *chip, int msec)
  84 {
  85         int retval;
  86
  87         rtsx_init_cmd(chip);
  88
  89         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
  90         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
  91                      SPI_TRANSFER0_START | SPI_POLLING_MODE0);
  92         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
  93                      SPI_TRANSFER0_END);
  94
  95         retval = rtsx_send_cmd(chip, 0, msec);
  96         if (retval < 0) {
  97                 rtsx_clear_spi_error(chip);
  98                 spi_set_err_code(chip, SPI_BUSY_ERR);
  99                 return STATUS_FAIL;
 100         }
 101
 102         return STATUS_SUCCESS;
 103 }
 104
 105 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
 106 {
 107         struct spi_info *spi = &chip->spi;
 108         int retval;
 109
 110         if (!spi->write_en)
 111                 return STATUS_SUCCESS;
 112
 113         rtsx_init_cmd(chip);
 114
 115         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 116         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 117                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 118         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 119                      SPI_TRANSFER0_START | SPI_C_MODE0);
 120         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 121                      SPI_TRANSFER0_END);
 122
 123         retval = rtsx_send_cmd(chip, 0, 100);
 124         if (retval < 0) {
 125                 rtsx_clear_spi_error(chip);
 126                 spi_set_err_code(chip, SPI_HW_ERR);
 127                 return STATUS_FAIL;
 128         }
 129
 130         return STATUS_SUCCESS;
 131 }
 132
 133 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
 134 {
 135         struct spi_info *spi = &chip->spi;
 136         int retval;
 137
 138         if (!spi->write_en)
 139                 return STATUS_SUCCESS;
 140
 141         rtsx_init_cmd(chip);
 142
 143         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 144         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 145                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 146         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 147                      SPI_TRANSFER0_START | SPI_C_MODE0);
 148         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 149                      SPI_TRANSFER0_END);
 150
 151         retval = rtsx_send_cmd(chip, 0, 100);
 152         if (retval < 0) {
 153                 rtsx_clear_spi_error(chip);
 154                 spi_set_err_code(chip, SPI_HW_ERR);
 155                 return STATUS_FAIL;
 156         }
 157
 158         return STATUS_SUCCESS;
 159 }
 160
 161 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
 162                        u16 len)
 163 {
 164         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 165         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 166                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 167         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
 168         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
 169         if (addr_mode) {
 170                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 171                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 172                              (u8)(addr >> 8));
 173                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 174                              (u8)(addr >> 16));
 175                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 176                              SPI_TRANSFER0_START | SPI_CADO_MODE0);
 177         } else {
 178                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 179                              SPI_TRANSFER0_START | SPI_CDO_MODE0);
 180         }
 181         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 182                      SPI_TRANSFER0_END);
 183 }
 184
 185 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
 186 {
 187         int retval;
 188
 189         rtsx_init_cmd(chip);
 190
 191         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 192         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 193                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 194         if (addr_mode) {
 195                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 196                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 197                              (u8)(addr >> 8));
 198                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 199                              (u8)(addr >> 16));
 200                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 201                              SPI_TRANSFER0_START | SPI_CA_MODE0);
 202         } else {
 203                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 204                              SPI_TRANSFER0_START | SPI_C_MODE0);
 205         }
 206         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 207                      SPI_TRANSFER0_END);
 208
 209         retval = rtsx_send_cmd(chip, 0, 100);
 210         if (retval < 0) {
 211                 rtsx_clear_spi_error(chip);
 212                 spi_set_err_code(chip, SPI_HW_ERR);
 213                 return STATUS_FAIL;
 214         }
 215
 216         return STATUS_SUCCESS;
 217 }
 218
 219 static int spi_init_eeprom(struct rtsx_chip *chip)
 220 {
 221         int retval;
 222         int clk;
 223
 224         if (chip->asic_code)
 225                 clk = 30;
 226         else
 227                 clk = CLK_30;
 228
 229         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
 230         if (retval)
 231                 return retval;
 232         retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
 233         if (retval)
 234                 return retval;
 235
 236         retval = switch_clock(chip, clk);
 237         if (retval != STATUS_SUCCESS)
 238                 return STATUS_FAIL;
 239
 240         retval = select_card(chip, SPI_CARD);
 241         if (retval != STATUS_SUCCESS)
 242                 return STATUS_FAIL;
 243
 244         retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
 245                                      SPI_CLK_EN);
 246         if (retval)
 247                 return retval;
 248         retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
 249                                      SPI_OUTPUT_EN);
 250         if (retval)
 251                 return retval;
 252
 253         wait_timeout(10);
 254
 255         retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
 256                                      CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
 257         if (retval)
 258                 return retval;
 259         retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
 260                                      SAMPLE_DELAY_HALF);
 261         if (retval)
 262                 return retval;
 263
 264         return STATUS_SUCCESS;
 265 }
 266
 267 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
 268 {
 269         int retval;
 270
 271         rtsx_init_cmd(chip);
 272
 273         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
 274         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
 275         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 276                      SPI_TRANSFER0_START | SPI_CA_MODE0);
 277         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 278                      SPI_TRANSFER0_END);
 279
 280         retval = rtsx_send_cmd(chip, 0, 100);
 281         if (retval < 0)
 282                 return STATUS_FAIL;
 283
 284         return STATUS_SUCCESS;
 285 }
 286
 287 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
 288 {
 289         int retval;
 290
 291         retval = spi_init_eeprom(chip);
 292         if (retval != STATUS_SUCCESS)
 293                 return STATUS_FAIL;
 294
 295         retval = spi_eeprom_program_enable(chip);
 296         if (retval != STATUS_SUCCESS)
 297                 return STATUS_FAIL;
 298
 299         rtsx_init_cmd(chip);
 300
 301         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 302         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 303         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
 304         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
 305         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 306                      SPI_TRANSFER0_START | SPI_CA_MODE0);
 307         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 308                      SPI_TRANSFER0_END);
 309
 310         retval = rtsx_send_cmd(chip, 0, 100);
 311         if (retval < 0)
 312                 return STATUS_FAIL;
 313
 314         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 315         if (retval)
 316                 return retval;
 317
 318         return STATUS_SUCCESS;
 319 }
 320
 321 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
 322 {
 323         int retval;
 324
 325         retval = spi_init_eeprom(chip);
 326         if (retval != STATUS_SUCCESS)
 327                 return STATUS_FAIL;
 328
 329         retval = spi_eeprom_program_enable(chip);
 330         if (retval != STATUS_SUCCESS)
 331                 return STATUS_FAIL;
 332
 333         rtsx_init_cmd(chip);
 334
 335         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 336         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 337         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
 338         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 339         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 340         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 341         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 342                      SPI_TRANSFER0_START | SPI_CA_MODE0);
 343         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 344                      SPI_TRANSFER0_END);
 345
 346         retval = rtsx_send_cmd(chip, 0, 100);
 347         if (retval < 0)
 348                 return STATUS_FAIL;
 349
 350         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 351         if (retval)
 352                 return retval;
 353
 354         return STATUS_SUCCESS;
 355 }
 356
 357 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
 358 {
 359         int retval;
 360         u8 data;
 361
 362         retval = spi_init_eeprom(chip);
 363         if (retval != STATUS_SUCCESS)
 364                 return STATUS_FAIL;
 365
 366         rtsx_init_cmd(chip);
 367
 368         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 369         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 370         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
 371         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 372         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 373         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 374         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
 375         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 376                      SPI_TRANSFER0_START | SPI_CADI_MODE0);
 377         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 378                      SPI_TRANSFER0_END);
 379
 380         retval = rtsx_send_cmd(chip, 0, 100);
 381         if (retval < 0)
 382                 return STATUS_FAIL;
 383
 384         wait_timeout(5);
 385         retval = rtsx_read_register(chip, SPI_DATA, &data);
 386         if (retval)
 387                 return retval;
 388
 389         if (val)
 390                 *val = data;
 391
 392         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 393         if (retval)
 394                 return retval;
 395
 396         return STATUS_SUCCESS;
 397 }
 398
 399 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
 400 {
 401         int retval;
 402
 403         retval = spi_init_eeprom(chip);
 404         if (retval != STATUS_SUCCESS)
 405                 return STATUS_FAIL;
 406
 407         retval = spi_eeprom_program_enable(chip);
 408         if (retval != STATUS_SUCCESS)
 409                 return STATUS_FAIL;
 410
 411         rtsx_init_cmd(chip);
 412
 413         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 414         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 415         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
 416         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
 417         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
 418         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
 419         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
 420         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 421                      SPI_TRANSFER0_START | SPI_CA_MODE0);
 422         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 423                      SPI_TRANSFER0_END);
 424
 425         retval = rtsx_send_cmd(chip, 0, 100);
 426         if (retval < 0)
 427                 return STATUS_FAIL;
 428
 429         retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
 430         if (retval)
 431                 return retval;
 432
 433         return STATUS_SUCCESS;
 434 }
 435
 436 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 437 {
 438         struct spi_info *spi = &chip->spi;
 439
 440         dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__,
 441                 spi->err_code);
 442         rtsx_stor_set_xfer_buf(&spi->err_code,
 443                                min_t(int, scsi_bufflen(srb), 1), srb);
 444         scsi_set_resid(srb, scsi_bufflen(srb) - 1);
 445
 446         return STATUS_SUCCESS;
 447 }
 448
 449 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 450 {
 451         struct spi_info *spi = &chip->spi;
 452
 453         spi_set_err_code(chip, SPI_NO_ERR);
 454
 455         if (chip->asic_code)
 456                 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
 457         else
 458                 spi->spi_clock = srb->cmnd[3];
 459
 460         spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
 461         spi->write_en = srb->cmnd[6];
 462
 463         dev_dbg(rtsx_dev(chip), "%s: ", __func__);
 464         dev_dbg(rtsx_dev(chip), "spi_clock = %d, ", spi->spi_clock);
 465         dev_dbg(rtsx_dev(chip), "clk_div = %d, ", spi->clk_div);
 466         dev_dbg(rtsx_dev(chip), "write_en = %d\n", spi->write_en);
 467
 468         return STATUS_SUCCESS;
 469 }
 470
 471 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 472 {
 473         int retval;
 474         u16 len;
 475         u8 *buf;
 476
 477         spi_set_err_code(chip, SPI_NO_ERR);
 478
 479         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 480         if (len > 512) {
 481                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 482                 return STATUS_FAIL;
 483         }
 484
 485         retval = spi_set_init_para(chip);
 486         if (retval != STATUS_SUCCESS) {
 487                 spi_set_err_code(chip, SPI_HW_ERR);
 488                 return STATUS_FAIL;
 489         }
 490
 491         rtsx_init_cmd(chip);
 492
 493         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 494                      PINGPONG_BUFFER);
 495
 496         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
 497         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
 498         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
 499         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
 500         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 501                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 502         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
 503         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
 504
 505         if (len == 0) {
 506                 if (srb->cmnd[9]) {
 507                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 508                                      0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
 509                 } else {
 510                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 511                                      0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
 512                 }
 513         } else {
 514                 if (srb->cmnd[9]) {
 515                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 516                                      SPI_TRANSFER0_START | SPI_CADI_MODE0);
 517                 } else {
 518                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 519                                      SPI_TRANSFER0_START | SPI_CDI_MODE0);
 520                 }
 521         }
 522
 523         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 524                      SPI_TRANSFER0_END);
 525
 526         retval = rtsx_send_cmd(chip, 0, 100);
 527         if (retval < 0) {
 528                 rtsx_clear_spi_error(chip);
 529                 spi_set_err_code(chip, SPI_HW_ERR);
 530                 return STATUS_FAIL;
 531         }
 532
 533         if (len) {
 534                 buf = kmalloc(len, GFP_KERNEL);
 535                 if (!buf)
 536                         return STATUS_ERROR;
 537
 538                 retval = rtsx_read_ppbuf(chip, buf, len);
 539                 if (retval != STATUS_SUCCESS) {
 540                         spi_set_err_code(chip, SPI_READ_ERR);
 541                         kfree(buf);
 542                         return STATUS_FAIL;
 543                 }
 544
 545                 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
 546                 scsi_set_resid(srb, 0);
 547
 548                 kfree(buf);
 549         }
 550
 551         return STATUS_SUCCESS;
 552 }
 553
 554 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 555 {
 556         int retval;
 557         unsigned int index = 0, offset = 0;
 558         u8 ins, slow_read;
 559         u32 addr;
 560         u16 len;
 561         u8 *buf;
 562
 563         spi_set_err_code(chip, SPI_NO_ERR);
 564
 565         ins = srb->cmnd[3];
 566         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 567                                         << 8) | srb->cmnd[6];
 568         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 569         slow_read = srb->cmnd[9];
 570
 571         retval = spi_set_init_para(chip);
 572         if (retval != STATUS_SUCCESS) {
 573                 spi_set_err_code(chip, SPI_HW_ERR);
 574                 return STATUS_FAIL;
 575         }
 576
 577         buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 578         if (!buf)
 579                 return STATUS_ERROR;
 580
 581         while (len) {
 582                 u16 pagelen = SF_PAGE_LEN - (u8)addr;
 583
 584                 if (pagelen > len)
 585                         pagelen = len;
 586
 587                 rtsx_init_cmd(chip);
 588
 589                 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
 590
 591                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 592
 593                 if (slow_read) {
 594                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
 595                                      (u8)addr);
 596                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 597                                      (u8)(addr >> 8));
 598                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 599                                      (u8)(addr >> 16));
 600                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 601                                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 602                 } else {
 603                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 604                                      (u8)addr);
 605                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 606                                      (u8)(addr >> 8));
 607                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
 608                                      (u8)(addr >> 16));
 609                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 610                                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
 611                 }
 612
 613                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
 614                              (u8)(pagelen >> 8));
 615                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
 616                              (u8)pagelen);
 617
 618                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 619                              SPI_TRANSFER0_START | SPI_CADI_MODE0);
 620                 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
 621                              SPI_TRANSFER0_END, SPI_TRANSFER0_END);
 622
 623                 rtsx_send_cmd_no_wait(chip);
 624
 625                 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 626                                             DMA_FROM_DEVICE, 10000);
 627                 if (retval < 0) {
 628                         kfree(buf);
 629                         rtsx_clear_spi_error(chip);
 630                         spi_set_err_code(chip, SPI_HW_ERR);
 631                         return STATUS_FAIL;
 632                 }
 633
 634                 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
 635                                           TO_XFER_BUF);
 636
 637                 addr += pagelen;
 638                 len -= pagelen;
 639         }
 640
 641         scsi_set_resid(srb, 0);
 642         kfree(buf);
 643
 644         return STATUS_SUCCESS;
 645 }
 646
 647 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 648 {
 649         int retval;
 650         u8 ins, program_mode;
 651         u32 addr;
 652         u16 len;
 653         u8 *buf;
 654         unsigned int index = 0, offset = 0;
 655
 656         spi_set_err_code(chip, SPI_NO_ERR);
 657
 658         ins = srb->cmnd[3];
 659         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 660                                         << 8) | srb->cmnd[6];
 661         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 662         program_mode = srb->cmnd[9];
 663
 664         retval = spi_set_init_para(chip);
 665         if (retval != STATUS_SUCCESS) {
 666                 spi_set_err_code(chip, SPI_HW_ERR);
 667                 return STATUS_FAIL;
 668         }
 669
 670         if (program_mode == BYTE_PROGRAM) {
 671                 buf = kmalloc(4, GFP_KERNEL);
 672                 if (!buf)
 673                         return STATUS_ERROR;
 674
 675                 while (len) {
 676                         retval = sf_enable_write(chip, SPI_WREN);
 677                         if (retval != STATUS_SUCCESS) {
 678                                 kfree(buf);
 679                                 return STATUS_FAIL;
 680                         }
 681
 682                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 683                                                   FROM_XFER_BUF);
 684
 685                         rtsx_init_cmd(chip);
 686
 687                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 688                                      0x01, PINGPONG_BUFFER);
 689                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 690                                      buf[0]);
 691                         sf_program(chip, ins, 1, addr, 1);
 692
 693                         retval = rtsx_send_cmd(chip, 0, 100);
 694                         if (retval < 0) {
 695                                 kfree(buf);
 696                                 rtsx_clear_spi_error(chip);
 697                                 spi_set_err_code(chip, SPI_HW_ERR);
 698                                 return STATUS_FAIL;
 699                         }
 700
 701                         retval = sf_polling_status(chip, 100);
 702                         if (retval != STATUS_SUCCESS) {
 703                                 kfree(buf);
 704                                 return STATUS_FAIL;
 705                         }
 706
 707                         addr++;
 708                         len--;
 709                 }
 710
 711                 kfree(buf);
 712
 713         } else if (program_mode == AAI_PROGRAM) {
 714                 int first_byte = 1;
 715
 716                 retval = sf_enable_write(chip, SPI_WREN);
 717                 if (retval != STATUS_SUCCESS)
 718                         return STATUS_FAIL;
 719
 720                 buf = kmalloc(4, GFP_KERNEL);
 721                 if (!buf)
 722                         return STATUS_ERROR;
 723
 724                 while (len) {
 725                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 726                                                   FROM_XFER_BUF);
 727
 728                         rtsx_init_cmd(chip);
 729
 730                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 731                                      0x01, PINGPONG_BUFFER);
 732                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 733                                      buf[0]);
 734                         if (first_byte) {
 735                                 sf_program(chip, ins, 1, addr, 1);
 736                                 first_byte = 0;
 737                         } else {
 738                                 sf_program(chip, ins, 0, 0, 1);
 739                         }
 740
 741                         retval = rtsx_send_cmd(chip, 0, 100);
 742                         if (retval < 0) {
 743                                 kfree(buf);
 744                                 rtsx_clear_spi_error(chip);
 745                                 spi_set_err_code(chip, SPI_HW_ERR);
 746                                 return STATUS_FAIL;
 747                         }
 748
 749                         retval = sf_polling_status(chip, 100);
 750                         if (retval != STATUS_SUCCESS) {
 751                                 kfree(buf);
 752                                 return STATUS_FAIL;
 753                         }
 754
 755                         len--;
 756                 }
 757
 758                 kfree(buf);
 759
 760                 retval = sf_disable_write(chip, SPI_WRDI);
 761                 if (retval != STATUS_SUCCESS)
 762                         return STATUS_FAIL;
 763
 764                 retval = sf_polling_status(chip, 100);
 765                 if (retval != STATUS_SUCCESS)
 766                         return STATUS_FAIL;
 767         } else if (program_mode == PAGE_PROGRAM) {
 768                 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 769                 if (!buf)
 770                         return STATUS_NOMEM;
 771
 772                 while (len) {
 773                         u16 pagelen = SF_PAGE_LEN - (u8)addr;
 774
 775                         if (pagelen > len)
 776                                 pagelen = len;
 777
 778                         retval = sf_enable_write(chip, SPI_WREN);
 779                         if (retval != STATUS_SUCCESS) {
 780                                 kfree(buf);
 781                                 return STATUS_FAIL;
 782                         }
 783
 784                         rtsx_init_cmd(chip);
 785
 786                         trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
 787                         sf_program(chip, ins, 1, addr, pagelen);
 788
 789                         rtsx_send_cmd_no_wait(chip);
 790
 791                         rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
 792                                                   &offset, FROM_XFER_BUF);
 793
 794                         retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 795                                                     DMA_TO_DEVICE, 100);
 796                         if (retval < 0) {
 797                                 kfree(buf);
 798                                 rtsx_clear_spi_error(chip);
 799                                 spi_set_err_code(chip, SPI_HW_ERR);
 800                                 return STATUS_FAIL;
 801                         }
 802
 803                         retval = sf_polling_status(chip, 100);
 804                         if (retval != STATUS_SUCCESS) {
 805                                 kfree(buf);
 806                                 return STATUS_FAIL;
 807                         }
 808
 809                         addr += pagelen;
 810                         len -= pagelen;
 811                 }
 812
 813                 kfree(buf);
 814         } else {
 815                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 816                 return STATUS_FAIL;
 817         }
 818
 819         return STATUS_SUCCESS;
 820 }
 821
 822 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 823 {
 824         int retval;
 825         u8 ins, erase_mode;
 826         u32 addr;
 827
 828         spi_set_err_code(chip, SPI_NO_ERR);
 829
 830         ins = srb->cmnd[3];
 831         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 832                                         << 8) | srb->cmnd[6];
 833         erase_mode = srb->cmnd[9];
 834
 835         retval = spi_set_init_para(chip);
 836         if (retval != STATUS_SUCCESS) {
 837                 spi_set_err_code(chip, SPI_HW_ERR);
 838                 return STATUS_FAIL;
 839         }
 840
 841         if (erase_mode == PAGE_ERASE) {
 842                 retval = sf_enable_write(chip, SPI_WREN);
 843                 if (retval != STATUS_SUCCESS)
 844                         return STATUS_FAIL;
 845
 846                 retval = sf_erase(chip, ins, 1, addr);
 847                 if (retval != STATUS_SUCCESS)
 848                         return STATUS_FAIL;
 849         } else if (erase_mode == CHIP_ERASE) {
 850                 retval = sf_enable_write(chip, SPI_WREN);
 851                 if (retval != STATUS_SUCCESS)
 852                         return STATUS_FAIL;
 853
 854                 retval = sf_erase(chip, ins, 0, 0);
 855                 if (retval != STATUS_SUCCESS)
 856                         return STATUS_FAIL;
 857         } else {
 858                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 859                 return STATUS_FAIL;
 860         }
 861
 862         return STATUS_SUCCESS;
 863 }
 864
 865 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 866 {
 867         int retval;
 868         u8 ins, status, ewsr;
 869
 870         ins = srb->cmnd[3];
 871         status = srb->cmnd[4];
 872         ewsr = srb->cmnd[5];
 873
 874         retval = spi_set_init_para(chip);
 875         if (retval != STATUS_SUCCESS) {
 876                 spi_set_err_code(chip, SPI_HW_ERR);
 877                 return STATUS_FAIL;
 878         }
 879
 880         retval = sf_enable_write(chip, ewsr);
 881         if (retval != STATUS_SUCCESS)
 882                 return STATUS_FAIL;
 883
 884         rtsx_init_cmd(chip);
 885
 886         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 887                      PINGPONG_BUFFER);
 888
 889         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 890         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 891                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 892         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
 893         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
 894         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
 895         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 896                      SPI_TRANSFER0_START | SPI_CDO_MODE0);
 897         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 898                      SPI_TRANSFER0_END);
 899
 900         retval = rtsx_send_cmd(chip, 0, 100);
 901         if (retval != STATUS_SUCCESS) {
 902                 rtsx_clear_spi_error(chip);
 903                 spi_set_err_code(chip, SPI_HW_ERR);
 904                 return STATUS_FAIL;
 905         }
 906
 907         return STATUS_SUCCESS;
 908 }