drivers/scsi/ufs/ufshcd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller driver Core
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <[email protected]>
   9  *      Vinayak Holikatti <[email protected]>
  10  */
  11
  12 #include <linux/async.h>
  13 #include <linux/devfreq.h>
  14 #include <linux/nls.h>
  15 #include <linux/of.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/blk-pm.h>
  18 #include <linux/blkdev.h>
  19 #include "ufshcd.h"
  20 #include "ufs_quirks.h"
  21 #include "unipro.h"
  22 #include "ufs-sysfs.h"
  23 #include "ufs_bsg.h"
  24 #include "ufshcd-crypto.h"
  25 #include <asm/unaligned.h>
  26 #include <linux/blkdev.h>
  27
  28 #define CREATE_TRACE_POINTS
  29 #include <trace/events/ufs.h>
  30
  31 #define UFSHCD_ENABLE_INTRS     (UTP_TRANSFER_REQ_COMPL |\
  32                                  UTP_TASK_REQ_COMPL |\
  33                                  UFSHCD_ERROR_MASK)
  34 /* UIC command timeout, unit: ms */
  35 #define UIC_CMD_TIMEOUT 500
  36
  37 /* NOP OUT retries waiting for NOP IN response */
  38 #define NOP_OUT_RETRIES    10
  39 /* Timeout after 50 msecs if NOP OUT hangs without response */
  40 #define NOP_OUT_TIMEOUT    50 /* msecs */
  41
  42 /* Query request retries */
  43 #define QUERY_REQ_RETRIES 3
  44 /* Query request timeout */
  45 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  46
  47 /* Task management command timeout */
  48 #define TM_CMD_TIMEOUT  100 /* msecs */
  49
  50 /* maximum number of retries for a general UIC command  */
  51 #define UFS_UIC_COMMAND_RETRIES 3
  52
  53 /* maximum number of link-startup retries */
  54 #define DME_LINKSTARTUP_RETRIES 3
  55
  56 /* Maximum retries for Hibern8 enter */
  57 #define UIC_HIBERN8_ENTER_RETRIES 3
  58
  59 /* maximum number of reset retries before giving up */
  60 #define MAX_HOST_RESET_RETRIES 5
  61
  62 /* Expose the flag value from utp_upiu_query.value */
  63 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  64
  65 /* Interrupt aggregation default timeout, unit: 40us */
  66 #define INT_AGGR_DEF_TO 0x02
  67
  68 /* default delay of autosuspend: 2000 ms */
  69 #define RPM_AUTOSUSPEND_DELAY_MS 2000
  70
  71 /* Default delay of RPM device flush delayed work */
  72 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
  73
  74 /* Default value of wait time before gating device ref clock */
  75 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
  76
  77 /* Polling time to wait for fDeviceInit */
  78 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
  79
  80 #define ufshcd_toggle_vreg(_dev, _vreg, _on)                            \
  81         ({                                                              \
  82                 int _ret;                                               \
  83                 if (_on)                                                \
  84                         _ret = ufshcd_enable_vreg(_dev, _vreg);         \
  85                 else                                                    \
  86                         _ret = ufshcd_disable_vreg(_dev, _vreg);        \
  87                 _ret;                                                   \
  88         })
  89
  90 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
  91         size_t __len = (len);                                            \
  92         print_hex_dump(KERN_ERR, prefix_str,                             \
  93                        __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
  94                        16, 4, buf, __len, false);                        \
  95 } while (0)
  96
  97 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
  98                      const char *prefix)
  99 {
 100         u32 *regs;
 101         size_t pos;
 102
 103         if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
 104                 return -EINVAL;
 105
 106         regs = kzalloc(len, GFP_ATOMIC);
 107         if (!regs)
 108                 return -ENOMEM;
 109
 110         for (pos = 0; pos < len; pos += 4)
 111                 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
 112
 113         ufshcd_hex_dump(prefix, regs, len);
 114         kfree(regs);
 115
 116         return 0;
 117 }
 118 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
 119
 120 enum {
 121         UFSHCD_MAX_CHANNEL      = 0,
 122         UFSHCD_MAX_ID           = 1,
 123         UFSHCD_CMD_PER_LUN      = 32,
 124         UFSHCD_CAN_QUEUE        = 32,
 125 };
 126
 127 /* UFSHCD states */
 128 enum {
 129         UFSHCD_STATE_RESET,
 130         UFSHCD_STATE_ERROR,
 131         UFSHCD_STATE_OPERATIONAL,
 132         UFSHCD_STATE_EH_SCHEDULED_FATAL,
 133         UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
 134 };
 135
 136 /* UFSHCD error handling flags */
 137 enum {
 138         UFSHCD_EH_IN_PROGRESS = (1 << 0),
 139 };
 140
 141 /* UFSHCD UIC layer error flags */
 142 enum {
 143         UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
 144         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
 145         UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
 146         UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
 147         UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
 148         UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
 149         UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
 150 };
 151
 152 #define ufshcd_set_eh_in_progress(h) \
 153         ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
 154 #define ufshcd_eh_in_progress(h) \
 155         ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
 156 #define ufshcd_clear_eh_in_progress(h) \
 157         ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
 158
 159 struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
 160         {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 161         {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 162         {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 163         {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 164         {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 165         {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
 166 };
 167
 168 static inline enum ufs_dev_pwr_mode
 169 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
 170 {
 171         return ufs_pm_lvl_states[lvl].dev_state;
 172 }
 173
 174 static inline enum uic_link_state
 175 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
 176 {
 177         return ufs_pm_lvl_states[lvl].link_state;
 178 }
 179
 180 static inline enum ufs_pm_level
 181 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
 182                                         enum uic_link_state link_state)
 183 {
 184         enum ufs_pm_level lvl;
 185
 186         for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
 187                 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
 188                         (ufs_pm_lvl_states[lvl].link_state == link_state))
 189                         return lvl;
 190         }
 191
 192         /* if no match found, return the level 0 */
 193         return UFS_PM_LVL_0;
 194 }
 195
 196 static struct ufs_dev_fix ufs_fixups[] = {
 197         /* UFS cards deviations table */
 198         UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
 199                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 200         UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
 201                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
 202                 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
 203                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
 204         UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
 205                 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
 206         UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
 207                 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
 208         UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
 209                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 210         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
 211                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 212         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
 213                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 214         END_FIX
 215 };
 216
 217 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
 218 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
 219 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
 220 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
 221 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
 222 static void ufshcd_hba_exit(struct ufs_hba *hba);
 223 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
 224 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
 225                                  bool skip_ref_clk);
 226 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
 227 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 228 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 229 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 230 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
 231 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 232 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 233 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
 234 static irqreturn_t ufshcd_intr(int irq, void *__hba);
 235 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 236                              struct ufs_pa_layer_attr *pwr_mode);
 237 static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
 238 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
 239 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
 240 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
 241                                          struct ufs_vreg *vreg);
 242 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
 243 static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba);
 244 static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba);
 245 static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable);
 246 static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
 247 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
 248
 249 static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
 250 {
 251         return tag >= 0 && tag < hba->nutrs;
 252 }
 253
 254 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
 255 {
 256         if (!hba->is_irq_enabled) {
 257                 enable_irq(hba->irq);
 258                 hba->is_irq_enabled = true;
 259         }
 260 }
 261
 262 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
 263 {
 264         if (hba->is_irq_enabled) {
 265                 disable_irq(hba->irq);
 266                 hba->is_irq_enabled = false;
 267         }
 268 }
 269
 270 static inline void ufshcd_wb_config(struct ufs_hba *hba)
 271 {
 272         int ret;
 273
 274         if (!ufshcd_is_wb_allowed(hba))
 275                 return;
 276
 277         ret = ufshcd_wb_ctrl(hba, true);
 278         if (ret)
 279                 dev_err(hba->dev, "%s: Enable WB failed: %d\n", __func__, ret);
 280         else
 281                 dev_info(hba->dev, "%s: Write Booster Configured\n", __func__);
 282         ret = ufshcd_wb_toggle_flush_during_h8(hba, true);
 283         if (ret)
 284                 dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
 285                         __func__, ret);
 286         ufshcd_wb_toggle_flush(hba, true);
 287 }
 288
 289 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 290 {
 291         if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
 292                 scsi_unblock_requests(hba->host);
 293 }
 294
 295 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
 296 {
 297         if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
 298                 scsi_block_requests(hba->host);
 299 }
 300
 301 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 302                 const char *str)
 303 {
 304         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 305
 306         trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
 307 }
 308
 309 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 310                 const char *str)
 311 {
 312         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 313
 314         trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
 315 }
 316
 317 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 318                 const char *str)
 319 {
 320         int off = (int)tag - hba->nutrs;
 321         struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
 322
 323         trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
 324                         &descp->input_param1);
 325 }
 326
 327 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
 328                                          struct uic_command *ucmd,
 329                                          const char *str)
 330 {
 331         u32 cmd;
 332
 333         if (!trace_ufshcd_uic_command_enabled())
 334                 return;
 335
 336         if (!strcmp(str, "send"))
 337                 cmd = ucmd->command;
 338         else
 339                 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
 340
 341         trace_ufshcd_uic_command(dev_name(hba->dev), str, cmd,
 342                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
 343                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
 344                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
 345 }
 346
 347 static void ufshcd_add_command_trace(struct ufs_hba *hba,
 348                 unsigned int tag, const char *str)
 349 {
 350         sector_t lba = -1;
 351         u8 opcode = 0;
 352         u32 intr, doorbell;
 353         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 354         struct scsi_cmnd *cmd = lrbp->cmd;
 355         int transfer_len = -1;
 356
 357         if (!trace_ufshcd_command_enabled()) {
 358                 /* trace UPIU W/O tracing command */
 359                 if (cmd)
 360                         ufshcd_add_cmd_upiu_trace(hba, tag, str);
 361                 return;
 362         }
 363
 364         if (cmd) { /* data phase exists */
 365                 /* trace UPIU also */
 366                 ufshcd_add_cmd_upiu_trace(hba, tag, str);
 367                 opcode = cmd->cmnd[0];
 368                 if ((opcode == READ_10) || (opcode == WRITE_10)) {
 369                         /*
 370                          * Currently we only fully trace read(10) and write(10)
 371                          * commands
 372                          */
 373                         if (cmd->request && cmd->request->bio)
 374                                 lba = cmd->request->bio->bi_iter.bi_sector;
 375                         transfer_len = be32_to_cpu(
 376                                 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
 377                 }
 378         }
 379
 380         intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
 381         doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
 382         trace_ufshcd_command(dev_name(hba->dev), str, tag,
 383                                 doorbell, transfer_len, intr, lba, opcode);
 384 }
 385
 386 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
 387 {
 388         struct ufs_clk_info *clki;
 389         struct list_head *head = &hba->clk_list_head;
 390
 391         if (list_empty(head))
 392                 return;
 393
 394         list_for_each_entry(clki, head, list) {
 395                 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
 396                                 clki->max_freq)
 397                         dev_err(hba->dev, "clk: %s, rate: %u\n",
 398                                         clki->name, clki->curr_freq);
 399         }
 400 }
 401
 402 static void ufshcd_print_err_hist(struct ufs_hba *hba,
 403                                   struct ufs_err_reg_hist *err_hist,
 404                                   char *err_name)
 405 {
 406         int i;
 407         bool found = false;
 408
 409         for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
 410                 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
 411
 412                 if (err_hist->tstamp[p] == 0)
 413                         continue;
 414                 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
 415                         err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
 416                 found = true;
 417         }
 418
 419         if (!found)
 420                 dev_err(hba->dev, "No record of %s\n", err_name);
 421 }
 422
 423 static void ufshcd_print_host_regs(struct ufs_hba *hba)
 424 {
 425         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
 426
 427         ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
 428         ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
 429         ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
 430         ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
 431         ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
 432         ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
 433                               "auto_hibern8_err");
 434         ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
 435         ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
 436                               "link_startup_fail");
 437         ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
 438         ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
 439                               "suspend_fail");
 440         ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
 441         ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
 442         ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
 443
 444         ufshcd_vops_dbg_register_dump(hba);
 445 }
 446
 447 static
 448 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
 449 {
 450         struct ufshcd_lrb *lrbp;
 451         int prdt_length;
 452         int tag;
 453
 454         for_each_set_bit(tag, &bitmap, hba->nutrs) {
 455                 lrbp = &hba->lrb[tag];
 456
 457                 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
 458                                 tag, ktime_to_us(lrbp->issue_time_stamp));
 459                 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
 460                                 tag, ktime_to_us(lrbp->compl_time_stamp));
 461                 dev_err(hba->dev,
 462                         "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
 463                         tag, (u64)lrbp->utrd_dma_addr);
 464
 465                 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
 466                                 sizeof(struct utp_transfer_req_desc));
 467                 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
 468                         (u64)lrbp->ucd_req_dma_addr);
 469                 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
 470                                 sizeof(struct utp_upiu_req));
 471                 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
 472                         (u64)lrbp->ucd_rsp_dma_addr);
 473                 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
 474                                 sizeof(struct utp_upiu_rsp));
 475
 476                 prdt_length = le16_to_cpu(
 477                         lrbp->utr_descriptor_ptr->prd_table_length);
 478                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
 479                         prdt_length /= sizeof(struct ufshcd_sg_entry);
 480
 481                 dev_err(hba->dev,
 482                         "UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
 483                         tag, prdt_length,
 484                         (u64)lrbp->ucd_prdt_dma_addr);
 485
 486                 if (pr_prdt)
 487                         ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
 488                                 sizeof(struct ufshcd_sg_entry) * prdt_length);
 489         }
 490 }
 491
 492 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
 493 {
 494         int tag;
 495
 496         for_each_set_bit(tag, &bitmap, hba->nutmrs) {
 497                 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
 498
 499                 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
 500                 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
 501         }
 502 }
 503
 504 static void ufshcd_print_host_state(struct ufs_hba *hba)
 505 {
 506         struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
 507
 508         dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
 509         dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
 510                 hba->outstanding_reqs, hba->outstanding_tasks);
 511         dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
 512                 hba->saved_err, hba->saved_uic_err);
 513         dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
 514                 hba->curr_dev_pwr_mode, hba->uic_link_state);
 515         dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
 516                 hba->pm_op_in_progress, hba->is_sys_suspended);
 517         dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
 518                 hba->auto_bkops_enabled, hba->host->host_self_blocked);
 519         dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
 520         dev_err(hba->dev,
 521                 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
 522                 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
 523                 hba->ufs_stats.hibern8_exit_cnt);
 524         dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
 525                 ktime_to_us(hba->ufs_stats.last_intr_ts),
 526                 hba->ufs_stats.last_intr_status);
 527         dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
 528                 hba->eh_flags, hba->req_abort_count);
 529         dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
 530                 hba->ufs_version, hba->capabilities, hba->caps);
 531         dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
 532                 hba->dev_quirks);
 533         if (sdev_ufs)
 534                 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
 535                         sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
 536
 537         ufshcd_print_clk_freqs(hba);
 538 }
 539
 540 /**
 541  * ufshcd_print_pwr_info - print power params as saved in hba
 542  * power info
 543  * @hba: per-adapter instance
 544  */
 545 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
 546 {
 547         static const char * const names[] = {
 548                 "INVALID MODE",
 549                 "FAST MODE",
 550                 "SLOW_MODE",
 551                 "INVALID MODE",
 552                 "FASTAUTO_MODE",
 553                 "SLOWAUTO_MODE",
 554                 "INVALID MODE",
 555         };
 556
 557         dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
 558                  __func__,
 559                  hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
 560                  hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
 561                  names[hba->pwr_info.pwr_rx],
 562                  names[hba->pwr_info.pwr_tx],
 563                  hba->pwr_info.hs_rate);
 564 }
 565
 566 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
 567 {
 568         if (!us)
 569                 return;
 570
 571         if (us < 10)
 572                 udelay(us);
 573         else
 574                 usleep_range(us, us + tolerance);
 575 }
 576 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
 577
 578 /**
 579  * ufshcd_wait_for_register - wait for register value to change
 580  * @hba: per-adapter interface
 581  * @reg: mmio register offset
 582  * @mask: mask to apply to the read register value
 583  * @val: value to wait for
 584  * @interval_us: polling interval in microseconds
 585  * @timeout_ms: timeout in milliseconds
 586  *
 587  * Return:
 588  * -ETIMEDOUT on error, zero on success.
 589  */
 590 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
 591                                 u32 val, unsigned long interval_us,
 592                                 unsigned long timeout_ms)
 593 {
 594         int err = 0;
 595         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
 596
 597         /* ignore bits that we don't intend to wait on */
 598         val = val & mask;
 599
 600         while ((ufshcd_readl(hba, reg) & mask) != val) {
 601                 usleep_range(interval_us, interval_us + 50);
 602                 if (time_after(jiffies, timeout)) {
 603                         if ((ufshcd_readl(hba, reg) & mask) != val)
 604                                 err = -ETIMEDOUT;
 605                         break;
 606                 }
 607         }
 608
 609         return err;
 610 }
 611
 612 /**
 613  * ufshcd_get_intr_mask - Get the interrupt bit mask
 614  * @hba: Pointer to adapter instance
 615  *
 616  * Returns interrupt bit mask per version
 617  */
 618 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
 619 {
 620         u32 intr_mask = 0;
 621
 622         switch (hba->ufs_version) {
 623         case UFSHCI_VERSION_10:
 624                 intr_mask = INTERRUPT_MASK_ALL_VER_10;
 625                 break;
 626         case UFSHCI_VERSION_11:
 627         case UFSHCI_VERSION_20:
 628                 intr_mask = INTERRUPT_MASK_ALL_VER_11;
 629                 break;
 630         case UFSHCI_VERSION_21:
 631         default:
 632                 intr_mask = INTERRUPT_MASK_ALL_VER_21;
 633                 break;
 634         }
 635
 636         return intr_mask;
 637 }
 638
 639 /**
 640  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
 641  * @hba: Pointer to adapter instance
 642  *
 643  * Returns UFSHCI version supported by the controller
 644  */
 645 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
 646 {
 647         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
 648                 return ufshcd_vops_get_ufs_hci_version(hba);
 649
 650         return ufshcd_readl(hba, REG_UFS_VERSION);
 651 }
 652
 653 /**
 654  * ufshcd_is_device_present - Check if any device connected to
 655  *                            the host controller
 656  * @hba: pointer to adapter instance
 657  *
 658  * Returns true if device present, false if no device detected
 659  */
 660 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
 661 {
 662         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
 663                                                 DEVICE_PRESENT) ? true : false;
 664 }
 665
 666 /**
 667  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
 668  * @lrbp: pointer to local command reference block
 669  *
 670  * This function is used to get the OCS field from UTRD
 671  * Returns the OCS field in the UTRD
 672  */
 673 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
 674 {
 675         return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
 676 }
 677
 678 /**
 679  * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
 680  * @hba: per adapter instance
 681  * @pos: position of the bit to be cleared
 682  */
 683 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
 684 {
 685         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 686                 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 687         else
 688                 ufshcd_writel(hba, ~(1 << pos),
 689                                 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 690 }
 691
 692 /**
 693  * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
 694  * @hba: per adapter instance
 695  * @pos: position of the bit to be cleared
 696  */
 697 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
 698 {
 699         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 700                 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 701         else
 702                 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 703 }
 704
 705 /**
 706  * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
 707  * @hba: per adapter instance
 708  * @tag: position of the bit to be cleared
 709  */
 710 static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
 711 {
 712         __clear_bit(tag, &hba->outstanding_reqs);
 713 }
 714
 715 /**
 716  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
 717  * @reg: Register value of host controller status
 718  *
 719  * Returns integer, 0 on Success and positive value if failed
 720  */
 721 static inline int ufshcd_get_lists_status(u32 reg)
 722 {
 723         return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
 724 }
 725
 726 /**
 727  * ufshcd_get_uic_cmd_result - Get the UIC command result
 728  * @hba: Pointer to adapter instance
 729  *
 730  * This function gets the result of UIC command completion
 731  * Returns 0 on success, non zero value on error
 732  */
 733 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
 734 {
 735         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
 736                MASK_UIC_COMMAND_RESULT;
 737 }
 738
 739 /**
 740  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
 741  * @hba: Pointer to adapter instance
 742  *
 743  * This function gets UIC command argument3
 744  * Returns 0 on success, non zero value on error
 745  */
 746 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
 747 {
 748         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
 749 }
 750
 751 /**
 752  * ufshcd_get_req_rsp - returns the TR response transaction type
 753  * @ucd_rsp_ptr: pointer to response UPIU
 754  */
 755 static inline int
 756 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
 757 {
 758         return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
 759 }
 760
 761 /**
 762  * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
 763  * @ucd_rsp_ptr: pointer to response UPIU
 764  *
 765  * This function gets the response status and scsi_status from response UPIU
 766  * Returns the response result code.
 767  */
 768 static inline int
 769 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
 770 {
 771         return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
 772 }
 773
 774 /*
 775  * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
 776  *                              from response UPIU
 777  * @ucd_rsp_ptr: pointer to response UPIU
 778  *
 779  * Return the data segment length.
 780  */
 781 static inline unsigned int
 782 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
 783 {
 784         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 785                 MASK_RSP_UPIU_DATA_SEG_LEN;
 786 }
 787
 788 /**
 789  * ufshcd_is_exception_event - Check if the device raised an exception event
 790  * @ucd_rsp_ptr: pointer to response UPIU
 791  *
 792  * The function checks if the device raised an exception event indicated in
 793  * the Device Information field of response UPIU.
 794  *
 795  * Returns true if exception is raised, false otherwise.
 796  */
 797 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
 798 {
 799         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 800                         MASK_RSP_EXCEPTION_EVENT ? true : false;
 801 }
 802
 803 /**
 804  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
 805  * @hba: per adapter instance
 806  */
 807 static inline void
 808 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
 809 {
 810         ufshcd_writel(hba, INT_AGGR_ENABLE |
 811                       INT_AGGR_COUNTER_AND_TIMER_RESET,
 812                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 813 }
 814
 815 /**
 816  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
 817  * @hba: per adapter instance
 818  * @cnt: Interrupt aggregation counter threshold
 819  * @tmout: Interrupt aggregation timeout value
 820  */
 821 static inline void
 822 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
 823 {
 824         ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
 825                       INT_AGGR_COUNTER_THLD_VAL(cnt) |
 826                       INT_AGGR_TIMEOUT_VAL(tmout),
 827                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 828 }
 829
 830 /**
 831  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
 832  * @hba: per adapter instance
 833  */
 834 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
 835 {
 836         ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 837 }
 838
 839 /**
 840  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
 841  *                      When run-stop registers are set to 1, it indicates the
 842  *                      host controller that it can process the requests
 843  * @hba: per adapter instance
 844  */
 845 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
 846 {
 847         ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
 848                       REG_UTP_TASK_REQ_LIST_RUN_STOP);
 849         ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
 850                       REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
 851 }
 852
 853 /**
 854  * ufshcd_hba_start - Start controller initialization sequence
 855  * @hba: per adapter instance
 856  */
 857 static inline void ufshcd_hba_start(struct ufs_hba *hba)
 858 {
 859         u32 val = CONTROLLER_ENABLE;
 860
 861         if (ufshcd_crypto_enable(hba))
 862                 val |= CRYPTO_GENERAL_ENABLE;
 863
 864         ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
 865 }
 866
 867 /**
 868  * ufshcd_is_hba_active - Get controller state
 869  * @hba: per adapter instance
 870  *
 871  * Returns false if controller is active, true otherwise
 872  */
 873 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
 874 {
 875         return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
 876                 ? false : true;
 877 }
 878
 879 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
 880 {
 881         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 882         if ((hba->ufs_version == UFSHCI_VERSION_10) ||
 883             (hba->ufs_version == UFSHCI_VERSION_11))
 884                 return UFS_UNIPRO_VER_1_41;
 885         else
 886                 return UFS_UNIPRO_VER_1_6;
 887 }
 888 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
 889
 890 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
 891 {
 892         /*
 893          * If both host and device support UniPro ver1.6 or later, PA layer
 894          * parameters tuning happens during link startup itself.
 895          *
 896          * We can manually tune PA layer parameters if either host or device
 897          * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
 898          * logic simple, we will only do manual tuning if local unipro version
 899          * doesn't support ver1.6 or later.
 900          */
 901         if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
 902                 return true;
 903         else
 904                 return false;
 905 }
 906
 907 /**
 908  * ufshcd_set_clk_freq - set UFS controller clock frequencies
 909  * @hba: per adapter instance
 910  * @scale_up: If True, set max possible frequency othewise set low frequency
 911  *
 912  * Returns 0 if successful
 913  * Returns < 0 for any other errors
 914  */
 915 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
 916 {
 917         int ret = 0;
 918         struct ufs_clk_info *clki;
 919         struct list_head *head = &hba->clk_list_head;
 920
 921         if (list_empty(head))
 922                 goto out;
 923
 924         list_for_each_entry(clki, head, list) {
 925                 if (!IS_ERR_OR_NULL(clki->clk)) {
 926                         if (scale_up && clki->max_freq) {
 927                                 if (clki->curr_freq == clki->max_freq)
 928                                         continue;
 929
 930                                 ret = clk_set_rate(clki->clk, clki->max_freq);
 931                                 if (ret) {
 932                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 933                                                 __func__, clki->name,
 934                                                 clki->max_freq, ret);
 935                                         break;
 936                                 }
 937                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 938                                                 "scaled up", clki->name,
 939                                                 clki->curr_freq,
 940                                                 clki->max_freq);
 941
 942                                 clki->curr_freq = clki->max_freq;
 943
 944                         } else if (!scale_up && clki->min_freq) {
 945                                 if (clki->curr_freq == clki->min_freq)
 946                                         continue;
 947
 948                                 ret = clk_set_rate(clki->clk, clki->min_freq);
 949                                 if (ret) {
 950                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 951                                                 __func__, clki->name,
 952                                                 clki->min_freq, ret);
 953                                         break;
 954                                 }
 955                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 956                                                 "scaled down", clki->name,
 957                                                 clki->curr_freq,
 958                                                 clki->min_freq);
 959                                 clki->curr_freq = clki->min_freq;
 960                         }
 961                 }
 962                 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
 963                                 clki->name, clk_get_rate(clki->clk));
 964         }
 965
 966 out:
 967         return ret;
 968 }
 969
 970 /**
 971  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
 972  * @hba: per adapter instance
 973  * @scale_up: True if scaling up and false if scaling down
 974  *
 975  * Returns 0 if successful
 976  * Returns < 0 for any other errors
 977  */
 978 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
 979 {
 980         int ret = 0;
 981         ktime_t start = ktime_get();
 982
 983         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
 984         if (ret)
 985                 goto out;
 986
 987         ret = ufshcd_set_clk_freq(hba, scale_up);
 988         if (ret)
 989                 goto out;
 990
 991         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
 992         if (ret)
 993                 ufshcd_set_clk_freq(hba, !scale_up);
 994
 995 out:
 996         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
 997                         (scale_up ? "up" : "down"),
 998                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
 999         return ret;
1000 }
1001
1002 /**
1003  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1004  * @hba: per adapter instance
1005  * @scale_up: True if scaling up and false if scaling down
1006  *
1007  * Returns true if scaling is required, false otherwise.
1008  */
1009 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1010                                                bool scale_up)
1011 {
1012         struct ufs_clk_info *clki;
1013         struct list_head *head = &hba->clk_list_head;
1014
1015         if (list_empty(head))
1016                 return false;
1017
1018         list_for_each_entry(clki, head, list) {
1019                 if (!IS_ERR_OR_NULL(clki->clk)) {
1020                         if (scale_up && clki->max_freq) {
1021                                 if (clki->curr_freq == clki->max_freq)
1022                                         continue;
1023                                 return true;
1024                         } else if (!scale_up && clki->min_freq) {
1025                                 if (clki->curr_freq == clki->min_freq)
1026                                         continue;
1027                                 return true;
1028                         }
1029                 }
1030         }
1031
1032         return false;
1033 }
1034
1035 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1036                                         u64 wait_timeout_us)
1037 {
1038         unsigned long flags;
1039         int ret = 0;
1040         u32 tm_doorbell;
1041         u32 tr_doorbell;
1042         bool timeout = false, do_last_check = false;
1043         ktime_t start;
1044
1045         ufshcd_hold(hba, false);
1046         spin_lock_irqsave(hba->host->host_lock, flags);
1047         /*
1048          * Wait for all the outstanding tasks/transfer requests.
1049          * Verify by checking the doorbell registers are clear.
1050          */
1051         start = ktime_get();
1052         do {
1053                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1054                         ret = -EBUSY;
1055                         goto out;
1056                 }
1057
1058                 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1059                 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1060                 if (!tm_doorbell && !tr_doorbell) {
1061                         timeout = false;
1062                         break;
1063                 } else if (do_last_check) {
1064                         break;
1065                 }
1066
1067                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1068                 schedule();
1069                 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1070                     wait_timeout_us) {
1071                         timeout = true;
1072                         /*
1073                          * We might have scheduled out for long time so make
1074                          * sure to check if doorbells are cleared by this time
1075                          * or not.
1076                          */
1077                         do_last_check = true;
1078                 }
1079                 spin_lock_irqsave(hba->host->host_lock, flags);
1080         } while (tm_doorbell || tr_doorbell);
1081
1082         if (timeout) {
1083                 dev_err(hba->dev,
1084                         "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1085                         __func__, tm_doorbell, tr_doorbell);
1086                 ret = -EBUSY;
1087         }
1088 out:
1089         spin_unlock_irqrestore(hba->host->host_lock, flags);
1090         ufshcd_release(hba);
1091         return ret;
1092 }
1093
1094 /**
1095  * ufshcd_scale_gear - scale up/down UFS gear
1096  * @hba: per adapter instance
1097  * @scale_up: True for scaling up gear and false for scaling down
1098  *
1099  * Returns 0 for success,
1100  * Returns -EBUSY if scaling can't happen at this time
1101  * Returns non-zero for any other errors
1102  */
1103 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1104 {
1105         #define UFS_MIN_GEAR_TO_SCALE_DOWN      UFS_HS_G1
1106         int ret = 0;
1107         struct ufs_pa_layer_attr new_pwr_info;
1108
1109         if (scale_up) {
1110                 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1111                        sizeof(struct ufs_pa_layer_attr));
1112         } else {
1113                 memcpy(&new_pwr_info, &hba->pwr_info,
1114                        sizeof(struct ufs_pa_layer_attr));
1115
1116                 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1117                     || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1118                         /* save the current power mode */
1119                         memcpy(&hba->clk_scaling.saved_pwr_info.info,
1120                                 &hba->pwr_info,
1121                                 sizeof(struct ufs_pa_layer_attr));
1122
1123                         /* scale down gear */
1124                         new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1125                         new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1126                 }
1127         }
1128
1129         /* check if the power mode needs to be changed or not? */
1130         ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1131         if (ret)
1132                 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1133                         __func__, ret,
1134                         hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1135                         new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1136
1137         return ret;
1138 }
1139
1140 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1141 {
1142         #define DOORBELL_CLR_TOUT_US            (1000 * 1000) /* 1 sec */
1143         int ret = 0;
1144         /*
1145          * make sure that there are no outstanding requests when
1146          * clock scaling is in progress
1147          */
1148         ufshcd_scsi_block_requests(hba);
1149         down_write(&hba->clk_scaling_lock);
1150         if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1151                 ret = -EBUSY;
1152                 up_write(&hba->clk_scaling_lock);
1153                 ufshcd_scsi_unblock_requests(hba);
1154         }
1155
1156         return ret;
1157 }
1158
1159 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1160 {
1161         up_write(&hba->clk_scaling_lock);
1162         ufshcd_scsi_unblock_requests(hba);
1163 }
1164
1165 /**
1166  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1167  * @hba: per adapter instance
1168  * @scale_up: True for scaling up and false for scalin down
1169  *
1170  * Returns 0 for success,
1171  * Returns -EBUSY if scaling can't happen at this time
1172  * Returns non-zero for any other errors
1173  */
1174 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1175 {
1176         int ret = 0;
1177
1178         /* let's not get into low power until clock scaling is completed */
1179         ufshcd_hold(hba, false);
1180
1181         ret = ufshcd_clock_scaling_prepare(hba);
1182         if (ret)
1183                 goto out;
1184
1185         /* scale down the gear before scaling down clocks */
1186         if (!scale_up) {
1187                 ret = ufshcd_scale_gear(hba, false);
1188                 if (ret)
1189                         goto out_unprepare;
1190         }
1191
1192         ret = ufshcd_scale_clks(hba, scale_up);
1193         if (ret) {
1194                 if (!scale_up)
1195                         ufshcd_scale_gear(hba, true);
1196                 goto out_unprepare;
1197         }
1198
1199         /* scale up the gear after scaling up clocks */
1200         if (scale_up) {
1201                 ret = ufshcd_scale_gear(hba, true);
1202                 if (ret) {
1203                         ufshcd_scale_clks(hba, false);
1204                         goto out_unprepare;
1205                 }
1206         }
1207
1208         /* Enable Write Booster if we have scaled up else disable it */
1209         up_write(&hba->clk_scaling_lock);
1210         ufshcd_wb_ctrl(hba, scale_up);
1211         down_write(&hba->clk_scaling_lock);
1212
1213 out_unprepare:
1214         ufshcd_clock_scaling_unprepare(hba);
1215 out:
1216         ufshcd_release(hba);
1217         return ret;
1218 }
1219
1220 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1221 {
1222         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1223                                            clk_scaling.suspend_work);
1224         unsigned long irq_flags;
1225
1226         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1227         if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1228                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1229                 return;
1230         }
1231         hba->clk_scaling.is_suspended = true;
1232         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1233
1234         __ufshcd_suspend_clkscaling(hba);
1235 }
1236
1237 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1238 {
1239         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1240                                            clk_scaling.resume_work);
1241         unsigned long irq_flags;
1242
1243         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1244         if (!hba->clk_scaling.is_suspended) {
1245                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1246                 return;
1247         }
1248         hba->clk_scaling.is_suspended = false;
1249         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1250
1251         devfreq_resume_device(hba->devfreq);
1252 }
1253
1254 static int ufshcd_devfreq_target(struct device *dev,
1255                                 unsigned long *freq, u32 flags)
1256 {
1257         int ret = 0;
1258         struct ufs_hba *hba = dev_get_drvdata(dev);
1259         ktime_t start;
1260         bool scale_up, sched_clk_scaling_suspend_work = false;
1261         struct list_head *clk_list = &hba->clk_list_head;
1262         struct ufs_clk_info *clki;
1263         unsigned long irq_flags;
1264
1265         if (!ufshcd_is_clkscaling_supported(hba))
1266                 return -EINVAL;
1267
1268         clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1269         /* Override with the closest supported frequency */
1270         *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1271         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1272         if (ufshcd_eh_in_progress(hba)) {
1273                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1274                 return 0;
1275         }
1276
1277         if (!hba->clk_scaling.active_reqs)
1278                 sched_clk_scaling_suspend_work = true;
1279
1280         if (list_empty(clk_list)) {
1281                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1282                 goto out;
1283         }
1284
1285         /* Decide based on the rounded-off frequency and update */
1286         scale_up = (*freq == clki->max_freq) ? true : false;
1287         if (!scale_up)
1288                 *freq = clki->min_freq;
1289         /* Update the frequency */
1290         if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1291                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1292                 ret = 0;
1293                 goto out; /* no state change required */
1294         }
1295         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1296
1297         start = ktime_get();
1298         ret = ufshcd_devfreq_scale(hba, scale_up);
1299
1300         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1301                 (scale_up ? "up" : "down"),
1302                 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1303
1304 out:
1305         if (sched_clk_scaling_suspend_work)
1306                 queue_work(hba->clk_scaling.workq,
1307                            &hba->clk_scaling.suspend_work);
1308
1309         return ret;
1310 }
1311
1312 static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1313 {
1314         int *busy = priv;
1315
1316         WARN_ON_ONCE(reserved);
1317         (*busy)++;
1318         return false;
1319 }
1320
1321 /* Whether or not any tag is in use by a request that is in progress. */
1322 static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1323 {
1324         struct request_queue *q = hba->cmd_queue;
1325         int busy = 0;
1326
1327         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1328         return busy;
1329 }
1330
1331 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1332                 struct devfreq_dev_status *stat)
1333 {
1334         struct ufs_hba *hba = dev_get_drvdata(dev);
1335         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1336         unsigned long flags;
1337         struct list_head *clk_list = &hba->clk_list_head;
1338         struct ufs_clk_info *clki;
1339         ktime_t curr_t;
1340
1341         if (!ufshcd_is_clkscaling_supported(hba))
1342                 return -EINVAL;
1343
1344         memset(stat, 0, sizeof(*stat));
1345
1346         spin_lock_irqsave(hba->host->host_lock, flags);
1347         curr_t = ktime_get();
1348         if (!scaling->window_start_t)
1349                 goto start_window;
1350
1351         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1352         /*
1353          * If current frequency is 0, then the ondemand governor considers
1354          * there's no initial frequency set. And it always requests to set
1355          * to max. frequency.
1356          */
1357         stat->current_frequency = clki->curr_freq;
1358         if (scaling->is_busy_started)
1359                 scaling->tot_busy_t += ktime_us_delta(curr_t,
1360                                 scaling->busy_start_t);
1361
1362         stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1363         stat->busy_time = scaling->tot_busy_t;
1364 start_window:
1365         scaling->window_start_t = curr_t;
1366         scaling->tot_busy_t = 0;
1367
1368         if (hba->outstanding_reqs) {
1369                 scaling->busy_start_t = curr_t;
1370                 scaling->is_busy_started = true;
1371         } else {
1372                 scaling->busy_start_t = 0;
1373                 scaling->is_busy_started = false;
1374         }
1375         spin_unlock_irqrestore(hba->host->host_lock, flags);
1376         return 0;
1377 }
1378
1379 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1380 {
1381         struct list_head *clk_list = &hba->clk_list_head;
1382         struct ufs_clk_info *clki;
1383         struct devfreq *devfreq;
1384         int ret;
1385
1386         /* Skip devfreq if we don't have any clocks in the list */
1387         if (list_empty(clk_list))
1388                 return 0;
1389
1390         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1391         dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1392         dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1393
1394         ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1395                                          &hba->vps->ondemand_data);
1396         devfreq = devfreq_add_device(hba->dev,
1397                         &hba->vps->devfreq_profile,
1398                         DEVFREQ_GOV_SIMPLE_ONDEMAND,
1399                         &hba->vps->ondemand_data);
1400         if (IS_ERR(devfreq)) {
1401                 ret = PTR_ERR(devfreq);
1402                 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1403
1404                 dev_pm_opp_remove(hba->dev, clki->min_freq);
1405                 dev_pm_opp_remove(hba->dev, clki->max_freq);
1406                 return ret;
1407         }
1408
1409         hba->devfreq = devfreq;
1410
1411         return 0;
1412 }
1413
1414 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1415 {
1416         struct list_head *clk_list = &hba->clk_list_head;
1417         struct ufs_clk_info *clki;
1418
1419         if (!hba->devfreq)
1420                 return;
1421
1422         devfreq_remove_device(hba->devfreq);
1423         hba->devfreq = NULL;
1424
1425         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1426         dev_pm_opp_remove(hba->dev, clki->min_freq);
1427         dev_pm_opp_remove(hba->dev, clki->max_freq);
1428 }
1429
1430 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1431 {
1432         unsigned long flags;
1433
1434         devfreq_suspend_device(hba->devfreq);
1435         spin_lock_irqsave(hba->host->host_lock, flags);
1436         hba->clk_scaling.window_start_t = 0;
1437         spin_unlock_irqrestore(hba->host->host_lock, flags);
1438 }
1439
1440 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1441 {
1442         unsigned long flags;
1443         bool suspend = false;
1444
1445         if (!ufshcd_is_clkscaling_supported(hba))
1446                 return;
1447
1448         spin_lock_irqsave(hba->host->host_lock, flags);
1449         if (!hba->clk_scaling.is_suspended) {
1450                 suspend = true;
1451                 hba->clk_scaling.is_suspended = true;
1452         }
1453         spin_unlock_irqrestore(hba->host->host_lock, flags);
1454
1455         if (suspend)
1456                 __ufshcd_suspend_clkscaling(hba);
1457 }
1458
1459 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1460 {
1461         unsigned long flags;
1462         bool resume = false;
1463
1464         if (!ufshcd_is_clkscaling_supported(hba))
1465                 return;
1466
1467         spin_lock_irqsave(hba->host->host_lock, flags);
1468         if (hba->clk_scaling.is_suspended) {
1469                 resume = true;
1470                 hba->clk_scaling.is_suspended = false;
1471         }
1472         spin_unlock_irqrestore(hba->host->host_lock, flags);
1473
1474         if (resume)
1475                 devfreq_resume_device(hba->devfreq);
1476 }
1477
1478 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1479                 struct device_attribute *attr, char *buf)
1480 {
1481         struct ufs_hba *hba = dev_get_drvdata(dev);
1482
1483         return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1484 }
1485
1486 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1487                 struct device_attribute *attr, const char *buf, size_t count)
1488 {
1489         struct ufs_hba *hba = dev_get_drvdata(dev);
1490         u32 value;
1491         int err;
1492
1493         if (kstrtou32(buf, 0, &value))
1494                 return -EINVAL;
1495
1496         value = !!value;
1497         if (value == hba->clk_scaling.is_allowed)
1498                 goto out;
1499
1500         pm_runtime_get_sync(hba->dev);
1501         ufshcd_hold(hba, false);
1502
1503         cancel_work_sync(&hba->clk_scaling.suspend_work);
1504         cancel_work_sync(&hba->clk_scaling.resume_work);
1505
1506         hba->clk_scaling.is_allowed = value;
1507
1508         if (value) {
1509                 ufshcd_resume_clkscaling(hba);
1510         } else {
1511                 ufshcd_suspend_clkscaling(hba);
1512                 err = ufshcd_devfreq_scale(hba, true);
1513                 if (err)
1514                         dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1515                                         __func__, err);
1516         }
1517
1518         ufshcd_release(hba);
1519         pm_runtime_put_sync(hba->dev);
1520 out:
1521         return count;
1522 }
1523
1524 static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1525 {
1526         hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1527         hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1528         sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1529         hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1530         hba->clk_scaling.enable_attr.attr.mode = 0644;
1531         if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1532                 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1533 }
1534
1535 static void ufshcd_ungate_work(struct work_struct *work)
1536 {
1537         int ret;
1538         unsigned long flags;
1539         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1540                         clk_gating.ungate_work);
1541
1542         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1543
1544         spin_lock_irqsave(hba->host->host_lock, flags);
1545         if (hba->clk_gating.state == CLKS_ON) {
1546                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1547                 goto unblock_reqs;
1548         }
1549
1550         spin_unlock_irqrestore(hba->host->host_lock, flags);
1551         ufshcd_setup_clocks(hba, true);
1552
1553         ufshcd_enable_irq(hba);
1554
1555         /* Exit from hibern8 */
1556         if (ufshcd_can_hibern8_during_gating(hba)) {
1557                 /* Prevent gating in this path */
1558                 hba->clk_gating.is_suspended = true;
1559                 if (ufshcd_is_link_hibern8(hba)) {
1560                         ret = ufshcd_uic_hibern8_exit(hba);
1561                         if (ret)
1562                                 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1563                                         __func__, ret);
1564                         else
1565                                 ufshcd_set_link_active(hba);
1566                 }
1567                 hba->clk_gating.is_suspended = false;
1568         }
1569 unblock_reqs:
1570         ufshcd_scsi_unblock_requests(hba);
1571 }
1572
1573 /**
1574  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1575  * Also, exit from hibern8 mode and set the link as active.
1576  * @hba: per adapter instance
1577  * @async: This indicates whether caller should ungate clocks asynchronously.
1578  */
1579 int ufshcd_hold(struct ufs_hba *hba, bool async)
1580 {
1581         int rc = 0;
1582         bool flush_result;
1583         unsigned long flags;
1584
1585         if (!ufshcd_is_clkgating_allowed(hba))
1586                 goto out;
1587         spin_lock_irqsave(hba->host->host_lock, flags);
1588         hba->clk_gating.active_reqs++;
1589
1590 start:
1591         switch (hba->clk_gating.state) {
1592         case CLKS_ON:
1593                 /*
1594                  * Wait for the ungate work to complete if in progress.
1595                  * Though the clocks may be in ON state, the link could
1596                  * still be in hibner8 state if hibern8 is allowed
1597                  * during clock gating.
1598                  * Make sure we exit hibern8 state also in addition to
1599                  * clocks being ON.
1600                  */
1601                 if (ufshcd_can_hibern8_during_gating(hba) &&
1602                     ufshcd_is_link_hibern8(hba)) {
1603                         if (async) {
1604                                 rc = -EAGAIN;
1605                                 hba->clk_gating.active_reqs--;
1606                                 break;
1607                         }
1608                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1609                         flush_result = flush_work(&hba->clk_gating.ungate_work);
1610                         if (hba->clk_gating.is_suspended && !flush_result)
1611                                 goto out;
1612                         spin_lock_irqsave(hba->host->host_lock, flags);
1613                         goto start;
1614                 }
1615                 break;
1616         case REQ_CLKS_OFF:
1617                 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1618                         hba->clk_gating.state = CLKS_ON;
1619                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1620                                                 hba->clk_gating.state);
1621                         break;
1622                 }
1623                 /*
1624                  * If we are here, it means gating work is either done or
1625                  * currently running. Hence, fall through to cancel gating
1626                  * work and to enable clocks.
1627                  */
1628                 fallthrough;
1629         case CLKS_OFF:
1630                 ufshcd_scsi_block_requests(hba);
1631                 hba->clk_gating.state = REQ_CLKS_ON;
1632                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1633                                         hba->clk_gating.state);
1634                 queue_work(hba->clk_gating.clk_gating_workq,
1635                            &hba->clk_gating.ungate_work);
1636                 /*
1637                  * fall through to check if we should wait for this
1638                  * work to be done or not.
1639                  */
1640                 fallthrough;
1641         case REQ_CLKS_ON:
1642                 if (async) {
1643                         rc = -EAGAIN;
1644                         hba->clk_gating.active_reqs--;
1645                         break;
1646                 }
1647
1648                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1649                 flush_work(&hba->clk_gating.ungate_work);
1650                 /* Make sure state is CLKS_ON before returning */
1651                 spin_lock_irqsave(hba->host->host_lock, flags);
1652                 goto start;
1653         default:
1654                 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1655                                 __func__, hba->clk_gating.state);
1656                 break;
1657         }
1658         spin_unlock_irqrestore(hba->host->host_lock, flags);
1659 out:
1660         return rc;
1661 }
1662 EXPORT_SYMBOL_GPL(ufshcd_hold);
1663
1664 static void ufshcd_gate_work(struct work_struct *work)
1665 {
1666         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1667                         clk_gating.gate_work.work);
1668         unsigned long flags;
1669         int ret;
1670
1671         spin_lock_irqsave(hba->host->host_lock, flags);
1672         /*
1673          * In case you are here to cancel this work the gating state
1674          * would be marked as REQ_CLKS_ON. In this case save time by
1675          * skipping the gating work and exit after changing the clock
1676          * state to CLKS_ON.
1677          */
1678         if (hba->clk_gating.is_suspended ||
1679                 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1680                 hba->clk_gating.state = CLKS_ON;
1681                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1682                                         hba->clk_gating.state);
1683                 goto rel_lock;
1684         }
1685
1686         if (hba->clk_gating.active_reqs
1687                 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1688                 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1689                 || hba->active_uic_cmd || hba->uic_async_done)
1690                 goto rel_lock;
1691
1692         spin_unlock_irqrestore(hba->host->host_lock, flags);
1693
1694         /* put the link into hibern8 mode before turning off clocks */
1695         if (ufshcd_can_hibern8_during_gating(hba)) {
1696                 ret = ufshcd_uic_hibern8_enter(hba);
1697                 if (ret) {
1698                         hba->clk_gating.state = CLKS_ON;
1699                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1700                                         __func__, ret);
1701                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1702                                                 hba->clk_gating.state);
1703                         goto out;
1704                 }
1705                 ufshcd_set_link_hibern8(hba);
1706         }
1707
1708         ufshcd_disable_irq(hba);
1709
1710         if (!ufshcd_is_link_active(hba))
1711                 ufshcd_setup_clocks(hba, false);
1712         else
1713                 /* If link is active, device ref_clk can't be switched off */
1714                 __ufshcd_setup_clocks(hba, false, true);
1715
1716         /*
1717          * In case you are here to cancel this work the gating state
1718          * would be marked as REQ_CLKS_ON. In this case keep the state
1719          * as REQ_CLKS_ON which would anyway imply that clocks are off
1720          * and a request to turn them on is pending. By doing this way,
1721          * we keep the state machine in tact and this would ultimately
1722          * prevent from doing cancel work multiple times when there are
1723          * new requests arriving before the current cancel work is done.
1724          */
1725         spin_lock_irqsave(hba->host->host_lock, flags);
1726         if (hba->clk_gating.state == REQ_CLKS_OFF) {
1727                 hba->clk_gating.state = CLKS_OFF;
1728                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1729                                         hba->clk_gating.state);
1730         }
1731 rel_lock:
1732         spin_unlock_irqrestore(hba->host->host_lock, flags);
1733 out:
1734         return;
1735 }
1736
1737 /* host lock must be held before calling this variant */
1738 static void __ufshcd_release(struct ufs_hba *hba)
1739 {
1740         if (!ufshcd_is_clkgating_allowed(hba))
1741                 return;
1742
1743         hba->clk_gating.active_reqs--;
1744
1745         if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1746             hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1747             ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks ||
1748             hba->active_uic_cmd || hba->uic_async_done)
1749                 return;
1750
1751         hba->clk_gating.state = REQ_CLKS_OFF;
1752         trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1753         queue_delayed_work(hba->clk_gating.clk_gating_workq,
1754                            &hba->clk_gating.gate_work,
1755                            msecs_to_jiffies(hba->clk_gating.delay_ms));
1756 }
1757
1758 void ufshcd_release(struct ufs_hba *hba)
1759 {
1760         unsigned long flags;
1761
1762         spin_lock_irqsave(hba->host->host_lock, flags);
1763         __ufshcd_release(hba);
1764         spin_unlock_irqrestore(hba->host->host_lock, flags);
1765 }
1766 EXPORT_SYMBOL_GPL(ufshcd_release);
1767
1768 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1769                 struct device_attribute *attr, char *buf)
1770 {
1771         struct ufs_hba *hba = dev_get_drvdata(dev);
1772
1773         return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1774 }
1775
1776 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1777                 struct device_attribute *attr, const char *buf, size_t count)
1778 {
1779         struct ufs_hba *hba = dev_get_drvdata(dev);
1780         unsigned long flags, value;
1781
1782         if (kstrtoul(buf, 0, &value))
1783                 return -EINVAL;
1784
1785         spin_lock_irqsave(hba->host->host_lock, flags);
1786         hba->clk_gating.delay_ms = value;
1787         spin_unlock_irqrestore(hba->host->host_lock, flags);
1788         return count;
1789 }
1790
1791 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1792                 struct device_attribute *attr, char *buf)
1793 {
1794         struct ufs_hba *hba = dev_get_drvdata(dev);
1795
1796         return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1797 }
1798
1799 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1800                 struct device_attribute *attr, const char *buf, size_t count)
1801 {
1802         struct ufs_hba *hba = dev_get_drvdata(dev);
1803         unsigned long flags;
1804         u32 value;
1805
1806         if (kstrtou32(buf, 0, &value))
1807                 return -EINVAL;
1808
1809         value = !!value;
1810         if (value == hba->clk_gating.is_enabled)
1811                 goto out;
1812
1813         if (value) {
1814                 ufshcd_release(hba);
1815         } else {
1816                 spin_lock_irqsave(hba->host->host_lock, flags);
1817                 hba->clk_gating.active_reqs++;
1818                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1819         }
1820
1821         hba->clk_gating.is_enabled = value;
1822 out:
1823         return count;
1824 }
1825
1826 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1827 {
1828         char wq_name[sizeof("ufs_clkscaling_00")];
1829
1830         if (!ufshcd_is_clkscaling_supported(hba))
1831                 return;
1832
1833         INIT_WORK(&hba->clk_scaling.suspend_work,
1834                   ufshcd_clk_scaling_suspend_work);
1835         INIT_WORK(&hba->clk_scaling.resume_work,
1836                   ufshcd_clk_scaling_resume_work);
1837
1838         snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1839                  hba->host->host_no);
1840         hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1841
1842         ufshcd_clkscaling_init_sysfs(hba);
1843 }
1844
1845 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1846 {
1847         if (!ufshcd_is_clkscaling_supported(hba))
1848                 return;
1849
1850         destroy_workqueue(hba->clk_scaling.workq);
1851         ufshcd_devfreq_remove(hba);
1852 }
1853
1854 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1855 {
1856         char wq_name[sizeof("ufs_clk_gating_00")];
1857
1858         if (!ufshcd_is_clkgating_allowed(hba))
1859                 return;
1860
1861         hba->clk_gating.state = CLKS_ON;
1862
1863         hba->clk_gating.delay_ms = 150;
1864         INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1865         INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1866
1867         snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1868                  hba->host->host_no);
1869         hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1870                                                            WQ_MEM_RECLAIM);
1871
1872         hba->clk_gating.is_enabled = true;
1873
1874         hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1875         hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1876         sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1877         hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1878         hba->clk_gating.delay_attr.attr.mode = 0644;
1879         if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1880                 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1881
1882         hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1883         hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1884         sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1885         hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1886         hba->clk_gating.enable_attr.attr.mode = 0644;
1887         if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1888                 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1889 }
1890
1891 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1892 {
1893         if (!ufshcd_is_clkgating_allowed(hba))
1894                 return;
1895         device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1896         device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1897         cancel_work_sync(&hba->clk_gating.ungate_work);
1898         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1899         destroy_workqueue(hba->clk_gating.clk_gating_workq);
1900 }
1901
1902 /* Must be called with host lock acquired */
1903 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1904 {
1905         bool queue_resume_work = false;
1906         ktime_t curr_t = ktime_get();
1907
1908         if (!ufshcd_is_clkscaling_supported(hba))
1909                 return;
1910
1911         if (!hba->clk_scaling.active_reqs++)
1912                 queue_resume_work = true;
1913
1914         if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1915                 return;
1916
1917         if (queue_resume_work)
1918                 queue_work(hba->clk_scaling.workq,
1919                            &hba->clk_scaling.resume_work);
1920
1921         if (!hba->clk_scaling.window_start_t) {
1922                 hba->clk_scaling.window_start_t = curr_t;
1923                 hba->clk_scaling.tot_busy_t = 0;
1924                 hba->clk_scaling.is_busy_started = false;
1925         }
1926
1927         if (!hba->clk_scaling.is_busy_started) {
1928                 hba->clk_scaling.busy_start_t = curr_t;
1929                 hba->clk_scaling.is_busy_started = true;
1930         }
1931 }
1932
1933 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1934 {
1935         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1936
1937         if (!ufshcd_is_clkscaling_supported(hba))
1938                 return;
1939
1940         if (!hba->outstanding_reqs && scaling->is_busy_started) {
1941                 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1942                                         scaling->busy_start_t));
1943                 scaling->busy_start_t = 0;
1944                 scaling->is_busy_started = false;
1945         }
1946 }
1947 /**
1948  * ufshcd_send_command - Send SCSI or device management commands
1949  * @hba: per adapter instance
1950  * @task_tag: Task tag of the command
1951  */
1952 static inline
1953 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1954 {
1955         struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
1956
1957         lrbp->issue_time_stamp = ktime_get();
1958         lrbp->compl_time_stamp = ktime_set(0, 0);
1959         ufshcd_vops_setup_xfer_req(hba, task_tag, (lrbp->cmd ? true : false));
1960         ufshcd_add_command_trace(hba, task_tag, "send");
1961         ufshcd_clk_scaling_start_busy(hba);
1962         __set_bit(task_tag, &hba->outstanding_reqs);
1963         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1964         /* Make sure that doorbell is committed immediately */
1965         wmb();
1966 }
1967
1968 /**
1969  * ufshcd_copy_sense_data - Copy sense data in case of check condition
1970  * @lrbp: pointer to local reference block
1971  */
1972 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1973 {
1974         int len;
1975         if (lrbp->sense_buffer &&
1976             ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
1977                 int len_to_copy;
1978
1979                 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
1980                 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
1981
1982                 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1983                        len_to_copy);
1984         }
1985 }
1986
1987 /**
1988  * ufshcd_copy_query_response() - Copy the Query Response and the data
1989  * descriptor
1990  * @hba: per adapter instance
1991  * @lrbp: pointer to local reference block
1992  */
1993 static
1994 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1995 {
1996         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1997
1998         memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
1999
2000         /* Get the descriptor */
2001         if (hba->dev_cmd.query.descriptor &&
2002             lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2003                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2004                                 GENERAL_UPIU_REQUEST_SIZE;
2005                 u16 resp_len;
2006                 u16 buf_len;
2007
2008                 /* data segment length */
2009                 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2010                                                 MASK_QUERY_DATA_SEG_LEN;
2011                 buf_len = be16_to_cpu(
2012                                 hba->dev_cmd.query.request.upiu_req.length);
2013                 if (likely(buf_len >= resp_len)) {
2014                         memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2015                 } else {
2016                         dev_warn(hba->dev,
2017                                  "%s: rsp size %d is bigger than buffer size %d",
2018                                  __func__, resp_len, buf_len);
2019                         return -EINVAL;
2020                 }
2021         }
2022
2023         return 0;
2024 }
2025
2026 /**
2027  * ufshcd_hba_capabilities - Read controller capabilities
2028  * @hba: per adapter instance
2029  *
2030  * Return: 0 on success, negative on error.
2031  */
2032 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2033 {
2034         int err;
2035
2036         hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2037
2038         /* nutrs and nutmrs are 0 based values */
2039         hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2040         hba->nutmrs =
2041         ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2042
2043         /* Read crypto capabilities */
2044         err = ufshcd_hba_init_crypto_capabilities(hba);
2045         if (err)
2046                 dev_err(hba->dev, "crypto setup failed\n");
2047
2048         return err;
2049 }
2050
2051 /**
2052  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2053  *                            to accept UIC commands
2054  * @hba: per adapter instance
2055  * Return true on success, else false
2056  */
2057 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2058 {
2059         if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2060                 return true;
2061         else
2062                 return false;
2063 }
2064
2065 /**
2066  * ufshcd_get_upmcrs - Get the power mode change request status
2067  * @hba: Pointer to adapter instance
2068  *
2069  * This function gets the UPMCRS field of HCS register
2070  * Returns value of UPMCRS field
2071  */
2072 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2073 {
2074         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2075 }
2076
2077 /**
2078  * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
2079  * @hba: per adapter instance
2080  * @uic_cmd: UIC command
2081  *
2082  * Mutex must be held.
2083  */
2084 static inline void
2085 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2086 {
2087         WARN_ON(hba->active_uic_cmd);
2088
2089         hba->active_uic_cmd = uic_cmd;
2090
2091         /* Write Args */
2092         ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2093         ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2094         ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2095
2096         ufshcd_add_uic_command_trace(hba, uic_cmd, "send");
2097
2098         /* Write UIC Cmd */
2099         ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2100                       REG_UIC_COMMAND);
2101 }
2102
2103 /**
2104  * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2105  * @hba: per adapter instance
2106  * @uic_cmd: UIC command
2107  *
2108  * Must be called with mutex held.
2109  * Returns 0 only if success.
2110  */
2111 static int
2112 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2113 {
2114         int ret;
2115         unsigned long flags;
2116
2117         if (wait_for_completion_timeout(&uic_cmd->done,
2118                                         msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2119                 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2120         else
2121                 ret = -ETIMEDOUT;
2122
2123         spin_lock_irqsave(hba->host->host_lock, flags);
2124         hba->active_uic_cmd = NULL;
2125         spin_unlock_irqrestore(hba->host->host_lock, flags);
2126
2127         return ret;
2128 }
2129
2130 /**
2131  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2132  * @hba: per adapter instance
2133  * @uic_cmd: UIC command
2134  * @completion: initialize the completion only if this is set to true
2135  *
2136  * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
2137  * with mutex held and host_lock locked.
2138  * Returns 0 only if success.
2139  */
2140 static int
2141 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2142                       bool completion)
2143 {
2144         if (!ufshcd_ready_for_uic_cmd(hba)) {
2145                 dev_err(hba->dev,
2146                         "Controller not ready to accept UIC commands\n");
2147                 return -EIO;
2148         }
2149
2150         if (completion)
2151                 init_completion(&uic_cmd->done);
2152
2153         ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2154
2155         return 0;
2156 }
2157
2158 /**
2159  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2160  * @hba: per adapter instance
2161  * @uic_cmd: UIC command
2162  *
2163  * Returns 0 only if success.
2164  */
2165 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2166 {
2167         int ret;
2168         unsigned long flags;
2169
2170         ufshcd_hold(hba, false);
2171         mutex_lock(&hba->uic_cmd_mutex);
2172         ufshcd_add_delay_before_dme_cmd(hba);
2173
2174         spin_lock_irqsave(hba->host->host_lock, flags);
2175         ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2176         spin_unlock_irqrestore(hba->host->host_lock, flags);
2177         if (!ret)
2178                 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2179
2180         mutex_unlock(&hba->uic_cmd_mutex);
2181
2182         ufshcd_release(hba);
2183         return ret;
2184 }
2185
2186 /**
2187  * ufshcd_map_sg - Map scatter-gather list to prdt
2188  * @hba: per adapter instance
2189  * @lrbp: pointer to local reference block
2190  *
2191  * Returns 0 in case of success, non-zero value in case of failure
2192  */
2193 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2194 {
2195         struct ufshcd_sg_entry *prd_table;
2196         struct scatterlist *sg;
2197         struct scsi_cmnd *cmd;
2198         int sg_segments;
2199         int i;
2200
2201         cmd = lrbp->cmd;
2202         sg_segments = scsi_dma_map(cmd);
2203         if (sg_segments < 0)
2204                 return sg_segments;
2205
2206         if (sg_segments) {
2207
2208                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2209                         lrbp->utr_descriptor_ptr->prd_table_length =
2210                                 cpu_to_le16((sg_segments *
2211                                         sizeof(struct ufshcd_sg_entry)));
2212                 else
2213                         lrbp->utr_descriptor_ptr->prd_table_length =
2214                                 cpu_to_le16((u16) (sg_segments));
2215
2216                 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2217
2218                 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2219                         prd_table[i].size  =
2220                                 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2221                         prd_table[i].base_addr =
2222                                 cpu_to_le32(lower_32_bits(sg->dma_address));
2223                         prd_table[i].upper_addr =
2224                                 cpu_to_le32(upper_32_bits(sg->dma_address));
2225                         prd_table[i].reserved = 0;
2226                 }
2227         } else {
2228                 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2229         }
2230
2231         return 0;
2232 }
2233
2234 /**
2235  * ufshcd_enable_intr - enable interrupts
2236  * @hba: per adapter instance
2237  * @intrs: interrupt bits
2238  */
2239 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2240 {
2241         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2242
2243         if (hba->ufs_version == UFSHCI_VERSION_10) {
2244                 u32 rw;
2245                 rw = set & INTERRUPT_MASK_RW_VER_10;
2246                 set = rw | ((set ^ intrs) & intrs);
2247         } else {
2248                 set |= intrs;
2249         }
2250
2251         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2252 }
2253
2254 /**
2255  * ufshcd_disable_intr - disable interrupts
2256  * @hba: per adapter instance
2257  * @intrs: interrupt bits
2258  */
2259 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2260 {
2261         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2262
2263         if (hba->ufs_version == UFSHCI_VERSION_10) {
2264                 u32 rw;
2265                 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2266                         ~(intrs & INTERRUPT_MASK_RW_VER_10);
2267                 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2268
2269         } else {
2270                 set &= ~intrs;
2271         }
2272
2273         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2274 }
2275
2276 /**
2277  * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2278  * descriptor according to request
2279  * @lrbp: pointer to local reference block
2280  * @upiu_flags: flags required in the header
2281  * @cmd_dir: requests data direction
2282  */
2283 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2284                         u8 *upiu_flags, enum dma_data_direction cmd_dir)
2285 {
2286         struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2287         u32 data_direction;
2288         u32 dword_0;
2289         u32 dword_1 = 0;
2290         u32 dword_3 = 0;
2291
2292         if (cmd_dir == DMA_FROM_DEVICE) {
2293                 data_direction = UTP_DEVICE_TO_HOST;
2294                 *upiu_flags = UPIU_CMD_FLAGS_READ;
2295         } else if (cmd_dir == DMA_TO_DEVICE) {
2296                 data_direction = UTP_HOST_TO_DEVICE;
2297                 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2298         } else {
2299                 data_direction = UTP_NO_DATA_TRANSFER;
2300                 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2301         }
2302
2303         dword_0 = data_direction | (lrbp->command_type
2304                                 << UPIU_COMMAND_TYPE_OFFSET);
2305         if (lrbp->intr_cmd)
2306                 dword_0 |= UTP_REQ_DESC_INT_CMD;
2307
2308         /* Prepare crypto related dwords */
2309         ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2310
2311         /* Transfer request descriptor header fields */
2312         req_desc->header.dword_0 = cpu_to_le32(dword_0);
2313         req_desc->header.dword_1 = cpu_to_le32(dword_1);
2314         /*
2315          * assigning invalid value for command status. Controller
2316          * updates OCS on command completion, with the command
2317          * status
2318          */
2319         req_desc->header.dword_2 =
2320                 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2321         req_desc->header.dword_3 = cpu_to_le32(dword_3);
2322
2323         req_desc->prd_table_length = 0;
2324 }
2325
2326 /**
2327  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2328  * for scsi commands
2329  * @lrbp: local reference block pointer
2330  * @upiu_flags: flags
2331  */
2332 static
2333 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2334 {
2335         struct scsi_cmnd *cmd = lrbp->cmd;
2336         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2337         unsigned short cdb_len;
2338
2339         /* command descriptor fields */
2340         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2341                                 UPIU_TRANSACTION_COMMAND, upiu_flags,
2342                                 lrbp->lun, lrbp->task_tag);
2343         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2344                                 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2345
2346         /* Total EHS length and Data segment length will be zero */
2347         ucd_req_ptr->header.dword_2 = 0;
2348
2349         ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2350
2351         cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2352         memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2353         memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2354
2355         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2356 }
2357
2358 /**
2359  * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2360  * for query requsts
2361  * @hba: UFS hba
2362  * @lrbp: local reference block pointer
2363  * @upiu_flags: flags
2364  */
2365 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2366                                 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2367 {
2368         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2369         struct ufs_query *query = &hba->dev_cmd.query;
2370         u16 len = be16_to_cpu(query->request.upiu_req.length);
2371
2372         /* Query request header */
2373         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2374                         UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2375                         lrbp->lun, lrbp->task_tag);
2376         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2377                         0, query->request.query_func, 0, 0);
2378
2379         /* Data segment length only need for WRITE_DESC */
2380         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2381                 ucd_req_ptr->header.dword_2 =
2382                         UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2383         else
2384                 ucd_req_ptr->header.dword_2 = 0;
2385
2386         /* Copy the Query Request buffer as is */
2387         memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2388                         QUERY_OSF_SIZE);
2389
2390         /* Copy the Descriptor */
2391         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2392                 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2393
2394         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2395 }
2396
2397 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2398 {
2399         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2400
2401         memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2402
2403         /* command descriptor fields */
2404         ucd_req_ptr->header.dword_0 =
2405                 UPIU_HEADER_DWORD(
2406                         UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2407         /* clear rest of the fields of basic header */
2408         ucd_req_ptr->header.dword_1 = 0;
2409         ucd_req_ptr->header.dword_2 = 0;
2410
2411         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2412 }
2413
2414 /**
2415  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2416  *                           for Device Management Purposes
2417  * @hba: per adapter instance
2418  * @lrbp: pointer to local reference block
2419  */
2420 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2421                                       struct ufshcd_lrb *lrbp)
2422 {
2423         u8 upiu_flags;
2424         int ret = 0;
2425
2426         if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2427             (hba->ufs_version == UFSHCI_VERSION_11))
2428                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2429         else
2430                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2431
2432         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2433         if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2434                 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2435         else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2436                 ufshcd_prepare_utp_nop_upiu(lrbp);
2437         else
2438                 ret = -EINVAL;
2439
2440         return ret;
2441 }
2442
2443 /**
2444  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2445  *                         for SCSI Purposes
2446  * @hba: per adapter instance
2447  * @lrbp: pointer to local reference block
2448  */
2449 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2450 {
2451         u8 upiu_flags;
2452         int ret = 0;
2453
2454         if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2455             (hba->ufs_version == UFSHCI_VERSION_11))
2456                 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2457         else
2458                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2459
2460         if (likely(lrbp->cmd)) {
2461                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2462                                                 lrbp->cmd->sc_data_direction);
2463                 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2464         } else {
2465                 ret = -EINVAL;
2466         }
2467
2468         return ret;
2469 }
2470
2471 /**
2472  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2473  * @upiu_wlun_id: UPIU W-LUN id
2474  *
2475  * Returns SCSI W-LUN id
2476  */
2477 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2478 {
2479         return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2480 }
2481
2482 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2483 {
2484         struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2485         struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2486         dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2487                 i * sizeof(struct utp_transfer_cmd_desc);
2488         u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2489                                        response_upiu);
2490         u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2491
2492         lrb->utr_descriptor_ptr = utrdlp + i;
2493         lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2494                 i * sizeof(struct utp_transfer_req_desc);
2495         lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2496         lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2497         lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2498         lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2499         lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2500         lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2501 }
2502
2503 /**
2504  * ufshcd_queuecommand - main entry point for SCSI requests
2505  * @host: SCSI host pointer
2506  * @cmd: command from SCSI Midlayer
2507  *
2508  * Returns 0 for success, non-zero in case of failure
2509  */
2510 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2511 {
2512         struct ufshcd_lrb *lrbp;
2513         struct ufs_hba *hba;
2514         unsigned long flags;
2515         int tag;
2516         int err = 0;
2517
2518         hba = shost_priv(host);
2519
2520         tag = cmd->request->tag;
2521         if (!ufshcd_valid_tag(hba, tag)) {
2522                 dev_err(hba->dev,
2523                         "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2524                         __func__, tag, cmd, cmd->request);
2525                 BUG();
2526         }
2527
2528         if (!down_read_trylock(&hba->clk_scaling_lock))
2529                 return SCSI_MLQUEUE_HOST_BUSY;
2530
2531         hba->req_abort_count = 0;
2532
2533         err = ufshcd_hold(hba, true);
2534         if (err) {
2535                 err = SCSI_MLQUEUE_HOST_BUSY;
2536                 goto out;
2537         }
2538         WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2539                 (hba->clk_gating.state != CLKS_ON));
2540
2541         lrbp = &hba->lrb[tag];
2542
2543         WARN_ON(lrbp->cmd);
2544         lrbp->cmd = cmd;
2545         lrbp->sense_bufflen = UFS_SENSE_SIZE;
2546         lrbp->sense_buffer = cmd->sense_buffer;
2547         lrbp->task_tag = tag;
2548         lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2549         lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2550
2551         ufshcd_prepare_lrbp_crypto(cmd->request, lrbp);
2552
2553         lrbp->req_abort_skip = false;
2554
2555         ufshcd_comp_scsi_upiu(hba, lrbp);
2556
2557         err = ufshcd_map_sg(hba, lrbp);
2558         if (err) {
2559                 lrbp->cmd = NULL;
2560                 ufshcd_release(hba);
2561                 goto out;
2562         }
2563         /* Make sure descriptors are ready before ringing the doorbell */
2564         wmb();
2565
2566         spin_lock_irqsave(hba->host->host_lock, flags);
2567         switch (hba->ufshcd_state) {
2568         case UFSHCD_STATE_OPERATIONAL:
2569         case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2570                 break;
2571         case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2572                 /*
2573                  * pm_runtime_get_sync() is used at error handling preparation
2574                  * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2575                  * PM ops, it can never be finished if we let SCSI layer keep
2576                  * retrying it, which gets err handler stuck forever. Neither
2577                  * can we let the scsi cmd pass through, because UFS is in bad
2578                  * state, the scsi cmd may eventually time out, which will get
2579                  * err handler blocked for too long. So, just fail the scsi cmd
2580                  * sent from PM ops, err handler can recover PM error anyways.
2581                  */
2582                 if (hba->pm_op_in_progress) {
2583                         hba->force_reset = true;
2584                         set_host_byte(cmd, DID_BAD_TARGET);
2585                         goto out_compl_cmd;
2586                 }
2587                 fallthrough;
2588         case UFSHCD_STATE_RESET:
2589                 err = SCSI_MLQUEUE_HOST_BUSY;
2590                 goto out_compl_cmd;
2591         case UFSHCD_STATE_ERROR:
2592                 set_host_byte(cmd, DID_ERROR);
2593                 goto out_compl_cmd;
2594         default:
2595                 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2596                                 __func__, hba->ufshcd_state);
2597                 set_host_byte(cmd, DID_BAD_TARGET);
2598                 goto out_compl_cmd;
2599         }
2600         ufshcd_send_command(hba, tag);
2601         spin_unlock_irqrestore(hba->host->host_lock, flags);
2602         goto out;
2603
2604 out_compl_cmd:
2605         scsi_dma_unmap(lrbp->cmd);
2606         lrbp->cmd = NULL;
2607         spin_unlock_irqrestore(hba->host->host_lock, flags);
2608         ufshcd_release(hba);
2609         if (!err)
2610                 cmd->scsi_done(cmd);
2611 out:
2612         up_read(&hba->clk_scaling_lock);
2613         return err;
2614 }
2615
2616 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2617                 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2618 {
2619         lrbp->cmd = NULL;
2620         lrbp->sense_bufflen = 0;
2621         lrbp->sense_buffer = NULL;
2622         lrbp->task_tag = tag;
2623         lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2624         lrbp->intr_cmd = true; /* No interrupt aggregation */
2625         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2626         hba->dev_cmd.type = cmd_type;
2627
2628         return ufshcd_compose_devman_upiu(hba, lrbp);
2629 }
2630
2631 static int
2632 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2633 {
2634         int err = 0;
2635         unsigned long flags;
2636         u32 mask = 1 << tag;
2637
2638         /* clear outstanding transaction before retry */
2639         spin_lock_irqsave(hba->host->host_lock, flags);
2640         ufshcd_utrl_clear(hba, tag);
2641         spin_unlock_irqrestore(hba->host->host_lock, flags);
2642
2643         /*
2644          * wait for for h/w to clear corresponding bit in door-bell.
2645          * max. wait is 1 sec.
2646          */
2647         err = ufshcd_wait_for_register(hba,
2648                         REG_UTP_TRANSFER_REQ_DOOR_BELL,
2649                         mask, ~mask, 1000, 1000);
2650
2651         return err;
2652 }
2653
2654 static int
2655 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2656 {
2657         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2658
2659         /* Get the UPIU response */
2660         query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2661                                 UPIU_RSP_CODE_OFFSET;
2662         return query_res->response;
2663 }
2664
2665 /**
2666  * ufshcd_dev_cmd_completion() - handles device management command responses
2667  * @hba: per adapter instance
2668  * @lrbp: pointer to local reference block
2669  */
2670 static int
2671 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2672 {
2673         int resp;
2674         int err = 0;
2675
2676         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2677         resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2678
2679         switch (resp) {
2680         case UPIU_TRANSACTION_NOP_IN:
2681                 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2682                         err = -EINVAL;
2683                         dev_err(hba->dev, "%s: unexpected response %x\n",
2684                                         __func__, resp);
2685                 }
2686                 break;
2687         case UPIU_TRANSACTION_QUERY_RSP:
2688                 err = ufshcd_check_query_response(hba, lrbp);
2689                 if (!err)
2690                         err = ufshcd_copy_query_response(hba, lrbp);
2691                 break;
2692         case UPIU_TRANSACTION_REJECT_UPIU:
2693                 /* TODO: handle Reject UPIU Response */
2694                 err = -EPERM;
2695                 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2696                                 __func__);
2697                 break;
2698         default:
2699                 err = -EINVAL;
2700                 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2701                                 __func__, resp);
2702                 break;
2703         }
2704
2705         return err;
2706 }
2707
2708 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2709                 struct ufshcd_lrb *lrbp, int max_timeout)
2710 {
2711         int err = 0;
2712         unsigned long time_left;
2713         unsigned long flags;
2714
2715         time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2716                         msecs_to_jiffies(max_timeout));
2717
2718         /* Make sure descriptors are ready before ringing the doorbell */
2719         wmb();
2720         spin_lock_irqsave(hba->host->host_lock, flags);
2721         hba->dev_cmd.complete = NULL;
2722         if (likely(time_left)) {
2723                 err = ufshcd_get_tr_ocs(lrbp);
2724                 if (!err)
2725                         err = ufshcd_dev_cmd_completion(hba, lrbp);
2726         }
2727         spin_unlock_irqrestore(hba->host->host_lock, flags);
2728
2729         if (!time_left) {
2730                 err = -ETIMEDOUT;
2731                 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2732                         __func__, lrbp->task_tag);
2733                 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2734                         /* successfully cleared the command, retry if needed */
2735                         err = -EAGAIN;
2736                 /*
2737                  * in case of an error, after clearing the doorbell,
2738                  * we also need to clear the outstanding_request
2739                  * field in hba
2740                  */
2741                 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
2742         }
2743
2744         return err;
2745 }
2746
2747 /**
2748  * ufshcd_exec_dev_cmd - API for sending device management requests
2749  * @hba: UFS hba
2750  * @cmd_type: specifies the type (NOP, Query...)
2751  * @timeout: time in seconds
2752  *
2753  * NOTE: Since there is only one available tag for device management commands,
2754  * it is expected you hold the hba->dev_cmd.lock mutex.
2755  */
2756 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2757                 enum dev_cmd_type cmd_type, int timeout)
2758 {
2759         struct request_queue *q = hba->cmd_queue;
2760         struct request *req;
2761         struct ufshcd_lrb *lrbp;
2762         int err;
2763         int tag;
2764         struct completion wait;
2765         unsigned long flags;
2766
2767         down_read(&hba->clk_scaling_lock);
2768
2769         /*
2770          * Get free slot, sleep if slots are unavailable.
2771          * Even though we use wait_event() which sleeps indefinitely,
2772          * the maximum wait time is bounded by SCSI request timeout.
2773          */
2774         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
2775         if (IS_ERR(req)) {
2776                 err = PTR_ERR(req);
2777                 goto out_unlock;
2778         }
2779         tag = req->tag;
2780         WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
2781
2782         init_completion(&wait);
2783         lrbp = &hba->lrb[tag];
2784         WARN_ON(lrbp->cmd);
2785         err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2786         if (unlikely(err))
2787                 goto out_put_tag;
2788
2789         hba->dev_cmd.complete = &wait;
2790
2791         ufshcd_add_query_upiu_trace(hba, tag, "query_send");
2792         /* Make sure descriptors are ready before ringing the doorbell */
2793         wmb();
2794         spin_lock_irqsave(hba->host->host_lock, flags);
2795         ufshcd_send_command(hba, tag);
2796         spin_unlock_irqrestore(hba->host->host_lock, flags);
2797
2798         err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2799
2800         ufshcd_add_query_upiu_trace(hba, tag,
2801                         err ? "query_complete_err" : "query_complete");
2802
2803 out_put_tag:
2804         blk_put_request(req);
2805 out_unlock:
2806         up_read(&hba->clk_scaling_lock);
2807         return err;
2808 }
2809
2810 /**
2811  * ufshcd_init_query() - init the query response and request parameters
2812  * @hba: per-adapter instance
2813  * @request: address of the request pointer to be initialized
2814  * @response: address of the response pointer to be initialized
2815  * @opcode: operation to perform
2816  * @idn: flag idn to access
2817  * @index: LU number to access
2818  * @selector: query/flag/descriptor further identification
2819  */
2820 static inline void ufshcd_init_query(struct ufs_hba *hba,
2821                 struct ufs_query_req **request, struct ufs_query_res **response,
2822                 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2823 {
2824         *request = &hba->dev_cmd.query.request;
2825         *response = &hba->dev_cmd.query.response;
2826         memset(*request, 0, sizeof(struct ufs_query_req));
2827         memset(*response, 0, sizeof(struct ufs_query_res));
2828         (*request)->upiu_req.opcode = opcode;
2829         (*request)->upiu_req.idn = idn;
2830         (*request)->upiu_req.index = index;
2831         (*request)->upiu_req.selector = selector;
2832 }
2833
2834 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2835         enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
2836 {
2837         int ret;
2838         int retries;
2839
2840         for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2841                 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
2842                 if (ret)
2843                         dev_dbg(hba->dev,
2844                                 "%s: failed with error %d, retries %d\n",
2845                                 __func__, ret, retries);
2846                 else
2847                         break;
2848         }
2849
2850         if (ret)
2851                 dev_err(hba->dev,
2852                         "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2853                         __func__, opcode, idn, ret, retries);
2854         return ret;
2855 }
2856
2857 /**
2858  * ufshcd_query_flag() - API function for sending flag query requests
2859  * @hba: per-adapter instance
2860  * @opcode: flag query to perform
2861  * @idn: flag idn to access
2862  * @index: flag index to access
2863  * @flag_res: the flag value after the query request completes
2864  *
2865  * Returns 0 for success, non-zero in case of failure
2866  */
2867 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
2868                         enum flag_idn idn, u8 index, bool *flag_res)
2869 {
2870         struct ufs_query_req *request = NULL;
2871         struct ufs_query_res *response = NULL;
2872         int err, selector = 0;
2873         int timeout = QUERY_REQ_TIMEOUT;
2874
2875         BUG_ON(!hba);
2876
2877         ufshcd_hold(hba, false);
2878         mutex_lock(&hba->dev_cmd.lock);
2879         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2880                         selector);
2881
2882         switch (opcode) {
2883         case UPIU_QUERY_OPCODE_SET_FLAG:
2884         case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2885         case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2886                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2887                 break;
2888         case UPIU_QUERY_OPCODE_READ_FLAG:
2889                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2890                 if (!flag_res) {
2891                         /* No dummy reads */
2892                         dev_err(hba->dev, "%s: Invalid argument for read request\n",
2893                                         __func__);
2894                         err = -EINVAL;
2895                         goto out_unlock;
2896                 }
2897                 break;
2898         default:
2899                 dev_err(hba->dev,
2900                         "%s: Expected query flag opcode but got = %d\n",
2901                         __func__, opcode);
2902                 err = -EINVAL;
2903                 goto out_unlock;
2904         }
2905
2906         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
2907
2908         if (err) {
2909                 dev_err(hba->dev,
2910                         "%s: Sending flag query for idn %d failed, err = %d\n",
2911                         __func__, idn, err);
2912                 goto out_unlock;
2913         }
2914
2915         if (flag_res)
2916                 *flag_res = (be32_to_cpu(response->upiu_res.value) &
2917                                 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2918
2919 out_unlock:
2920         mutex_unlock(&hba->dev_cmd.lock);
2921         ufshcd_release(hba);
2922         return err;
2923 }
2924
2925 /**
2926  * ufshcd_query_attr - API function for sending attribute requests
2927  * @hba: per-adapter instance
2928  * @opcode: attribute opcode
2929  * @idn: attribute idn to access
2930  * @index: index field
2931  * @selector: selector field
2932  * @attr_val: the attribute value after the query request completes
2933  *
2934  * Returns 0 for success, non-zero in case of failure
2935 */
2936 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2937                       enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2938 {
2939         struct ufs_query_req *request = NULL;
2940         struct ufs_query_res *response = NULL;
2941         int err;
2942
2943         BUG_ON(!hba);
2944
2945         ufshcd_hold(hba, false);
2946         if (!attr_val) {
2947                 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2948                                 __func__, opcode);
2949                 err = -EINVAL;
2950                 goto out;
2951         }
2952
2953         mutex_lock(&hba->dev_cmd.lock);
2954         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2955                         selector);
2956
2957         switch (opcode) {
2958         case UPIU_QUERY_OPCODE_WRITE_ATTR:
2959                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2960                 request->upiu_req.value = cpu_to_be32(*attr_val);
2961                 break;
2962         case UPIU_QUERY_OPCODE_READ_ATTR:
2963                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2964                 break;
2965         default:
2966                 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2967                                 __func__, opcode);
2968                 err = -EINVAL;
2969                 goto out_unlock;
2970         }
2971
2972         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2973
2974         if (err) {
2975                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2976                                 __func__, opcode, idn, index, err);
2977                 goto out_unlock;
2978         }
2979
2980         *attr_val = be32_to_cpu(response->upiu_res.value);
2981
2982 out_unlock:
2983         mutex_unlock(&hba->dev_cmd.lock);
2984 out:
2985         ufshcd_release(hba);
2986         return err;
2987 }
2988
2989 /**
2990  * ufshcd_query_attr_retry() - API function for sending query
2991  * attribute with retries
2992  * @hba: per-adapter instance
2993  * @opcode: attribute opcode
2994  * @idn: attribute idn to access
2995  * @index: index field
2996  * @selector: selector field
2997  * @attr_val: the attribute value after the query request
2998  * completes
2999  *
3000  * Returns 0 for success, non-zero in case of failure
3001 */
3002 static int ufshcd_query_attr_retry(struct ufs_hba *hba,
3003         enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3004         u32 *attr_val)
3005 {
3006         int ret = 0;
3007         u32 retries;
3008
3009         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3010                 ret = ufshcd_query_attr(hba, opcode, idn, index,
3011                                                 selector, attr_val);
3012                 if (ret)
3013                         dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3014                                 __func__, ret, retries);
3015                 else
3016                         break;
3017         }
3018
3019         if (ret)
3020                 dev_err(hba->dev,
3021                         "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3022                         __func__, idn, ret, QUERY_REQ_RETRIES);
3023         return ret;
3024 }
3025
3026 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3027                         enum query_opcode opcode, enum desc_idn idn, u8 index,
3028                         u8 selector, u8 *desc_buf, int *buf_len)
3029 {
3030         struct ufs_query_req *request = NULL;
3031         struct ufs_query_res *response = NULL;
3032         int err;
3033
3034         BUG_ON(!hba);
3035
3036         ufshcd_hold(hba, false);
3037         if (!desc_buf) {
3038                 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3039                                 __func__, opcode);
3040                 err = -EINVAL;
3041                 goto out;
3042         }
3043
3044         if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3045                 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3046                                 __func__, *buf_len);
3047                 err = -EINVAL;
3048                 goto out;
3049         }
3050
3051         mutex_lock(&hba->dev_cmd.lock);
3052         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3053                         selector);
3054         hba->dev_cmd.query.descriptor = desc_buf;
3055         request->upiu_req.length = cpu_to_be16(*buf_len);
3056
3057         switch (opcode) {
3058         case UPIU_QUERY_OPCODE_WRITE_DESC:
3059                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3060                 break;
3061         case UPIU_QUERY_OPCODE_READ_DESC:
3062                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3063                 break;
3064         default:
3065                 dev_err(hba->dev,
3066                                 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3067                                 __func__, opcode);
3068                 err = -EINVAL;
3069                 goto out_unlock;
3070         }
3071
3072         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3073
3074         if (err) {
3075                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3076                                 __func__, opcode, idn, index, err);
3077                 goto out_unlock;
3078         }
3079
3080         *buf_len = be16_to_cpu(response->upiu_res.length);
3081
3082 out_unlock:
3083         hba->dev_cmd.query.descriptor = NULL;
3084         mutex_unlock(&hba->dev_cmd.lock);
3085 out:
3086         ufshcd_release(hba);
3087         return err;
3088 }
3089
3090 /**
3091  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3092  * @hba: per-adapter instance
3093  * @opcode: attribute opcode
3094  * @idn: attribute idn to access
3095  * @index: index field
3096  * @selector: selector field
3097  * @desc_buf: the buffer that contains the descriptor
3098  * @buf_len: length parameter passed to the device
3099  *
3100  * Returns 0 for success, non-zero in case of failure.
3101  * The buf_len parameter will contain, on return, the length parameter
3102  * received on the response.
3103  */
3104 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3105                                   enum query_opcode opcode,
3106                                   enum desc_idn idn, u8 index,
3107                                   u8 selector,
3108                                   u8 *desc_buf, int *buf_len)
3109 {
3110         int err;
3111         int retries;
3112
3113         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3114                 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3115                                                 selector, desc_buf, buf_len);
3116                 if (!err || err == -EINVAL)
3117                         break;
3118         }
3119
3120         return err;
3121 }
3122
3123 /**
3124  * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3125  * @hba: Pointer to adapter instance
3126  * @desc_id: descriptor idn value
3127  * @desc_len: mapped desc length (out)
3128  */
3129 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3130                                   int *desc_len)
3131 {
3132         if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3133             desc_id == QUERY_DESC_IDN_RFU_1)
3134                 *desc_len = 0;
3135         else
3136                 *desc_len = hba->desc_size[desc_id];
3137 }
3138 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3139
3140 static void ufshcd_update_desc_length(struct ufs_hba *hba,
3141                                       enum desc_idn desc_id, int desc_index,
3142                                       unsigned char desc_len)
3143 {
3144         if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3145             desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3146                 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3147                  * than the RPMB unit, however, both descriptors share the same
3148                  * desc_idn, to cover both unit descriptors with one length, we
3149                  * choose the normal unit descriptor length by desc_index.
3150                  */
3151                 hba->desc_size[desc_id] = desc_len;
3152 }
3153
3154 /**
3155  * ufshcd_read_desc_param - read the specified descriptor parameter
3156  * @hba: Pointer to adapter instance
3157  * @desc_id: descriptor idn value
3158  * @desc_index: descriptor index
3159  * @param_offset: offset of the parameter to read
3160  * @param_read_buf: pointer to buffer where parameter would be read
3161  * @param_size: sizeof(param_read_buf)
3162  *
3163  * Return 0 in case of success, non-zero otherwise
3164  */
3165 int ufshcd_read_desc_param(struct ufs_hba *hba,
3166                            enum desc_idn desc_id,
3167                            int desc_index,
3168                            u8 param_offset,
3169                            u8 *param_read_buf,
3170                            u8 param_size)
3171 {
3172         int ret;
3173         u8 *desc_buf;
3174         int buff_len;
3175         bool is_kmalloc = true;
3176
3177         /* Safety check */
3178         if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3179                 return -EINVAL;
3180
3181         /* Get the length of descriptor */
3182         ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3183         if (!buff_len) {
3184                 dev_err(hba->dev, "%s: Failed to get desc length", __func__);
3185                 return -EINVAL;
3186         }
3187
3188         /* Check whether we need temp memory */
3189         if (param_offset != 0 || param_size < buff_len) {
3190                 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3191                 if (!desc_buf)
3192                         return -ENOMEM;
3193         } else {
3194                 desc_buf = param_read_buf;
3195                 is_kmalloc = false;
3196         }
3197
3198         /* Request for full descriptor */
3199         ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3200                                         desc_id, desc_index, 0,
3201                                         desc_buf, &buff_len);
3202
3203         if (ret) {
3204                 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3205                         __func__, desc_id, desc_index, param_offset, ret);
3206                 goto out;
3207         }
3208
3209         /* Sanity check */
3210         if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3211                 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3212                         __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3213                 ret = -EINVAL;
3214                 goto out;
3215         }
3216
3217         /* Update descriptor length */
3218         buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3219         ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3220
3221         /* Check wherher we will not copy more data, than available */
3222         if (is_kmalloc && (param_offset + param_size) > buff_len)
3223                 param_size = buff_len - param_offset;
3224
3225         if (is_kmalloc)
3226                 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3227 out:
3228         if (is_kmalloc)
3229                 kfree(desc_buf);
3230         return ret;
3231 }
3232
3233 /**
3234  * struct uc_string_id - unicode string
3235  *
3236  * @len: size of this descriptor inclusive
3237  * @type: descriptor type
3238  * @uc: unicode string character
3239  */
3240 struct uc_string_id {
3241         u8 len;
3242         u8 type;
3243         wchar_t uc[];
3244 } __packed;
3245
3246 /* replace non-printable or non-ASCII characters with spaces */
3247 static inline char ufshcd_remove_non_printable(u8 ch)
3248 {
3249         return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3250 }
3251
3252 /**
3253  * ufshcd_read_string_desc - read string descriptor
3254  * @hba: pointer to adapter instance
3255  * @desc_index: descriptor index
3256  * @buf: pointer to buffer where descriptor would be read,
3257  *       the caller should free the memory.
3258  * @ascii: if true convert from unicode to ascii characters
3259  *         null terminated string.
3260  *
3261  * Return:
3262  * *      string size on success.
3263  * *      -ENOMEM: on allocation failure
3264  * *      -EINVAL: on a wrong parameter
3265  */
3266 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3267                             u8 **buf, bool ascii)
3268 {
3269         struct uc_string_id *uc_str;
3270         u8 *str;
3271         int ret;
3272
3273         if (!buf)
3274                 return -EINVAL;
3275
3276         uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3277         if (!uc_str)
3278                 return -ENOMEM;
3279
3280         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3281                                      (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3282         if (ret < 0) {
3283                 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3284                         QUERY_REQ_RETRIES, ret);
3285                 str = NULL;
3286                 goto out;
3287         }
3288
3289         if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3290                 dev_dbg(hba->dev, "String Desc is of zero length\n");
3291                 str = NULL;
3292                 ret = 0;
3293                 goto out;
3294         }
3295
3296         if (ascii) {
3297                 ssize_t ascii_len;
3298                 int i;
3299                 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3300                 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3301                 str = kzalloc(ascii_len, GFP_KERNEL);
3302                 if (!str) {
3303                         ret = -ENOMEM;
3304                         goto out;
3305                 }
3306
3307                 /*
3308                  * the descriptor contains string in UTF16 format
3309                  * we need to convert to utf-8 so it can be displayed
3310                  */
3311                 ret = utf16s_to_utf8s(uc_str->uc,
3312                                       uc_str->len - QUERY_DESC_HDR_SIZE,
3313                                       UTF16_BIG_ENDIAN, str, ascii_len);
3314
3315                 /* replace non-printable or non-ASCII characters with spaces */
3316                 for (i = 0; i < ret; i++)
3317                         str[i] = ufshcd_remove_non_printable(str[i]);
3318
3319                 str[ret++] = '\0';
3320
3321         } else {
3322                 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3323                 if (!str) {
3324                         ret = -ENOMEM;
3325                         goto out;
3326                 }
3327                 ret = uc_str->len;
3328         }
3329 out:
3330         *buf = str;
3331         kfree(uc_str);
3332         return ret;
3333 }
3334
3335 /**
3336  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3337  * @hba: Pointer to adapter instance
3338  * @lun: lun id
3339  * @param_offset: offset of the parameter to read
3340  * @param_read_buf: pointer to buffer where parameter would be read
3341  * @param_size: sizeof(param_read_buf)
3342  *
3343  * Return 0 in case of success, non-zero otherwise
3344  */
3345 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3346                                               int lun,
3347                                               enum unit_desc_param param_offset,
3348                                               u8 *param_read_buf,
3349                                               u32 param_size)
3350 {
3351         /*
3352          * Unit descriptors are only available for general purpose LUs (LUN id
3353          * from 0 to 7) and RPMB Well known LU.
3354          */
3355         if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3356                 return -EOPNOTSUPP;
3357
3358         return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3359                                       param_offset, param_read_buf, param_size);
3360 }
3361
3362 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3363 {
3364         int err = 0;
3365         u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3366
3367         if (hba->dev_info.wspecversion >= 0x300) {
3368                 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3369                                 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3370                                 &gating_wait);
3371                 if (err)
3372                         dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3373                                          err, gating_wait);
3374
3375                 if (gating_wait == 0) {
3376                         gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3377                         dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3378                                          gating_wait);
3379                 }
3380
3381                 hba->dev_info.clk_gating_wait_us = gating_wait;
3382         }
3383
3384         return err;
3385 }
3386
3387 /**
3388  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3389  * @hba: per adapter instance
3390  *
3391  * 1. Allocate DMA memory for Command Descriptor array
3392  *      Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3393  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3394  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3395  *      (UTMRDL)
3396  * 4. Allocate memory for local reference block(lrb).
3397  *
3398  * Returns 0 for success, non-zero in case of failure
3399  */
3400 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3401 {
3402         size_t utmrdl_size, utrdl_size, ucdl_size;
3403
3404         /* Allocate memory for UTP command descriptors */
3405         ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3406         hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3407                                                   ucdl_size,
3408                                                   &hba->ucdl_dma_addr,
3409                                                   GFP_KERNEL);
3410
3411         /*
3412          * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3413          * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3414          * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3415          * be aligned to 128 bytes as well
3416          */
3417         if (!hba->ucdl_base_addr ||
3418             WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3419                 dev_err(hba->dev,
3420                         "Command Descriptor Memory allocation failed\n");
3421                 goto out;
3422         }
3423
3424         /*
3425          * Allocate memory for UTP Transfer descriptors
3426          * UFSHCI requires 1024 byte alignment of UTRD
3427          */
3428         utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3429         hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3430                                                    utrdl_size,
3431                                                    &hba->utrdl_dma_addr,
3432                                                    GFP_KERNEL);
3433         if (!hba->utrdl_base_addr ||
3434             WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3435                 dev_err(hba->dev,
3436                         "Transfer Descriptor Memory allocation failed\n");
3437                 goto out;
3438         }
3439
3440         /*
3441          * Allocate memory for UTP Task Management descriptors
3442          * UFSHCI requires 1024 byte alignment of UTMRD
3443          */
3444         utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3445         hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3446                                                     utmrdl_size,
3447                                                     &hba->utmrdl_dma_addr,
3448                                                     GFP_KERNEL);
3449         if (!hba->utmrdl_base_addr ||
3450             WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3451                 dev_err(hba->dev,
3452                 "Task Management Descriptor Memory allocation failed\n");
3453                 goto out;
3454         }
3455
3456         /* Allocate memory for local reference block */
3457         hba->lrb = devm_kcalloc(hba->dev,
3458                                 hba->nutrs, sizeof(struct ufshcd_lrb),
3459                                 GFP_KERNEL);
3460         if (!hba->lrb) {
3461                 dev_err(hba->dev, "LRB Memory allocation failed\n");
3462                 goto out;
3463         }
3464         return 0;
3465 out:
3466         return -ENOMEM;
3467 }
3468
3469 /**
3470  * ufshcd_host_memory_configure - configure local reference block with
3471  *                              memory offsets
3472  * @hba: per adapter instance
3473  *
3474  * Configure Host memory space
3475  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3476  * address.
3477  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3478  * and PRDT offset.
3479  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3480  * into local reference block.
3481  */
3482 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3483 {
3484         struct utp_transfer_req_desc *utrdlp;
3485         dma_addr_t cmd_desc_dma_addr;
3486         dma_addr_t cmd_desc_element_addr;
3487         u16 response_offset;
3488         u16 prdt_offset;
3489         int cmd_desc_size;
3490         int i;
3491
3492         utrdlp = hba->utrdl_base_addr;
3493
3494         response_offset =
3495                 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3496         prdt_offset =
3497                 offsetof(struct utp_transfer_cmd_desc, prd_table);
3498
3499         cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3500         cmd_desc_dma_addr = hba->ucdl_dma_addr;
3501
3502         for (i = 0; i < hba->nutrs; i++) {
3503                 /* Configure UTRD with command descriptor base address */
3504                 cmd_desc_element_addr =
3505                                 (cmd_desc_dma_addr + (cmd_desc_size * i));
3506                 utrdlp[i].command_desc_base_addr_lo =
3507                                 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3508                 utrdlp[i].command_desc_base_addr_hi =
3509                                 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3510
3511                 /* Response upiu and prdt offset should be in double words */
3512                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3513                         utrdlp[i].response_upiu_offset =
3514                                 cpu_to_le16(response_offset);
3515                         utrdlp[i].prd_table_offset =
3516                                 cpu_to_le16(prdt_offset);
3517                         utrdlp[i].response_upiu_length =
3518                                 cpu_to_le16(ALIGNED_UPIU_SIZE);
3519                 } else {
3520                         utrdlp[i].response_upiu_offset =
3521                                 cpu_to_le16(response_offset >> 2);
3522                         utrdlp[i].prd_table_offset =
3523                                 cpu_to_le16(prdt_offset >> 2);
3524                         utrdlp[i].response_upiu_length =
3525                                 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3526                 }
3527
3528                 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3529         }
3530 }
3531
3532 /**
3533  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3534  * @hba: per adapter instance
3535  *
3536  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3537  * in order to initialize the Unipro link startup procedure.
3538  * Once the Unipro links are up, the device connected to the controller
3539  * is detected.
3540  *
3541  * Returns 0 on success, non-zero value on failure
3542  */
3543 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3544 {
3545         struct uic_command uic_cmd = {0};
3546         int ret;
3547
3548         uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3549
3550         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3551         if (ret)
3552                 dev_dbg(hba->dev,
3553                         "dme-link-startup: error code %d\n", ret);
3554         return ret;
3555 }
3556 /**
3557  * ufshcd_dme_reset - UIC command for DME_RESET
3558  * @hba: per adapter instance
3559  *
3560  * DME_RESET command is issued in order to reset UniPro stack.
3561  * This function now deals with cold reset.
3562  *
3563  * Returns 0 on success, non-zero value on failure
3564  */
3565 static int ufshcd_dme_reset(struct ufs_hba *hba)
3566 {
3567         struct uic_command uic_cmd = {0};
3568         int ret;
3569
3570         uic_cmd.command = UIC_CMD_DME_RESET;
3571
3572         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3573         if (ret)
3574                 dev_err(hba->dev,
3575                         "dme-reset: error code %d\n", ret);
3576
3577         return ret;
3578 }
3579
3580 /**
3581  * ufshcd_dme_enable - UIC command for DME_ENABLE
3582  * @hba: per adapter instance
3583  *
3584  * DME_ENABLE command is issued in order to enable UniPro stack.
3585  *
3586  * Returns 0 on success, non-zero value on failure
3587  */
3588 static int ufshcd_dme_enable(struct ufs_hba *hba)
3589 {
3590         struct uic_command uic_cmd = {0};
3591         int ret;
3592
3593         uic_cmd.command = UIC_CMD_DME_ENABLE;
3594
3595         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3596         if (ret)
3597                 dev_err(hba->dev,
3598                         "dme-reset: error code %d\n", ret);
3599
3600         return ret;
3601 }
3602
3603 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3604 {
3605         #define MIN_DELAY_BEFORE_DME_CMDS_US    1000
3606         unsigned long min_sleep_time_us;
3607
3608         if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3609                 return;
3610
3611         /*
3612          * last_dme_cmd_tstamp will be 0 only for 1st call to
3613          * this function
3614          */
3615         if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3616                 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3617         } else {
3618                 unsigned long delta =
3619                         (unsigned long) ktime_to_us(
3620                                 ktime_sub(ktime_get(),
3621                                 hba->last_dme_cmd_tstamp));
3622
3623                 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3624                         min_sleep_time_us =
3625                                 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3626                 else
3627                         return; /* no more delay required */
3628         }
3629
3630         /* allow sleep for extra 50us if needed */
3631         usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3632 }
3633
3634 /**
3635  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3636  * @hba: per adapter instance
3637  * @attr_sel: uic command argument1
3638  * @attr_set: attribute set type as uic command argument2
3639  * @mib_val: setting value as uic command argument3
3640  * @peer: indicate whether peer or local
3641  *
3642  * Returns 0 on success, non-zero value on failure
3643  */
3644 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3645                         u8 attr_set, u32 mib_val, u8 peer)
3646 {
3647         struct uic_command uic_cmd = {0};
3648         static const char *const action[] = {
3649                 "dme-set",
3650                 "dme-peer-set"
3651         };
3652         const char *set = action[!!peer];
3653         int ret;
3654         int retries = UFS_UIC_COMMAND_RETRIES;
3655
3656         uic_cmd.command = peer ?
3657                 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3658         uic_cmd.argument1 = attr_sel;
3659         uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3660         uic_cmd.argument3 = mib_val;
3661
3662         do {
3663                 /* for peer attributes we retry upon failure */
3664                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3665                 if (ret)
3666                         dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3667                                 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3668         } while (ret && peer && --retries);
3669
3670         if (ret)
3671                 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3672                         set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3673                         UFS_UIC_COMMAND_RETRIES - retries);
3674
3675         return ret;
3676 }
3677 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3678
3679 /**
3680  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3681  * @hba: per adapter instance
3682  * @attr_sel: uic command argument1
3683  * @mib_val: the value of the attribute as returned by the UIC command
3684  * @peer: indicate whether peer or local
3685  *
3686  * Returns 0 on success, non-zero value on failure
3687  */
3688 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3689                         u32 *mib_val, u8 peer)
3690 {
3691         struct uic_command uic_cmd = {0};
3692         static const char *const action[] = {
3693                 "dme-get",
3694                 "dme-peer-get"
3695         };
3696         const char *get = action[!!peer];
3697         int ret;
3698         int retries = UFS_UIC_COMMAND_RETRIES;
3699         struct ufs_pa_layer_attr orig_pwr_info;
3700         struct ufs_pa_layer_attr temp_pwr_info;
3701         bool pwr_mode_change = false;
3702
3703         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3704                 orig_pwr_info = hba->pwr_info;
3705                 temp_pwr_info = orig_pwr_info;
3706
3707                 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3708                     orig_pwr_info.pwr_rx == FAST_MODE) {
3709                         temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3710                         temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3711                         pwr_mode_change = true;
3712                 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3713                     orig_pwr_info.pwr_rx == SLOW_MODE) {
3714                         temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3715                         temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3716                         pwr_mode_change = true;
3717                 }
3718                 if (pwr_mode_change) {
3719                         ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3720                         if (ret)
3721                                 goto out;
3722                 }
3723         }
3724
3725         uic_cmd.command = peer ?
3726                 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3727         uic_cmd.argument1 = attr_sel;
3728
3729         do {
3730                 /* for peer attributes we retry upon failure */
3731                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3732                 if (ret)
3733                         dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3734                                 get, UIC_GET_ATTR_ID(attr_sel), ret);
3735         } while (ret && peer && --retries);
3736
3737         if (ret)
3738                 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3739                         get, UIC_GET_ATTR_ID(attr_sel),
3740                         UFS_UIC_COMMAND_RETRIES - retries);
3741
3742         if (mib_val && !ret)
3743                 *mib_val = uic_cmd.argument3;
3744
3745         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3746             && pwr_mode_change)
3747                 ufshcd_change_power_mode(hba, &orig_pwr_info);
3748 out:
3749         return ret;
3750 }
3751 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3752
3753 /**
3754  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3755  * state) and waits for it to take effect.
3756  *
3757  * @hba: per adapter instance
3758  * @cmd: UIC command to execute
3759  *
3760  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3761  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3762  * and device UniPro link and hence it's final completion would be indicated by
3763  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3764  * addition to normal UIC command completion Status (UCCS). This function only
3765  * returns after the relevant status bits indicate the completion.
3766  *
3767  * Returns 0 on success, non-zero value on failure
3768  */
3769 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3770 {
3771         struct completion uic_async_done;
3772         unsigned long flags;
3773         u8 status;
3774         int ret;
3775         bool reenable_intr = false;
3776
3777         mutex_lock(&hba->uic_cmd_mutex);
3778         init_completion(&uic_async_done);
3779         ufshcd_add_delay_before_dme_cmd(hba);
3780
3781         spin_lock_irqsave(hba->host->host_lock, flags);
3782         if (ufshcd_is_link_broken(hba)) {
3783                 ret = -ENOLINK;
3784                 goto out_unlock;
3785         }
3786         hba->uic_async_done = &uic_async_done;
3787         if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3788                 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3789                 /*
3790                  * Make sure UIC command completion interrupt is disabled before
3791                  * issuing UIC command.
3792                  */
3793                 wmb();
3794                 reenable_intr = true;
3795         }
3796         ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3797         spin_unlock_irqrestore(hba->host->host_lock, flags);
3798         if (ret) {
3799                 dev_err(hba->dev,
3800                         "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3801                         cmd->command, cmd->argument3, ret);
3802                 goto out;
3803         }
3804
3805         if (!wait_for_completion_timeout(hba->uic_async_done,
3806                                          msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3807                 dev_err(hba->dev,
3808                         "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3809                         cmd->command, cmd->argument3);
3810                 ret = -ETIMEDOUT;
3811                 goto out;
3812         }
3813
3814         status = ufshcd_get_upmcrs(hba);
3815         if (status != PWR_LOCAL) {
3816                 dev_err(hba->dev,
3817                         "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
3818                         cmd->command, status);
3819                 ret = (status != PWR_OK) ? status : -1;
3820         }
3821 out:
3822         if (ret) {
3823                 ufshcd_print_host_state(hba);
3824                 ufshcd_print_pwr_info(hba);
3825                 ufshcd_print_host_regs(hba);
3826         }
3827
3828         spin_lock_irqsave(hba->host->host_lock, flags);
3829         hba->active_uic_cmd = NULL;
3830         hba->uic_async_done = NULL;
3831         if (reenable_intr)
3832                 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
3833         if (ret) {
3834                 ufshcd_set_link_broken(hba);
3835                 ufshcd_schedule_eh_work(hba);
3836         }
3837 out_unlock:
3838         spin_unlock_irqrestore(hba->host->host_lock, flags);
3839         mutex_unlock(&hba->uic_cmd_mutex);
3840
3841         return ret;
3842 }
3843
3844 /**
3845  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3846  *                              using DME_SET primitives.
3847  * @hba: per adapter instance
3848  * @mode: powr mode value
3849  *
3850  * Returns 0 on success, non-zero value on failure
3851  */
3852 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3853 {
3854         struct uic_command uic_cmd = {0};
3855         int ret;
3856
3857         if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3858                 ret = ufshcd_dme_set(hba,
3859                                 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3860                 if (ret) {
3861                         dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3862                                                 __func__, ret);
3863                         goto out;
3864                 }
3865         }
3866
3867         uic_cmd.command = UIC_CMD_DME_SET;
3868         uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3869         uic_cmd.argument3 = mode;
3870         ufshcd_hold(hba, false);
3871         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3872         ufshcd_release(hba);
3873
3874 out:
3875         return ret;
3876 }
3877
3878 int ufshcd_link_recovery(struct ufs_hba *hba)
3879 {
3880         int ret;
3881         unsigned long flags;
3882
3883         spin_lock_irqsave(hba->host->host_lock, flags);
3884         hba->ufshcd_state = UFSHCD_STATE_RESET;
3885         ufshcd_set_eh_in_progress(hba);
3886         spin_unlock_irqrestore(hba->host->host_lock, flags);
3887
3888         /* Reset the attached device */
3889         ufshcd_vops_device_reset(hba);
3890
3891         ret = ufshcd_host_reset_and_restore(hba);
3892
3893         spin_lock_irqsave(hba->host->host_lock, flags);
3894         if (ret)
3895                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3896         ufshcd_clear_eh_in_progress(hba);
3897         spin_unlock_irqrestore(hba->host->host_lock, flags);
3898
3899         if (ret)
3900                 dev_err(hba->dev, "%s: link recovery failed, err %d",
3901                         __func__, ret);
3902
3903         return ret;
3904 }
3905 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
3906
3907 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3908 {
3909         int ret;
3910         struct uic_command uic_cmd = {0};
3911         ktime_t start = ktime_get();
3912
3913         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3914
3915         uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
3916         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3917         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3918                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3919
3920         if (ret)
3921                 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3922                         __func__, ret);
3923         else
3924                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3925                                                                 POST_CHANGE);
3926
3927         return ret;
3928 }
3929
3930 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3931 {
3932         struct uic_command uic_cmd = {0};
3933         int ret;
3934         ktime_t start = ktime_get();
3935
3936         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3937
3938         uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3939         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3940         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3941                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3942
3943         if (ret) {
3944                 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3945                         __func__, ret);
3946         } else {
3947                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3948                                                                 POST_CHANGE);
3949                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3950                 hba->ufs_stats.hibern8_exit_cnt++;
3951         }
3952
3953         return ret;
3954 }
3955 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
3956
3957 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
3958 {
3959         unsigned long flags;
3960         bool update = false;
3961
3962         if (!ufshcd_is_auto_hibern8_supported(hba))
3963                 return;
3964
3965         spin_lock_irqsave(hba->host->host_lock, flags);
3966         if (hba->ahit != ahit) {
3967                 hba->ahit = ahit;
3968                 update = true;
3969         }
3970         spin_unlock_irqrestore(hba->host->host_lock, flags);
3971
3972         if (update && !pm_runtime_suspended(hba->dev)) {
3973                 pm_runtime_get_sync(hba->dev);
3974                 ufshcd_hold(hba, false);
3975                 ufshcd_auto_hibern8_enable(hba);
3976                 ufshcd_release(hba);
3977                 pm_runtime_put(hba->dev);
3978         }
3979 }
3980 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
3981
3982 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3983 {
3984         unsigned long flags;
3985
3986         if (!ufshcd_is_auto_hibern8_supported(hba))
3987                 return;
3988
3989         spin_lock_irqsave(hba->host->host_lock, flags);
3990         ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3991         spin_unlock_irqrestore(hba->host->host_lock, flags);
3992 }
3993
3994  /**
3995  * ufshcd_init_pwr_info - setting the POR (power on reset)
3996  * values in hba power info
3997  * @hba: per-adapter instance
3998  */
3999 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4000 {
4001         hba->pwr_info.gear_rx = UFS_PWM_G1;
4002         hba->pwr_info.gear_tx = UFS_PWM_G1;
4003         hba->pwr_info.lane_rx = 1;
4004         hba->pwr_info.lane_tx = 1;
4005         hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4006         hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4007         hba->pwr_info.hs_rate = 0;
4008 }
4009
4010 /**
4011  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4012  * @hba: per-adapter instance
4013  */
4014 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4015 {
4016         struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4017
4018         if (hba->max_pwr_info.is_valid)
4019                 return 0;
4020
4021         pwr_info->pwr_tx = FAST_MODE;
4022         pwr_info->pwr_rx = FAST_MODE;
4023         pwr_info->hs_rate = PA_HS_MODE_B;
4024
4025         /* Get the connected lane count */
4026         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4027                         &pwr_info->lane_rx);
4028         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4029                         &pwr_info->lane_tx);
4030
4031         if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4032                 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4033                                 __func__,
4034                                 pwr_info->lane_rx,
4035                                 pwr_info->lane_tx);
4036                 return -EINVAL;
4037         }
4038
4039         /*
4040          * First, get the maximum gears of HS speed.
4041          * If a zero value, it means there is no HSGEAR capability.
4042          * Then, get the maximum gears of PWM speed.
4043          */
4044         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4045         if (!pwr_info->gear_rx) {
4046                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4047                                 &pwr_info->gear_rx);
4048                 if (!pwr_info->gear_rx) {
4049                         dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4050                                 __func__, pwr_info->gear_rx);
4051                         return -EINVAL;
4052                 }
4053                 pwr_info->pwr_rx = SLOW_MODE;
4054         }
4055
4056         ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4057                         &pwr_info->gear_tx);
4058         if (!pwr_info->gear_tx) {
4059                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4060                                 &pwr_info->gear_tx);
4061                 if (!pwr_info->gear_tx) {
4062                         dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4063                                 __func__, pwr_info->gear_tx);
4064                         return -EINVAL;
4065                 }
4066                 pwr_info->pwr_tx = SLOW_MODE;
4067         }
4068
4069         hba->max_pwr_info.is_valid = true;
4070         return 0;
4071 }
4072
4073 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4074                              struct ufs_pa_layer_attr *pwr_mode)
4075 {
4076         int ret;
4077
4078         /* if already configured to the requested pwr_mode */
4079         if (!hba->force_pmc &&
4080             pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4081             pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4082             pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4083             pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4084             pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4085             pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4086             pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4087                 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4088                 return 0;
4089         }
4090
4091         /*
4092          * Configure attributes for power mode change with below.
4093          * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4094          * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4095          * - PA_HSSERIES
4096          */
4097         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4098         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4099                         pwr_mode->lane_rx);
4100         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4101                         pwr_mode->pwr_rx == FAST_MODE)
4102                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4103         else
4104                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4105
4106         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4107         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4108                         pwr_mode->lane_tx);
4109         if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4110                         pwr_mode->pwr_tx == FAST_MODE)
4111                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4112         else
4113                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4114
4115         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4116             pwr_mode->pwr_tx == FASTAUTO_MODE ||
4117             pwr_mode->pwr_rx == FAST_MODE ||
4118             pwr_mode->pwr_tx == FAST_MODE)
4119                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4120                                                 pwr_mode->hs_rate);
4121
4122         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4123                         DL_FC0ProtectionTimeOutVal_Default);
4124         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4125                         DL_TC0ReplayTimeOutVal_Default);
4126         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4127                         DL_AFC0ReqTimeOutVal_Default);
4128         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4129                         DL_FC1ProtectionTimeOutVal_Default);
4130         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4131                         DL_TC1ReplayTimeOutVal_Default);
4132         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4133                         DL_AFC1ReqTimeOutVal_Default);
4134
4135         ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4136                         DL_FC0ProtectionTimeOutVal_Default);
4137         ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4138                         DL_TC0ReplayTimeOutVal_Default);
4139         ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4140                         DL_AFC0ReqTimeOutVal_Default);
4141
4142         ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4143                         | pwr_mode->pwr_tx);
4144
4145         if (ret) {
4146                 dev_err(hba->dev,
4147                         "%s: power mode change failed %d\n", __func__, ret);
4148         } else {
4149                 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4150                                                                 pwr_mode);
4151
4152                 memcpy(&hba->pwr_info, pwr_mode,
4153                         sizeof(struct ufs_pa_layer_attr));
4154         }
4155
4156         return ret;
4157 }
4158
4159 /**
4160  * ufshcd_config_pwr_mode - configure a new power mode
4161  * @hba: per-adapter instance
4162  * @desired_pwr_mode: desired power configuration
4163  */
4164 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4165                 struct ufs_pa_layer_attr *desired_pwr_mode)
4166 {
4167         struct ufs_pa_layer_attr final_params = { 0 };
4168         int ret;
4169
4170         ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4171                                         desired_pwr_mode, &final_params);
4172
4173         if (ret)
4174                 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4175
4176         ret = ufshcd_change_power_mode(hba, &final_params);
4177
4178         return ret;
4179 }
4180 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4181
4182 /**
4183  * ufshcd_complete_dev_init() - checks device readiness
4184  * @hba: per-adapter instance
4185  *
4186  * Set fDeviceInit flag and poll until device toggles it.
4187  */
4188 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4189 {
4190         int err;
4191         bool flag_res = true;
4192         ktime_t timeout;
4193
4194         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4195                 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4196         if (err) {
4197                 dev_err(hba->dev,
4198                         "%s setting fDeviceInit flag failed with error %d\n",
4199                         __func__, err);
4200                 goto out;
4201         }
4202
4203         /* Poll fDeviceInit flag to be cleared */
4204         timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4205         do {
4206                 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4207                                         QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4208                 if (!flag_res)
4209                         break;
4210                 usleep_range(5000, 10000);
4211         } while (ktime_before(ktime_get(), timeout));
4212
4213         if (err) {
4214                 dev_err(hba->dev,
4215                                 "%s reading fDeviceInit flag failed with error %d\n",
4216                                 __func__, err);
4217         } else if (flag_res) {
4218                 dev_err(hba->dev,
4219                                 "%s fDeviceInit was not cleared by the device\n",
4220                                 __func__);
4221                 err = -EBUSY;
4222         }
4223 out:
4224         return err;
4225 }
4226
4227 /**
4228  * ufshcd_make_hba_operational - Make UFS controller operational
4229  * @hba: per adapter instance
4230  *
4231  * To bring UFS host controller to operational state,
4232  * 1. Enable required interrupts
4233  * 2. Configure interrupt aggregation
4234  * 3. Program UTRL and UTMRL base address
4235  * 4. Configure run-stop-registers
4236  *
4237  * Returns 0 on success, non-zero value on failure
4238  */
4239 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4240 {
4241         int err = 0;
4242         u32 reg;
4243
4244         /* Enable required interrupts */
4245         ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4246
4247         /* Configure interrupt aggregation */
4248         if (ufshcd_is_intr_aggr_allowed(hba))
4249                 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4250         else
4251                 ufshcd_disable_intr_aggr(hba);
4252
4253         /* Configure UTRL and UTMRL base address registers */
4254         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4255                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4256         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4257                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4258         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4259                         REG_UTP_TASK_REQ_LIST_BASE_L);
4260         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4261                         REG_UTP_TASK_REQ_LIST_BASE_H);
4262
4263         /*
4264          * Make sure base address and interrupt setup are updated before
4265          * enabling the run/stop registers below.
4266          */
4267         wmb();
4268
4269         /*
4270          * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4271          */
4272         reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4273         if (!(ufshcd_get_lists_status(reg))) {
4274                 ufshcd_enable_run_stop_reg(hba);
4275         } else {
4276                 dev_err(hba->dev,
4277                         "Host controller not ready to process requests");
4278                 err = -EIO;
4279         }
4280
4281         return err;
4282 }
4283 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4284
4285 /**
4286  * ufshcd_hba_stop - Send controller to reset state
4287  * @hba: per adapter instance
4288  */
4289 static inline void ufshcd_hba_stop(struct ufs_hba *hba)
4290 {
4291         unsigned long flags;
4292         int err;
4293
4294         /*
4295          * Obtain the host lock to prevent that the controller is disabled
4296          * while the UFS interrupt handler is active on another CPU.
4297          */
4298         spin_lock_irqsave(hba->host->host_lock, flags);
4299         ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4300         spin_unlock_irqrestore(hba->host->host_lock, flags);
4301
4302         err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4303                                         CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4304                                         10, 1);
4305         if (err)
4306                 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4307 }
4308
4309 /**
4310  * ufshcd_hba_execute_hce - initialize the controller
4311  * @hba: per adapter instance
4312  *
4313  * The controller resets itself and controller firmware initialization
4314  * sequence kicks off. When controller is ready it will set
4315  * the Host Controller Enable bit to 1.
4316  *
4317  * Returns 0 on success, non-zero value on failure
4318  */
4319 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4320 {
4321         int retry;
4322
4323         if (!ufshcd_is_hba_active(hba))
4324                 /* change controller state to "reset state" */
4325                 ufshcd_hba_stop(hba);
4326
4327         /* UniPro link is disabled at this point */
4328         ufshcd_set_link_off(hba);
4329
4330         ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4331
4332         /* start controller initialization sequence */
4333         ufshcd_hba_start(hba);
4334
4335         /*
4336          * To initialize a UFS host controller HCE bit must be set to 1.
4337          * During initialization the HCE bit value changes from 1->0->1.
4338          * When the host controller completes initialization sequence
4339          * it sets the value of HCE bit to 1. The same HCE bit is read back
4340          * to check if the controller has completed initialization sequence.
4341          * So without this delay the value HCE = 1, set in the previous
4342          * instruction might be read back.
4343          * This delay can be changed based on the controller.
4344          */
4345         ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4346
4347         /* wait for the host controller to complete initialization */
4348         retry = 50;
4349         while (ufshcd_is_hba_active(hba)) {
4350                 if (retry) {
4351                         retry--;
4352                 } else {
4353                         dev_err(hba->dev,
4354                                 "Controller enable failed\n");
4355                         return -EIO;
4356                 }
4357                 usleep_range(1000, 1100);
4358         }
4359
4360         /* enable UIC related interrupts */
4361         ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4362
4363         ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4364
4365         return 0;
4366 }
4367
4368 int ufshcd_hba_enable(struct ufs_hba *hba)
4369 {
4370         int ret;
4371
4372         if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4373                 ufshcd_set_link_off(hba);
4374                 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4375
4376                 /* enable UIC related interrupts */
4377                 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4378                 ret = ufshcd_dme_reset(hba);
4379                 if (!ret) {
4380                         ret = ufshcd_dme_enable(hba);
4381                         if (!ret)
4382                                 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4383                         if (ret)
4384                                 dev_err(hba->dev,
4385                                         "Host controller enable failed with non-hce\n");
4386                 }
4387         } else {
4388                 ret = ufshcd_hba_execute_hce(hba);
4389         }
4390
4391         return ret;
4392 }
4393 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4394
4395 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4396 {
4397         int tx_lanes = 0, i, err = 0;
4398
4399         if (!peer)
4400                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4401                                &tx_lanes);
4402         else
4403                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4404                                     &tx_lanes);
4405         for (i = 0; i < tx_lanes; i++) {
4406                 if (!peer)
4407                         err = ufshcd_dme_set(hba,
4408                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4409                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4410                                         0);
4411                 else
4412                         err = ufshcd_dme_peer_set(hba,
4413                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4414                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4415                                         0);
4416                 if (err) {
4417                         dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4418                                 __func__, peer, i, err);
4419                         break;
4420                 }
4421         }
4422
4423         return err;
4424 }
4425
4426 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4427 {
4428         return ufshcd_disable_tx_lcc(hba, true);
4429 }
4430
4431 void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4432                             u32 reg)
4433 {
4434         reg_hist->reg[reg_hist->pos] = reg;
4435         reg_hist->tstamp[reg_hist->pos] = ktime_get();
4436         reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4437 }
4438 EXPORT_SYMBOL_GPL(ufshcd_update_reg_hist);
4439
4440 /**
4441  * ufshcd_link_startup - Initialize unipro link startup
4442  * @hba: per adapter instance
4443  *
4444  * Returns 0 for success, non-zero in case of failure
4445  */
4446 static int ufshcd_link_startup(struct ufs_hba *hba)
4447 {
4448         int ret;
4449         int retries = DME_LINKSTARTUP_RETRIES;
4450         bool link_startup_again = false;
4451
4452         /*
4453          * If UFS device isn't active then we will have to issue link startup
4454          * 2 times to make sure the device state move to active.
4455          */
4456         if (!ufshcd_is_ufs_dev_active(hba))
4457                 link_startup_again = true;
4458
4459 link_startup:
4460         do {
4461                 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4462
4463                 ret = ufshcd_dme_link_startup(hba);
4464
4465                 /* check if device is detected by inter-connect layer */
4466                 if (!ret && !ufshcd_is_device_present(hba)) {
4467                         ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4468                                                0);
4469                         dev_err(hba->dev, "%s: Device not present\n", __func__);
4470                         ret = -ENXIO;
4471                         goto out;
4472                 }
4473
4474                 /*
4475                  * DME link lost indication is only received when link is up,
4476                  * but we can't be sure if the link is up until link startup
4477                  * succeeds. So reset the local Uni-Pro and try again.
4478                  */
4479                 if (ret && ufshcd_hba_enable(hba)) {
4480                         ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4481                                                (u32)ret);
4482                         goto out;
4483                 }
4484         } while (ret && retries--);
4485
4486         if (ret) {
4487                 /* failed to get the link up... retire */
4488                 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4489                                        (u32)ret);
4490                 goto out;
4491         }
4492
4493         if (link_startup_again) {
4494                 link_startup_again = false;
4495                 retries = DME_LINKSTARTUP_RETRIES;
4496                 goto link_startup;
4497         }
4498
4499         /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4500         ufshcd_init_pwr_info(hba);
4501         ufshcd_print_pwr_info(hba);
4502
4503         if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4504                 ret = ufshcd_disable_device_tx_lcc(hba);
4505                 if (ret)
4506                         goto out;
4507         }
4508
4509         /* Include any host controller configuration via UIC commands */
4510         ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4511         if (ret)
4512                 goto out;
4513
4514         /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4515         ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4516         ret = ufshcd_make_hba_operational(hba);
4517 out:
4518         if (ret) {
4519                 dev_err(hba->dev, "link startup failed %d\n", ret);
4520                 ufshcd_print_host_state(hba);
4521                 ufshcd_print_pwr_info(hba);
4522                 ufshcd_print_host_regs(hba);
4523         }
4524         return ret;
4525 }
4526
4527 /**
4528  * ufshcd_verify_dev_init() - Verify device initialization
4529  * @hba: per-adapter instance
4530  *
4531  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4532  * device Transport Protocol (UTP) layer is ready after a reset.
4533  * If the UTP layer at the device side is not initialized, it may
4534  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4535  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4536  */
4537 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4538 {
4539         int err = 0;
4540         int retries;
4541
4542         ufshcd_hold(hba, false);
4543         mutex_lock(&hba->dev_cmd.lock);
4544         for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4545                 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4546                                                NOP_OUT_TIMEOUT);
4547
4548                 if (!err || err == -ETIMEDOUT)
4549                         break;
4550
4551                 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4552         }
4553         mutex_unlock(&hba->dev_cmd.lock);
4554         ufshcd_release(hba);
4555
4556         if (err)
4557                 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4558         return err;
4559 }
4560
4561 /**
4562  * ufshcd_set_queue_depth - set lun queue depth
4563  * @sdev: pointer to SCSI device
4564  *
4565  * Read bLUQueueDepth value and activate scsi tagged command
4566  * queueing. For WLUN, queue depth is set to 1. For best-effort
4567  * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4568  * value that host can queue.
4569  */
4570 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4571 {
4572         int ret = 0;
4573         u8 lun_qdepth;
4574         struct ufs_hba *hba;
4575
4576         hba = shost_priv(sdev->host);
4577
4578         lun_qdepth = hba->nutrs;
4579         ret = ufshcd_read_unit_desc_param(hba,
4580                                           ufshcd_scsi_to_upiu_lun(sdev->lun),
4581                                           UNIT_DESC_PARAM_LU_Q_DEPTH,
4582                                           &lun_qdepth,
4583                                           sizeof(lun_qdepth));
4584
4585         /* Some WLUN doesn't support unit descriptor */
4586         if (ret == -EOPNOTSUPP)
4587                 lun_qdepth = 1;
4588         else if (!lun_qdepth)
4589                 /* eventually, we can figure out the real queue depth */
4590                 lun_qdepth = hba->nutrs;
4591         else
4592                 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4593
4594         dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4595                         __func__, lun_qdepth);
4596         scsi_change_queue_depth(sdev, lun_qdepth);
4597 }
4598
4599 /*
4600  * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4601  * @hba: per-adapter instance
4602  * @lun: UFS device lun id
4603  * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4604  *
4605  * Returns 0 in case of success and b_lu_write_protect status would be returned
4606  * @b_lu_write_protect parameter.
4607  * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4608  * Returns -EINVAL in case of invalid parameters passed to this function.
4609  */
4610 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4611                             u8 lun,
4612                             u8 *b_lu_write_protect)
4613 {
4614         int ret;
4615
4616         if (!b_lu_write_protect)
4617                 ret = -EINVAL;
4618         /*
4619          * According to UFS device spec, RPMB LU can't be write
4620          * protected so skip reading bLUWriteProtect parameter for
4621          * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4622          */
4623         else if (lun >= hba->dev_info.max_lu_supported)
4624                 ret = -ENOTSUPP;
4625         else
4626                 ret = ufshcd_read_unit_desc_param(hba,
4627                                           lun,
4628                                           UNIT_DESC_PARAM_LU_WR_PROTECT,
4629                                           b_lu_write_protect,
4630                                           sizeof(*b_lu_write_protect));
4631         return ret;
4632 }
4633
4634 /**
4635  * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4636  * status
4637  * @hba: per-adapter instance
4638  * @sdev: pointer to SCSI device
4639  *
4640  */
4641 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4642                                                     struct scsi_device *sdev)
4643 {
4644         if (hba->dev_info.f_power_on_wp_en &&
4645             !hba->dev_info.is_lu_power_on_wp) {
4646                 u8 b_lu_write_protect;
4647
4648                 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4649                                       &b_lu_write_protect) &&
4650                     (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4651                         hba->dev_info.is_lu_power_on_wp = true;
4652         }
4653 }
4654
4655 /**
4656  * ufshcd_slave_alloc - handle initial SCSI device configurations
4657  * @sdev: pointer to SCSI device
4658  *
4659  * Returns success
4660  */
4661 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4662 {
4663         struct ufs_hba *hba;
4664
4665         hba = shost_priv(sdev->host);
4666
4667         /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4668         sdev->use_10_for_ms = 1;
4669
4670         /* DBD field should be set to 1 in mode sense(10) */
4671         sdev->set_dbd_for_ms = 1;
4672
4673         /* allow SCSI layer to restart the device in case of errors */
4674         sdev->allow_restart = 1;
4675
4676         /* REPORT SUPPORTED OPERATION CODES is not supported */
4677         sdev->no_report_opcodes = 1;
4678
4679         /* WRITE_SAME command is not supported */
4680         sdev->no_write_same = 1;
4681
4682         ufshcd_set_queue_depth(sdev);
4683
4684         ufshcd_get_lu_power_on_wp_status(hba, sdev);
4685
4686         return 0;
4687 }
4688
4689 /**
4690  * ufshcd_change_queue_depth - change queue depth
4691  * @sdev: pointer to SCSI device
4692  * @depth: required depth to set
4693  *
4694  * Change queue depth and make sure the max. limits are not crossed.
4695  */
4696 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4697 {
4698         struct ufs_hba *hba = shost_priv(sdev->host);
4699
4700         if (depth > hba->nutrs)
4701                 depth = hba->nutrs;
4702         return scsi_change_queue_depth(sdev, depth);
4703 }
4704
4705 /**
4706  * ufshcd_slave_configure - adjust SCSI device configurations
4707  * @sdev: pointer to SCSI device
4708  */
4709 static int ufshcd_slave_configure(struct scsi_device *sdev)
4710 {
4711         struct ufs_hba *hba = shost_priv(sdev->host);
4712         struct request_queue *q = sdev->request_queue;
4713
4714         blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4715
4716         if (ufshcd_is_rpm_autosuspend_allowed(hba))
4717                 sdev->rpm_autosuspend = 1;
4718
4719         ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
4720
4721         return 0;
4722 }
4723
4724 /**
4725  * ufshcd_slave_destroy - remove SCSI device configurations
4726  * @sdev: pointer to SCSI device
4727  */
4728 static void ufshcd_slave_destroy(struct scsi_device *sdev)
4729 {
4730         struct ufs_hba *hba;
4731
4732         hba = shost_priv(sdev->host);
4733         /* Drop the reference as it won't be needed anymore */
4734         if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4735                 unsigned long flags;
4736
4737                 spin_lock_irqsave(hba->host->host_lock, flags);
4738                 hba->sdev_ufs_device = NULL;
4739                 spin_unlock_irqrestore(hba->host->host_lock, flags);
4740         }
4741 }
4742
4743 /**
4744  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4745  * @lrbp: pointer to local reference block of completed command
4746  * @scsi_status: SCSI command status
4747  *
4748  * Returns value base on SCSI command status
4749  */
4750 static inline int
4751 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4752 {
4753         int result = 0;
4754
4755         switch (scsi_status) {
4756         case SAM_STAT_CHECK_CONDITION:
4757                 ufshcd_copy_sense_data(lrbp);
4758                 fallthrough;
4759         case SAM_STAT_GOOD:
4760                 result |= DID_OK << 16 |
4761                           COMMAND_COMPLETE << 8 |
4762                           scsi_status;
4763                 break;
4764         case SAM_STAT_TASK_SET_FULL:
4765         case SAM_STAT_BUSY:
4766         case SAM_STAT_TASK_ABORTED:
4767                 ufshcd_copy_sense_data(lrbp);
4768                 result |= scsi_status;
4769                 break;
4770         default:
4771                 result |= DID_ERROR << 16;
4772                 break;
4773         } /* end of switch */
4774
4775         return result;
4776 }
4777
4778 /**
4779  * ufshcd_transfer_rsp_status - Get overall status of the response
4780  * @hba: per adapter instance
4781  * @lrbp: pointer to local reference block of completed command
4782  *
4783  * Returns result of the command to notify SCSI midlayer
4784  */
4785 static inline int
4786 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4787 {
4788         int result = 0;
4789         int scsi_status;
4790         int ocs;
4791
4792         /* overall command status of utrd */
4793         ocs = ufshcd_get_tr_ocs(lrbp);
4794
4795         if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
4796                 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
4797                                         MASK_RSP_UPIU_RESULT)
4798                         ocs = OCS_SUCCESS;
4799         }
4800
4801         switch (ocs) {
4802         case OCS_SUCCESS:
4803                 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
4804                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
4805                 switch (result) {
4806                 case UPIU_TRANSACTION_RESPONSE:
4807                         /*
4808                          * get the response UPIU result to extract
4809                          * the SCSI command status
4810                          */
4811                         result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4812
4813                         /*
4814                          * get the result based on SCSI status response
4815                          * to notify the SCSI midlayer of the command status
4816                          */
4817                         scsi_status = result & MASK_SCSI_STATUS;
4818                         result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
4819
4820                         /*
4821                          * Currently we are only supporting BKOPs exception
4822                          * events hence we can ignore BKOPs exception event
4823                          * during power management callbacks. BKOPs exception
4824                          * event is not expected to be raised in runtime suspend
4825                          * callback as it allows the urgent bkops.
4826                          * During system suspend, we are anyway forcefully
4827                          * disabling the bkops and if urgent bkops is needed
4828                          * it will be enabled on system resume. Long term
4829                          * solution could be to abort the system suspend if
4830                          * UFS device needs urgent BKOPs.
4831                          */
4832                         if (!hba->pm_op_in_progress &&
4833                             ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4834                             schedule_work(&hba->eeh_work)) {
4835                                 /*
4836                                  * Prevent suspend once eeh_work is scheduled
4837                                  * to avoid deadlock between ufshcd_suspend
4838                                  * and exception event handler.
4839                                  */
4840                                 pm_runtime_get_noresume(hba->dev);
4841                         }
4842                         break;
4843                 case UPIU_TRANSACTION_REJECT_UPIU:
4844                         /* TODO: handle Reject UPIU Response */
4845                         result = DID_ERROR << 16;
4846                         dev_err(hba->dev,
4847                                 "Reject UPIU not fully implemented\n");
4848                         break;
4849                 default:
4850                         dev_err(hba->dev,
4851                                 "Unexpected request response code = %x\n",
4852                                 result);
4853                         result = DID_ERROR << 16;
4854                         break;
4855                 }
4856                 break;
4857         case OCS_ABORTED:
4858                 result |= DID_ABORT << 16;
4859                 break;
4860         case OCS_INVALID_COMMAND_STATUS:
4861                 result |= DID_REQUEUE << 16;
4862                 break;
4863         case OCS_INVALID_CMD_TABLE_ATTR:
4864         case OCS_INVALID_PRDT_ATTR:
4865         case OCS_MISMATCH_DATA_BUF_SIZE:
4866         case OCS_MISMATCH_RESP_UPIU_SIZE:
4867         case OCS_PEER_COMM_FAILURE:
4868         case OCS_FATAL_ERROR:
4869         case OCS_DEVICE_FATAL_ERROR:
4870         case OCS_INVALID_CRYPTO_CONFIG:
4871         case OCS_GENERAL_CRYPTO_ERROR:
4872         default:
4873                 result |= DID_ERROR << 16;
4874                 dev_err(hba->dev,
4875                                 "OCS error from controller = %x for tag %d\n",
4876                                 ocs, lrbp->task_tag);
4877                 ufshcd_print_host_regs(hba);
4878                 ufshcd_print_host_state(hba);
4879                 break;
4880         } /* end of switch */
4881
4882         if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
4883                 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
4884         return result;
4885 }
4886
4887 /**
4888  * ufshcd_uic_cmd_compl - handle completion of uic command
4889  * @hba: per adapter instance
4890  * @intr_status: interrupt status generated by the controller
4891  *
4892  * Returns
4893  *  IRQ_HANDLED - If interrupt is valid
4894  *  IRQ_NONE    - If invalid interrupt
4895  */
4896 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
4897 {
4898         irqreturn_t retval = IRQ_NONE;
4899
4900         if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
4901                 hba->active_uic_cmd->argument2 |=
4902                         ufshcd_get_uic_cmd_result(hba);
4903                 hba->active_uic_cmd->argument3 =
4904                         ufshcd_get_dme_attr_val(hba);
4905                 complete(&hba->active_uic_cmd->done);
4906                 retval = IRQ_HANDLED;
4907         }
4908
4909         if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
4910                 complete(hba->uic_async_done);
4911                 retval = IRQ_HANDLED;
4912         }
4913
4914         if (retval == IRQ_HANDLED)
4915                 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
4916                                              "complete");
4917         return retval;
4918 }
4919
4920 /**
4921  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
4922  * @hba: per adapter instance
4923  * @completed_reqs: requests to complete
4924  */
4925 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4926                                         unsigned long completed_reqs)
4927 {
4928         struct ufshcd_lrb *lrbp;
4929         struct scsi_cmnd *cmd;
4930         int result;
4931         int index;
4932
4933         for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4934                 lrbp = &hba->lrb[index];
4935                 lrbp->compl_time_stamp = ktime_get();
4936                 cmd = lrbp->cmd;
4937                 if (cmd) {
4938                         ufshcd_add_command_trace(hba, index, "complete");
4939                         result = ufshcd_transfer_rsp_status(hba, lrbp);
4940                         scsi_dma_unmap(cmd);
4941                         cmd->result = result;
4942                         /* Mark completed command as NULL in LRB */
4943                         lrbp->cmd = NULL;
4944                         /* Do not touch lrbp after scsi done */
4945                         cmd->scsi_done(cmd);
4946                         __ufshcd_release(hba);
4947                 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4948                         lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
4949                         if (hba->dev_cmd.complete) {
4950                                 ufshcd_add_command_trace(hba, index,
4951                                                 "dev_complete");
4952                                 complete(hba->dev_cmd.complete);
4953                         }
4954                 }
4955                 if (ufshcd_is_clkscaling_supported(hba))
4956                         hba->clk_scaling.active_reqs--;
4957         }
4958
4959         /* clear corresponding bits of completed commands */
4960         hba->outstanding_reqs ^= completed_reqs;
4961
4962         ufshcd_clk_scaling_update_busy(hba);
4963 }
4964
4965 /**
4966  * ufshcd_transfer_req_compl - handle SCSI and query command completion
4967  * @hba: per adapter instance
4968  *
4969  * Returns
4970  *  IRQ_HANDLED - If interrupt is valid
4971  *  IRQ_NONE    - If invalid interrupt
4972  */
4973 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
4974 {
4975         unsigned long completed_reqs;
4976         u32 tr_doorbell;
4977
4978         /* Resetting interrupt aggregation counters first and reading the
4979          * DOOR_BELL afterward allows us to handle all the completed requests.
4980          * In order to prevent other interrupts starvation the DB is read once
4981          * after reset. The down side of this solution is the possibility of
4982          * false interrupt if device completes another request after resetting
4983          * aggregation and before reading the DB.
4984          */
4985         if (ufshcd_is_intr_aggr_allowed(hba) &&
4986             !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
4987                 ufshcd_reset_intr_aggr(hba);
4988
4989         tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4990         completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4991
4992         if (completed_reqs) {
4993                 __ufshcd_transfer_req_compl(hba, completed_reqs);
4994                 return IRQ_HANDLED;
4995         } else {
4996                 return IRQ_NONE;
4997         }
4998 }
4999
5000 /**
5001  * ufshcd_disable_ee - disable exception event
5002  * @hba: per-adapter instance
5003  * @mask: exception event to disable
5004  *
5005  * Disables exception event in the device so that the EVENT_ALERT
5006  * bit is not set.
5007  *
5008  * Returns zero on success, non-zero error value on failure.
5009  */
5010 static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5011 {
5012         int err = 0;
5013         u32 val;
5014
5015         if (!(hba->ee_ctrl_mask & mask))
5016                 goto out;
5017
5018         val = hba->ee_ctrl_mask & ~mask;
5019         val &= MASK_EE_STATUS;
5020         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5021                         QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
5022         if (!err)
5023                 hba->ee_ctrl_mask &= ~mask;
5024 out:
5025         return err;
5026 }
5027
5028 /**
5029  * ufshcd_enable_ee - enable exception event
5030  * @hba: per-adapter instance
5031  * @mask: exception event to enable
5032  *
5033  * Enable corresponding exception event in the device to allow
5034  * device to alert host in critical scenarios.
5035  *
5036  * Returns zero on success, non-zero error value on failure.
5037  */
5038 static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5039 {
5040         int err = 0;
5041         u32 val;
5042
5043         if (hba->ee_ctrl_mask & mask)
5044                 goto out;
5045
5046         val = hba->ee_ctrl_mask | mask;
5047         val &= MASK_EE_STATUS;
5048         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5049                         QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
5050         if (!err)
5051                 hba->ee_ctrl_mask |= mask;
5052 out:
5053         return err;
5054 }
5055
5056 /**
5057  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5058  * @hba: per-adapter instance
5059  *
5060  * Allow device to manage background operations on its own. Enabling
5061  * this might lead to inconsistent latencies during normal data transfers
5062  * as the device is allowed to manage its own way of handling background
5063  * operations.
5064  *
5065  * Returns zero on success, non-zero on failure.
5066  */
5067 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5068 {
5069         int err = 0;
5070
5071         if (hba->auto_bkops_enabled)
5072                 goto out;
5073
5074         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5075                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5076         if (err) {
5077                 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5078                                 __func__, err);
5079                 goto out;
5080         }
5081
5082         hba->auto_bkops_enabled = true;
5083         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5084
5085         /* No need of URGENT_BKOPS exception from the device */
5086         err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5087         if (err)
5088                 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5089                                 __func__, err);
5090 out:
5091         return err;
5092 }
5093
5094 /**
5095  * ufshcd_disable_auto_bkops - block device in doing background operations
5096  * @hba: per-adapter instance
5097  *
5098  * Disabling background operations improves command response latency but
5099  * has drawback of device moving into critical state where the device is
5100  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5101  * host is idle so that BKOPS are managed effectively without any negative
5102  * impacts.
5103  *
5104  * Returns zero on success, non-zero on failure.
5105  */
5106 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5107 {
5108         int err = 0;
5109
5110         if (!hba->auto_bkops_enabled)
5111                 goto out;
5112
5113         /*
5114          * If host assisted BKOPs is to be enabled, make sure
5115          * urgent bkops exception is allowed.
5116          */
5117         err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5118         if (err) {
5119                 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5120                                 __func__, err);
5121                 goto out;
5122         }
5123
5124         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5125                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5126         if (err) {
5127                 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5128                                 __func__, err);
5129                 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5130                 goto out;
5131         }
5132
5133         hba->auto_bkops_enabled = false;
5134         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5135         hba->is_urgent_bkops_lvl_checked = false;
5136 out:
5137         return err;
5138 }
5139
5140 /**
5141  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5142  * @hba: per adapter instance
5143  *
5144  * After a device reset the device may toggle the BKOPS_EN flag
5145  * to default value. The s/w tracking variables should be updated
5146  * as well. This function would change the auto-bkops state based on
5147  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5148  */
5149 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5150 {
5151         if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5152                 hba->auto_bkops_enabled = false;
5153                 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5154                 ufshcd_enable_auto_bkops(hba);
5155         } else {
5156                 hba->auto_bkops_enabled = true;
5157                 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5158                 ufshcd_disable_auto_bkops(hba);
5159         }
5160         hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5161         hba->is_urgent_bkops_lvl_checked = false;
5162 }
5163
5164 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5165 {
5166         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5167                         QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5168 }
5169
5170 /**
5171  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5172  * @hba: per-adapter instance
5173  * @status: bkops_status value
5174  *
5175  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5176  * flag in the device to permit background operations if the device
5177  * bkops_status is greater than or equal to "status" argument passed to
5178  * this function, disable otherwise.
5179  *
5180  * Returns 0 for success, non-zero in case of failure.
5181  *
5182  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5183  * to know whether auto bkops is enabled or disabled after this function
5184  * returns control to it.
5185  */
5186 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5187                              enum bkops_status status)
5188 {
5189         int err;
5190         u32 curr_status = 0;
5191
5192         err = ufshcd_get_bkops_status(hba, &curr_status);
5193         if (err) {
5194                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5195                                 __func__, err);
5196                 goto out;
5197         } else if (curr_status > BKOPS_STATUS_MAX) {
5198                 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5199                                 __func__, curr_status);
5200                 err = -EINVAL;
5201                 goto out;
5202         }
5203
5204         if (curr_status >= status)
5205                 err = ufshcd_enable_auto_bkops(hba);
5206         else
5207                 err = ufshcd_disable_auto_bkops(hba);
5208 out:
5209         return err;
5210 }
5211
5212 /**
5213  * ufshcd_urgent_bkops - handle urgent bkops exception event
5214  * @hba: per-adapter instance
5215  *
5216  * Enable fBackgroundOpsEn flag in the device to permit background
5217  * operations.
5218  *
5219  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5220  * and negative error value for any other failure.
5221  */
5222 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5223 {
5224         return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5225 }
5226
5227 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5228 {
5229         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5230                         QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5231 }
5232
5233 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5234 {
5235         int err;
5236         u32 curr_status = 0;
5237
5238         if (hba->is_urgent_bkops_lvl_checked)
5239                 goto enable_auto_bkops;
5240
5241         err = ufshcd_get_bkops_status(hba, &curr_status);
5242         if (err) {
5243                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5244                                 __func__, err);
5245                 goto out;
5246         }
5247
5248         /*
5249          * We are seeing that some devices are raising the urgent bkops
5250          * exception events even when BKOPS status doesn't indicate performace
5251          * impacted or critical. Handle these device by determining their urgent
5252          * bkops status at runtime.
5253          */
5254         if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5255                 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5256                                 __func__, curr_status);
5257                 /* update the current status as the urgent bkops level */
5258                 hba->urgent_bkops_lvl = curr_status;
5259                 hba->is_urgent_bkops_lvl_checked = true;
5260         }
5261
5262 enable_auto_bkops:
5263         err = ufshcd_enable_auto_bkops(hba);
5264 out:
5265         if (err < 0)
5266                 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5267                                 __func__, err);
5268 }
5269
5270 static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable)
5271 {
5272         int ret;
5273         u8 index;
5274         enum query_opcode opcode;
5275
5276         if (!ufshcd_is_wb_allowed(hba))
5277                 return 0;
5278
5279         if (!(enable ^ hba->wb_enabled))
5280                 return 0;
5281         if (enable)
5282                 opcode = UPIU_QUERY_OPCODE_SET_FLAG;
5283         else
5284                 opcode = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5285
5286         index = ufshcd_wb_get_query_index(hba);
5287         ret = ufshcd_query_flag_retry(hba, opcode,
5288                                       QUERY_FLAG_IDN_WB_EN, index, NULL);
5289         if (ret) {
5290                 dev_err(hba->dev, "%s write booster %s failed %d\n",
5291                         __func__, enable ? "enable" : "disable", ret);
5292                 return ret;
5293         }
5294
5295         hba->wb_enabled = enable;
5296         dev_dbg(hba->dev, "%s write booster %s %d\n",
5297                         __func__, enable ? "enable" : "disable", ret);
5298
5299         return ret;
5300 }
5301
5302 static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5303 {
5304         int val;
5305         u8 index;
5306
5307         if (set)
5308                 val =  UPIU_QUERY_OPCODE_SET_FLAG;
5309         else
5310                 val = UPIU_QUERY_OPCODE_CLEAR_FLAG;
5311
5312         index = ufshcd_wb_get_query_index(hba);
5313         return ufshcd_query_flag_retry(hba, val,
5314                                 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8,
5315                                 index, NULL);
5316 }
5317
5318 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5319 {
5320         if (hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL)
5321                 return;
5322
5323         if (enable)
5324                 ufshcd_wb_buf_flush_enable(hba);
5325         else
5326                 ufshcd_wb_buf_flush_disable(hba);
5327
5328 }
5329
5330 static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba)
5331 {
5332         int ret;
5333         u8 index;
5334
5335         if (!ufshcd_is_wb_allowed(hba) || hba->wb_buf_flush_enabled)
5336                 return 0;
5337
5338         index = ufshcd_wb_get_query_index(hba);
5339         ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5340                                       QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
5341                                       index, NULL);
5342         if (ret)
5343                 dev_err(hba->dev, "%s WB - buf flush enable failed %d\n",
5344                         __func__, ret);
5345         else
5346                 hba->wb_buf_flush_enabled = true;
5347
5348         dev_dbg(hba->dev, "WB - Flush enabled: %d\n", ret);
5349         return ret;
5350 }
5351
5352 static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba)
5353 {
5354         int ret;
5355         u8 index;
5356
5357         if (!ufshcd_is_wb_allowed(hba) || !hba->wb_buf_flush_enabled)
5358                 return 0;
5359
5360         index = ufshcd_wb_get_query_index(hba);
5361         ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5362                                       QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
5363                                       index, NULL);
5364         if (ret) {
5365                 dev_warn(hba->dev, "%s: WB - buf flush disable failed %d\n",
5366                          __func__, ret);
5367         } else {
5368                 hba->wb_buf_flush_enabled = false;
5369                 dev_dbg(hba->dev, "WB - Flush disabled: %d\n", ret);
5370         }
5371
5372         return ret;
5373 }
5374
5375 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5376                                                 u32 avail_buf)
5377 {
5378         u32 cur_buf;
5379         int ret;
5380         u8 index;
5381
5382         index = ufshcd_wb_get_query_index(hba);
5383         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5384                                               QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5385                                               index, 0, &cur_buf);
5386         if (ret) {
5387                 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5388                         __func__, ret);
5389                 return false;
5390         }
5391
5392         if (!cur_buf) {
5393                 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5394                          cur_buf);
5395                 return false;
5396         }
5397         /* Let it continue to flush when available buffer exceeds threshold */
5398         if (avail_buf < hba->vps->wb_flush_threshold)
5399                 return true;
5400
5401         return false;
5402 }
5403
5404 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5405 {
5406         int ret;
5407         u32 avail_buf;
5408         u8 index;
5409
5410         if (!ufshcd_is_wb_allowed(hba))
5411                 return false;
5412         /*
5413          * The ufs device needs the vcc to be ON to flush.
5414          * With user-space reduction enabled, it's enough to enable flush
5415          * by checking only the available buffer. The threshold
5416          * defined here is > 90% full.
5417          * With user-space preserved enabled, the current-buffer
5418          * should be checked too because the wb buffer size can reduce
5419          * when disk tends to be full. This info is provided by current
5420          * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5421          * keeping vcc on when current buffer is empty.
5422          */
5423         index = ufshcd_wb_get_query_index(hba);
5424         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5425                                       QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5426                                       index, 0, &avail_buf);
5427         if (ret) {
5428                 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5429                          __func__, ret);
5430                 return false;
5431         }
5432
5433         if (!hba->dev_info.b_presrv_uspc_en) {
5434                 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
5435                         return true;
5436                 return false;
5437         }
5438
5439         return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5440 }
5441
5442 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5443 {
5444         struct ufs_hba *hba = container_of(to_delayed_work(work),
5445                                            struct ufs_hba,
5446                                            rpm_dev_flush_recheck_work);
5447         /*
5448          * To prevent unnecessary VCC power drain after device finishes
5449          * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5450          * after a certain delay to recheck the threshold by next runtime
5451          * suspend.
5452          */
5453         pm_runtime_get_sync(hba->dev);
5454         pm_runtime_put_sync(hba->dev);
5455 }
5456
5457 /**
5458  * ufshcd_exception_event_handler - handle exceptions raised by device
5459  * @work: pointer to work data
5460  *
5461  * Read bExceptionEventStatus attribute from the device and handle the
5462  * exception event accordingly.
5463  */
5464 static void ufshcd_exception_event_handler(struct work_struct *work)
5465 {
5466         struct ufs_hba *hba;
5467         int err;
5468         u32 status = 0;
5469         hba = container_of(work, struct ufs_hba, eeh_work);
5470
5471         pm_runtime_get_sync(hba->dev);
5472         ufshcd_scsi_block_requests(hba);
5473         err = ufshcd_get_ee_status(hba, &status);
5474         if (err) {
5475                 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5476                                 __func__, err);
5477                 goto out;
5478         }
5479
5480         status &= hba->ee_ctrl_mask;
5481
5482         if (status & MASK_EE_URGENT_BKOPS)
5483                 ufshcd_bkops_exception_event_handler(hba);
5484
5485 out:
5486         ufshcd_scsi_unblock_requests(hba);
5487         /*
5488          * pm_runtime_get_noresume is called while scheduling
5489          * eeh_work to avoid suspend racing with exception work.
5490          * Hence decrement usage counter using pm_runtime_put_noidle
5491          * to allow suspend on completion of exception event handler.
5492          */
5493         pm_runtime_put_noidle(hba->dev);
5494         pm_runtime_put(hba->dev);
5495         return;
5496 }
5497
5498 /* Complete requests that have door-bell cleared */
5499 static void ufshcd_complete_requests(struct ufs_hba *hba)
5500 {
5501         ufshcd_transfer_req_compl(hba);
5502         ufshcd_tmc_handler(hba);
5503 }
5504
5505 /**
5506  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5507  *                              to recover from the DL NAC errors or not.
5508  * @hba: per-adapter instance
5509  *
5510  * Returns true if error handling is required, false otherwise
5511  */
5512 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5513 {
5514         unsigned long flags;
5515         bool err_handling = true;
5516
5517         spin_lock_irqsave(hba->host->host_lock, flags);
5518         /*
5519          * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5520          * device fatal error and/or DL NAC & REPLAY timeout errors.
5521          */
5522         if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5523                 goto out;
5524
5525         if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5526             ((hba->saved_err & UIC_ERROR) &&
5527              (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5528                 goto out;
5529
5530         if ((hba->saved_err & UIC_ERROR) &&
5531             (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5532                 int err;
5533                 /*
5534                  * wait for 50ms to see if we can get any other errors or not.
5535                  */
5536                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5537                 msleep(50);
5538                 spin_lock_irqsave(hba->host->host_lock, flags);
5539
5540                 /*
5541                  * now check if we have got any other severe errors other than
5542                  * DL NAC error?
5543                  */
5544                 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5545                     ((hba->saved_err & UIC_ERROR) &&
5546                     (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5547                         goto out;
5548
5549                 /*
5550                  * As DL NAC is the only error received so far, send out NOP
5551                  * command to confirm if link is still active or not.
5552                  *   - If we don't get any response then do error recovery.
5553                  *   - If we get response then clear the DL NAC error bit.
5554                  */
5555
5556                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5557                 err = ufshcd_verify_dev_init(hba);
5558                 spin_lock_irqsave(hba->host->host_lock, flags);
5559
5560                 if (err)
5561                         goto out;
5562
5563                 /* Link seems to be alive hence ignore the DL NAC errors */
5564                 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5565                         hba->saved_err &= ~UIC_ERROR;
5566                 /* clear NAC error */
5567                 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5568                 if (!hba->saved_uic_err)
5569                         err_handling = false;
5570         }
5571 out:
5572         spin_unlock_irqrestore(hba->host->host_lock, flags);
5573         return err_handling;
5574 }
5575
5576 /* host lock must be held before calling this func */
5577 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
5578 {
5579         return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
5580                (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
5581 }
5582
5583 /* host lock must be held before calling this func */
5584 static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
5585 {
5586         /* handle fatal errors only when link is not in error state */
5587         if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
5588                 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
5589                     ufshcd_is_saved_err_fatal(hba))
5590                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
5591                 else
5592                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
5593                 queue_work(hba->eh_wq, &hba->eh_work);
5594         }
5595 }
5596
5597 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5598 {
5599         pm_runtime_get_sync(hba->dev);
5600         if (pm_runtime_suspended(hba->dev)) {
5601                 /*
5602                  * Don't assume anything of pm_runtime_get_sync(), if
5603                  * resume fails, irq and clocks can be OFF, and powers
5604                  * can be OFF or in LPM.
5605                  */
5606                 ufshcd_setup_hba_vreg(hba, true);
5607                 ufshcd_enable_irq(hba);
5608                 ufshcd_setup_vreg(hba, true);
5609                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5610                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5611                 ufshcd_hold(hba, false);
5612                 if (!ufshcd_is_clkgating_allowed(hba))
5613                         ufshcd_setup_clocks(hba, true);
5614                 ufshcd_release(hba);
5615                 ufshcd_vops_resume(hba, UFS_RUNTIME_PM);
5616         } else {
5617                 ufshcd_hold(hba, false);
5618                 if (hba->clk_scaling.is_allowed) {
5619                         cancel_work_sync(&hba->clk_scaling.suspend_work);
5620                         cancel_work_sync(&hba->clk_scaling.resume_work);
5621                         ufshcd_suspend_clkscaling(hba);
5622                 }
5623         }
5624 }
5625
5626 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5627 {
5628         ufshcd_release(hba);
5629         if (hba->clk_scaling.is_allowed)
5630                 ufshcd_resume_clkscaling(hba);
5631         pm_runtime_put(hba->dev);
5632 }
5633
5634 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5635 {
5636         return (hba->ufshcd_state == UFSHCD_STATE_ERROR ||
5637                 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
5638                         ufshcd_is_link_broken(hba))));
5639 }
5640
5641 #ifdef CONFIG_PM
5642 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5643 {
5644         struct Scsi_Host *shost = hba->host;
5645         struct scsi_device *sdev;
5646         struct request_queue *q;
5647         int ret;
5648
5649         /*
5650          * Set RPM status of hba device to RPM_ACTIVE,
5651          * this also clears its runtime error.
5652          */
5653         ret = pm_runtime_set_active(hba->dev);
5654         /*
5655          * If hba device had runtime error, we also need to resume those
5656          * scsi devices under hba in case any of them has failed to be
5657          * resumed due to hba runtime resume failure. This is to unblock
5658          * blk_queue_enter in case there are bios waiting inside it.
5659          */
5660         if (!ret) {
5661                 shost_for_each_device(sdev, shost) {
5662                         q = sdev->request_queue;
5663                         if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
5664                                        q->rpm_status == RPM_SUSPENDING))
5665                                 pm_request_resume(q->dev);
5666                 }
5667         }
5668 }
5669 #else
5670 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
5671 {
5672 }
5673 #endif
5674
5675 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
5676 {
5677         struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
5678         u32 mode;
5679
5680         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
5681
5682         if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
5683                 return true;
5684
5685         if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
5686                 return true;
5687
5688         return false;
5689 }
5690
5691 /**
5692  * ufshcd_err_handler - handle UFS errors that require s/w attention
5693  * @work: pointer to work structure
5694  */
5695 static void ufshcd_err_handler(struct work_struct *work)
5696 {
5697         struct ufs_hba *hba;
5698         unsigned long flags;
5699         bool err_xfer = false;
5700         bool err_tm = false;
5701         int err = 0, pmc_err;
5702         int tag;
5703         bool needs_reset = false, needs_restore = false;
5704
5705         hba = container_of(work, struct ufs_hba, eh_work);
5706
5707         spin_lock_irqsave(hba->host->host_lock, flags);
5708         if (ufshcd_err_handling_should_stop(hba)) {
5709                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
5710                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5711                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5712                 return;
5713         }
5714         ufshcd_set_eh_in_progress(hba);
5715         spin_unlock_irqrestore(hba->host->host_lock, flags);
5716         ufshcd_err_handling_prepare(hba);
5717         spin_lock_irqsave(hba->host->host_lock, flags);
5718         ufshcd_scsi_block_requests(hba);
5719         /*
5720          * A full reset and restore might have happened after preparation
5721          * is finished, double check whether we should stop.
5722          */
5723         if (ufshcd_err_handling_should_stop(hba)) {
5724                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
5725                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5726                 goto out;
5727         }
5728         hba->ufshcd_state = UFSHCD_STATE_RESET;
5729
5730         /* Complete requests that have door-bell cleared by h/w */
5731         ufshcd_complete_requests(hba);
5732
5733         if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5734                 bool ret;
5735
5736                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5737                 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5738                 ret = ufshcd_quirk_dl_nac_errors(hba);
5739                 spin_lock_irqsave(hba->host->host_lock, flags);
5740                 if (!ret && !hba->force_reset && ufshcd_is_link_active(hba))
5741                         goto skip_err_handling;
5742         }
5743
5744         if (hba->force_reset || ufshcd_is_link_broken(hba) ||
5745             ufshcd_is_saved_err_fatal(hba) ||
5746             ((hba->saved_err & UIC_ERROR) &&
5747              (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5748                                     UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5749                 needs_reset = true;
5750
5751         if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
5752             (hba->saved_uic_err &&
5753              (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
5754                 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
5755
5756                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5757                 ufshcd_print_host_state(hba);
5758                 ufshcd_print_pwr_info(hba);
5759                 ufshcd_print_host_regs(hba);
5760                 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5761                 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
5762                 spin_lock_irqsave(hba->host->host_lock, flags);
5763         }
5764
5765         /*
5766          * if host reset is required then skip clearing the pending
5767          * transfers forcefully because they will get cleared during
5768          * host reset and restore
5769          */
5770         if (needs_reset)
5771                 goto do_reset;
5772
5773         /*
5774          * If LINERESET was caught, UFS might have been put to PWM mode,
5775          * check if power mode restore is needed.
5776          */
5777         if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
5778                 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
5779                 if (!hba->saved_uic_err)
5780                         hba->saved_err &= ~UIC_ERROR;
5781                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5782                 if (ufshcd_is_pwr_mode_restore_needed(hba))
5783                         needs_restore = true;
5784                 spin_lock_irqsave(hba->host->host_lock, flags);
5785                 if (!hba->saved_err && !needs_restore)
5786                         goto skip_err_handling;
5787         }
5788
5789         hba->silence_err_logs = true;
5790         /* release lock as clear command might sleep */
5791         spin_unlock_irqrestore(hba->host->host_lock, flags);
5792         /* Clear pending transfer requests */
5793         for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5794                 if (ufshcd_try_to_abort_task(hba, tag)) {
5795                         err_xfer = true;
5796                         goto lock_skip_pending_xfer_clear;
5797                 }
5798         }
5799
5800         /* Clear pending task management requests */
5801         for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5802                 if (ufshcd_clear_tm_cmd(hba, tag)) {
5803                         err_tm = true;
5804                         goto lock_skip_pending_xfer_clear;
5805                 }
5806         }
5807
5808 lock_skip_pending_xfer_clear:
5809         spin_lock_irqsave(hba->host->host_lock, flags);
5810
5811         /* Complete the requests that are cleared by s/w */
5812         ufshcd_complete_requests(hba);
5813         hba->silence_err_logs = false;
5814
5815         if (err_xfer || err_tm) {
5816                 needs_reset = true;
5817                 goto do_reset;
5818         }
5819
5820         /*
5821          * After all reqs and tasks are cleared from doorbell,
5822          * now it is safe to retore power mode.
5823          */
5824         if (needs_restore) {
5825                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5826                 /*
5827                  * Hold the scaling lock just in case dev cmds
5828                  * are sent via bsg and/or sysfs.
5829                  */
5830                 down_write(&hba->clk_scaling_lock);
5831                 hba->force_pmc = true;
5832                 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
5833                 if (pmc_err) {
5834                         needs_reset = true;
5835                         dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
5836                                         __func__, pmc_err);
5837                 }
5838                 hba->force_pmc = false;
5839                 ufshcd_print_pwr_info(hba);
5840                 up_write(&hba->clk_scaling_lock);
5841                 spin_lock_irqsave(hba->host->host_lock, flags);
5842         }
5843
5844 do_reset:
5845         /* Fatal errors need reset */
5846         if (needs_reset) {
5847                 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5848
5849                 /*
5850                  * ufshcd_reset_and_restore() does the link reinitialization
5851                  * which will need atleast one empty doorbell slot to send the
5852                  * device management commands (NOP and query commands).
5853                  * If there is no slot empty at this moment then free up last
5854                  * slot forcefully.
5855                  */
5856                 if (hba->outstanding_reqs == max_doorbells)
5857                         __ufshcd_transfer_req_compl(hba,
5858                                                     (1UL << (hba->nutrs - 1)));
5859
5860                 hba->force_reset = false;
5861                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5862                 err = ufshcd_reset_and_restore(hba);
5863                 if (err)
5864                         dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
5865                                         __func__, err);
5866                 else
5867                         ufshcd_recover_pm_error(hba);
5868                 spin_lock_irqsave(hba->host->host_lock, flags);
5869         }
5870
5871 skip_err_handling:
5872         if (!needs_reset) {
5873                 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
5874                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5875                 if (hba->saved_err || hba->saved_uic_err)
5876                         dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5877                             __func__, hba->saved_err, hba->saved_uic_err);
5878         }
5879
5880 out:
5881         ufshcd_clear_eh_in_progress(hba);
5882         spin_unlock_irqrestore(hba->host->host_lock, flags);
5883         ufshcd_scsi_unblock_requests(hba);
5884         ufshcd_err_handling_unprepare(hba);
5885 }
5886
5887 /**
5888  * ufshcd_update_uic_error - check and set fatal UIC error flags.
5889  * @hba: per-adapter instance
5890  *
5891  * Returns
5892  *  IRQ_HANDLED - If interrupt is valid
5893  *  IRQ_NONE    - If invalid interrupt
5894  */
5895 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
5896 {
5897         u32 reg;
5898         irqreturn_t retval = IRQ_NONE;
5899
5900         /* PHY layer error */
5901         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5902         if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
5903             (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
5904                 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
5905                 /*
5906                  * To know whether this error is fatal or not, DB timeout
5907                  * must be checked but this error is handled separately.
5908                  */
5909                 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
5910                         dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
5911                                         __func__);
5912
5913                 /* Got a LINERESET indication. */
5914                 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
5915                         struct uic_command *cmd = NULL;
5916
5917                         hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
5918                         if (hba->uic_async_done && hba->active_uic_cmd)
5919                                 cmd = hba->active_uic_cmd;
5920                         /*
5921                          * Ignore the LINERESET during power mode change
5922                          * operation via DME_SET command.
5923                          */
5924                         if (cmd && (cmd->command == UIC_CMD_DME_SET))
5925                                 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
5926                 }
5927                 retval |= IRQ_HANDLED;
5928         }
5929
5930         /* PA_INIT_ERROR is fatal and needs UIC reset */
5931         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
5932         if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
5933             (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
5934                 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
5935
5936                 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5937                         hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5938                 else if (hba->dev_quirks &
5939                                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5940                         if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5941                                 hba->uic_error |=
5942                                         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5943                         else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5944                                 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5945                 }
5946                 retval |= IRQ_HANDLED;
5947         }
5948
5949         /* UIC NL/TL/DME errors needs software retry */
5950         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
5951         if ((reg & UIC_NETWORK_LAYER_ERROR) &&
5952             (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
5953                 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
5954                 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
5955                 retval |= IRQ_HANDLED;
5956         }
5957
5958         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
5959         if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
5960             (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
5961                 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
5962                 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
5963                 retval |= IRQ_HANDLED;
5964         }
5965
5966         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
5967         if ((reg & UIC_DME_ERROR) &&
5968             (reg & UIC_DME_ERROR_CODE_MASK)) {
5969                 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
5970                 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
5971                 retval |= IRQ_HANDLED;
5972         }
5973
5974         dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5975                         __func__, hba->uic_error);
5976         return retval;
5977 }
5978
5979 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5980                                          u32 intr_mask)
5981 {
5982         if (!ufshcd_is_auto_hibern8_supported(hba) ||
5983             !ufshcd_is_auto_hibern8_enabled(hba))
5984                 return false;
5985
5986         if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5987                 return false;
5988
5989         if (hba->active_uic_cmd &&
5990             (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5991             hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5992                 return false;
5993
5994         return true;
5995 }
5996
5997 /**
5998  * ufshcd_check_errors - Check for errors that need s/w attention
5999  * @hba: per-adapter instance
6000  *
6001  * Returns
6002  *  IRQ_HANDLED - If interrupt is valid
6003  *  IRQ_NONE    - If invalid interrupt
6004  */
6005 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
6006 {
6007         bool queue_eh_work = false;
6008         irqreturn_t retval = IRQ_NONE;
6009
6010         if (hba->errors & INT_FATAL_ERRORS) {
6011                 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
6012                 queue_eh_work = true;
6013         }
6014
6015         if (hba->errors & UIC_ERROR) {
6016                 hba->uic_error = 0;
6017                 retval = ufshcd_update_uic_error(hba);
6018                 if (hba->uic_error)
6019                         queue_eh_work = true;
6020         }
6021
6022         if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6023                 dev_err(hba->dev,
6024                         "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6025                         __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6026                         "Enter" : "Exit",
6027                         hba->errors, ufshcd_get_upmcrs(hba));
6028                 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
6029                                        hba->errors);
6030                 ufshcd_set_link_broken(hba);
6031                 queue_eh_work = true;
6032         }
6033
6034         if (queue_eh_work) {
6035                 /*
6036                  * update the transfer error masks to sticky bits, let's do this
6037                  * irrespective of current ufshcd_state.
6038                  */
6039                 hba->saved_err |= hba->errors;
6040                 hba->saved_uic_err |= hba->uic_error;
6041
6042                 /* dump controller state before resetting */
6043                 if ((hba->saved_err & (INT_FATAL_ERRORS)) ||
6044                     (hba->saved_uic_err &&
6045                      (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6046                         dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6047                                         __func__, hba->saved_err,
6048                                         hba->saved_uic_err);
6049                         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6050                                          "host_regs: ");
6051                         ufshcd_print_pwr_info(hba);
6052                 }
6053                 ufshcd_schedule_eh_work(hba);
6054                 retval |= IRQ_HANDLED;
6055         }
6056         /*
6057          * if (!queue_eh_work) -
6058          * Other errors are either non-fatal where host recovers
6059          * itself without s/w intervention or errors that will be
6060          * handled by the SCSI core layer.
6061          */
6062         return retval;
6063 }
6064
6065 struct ctm_info {
6066         struct ufs_hba  *hba;
6067         unsigned long   pending;
6068         unsigned int    ncpl;
6069 };
6070
6071 static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
6072 {
6073         struct ctm_info *const ci = priv;
6074         struct completion *c;
6075
6076         WARN_ON_ONCE(reserved);
6077         if (test_bit(req->tag, &ci->pending))
6078                 return true;
6079         ci->ncpl++;
6080         c = req->end_io_data;
6081         if (c)
6082                 complete(c);
6083         return true;
6084 }
6085
6086 /**
6087  * ufshcd_tmc_handler - handle task management function completion
6088  * @hba: per adapter instance
6089  *
6090  * Returns
6091  *  IRQ_HANDLED - If interrupt is valid
6092  *  IRQ_NONE    - If invalid interrupt
6093  */
6094 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6095 {
6096         struct request_queue *q = hba->tmf_queue;
6097         struct ctm_info ci = {
6098                 .hba     = hba,
6099                 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
6100         };
6101
6102         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
6103         return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
6104 }
6105
6106 /**
6107  * ufshcd_sl_intr - Interrupt service routine
6108  * @hba: per adapter instance
6109  * @intr_status: contains interrupts generated by the controller
6110  *
6111  * Returns
6112  *  IRQ_HANDLED - If interrupt is valid
6113  *  IRQ_NONE    - If invalid interrupt
6114  */
6115 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6116 {
6117         irqreturn_t retval = IRQ_NONE;
6118
6119         hba->errors = UFSHCD_ERROR_MASK & intr_status;
6120
6121         if (ufshcd_is_auto_hibern8_error(hba, intr_status))
6122                 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
6123
6124         if (hba->errors)
6125                 retval |= ufshcd_check_errors(hba);
6126
6127         if (intr_status & UFSHCD_UIC_MASK)
6128                 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6129
6130         if (intr_status & UTP_TASK_REQ_COMPL)
6131                 retval |= ufshcd_tmc_handler(hba);
6132
6133         if (intr_status & UTP_TRANSFER_REQ_COMPL)
6134                 retval |= ufshcd_transfer_req_compl(hba);
6135
6136         return retval;
6137 }
6138
6139 /**
6140  * ufshcd_intr - Main interrupt service routine
6141  * @irq: irq number
6142  * @__hba: pointer to adapter instance
6143  *
6144  * Returns
6145  *  IRQ_HANDLED - If interrupt is valid
6146  *  IRQ_NONE    - If invalid interrupt
6147  */
6148 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6149 {
6150         u32 intr_status, enabled_intr_status = 0;
6151         irqreturn_t retval = IRQ_NONE;
6152         struct ufs_hba *hba = __hba;
6153         int retries = hba->nutrs;
6154
6155         spin_lock(hba->host->host_lock);
6156         intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6157         hba->ufs_stats.last_intr_status = intr_status;
6158         hba->ufs_stats.last_intr_ts = ktime_get();
6159
6160         /*
6161          * There could be max of hba->nutrs reqs in flight and in worst case
6162          * if the reqs get finished 1 by 1 after the interrupt status is
6163          * read, make sure we handle them by checking the interrupt status
6164          * again in a loop until we process all of the reqs before returning.
6165          */
6166         while (intr_status && retries--) {
6167                 enabled_intr_status =
6168                         intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6169                 if (intr_status)
6170                         ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6171                 if (enabled_intr_status)
6172                         retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6173
6174                 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6175         }
6176
6177         if (enabled_intr_status && retval == IRQ_NONE) {
6178                 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
6179                                         __func__, intr_status);
6180                 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6181         }
6182
6183         spin_unlock(hba->host->host_lock);
6184         return retval;
6185 }
6186
6187 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6188 {
6189         int err = 0;
6190         u32 mask = 1 << tag;
6191         unsigned long flags;
6192
6193         if (!test_bit(tag, &hba->outstanding_tasks))
6194                 goto out;
6195
6196         spin_lock_irqsave(hba->host->host_lock, flags);
6197         ufshcd_utmrl_clear(hba, tag);
6198         spin_unlock_irqrestore(hba->host->host_lock, flags);
6199
6200         /* poll for max. 1 sec to clear door bell register by h/w */
6201         err = ufshcd_wait_for_register(hba,
6202                         REG_UTP_TASK_REQ_DOOR_BELL,
6203                         mask, 0, 1000, 1000);
6204 out:
6205         return err;
6206 }
6207
6208 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6209                 struct utp_task_req_desc *treq, u8 tm_function)
6210 {
6211         struct request_queue *q = hba->tmf_queue;
6212         struct Scsi_Host *host = hba->host;
6213         DECLARE_COMPLETION_ONSTACK(wait);
6214         struct request *req;
6215         unsigned long flags;
6216         int free_slot, task_tag, err;
6217
6218         /*
6219          * Get free slot, sleep if slots are unavailable.
6220          * Even though we use wait_event() which sleeps indefinitely,
6221          * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
6222          */
6223         req = blk_get_request(q, REQ_OP_DRV_OUT, BLK_MQ_REQ_RESERVED);
6224         req->end_io_data = &wait;
6225         free_slot = req->tag;
6226         WARN_ON_ONCE(free_slot < 0 || free_slot >= hba->nutmrs);
6227         ufshcd_hold(hba, false);
6228
6229         spin_lock_irqsave(host->host_lock, flags);
6230         task_tag = hba->nutrs + free_slot;
6231
6232         treq->req_header.dword_0 |= cpu_to_be32(task_tag);
6233
6234         memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
6235         ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
6236
6237         /* send command to the controller */
6238         __set_bit(free_slot, &hba->outstanding_tasks);
6239
6240         /* Make sure descriptors are ready before ringing the task doorbell */
6241         wmb();
6242
6243         ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
6244         /* Make sure that doorbell is committed immediately */
6245         wmb();
6246
6247         spin_unlock_irqrestore(host->host_lock, flags);
6248
6249         ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
6250
6251         /* wait until the task management command is completed */
6252         err = wait_for_completion_io_timeout(&wait,
6253                         msecs_to_jiffies(TM_CMD_TIMEOUT));
6254         if (!err) {
6255                 /*
6256                  * Make sure that ufshcd_compl_tm() does not trigger a
6257                  * use-after-free.
6258                  */
6259                 req->end_io_data = NULL;
6260                 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
6261                 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6262                                 __func__, tm_function);
6263                 if (ufshcd_clear_tm_cmd(hba, free_slot))
6264                         dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
6265                                         __func__, free_slot);
6266                 err = -ETIMEDOUT;
6267         } else {
6268                 err = 0;
6269                 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
6270
6271                 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
6272         }
6273
6274         spin_lock_irqsave(hba->host->host_lock, flags);
6275         __clear_bit(free_slot, &hba->outstanding_tasks);
6276         spin_unlock_irqrestore(hba->host->host_lock, flags);
6277
6278         blk_put_request(req);
6279
6280         ufshcd_release(hba);
6281         return err;
6282 }
6283
6284 /**
6285  * ufshcd_issue_tm_cmd - issues task management commands to controller
6286  * @hba: per adapter instance
6287  * @lun_id: LUN ID to which TM command is sent
6288  * @task_id: task ID to which the TM command is applicable
6289  * @tm_function: task management function opcode
6290  * @tm_response: task management service response return value
6291  *
6292  * Returns non-zero value on error, zero on success.
6293  */
6294 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6295                 u8 tm_function, u8 *tm_response)
6296 {
6297         struct utp_task_req_desc treq = { { 0 }, };
6298         int ocs_value, err;
6299
6300         /* Configure task request descriptor */
6301         treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6302         treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6303
6304         /* Configure task request UPIU */
6305         treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6306                                   cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6307         treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6308
6309         /*
6310          * The host shall provide the same value for LUN field in the basic
6311          * header and for Input Parameter.
6312          */
6313         treq.input_param1 = cpu_to_be32(lun_id);
6314         treq.input_param2 = cpu_to_be32(task_id);
6315
6316         err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6317         if (err == -ETIMEDOUT)
6318                 return err;
6319
6320         ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6321         if (ocs_value != OCS_SUCCESS)
6322                 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6323                                 __func__, ocs_value);
6324         else if (tm_response)
6325                 *tm_response = be32_to_cpu(treq.output_param1) &
6326                                 MASK_TM_SERVICE_RESP;
6327         return err;
6328 }
6329
6330 /**
6331  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6332  * @hba:        per-adapter instance
6333  * @req_upiu:   upiu request
6334  * @rsp_upiu:   upiu reply
6335  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6336  * @buff_len:   descriptor size, 0 if NA
6337  * @cmd_type:   specifies the type (NOP, Query...)
6338  * @desc_op:    descriptor operation
6339  *
6340  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6341  * Therefore, it "rides" the device management infrastructure: uses its tag and
6342  * tasks work queues.
6343  *
6344  * Since there is only one available tag for device management commands,
6345  * the caller is expected to hold the hba->dev_cmd.lock mutex.
6346  */
6347 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6348                                         struct utp_upiu_req *req_upiu,
6349                                         struct utp_upiu_req *rsp_upiu,
6350                                         u8 *desc_buff, int *buff_len,
6351                                         enum dev_cmd_type cmd_type,
6352                                         enum query_opcode desc_op)
6353 {
6354         struct request_queue *q = hba->cmd_queue;
6355         struct request *req;
6356         struct ufshcd_lrb *lrbp;
6357         int err = 0;
6358         int tag;
6359         struct completion wait;
6360         unsigned long flags;
6361         u8 upiu_flags;
6362
6363         down_read(&hba->clk_scaling_lock);
6364
6365         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6366         if (IS_ERR(req)) {
6367                 err = PTR_ERR(req);
6368                 goto out_unlock;
6369         }
6370         tag = req->tag;
6371         WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
6372
6373         init_completion(&wait);
6374         lrbp = &hba->lrb[tag];
6375         WARN_ON(lrbp->cmd);
6376
6377         lrbp->cmd = NULL;
6378         lrbp->sense_bufflen = 0;
6379         lrbp->sense_buffer = NULL;
6380         lrbp->task_tag = tag;
6381         lrbp->lun = 0;
6382         lrbp->intr_cmd = true;
6383         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6384         hba->dev_cmd.type = cmd_type;
6385
6386         switch (hba->ufs_version) {
6387         case UFSHCI_VERSION_10:
6388         case UFSHCI_VERSION_11:
6389                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6390                 break;
6391         default:
6392                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6393                 break;
6394         }
6395
6396         /* update the task tag in the request upiu */
6397         req_upiu->header.dword_0 |= cpu_to_be32(tag);
6398
6399         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6400
6401         /* just copy the upiu request as it is */
6402         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6403         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6404                 /* The Data Segment Area is optional depending upon the query
6405                  * function value. for WRITE DESCRIPTOR, the data segment
6406                  * follows right after the tsf.
6407                  */
6408                 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6409                 *buff_len = 0;
6410         }
6411
6412         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6413
6414         hba->dev_cmd.complete = &wait;
6415
6416         /* Make sure descriptors are ready before ringing the doorbell */
6417         wmb();
6418         spin_lock_irqsave(hba->host->host_lock, flags);
6419         ufshcd_send_command(hba, tag);
6420         spin_unlock_irqrestore(hba->host->host_lock, flags);
6421
6422         /*
6423          * ignore the returning value here - ufshcd_check_query_response is
6424          * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6425          * read the response directly ignoring all errors.
6426          */
6427         ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6428
6429         /* just copy the upiu response as it is */
6430         memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6431         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6432                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6433                 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6434                                MASK_QUERY_DATA_SEG_LEN;
6435
6436                 if (*buff_len >= resp_len) {
6437                         memcpy(desc_buff, descp, resp_len);
6438                         *buff_len = resp_len;
6439                 } else {
6440                         dev_warn(hba->dev,
6441                                  "%s: rsp size %d is bigger than buffer size %d",
6442                                  __func__, resp_len, *buff_len);
6443                         *buff_len = 0;
6444                         err = -EINVAL;
6445                 }
6446         }
6447
6448         blk_put_request(req);
6449 out_unlock:
6450         up_read(&hba->clk_scaling_lock);
6451         return err;
6452 }
6453
6454 /**
6455  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6456  * @hba:        per-adapter instance
6457  * @req_upiu:   upiu request
6458  * @rsp_upiu:   upiu reply - only 8 DW as we do not support scsi commands
6459  * @msgcode:    message code, one of UPIU Transaction Codes Initiator to Target
6460  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6461  * @buff_len:   descriptor size, 0 if NA
6462  * @desc_op:    descriptor operation
6463  *
6464  * Supports UTP Transfer requests (nop and query), and UTP Task
6465  * Management requests.
6466  * It is up to the caller to fill the upiu conent properly, as it will
6467  * be copied without any further input validations.
6468  */
6469 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6470                              struct utp_upiu_req *req_upiu,
6471                              struct utp_upiu_req *rsp_upiu,
6472                              int msgcode,
6473                              u8 *desc_buff, int *buff_len,
6474                              enum query_opcode desc_op)
6475 {
6476         int err;
6477         enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6478         struct utp_task_req_desc treq = { { 0 }, };
6479         int ocs_value;
6480         u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6481
6482         switch (msgcode) {
6483         case UPIU_TRANSACTION_NOP_OUT:
6484                 cmd_type = DEV_CMD_TYPE_NOP;
6485                 fallthrough;
6486         case UPIU_TRANSACTION_QUERY_REQ:
6487                 ufshcd_hold(hba, false);
6488                 mutex_lock(&hba->dev_cmd.lock);
6489                 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6490                                                    desc_buff, buff_len,
6491                                                    cmd_type, desc_op);
6492                 mutex_unlock(&hba->dev_cmd.lock);
6493                 ufshcd_release(hba);
6494
6495                 break;
6496         case UPIU_TRANSACTION_TASK_REQ:
6497                 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6498                 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6499
6500                 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
6501
6502                 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6503                 if (err == -ETIMEDOUT)
6504                         break;
6505
6506                 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6507                 if (ocs_value != OCS_SUCCESS) {
6508                         dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6509                                 ocs_value);
6510                         break;
6511                 }
6512
6513                 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
6514
6515                 break;
6516         default:
6517                 err = -EINVAL;
6518
6519                 break;
6520         }
6521
6522         return err;
6523 }
6524
6525 /**
6526  * ufshcd_eh_device_reset_handler - device reset handler registered to
6527  *                                    scsi layer.
6528  * @cmd: SCSI command pointer
6529  *
6530  * Returns SUCCESS/FAILED
6531  */
6532 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
6533 {
6534         struct Scsi_Host *host;
6535         struct ufs_hba *hba;
6536         unsigned int tag;
6537         u32 pos;
6538         int err;
6539         u8 resp = 0xF;
6540         struct ufshcd_lrb *lrbp;
6541         unsigned long flags;
6542
6543         host = cmd->device->host;
6544         hba = shost_priv(host);
6545         tag = cmd->request->tag;
6546
6547         lrbp = &hba->lrb[tag];
6548         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
6549         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6550                 if (!err)
6551                         err = resp;
6552                 goto out;
6553         }
6554
6555         /* clear the commands that were pending for corresponding LUN */
6556         for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6557                 if (hba->lrb[pos].lun == lrbp->lun) {
6558                         err = ufshcd_clear_cmd(hba, pos);
6559                         if (err)
6560                                 break;
6561                 }
6562         }
6563         spin_lock_irqsave(host->host_lock, flags);
6564         ufshcd_transfer_req_compl(hba);
6565         spin_unlock_irqrestore(host->host_lock, flags);
6566
6567 out:
6568         hba->req_abort_count = 0;
6569         ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
6570         if (!err) {
6571                 err = SUCCESS;
6572         } else {
6573                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6574                 err = FAILED;
6575         }
6576         return err;
6577 }
6578
6579 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6580 {
6581         struct ufshcd_lrb *lrbp;
6582         int tag;
6583
6584         for_each_set_bit(tag, &bitmap, hba->nutrs) {
6585                 lrbp = &hba->lrb[tag];
6586                 lrbp->req_abort_skip = true;
6587         }
6588 }
6589
6590 /**
6591  * ufshcd_try_to_abort_task - abort a specific task
6592  * @cmd: SCSI command pointer
6593  *
6594  * Abort the pending command in device by sending UFS_ABORT_TASK task management
6595  * command, and in host controller by clearing the door-bell register. There can
6596  * be race between controller sending the command to the device while abort is
6597  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6598  * really issued and then try to abort it.
6599  *
6600  * Returns zero on success, non-zero on failure
6601  */
6602 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6603 {
6604         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6605         int err = 0;
6606         int poll_cnt;
6607         u8 resp = 0xF;
6608         u32 reg;
6609
6610         for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6611                 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6612                                 UFS_QUERY_TASK, &resp);
6613                 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6614                         /* cmd pending in the device */
6615                         dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6616                                 __func__, tag);
6617                         break;
6618                 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6619                         /*
6620                          * cmd not pending in the device, check if it is
6621                          * in transition.
6622                          */
6623                         dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6624                                 __func__, tag);
6625                         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6626                         if (reg & (1 << tag)) {
6627                                 /* sleep for max. 200us to stabilize */
6628                                 usleep_range(100, 200);
6629                                 continue;
6630                         }
6631                         /* command completed already */
6632                         dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6633                                 __func__, tag);
6634                         goto out;
6635                 } else {
6636                         dev_err(hba->dev,
6637                                 "%s: no response from device. tag = %d, err %d\n",
6638                                 __func__, tag, err);
6639                         if (!err)
6640                                 err = resp; /* service response error */
6641                         goto out;
6642                 }
6643         }
6644
6645         if (!poll_cnt) {
6646                 err = -EBUSY;
6647                 goto out;
6648         }
6649
6650         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6651                         UFS_ABORT_TASK, &resp);
6652         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6653                 if (!err) {
6654                         err = resp; /* service response error */
6655                         dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6656                                 __func__, tag, err);
6657                 }
6658                 goto out;
6659         }
6660
6661         err = ufshcd_clear_cmd(hba, tag);
6662         if (err)
6663                 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6664                         __func__, tag, err);
6665
6666 out:
6667         return err;
6668 }
6669
6670 /**
6671  * ufshcd_abort - scsi host template eh_abort_handler callback
6672  * @cmd: SCSI command pointer
6673  *
6674  * Returns SUCCESS/FAILED
6675  */
6676 static int ufshcd_abort(struct scsi_cmnd *cmd)
6677 {
6678         struct Scsi_Host *host;
6679         struct ufs_hba *hba;
6680         unsigned long flags;
6681         unsigned int tag;
6682         int err = 0;
6683         struct ufshcd_lrb *lrbp;
6684         u32 reg;
6685
6686         host = cmd->device->host;
6687         hba = shost_priv(host);
6688         tag = cmd->request->tag;
6689         lrbp = &hba->lrb[tag];
6690         if (!ufshcd_valid_tag(hba, tag)) {
6691                 dev_err(hba->dev,
6692                         "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6693                         __func__, tag, cmd, cmd->request);
6694                 BUG();
6695         }
6696
6697         /*
6698          * Task abort to the device W-LUN is illegal. When this command
6699          * will fail, due to spec violation, scsi err handling next step
6700          * will be to send LU reset which, again, is a spec violation.
6701          * To avoid these unnecessary/illegal step we skip to the last error
6702          * handling stage: reset and restore.
6703          */
6704         if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6705                 return ufshcd_eh_host_reset_handler(cmd);
6706
6707         ufshcd_hold(hba, false);
6708         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6709         /* If command is already aborted/completed, return SUCCESS */
6710         if (!(test_bit(tag, &hba->outstanding_reqs))) {
6711                 dev_err(hba->dev,
6712                         "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6713                         __func__, tag, hba->outstanding_reqs, reg);
6714                 goto out;
6715         }
6716
6717         /* Print Transfer Request of aborted task */
6718         dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6719
6720         /*
6721          * Print detailed info about aborted request.
6722          * As more than one request might get aborted at the same time,
6723          * print full information only for the first aborted request in order
6724          * to reduce repeated printouts. For other aborted requests only print
6725          * basic details.
6726          */
6727         scsi_print_command(hba->lrb[tag].cmd);
6728         if (!hba->req_abort_count) {
6729                 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
6730                 ufshcd_print_host_regs(hba);
6731                 ufshcd_print_host_state(hba);
6732                 ufshcd_print_pwr_info(hba);
6733                 ufshcd_print_trs(hba, 1 << tag, true);
6734         } else {
6735                 ufshcd_print_trs(hba, 1 << tag, false);
6736         }
6737         hba->req_abort_count++;
6738
6739         if (!(reg & (1 << tag))) {
6740                 dev_err(hba->dev,
6741                 "%s: cmd was completed, but without a notifying intr, tag = %d",
6742                 __func__, tag);
6743                 goto cleanup;
6744         }
6745
6746         /* Skip task abort in case previous aborts failed and report failure */
6747         if (lrbp->req_abort_skip)
6748                 err = -EIO;
6749         else
6750                 err = ufshcd_try_to_abort_task(hba, tag);
6751
6752         if (!err) {
6753 cleanup:
6754                 spin_lock_irqsave(host->host_lock, flags);
6755                 __ufshcd_transfer_req_compl(hba, (1UL << tag));
6756                 spin_unlock_irqrestore(host->host_lock, flags);
6757 out:
6758                 err = SUCCESS;
6759         } else {
6760                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6761                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
6762                 err = FAILED;
6763         }
6764
6765         /*
6766          * This ufshcd_release() corresponds to the original scsi cmd that got
6767          * aborted here (as we won't get any IRQ for it).
6768          */
6769         ufshcd_release(hba);
6770         return err;
6771 }
6772
6773 /**
6774  * ufshcd_host_reset_and_restore - reset and restore host controller
6775  * @hba: per-adapter instance
6776  *
6777  * Note that host controller reset may issue DME_RESET to
6778  * local and remote (device) Uni-Pro stack and the attributes
6779  * are reset to default state.
6780  *
6781  * Returns zero on success, non-zero on failure
6782  */
6783 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6784 {
6785         int err;
6786         unsigned long flags;
6787
6788         /*
6789          * Stop the host controller and complete the requests
6790          * cleared by h/w
6791          */
6792         ufshcd_hba_stop(hba);
6793
6794         spin_lock_irqsave(hba->host->host_lock, flags);
6795         hba->silence_err_logs = true;
6796         ufshcd_complete_requests(hba);
6797         hba->silence_err_logs = false;
6798         spin_unlock_irqrestore(hba->host->host_lock, flags);
6799
6800         /* scale up clocks to max frequency before full reinitialization */
6801         ufshcd_set_clk_freq(hba, true);
6802
6803         err = ufshcd_hba_enable(hba);
6804         if (err)
6805                 goto out;
6806
6807         /* Establish the link again and restore the device */
6808         err = ufshcd_probe_hba(hba, false);
6809
6810 out:
6811         if (err)
6812                 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
6813         ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
6814         return err;
6815 }
6816
6817 /**
6818  * ufshcd_reset_and_restore - reset and re-initialize host/device
6819  * @hba: per-adapter instance
6820  *
6821  * Reset and recover device, host and re-establish link. This
6822  * is helpful to recover the communication in fatal error conditions.
6823  *
6824  * Returns zero on success, non-zero on failure
6825  */
6826 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6827 {
6828         u32 saved_err;
6829         u32 saved_uic_err;
6830         int err = 0;
6831         unsigned long flags;
6832         int retries = MAX_HOST_RESET_RETRIES;
6833
6834         /*
6835          * This is a fresh start, cache and clear saved error first,
6836          * in case new error generated during reset and restore.
6837          */
6838         spin_lock_irqsave(hba->host->host_lock, flags);
6839         saved_err = hba->saved_err;
6840         saved_uic_err = hba->saved_uic_err;
6841         hba->saved_err = 0;
6842         hba->saved_uic_err = 0;
6843         spin_unlock_irqrestore(hba->host->host_lock, flags);
6844
6845         do {
6846                 /* Reset the attached device */
6847                 ufshcd_vops_device_reset(hba);
6848
6849                 err = ufshcd_host_reset_and_restore(hba);
6850         } while (err && --retries);
6851
6852         spin_lock_irqsave(hba->host->host_lock, flags);
6853         /*
6854          * Inform scsi mid-layer that we did reset and allow to handle
6855          * Unit Attention properly.
6856          */
6857         scsi_report_bus_reset(hba->host, 0);
6858         if (err) {
6859                 hba->saved_err |= saved_err;
6860                 hba->saved_uic_err |= saved_uic_err;
6861         }
6862         spin_unlock_irqrestore(hba->host->host_lock, flags);
6863
6864         return err;
6865 }
6866
6867 /**
6868  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
6869  * @cmd: SCSI command pointer
6870  *
6871  * Returns SUCCESS/FAILED
6872  */
6873 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6874 {
6875         int err = SUCCESS;
6876         unsigned long flags;
6877         struct ufs_hba *hba;
6878
6879         hba = shost_priv(cmd->device->host);
6880
6881         spin_lock_irqsave(hba->host->host_lock, flags);
6882         hba->force_reset = true;
6883         ufshcd_schedule_eh_work(hba);
6884         dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
6885         spin_unlock_irqrestore(hba->host->host_lock, flags);
6886
6887         flush_work(&hba->eh_work);
6888
6889         spin_lock_irqsave(hba->host->host_lock, flags);
6890         if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
6891                 err = FAILED;
6892         spin_unlock_irqrestore(hba->host->host_lock, flags);
6893
6894         return err;
6895 }
6896
6897 /**
6898  * ufshcd_get_max_icc_level - calculate the ICC level
6899  * @sup_curr_uA: max. current supported by the regulator
6900  * @start_scan: row at the desc table to start scan from
6901  * @buff: power descriptor buffer
6902  *
6903  * Returns calculated max ICC level for specific regulator
6904  */
6905 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6906 {
6907         int i;
6908         int curr_uA;
6909         u16 data;
6910         u16 unit;
6911
6912         for (i = start_scan; i >= 0; i--) {
6913                 data = be16_to_cpup((__be16 *)&buff[2 * i]);
6914                 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6915                                                 ATTR_ICC_LVL_UNIT_OFFSET;
6916                 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6917                 switch (unit) {
6918                 case UFSHCD_NANO_AMP:
6919                         curr_uA = curr_uA / 1000;
6920                         break;
6921                 case UFSHCD_MILI_AMP:
6922                         curr_uA = curr_uA * 1000;
6923                         break;
6924                 case UFSHCD_AMP:
6925                         curr_uA = curr_uA * 1000 * 1000;
6926                         break;
6927                 case UFSHCD_MICRO_AMP:
6928                 default:
6929                         break;
6930                 }
6931                 if (sup_curr_uA >= curr_uA)
6932                         break;
6933         }
6934         if (i < 0) {
6935                 i = 0;
6936                 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6937         }
6938
6939         return (u32)i;
6940 }
6941
6942 /**
6943  * ufshcd_calc_icc_level - calculate the max ICC level
6944  * In case regulators are not initialized we'll return 0
6945  * @hba: per-adapter instance
6946  * @desc_buf: power descriptor buffer to extract ICC levels from.
6947  * @len: length of desc_buff
6948  *
6949  * Returns calculated ICC level
6950  */
6951 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6952                                                         u8 *desc_buf, int len)
6953 {
6954         u32 icc_level = 0;
6955
6956         if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6957                                                 !hba->vreg_info.vccq2) {
6958                 dev_err(hba->dev,
6959                         "%s: Regulator capability was not set, actvIccLevel=%d",
6960                                                         __func__, icc_level);
6961                 goto out;
6962         }
6963
6964         if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
6965                 icc_level = ufshcd_get_max_icc_level(
6966                                 hba->vreg_info.vcc->max_uA,
6967                                 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6968                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6969
6970         if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
6971                 icc_level = ufshcd_get_max_icc_level(
6972                                 hba->vreg_info.vccq->max_uA,
6973                                 icc_level,
6974                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6975
6976         if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
6977                 icc_level = ufshcd_get_max_icc_level(
6978                                 hba->vreg_info.vccq2->max_uA,
6979                                 icc_level,
6980                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6981 out:
6982         return icc_level;
6983 }
6984
6985 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
6986 {
6987         int ret;
6988         int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
6989         u8 *desc_buf;
6990         u32 icc_level;
6991
6992         desc_buf = kmalloc(buff_len, GFP_KERNEL);
6993         if (!desc_buf)
6994                 return;
6995
6996         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
6997                                      desc_buf, buff_len);
6998         if (ret) {
6999                 dev_err(hba->dev,
7000                         "%s: Failed reading power descriptor.len = %d ret = %d",
7001                         __func__, buff_len, ret);
7002                 goto out;
7003         }
7004
7005         icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7006                                                          buff_len);
7007         dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7008
7009         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7010                 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7011
7012         if (ret)
7013                 dev_err(hba->dev,
7014                         "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7015                         __func__, icc_level, ret);
7016
7017 out:
7018         kfree(desc_buf);
7019 }
7020
7021 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7022 {
7023         scsi_autopm_get_device(sdev);
7024         blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7025         if (sdev->rpm_autosuspend)
7026                 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7027                                                  RPM_AUTOSUSPEND_DELAY_MS);
7028         scsi_autopm_put_device(sdev);
7029 }
7030
7031 /**
7032  * ufshcd_scsi_add_wlus - Adds required W-LUs
7033  * @hba: per-adapter instance
7034  *
7035  * UFS device specification requires the UFS devices to support 4 well known
7036  * logical units:
7037  *      "REPORT_LUNS" (address: 01h)
7038  *      "UFS Device" (address: 50h)
7039  *      "RPMB" (address: 44h)
7040  *      "BOOT" (address: 30h)
7041  * UFS device's power management needs to be controlled by "POWER CONDITION"
7042  * field of SSU (START STOP UNIT) command. But this "power condition" field
7043  * will take effect only when its sent to "UFS device" well known logical unit
7044  * hence we require the scsi_device instance to represent this logical unit in
7045  * order for the UFS host driver to send the SSU command for power management.
7046  *
7047  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7048  * Block) LU so user space process can control this LU. User space may also
7049  * want to have access to BOOT LU.
7050  *
7051  * This function adds scsi device instances for each of all well known LUs
7052  * (except "REPORT LUNS" LU).
7053  *
7054  * Returns zero on success (all required W-LUs are added successfully),
7055  * non-zero error value on failure (if failed to add any of the required W-LU).
7056  */
7057 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7058 {
7059         int ret = 0;
7060         struct scsi_device *sdev_rpmb;
7061         struct scsi_device *sdev_boot;
7062
7063         hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7064                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7065         if (IS_ERR(hba->sdev_ufs_device)) {
7066                 ret = PTR_ERR(hba->sdev_ufs_device);
7067                 hba->sdev_ufs_device = NULL;
7068                 goto out;
7069         }
7070         ufshcd_blk_pm_runtime_init(hba->sdev_ufs_device);
7071         scsi_device_put(hba->sdev_ufs_device);
7072
7073         sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7074                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7075         if (IS_ERR(sdev_rpmb)) {
7076                 ret = PTR_ERR(sdev_rpmb);
7077                 goto remove_sdev_ufs_device;
7078         }
7079         ufshcd_blk_pm_runtime_init(sdev_rpmb);
7080         scsi_device_put(sdev_rpmb);
7081
7082         sdev_boot = __scsi_add_device(hba->host, 0, 0,
7083                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7084         if (IS_ERR(sdev_boot)) {
7085                 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7086         } else {
7087                 ufshcd_blk_pm_runtime_init(sdev_boot);
7088                 scsi_device_put(sdev_boot);
7089         }
7090         goto out;
7091
7092 remove_sdev_ufs_device:
7093         scsi_remove_device(hba->sdev_ufs_device);
7094 out:
7095         return ret;
7096 }
7097
7098 static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7099 {
7100         struct ufs_dev_info *dev_info = &hba->dev_info;
7101         u8 lun;
7102         u32 d_lu_wb_buf_alloc;
7103
7104         if (!ufshcd_is_wb_allowed(hba))
7105                 return;
7106         /*
7107          * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7108          * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7109          * enabled
7110          */
7111         if (!(dev_info->wspecversion >= 0x310 ||
7112               dev_info->wspecversion == 0x220 ||
7113              (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7114                 goto wb_disabled;
7115
7116         if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7117             DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7118                 goto wb_disabled;
7119
7120         dev_info->d_ext_ufs_feature_sup =
7121                 get_unaligned_be32(desc_buf +
7122                                    DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7123
7124         if (!(dev_info->d_ext_ufs_feature_sup & UFS_DEV_WRITE_BOOSTER_SUP))
7125                 goto wb_disabled;
7126
7127         /*
7128          * WB may be supported but not configured while provisioning.
7129          * The spec says, in dedicated wb buffer mode,
7130          * a max of 1 lun would have wb buffer configured.
7131          * Now only shared buffer mode is supported.
7132          */
7133         dev_info->b_wb_buffer_type =
7134                 desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7135
7136         dev_info->b_presrv_uspc_en =
7137                 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7138
7139         if (dev_info->b_wb_buffer_type == WB_BUF_MODE_SHARED) {
7140                 dev_info->d_wb_alloc_units =
7141                 get_unaligned_be32(desc_buf +
7142                                    DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS);
7143                 if (!dev_info->d_wb_alloc_units)
7144                         goto wb_disabled;
7145         } else {
7146                 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7147                         d_lu_wb_buf_alloc = 0;
7148                         ufshcd_read_unit_desc_param(hba,
7149                                         lun,
7150                                         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7151                                         (u8 *)&d_lu_wb_buf_alloc,
7152                                         sizeof(d_lu_wb_buf_alloc));
7153                         if (d_lu_wb_buf_alloc) {
7154                                 dev_info->wb_dedicated_lu = lun;
7155                                 break;
7156                         }
7157                 }
7158
7159                 if (!d_lu_wb_buf_alloc)
7160                         goto wb_disabled;
7161         }
7162         return;
7163
7164 wb_disabled:
7165         hba->caps &= ~UFSHCD_CAP_WB_EN;
7166 }
7167
7168 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
7169 {
7170         struct ufs_dev_fix *f;
7171         struct ufs_dev_info *dev_info = &hba->dev_info;
7172
7173         if (!fixups)
7174                 return;
7175
7176         for (f = fixups; f->quirk; f++) {
7177                 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7178                      f->wmanufacturerid == UFS_ANY_VENDOR) &&
7179                      ((dev_info->model &&
7180                        STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7181                       !strcmp(f->model, UFS_ANY_MODEL)))
7182                         hba->dev_quirks |= f->quirk;
7183         }
7184 }
7185 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7186
7187 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7188 {
7189         /* fix by general quirk table */
7190         ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7191
7192         /* allow vendors to fix quirks */
7193         ufshcd_vops_fixup_dev_quirks(hba);
7194 }
7195
7196 static int ufs_get_device_desc(struct ufs_hba *hba)
7197 {
7198         int err;
7199         u8 model_index;
7200         u8 *desc_buf;
7201         struct ufs_dev_info *dev_info = &hba->dev_info;
7202
7203         desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7204         if (!desc_buf) {
7205                 err = -ENOMEM;
7206                 goto out;
7207         }
7208
7209         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7210                                      hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7211         if (err) {
7212                 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7213                         __func__, err);
7214                 goto out;
7215         }
7216
7217         /*
7218          * getting vendor (manufacturerID) and Bank Index in big endian
7219          * format
7220          */
7221         dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7222                                      desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7223
7224         /* getting Specification Version in big endian format */
7225         dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7226                                       desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7227
7228         model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7229
7230         err = ufshcd_read_string_desc(hba, model_index,
7231                                       &dev_info->model, SD_ASCII_STD);
7232         if (err < 0) {
7233                 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7234                         __func__, err);
7235                 goto out;
7236         }
7237
7238         ufs_fixup_device_setup(hba);
7239
7240         ufshcd_wb_probe(hba, desc_buf);
7241
7242         /*
7243          * ufshcd_read_string_desc returns size of the string
7244          * reset the error value
7245          */
7246         err = 0;
7247
7248 out:
7249         kfree(desc_buf);
7250         return err;
7251 }
7252
7253 static void ufs_put_device_desc(struct ufs_hba *hba)
7254 {
7255         struct ufs_dev_info *dev_info = &hba->dev_info;
7256
7257         kfree(dev_info->model);
7258         dev_info->model = NULL;
7259 }
7260
7261 /**
7262  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7263  * @hba: per-adapter instance
7264  *
7265  * PA_TActivate parameter can be tuned manually if UniPro version is less than
7266  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7267  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7268  * the hibern8 exit latency.
7269  *
7270  * Returns zero on success, non-zero error value on failure.
7271  */
7272 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7273 {
7274         int ret = 0;
7275         u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7276
7277         ret = ufshcd_dme_peer_get(hba,
7278                                   UIC_ARG_MIB_SEL(
7279                                         RX_MIN_ACTIVATETIME_CAPABILITY,
7280                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7281                                   &peer_rx_min_activatetime);
7282         if (ret)
7283                 goto out;
7284
7285         /* make sure proper unit conversion is applied */
7286         tuned_pa_tactivate =
7287                 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7288                  / PA_TACTIVATE_TIME_UNIT_US);
7289         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7290                              tuned_pa_tactivate);
7291
7292 out:
7293         return ret;
7294 }
7295
7296 /**
7297  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7298  * @hba: per-adapter instance
7299  *
7300  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7301  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7302  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7303  * This optimal value can help reduce the hibern8 exit latency.
7304  *
7305  * Returns zero on success, non-zero error value on failure.
7306  */
7307 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7308 {
7309         int ret = 0;
7310         u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7311         u32 max_hibern8_time, tuned_pa_hibern8time;
7312
7313         ret = ufshcd_dme_get(hba,
7314                              UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7315                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7316                                   &local_tx_hibern8_time_cap);
7317         if (ret)
7318                 goto out;
7319
7320         ret = ufshcd_dme_peer_get(hba,
7321                                   UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7322                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7323                                   &peer_rx_hibern8_time_cap);
7324         if (ret)
7325                 goto out;
7326
7327         max_hibern8_time = max(local_tx_hibern8_time_cap,
7328                                peer_rx_hibern8_time_cap);
7329         /* make sure proper unit conversion is applied */
7330         tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7331                                 / PA_HIBERN8_TIME_UNIT_US);
7332         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7333                              tuned_pa_hibern8time);
7334 out:
7335         return ret;
7336 }
7337
7338 /**
7339  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7340  * less than device PA_TACTIVATE time.
7341  * @hba: per-adapter instance
7342  *
7343  * Some UFS devices require host PA_TACTIVATE to be lower than device
7344  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7345  * for such devices.
7346  *
7347  * Returns zero on success, non-zero error value on failure.
7348  */
7349 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7350 {
7351         int ret = 0;
7352         u32 granularity, peer_granularity;
7353         u32 pa_tactivate, peer_pa_tactivate;
7354         u32 pa_tactivate_us, peer_pa_tactivate_us;
7355         u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7356
7357         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7358                                   &granularity);
7359         if (ret)
7360                 goto out;
7361
7362         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7363                                   &peer_granularity);
7364         if (ret)
7365                 goto out;
7366
7367         if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7368             (granularity > PA_GRANULARITY_MAX_VAL)) {
7369                 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7370                         __func__, granularity);
7371                 return -EINVAL;
7372         }
7373
7374         if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7375             (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7376                 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7377                         __func__, peer_granularity);
7378                 return -EINVAL;
7379         }
7380
7381         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7382         if (ret)
7383                 goto out;
7384
7385         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7386                                   &peer_pa_tactivate);
7387         if (ret)
7388                 goto out;
7389
7390         pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7391         peer_pa_tactivate_us = peer_pa_tactivate *
7392                              gran_to_us_table[peer_granularity - 1];
7393
7394         if (pa_tactivate_us > peer_pa_tactivate_us) {
7395                 u32 new_peer_pa_tactivate;
7396
7397                 new_peer_pa_tactivate = pa_tactivate_us /
7398                                       gran_to_us_table[peer_granularity - 1];
7399                 new_peer_pa_tactivate++;
7400                 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7401                                           new_peer_pa_tactivate);
7402         }
7403
7404 out:
7405         return ret;
7406 }
7407
7408 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7409 {
7410         if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7411                 ufshcd_tune_pa_tactivate(hba);
7412                 ufshcd_tune_pa_hibern8time(hba);
7413         }
7414
7415         ufshcd_vops_apply_dev_quirks(hba);
7416
7417         if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7418                 /* set 1ms timeout for PA_TACTIVATE */
7419                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7420
7421         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7422                 ufshcd_quirk_tune_host_pa_tactivate(hba);
7423 }
7424
7425 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7426 {
7427         hba->ufs_stats.hibern8_exit_cnt = 0;
7428         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7429         hba->req_abort_count = 0;
7430 }
7431
7432 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7433 {
7434         int err;
7435         size_t buff_len;
7436         u8 *desc_buf;
7437
7438         buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7439         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7440         if (!desc_buf) {
7441                 err = -ENOMEM;
7442                 goto out;
7443         }
7444
7445         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7446                                      desc_buf, buff_len);
7447         if (err) {
7448                 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7449                                 __func__, err);
7450                 goto out;
7451         }
7452
7453         if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7454                 hba->dev_info.max_lu_supported = 32;
7455         else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7456                 hba->dev_info.max_lu_supported = 8;
7457
7458 out:
7459         kfree(desc_buf);
7460         return err;
7461 }
7462
7463 static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7464         {19200000, REF_CLK_FREQ_19_2_MHZ},
7465         {26000000, REF_CLK_FREQ_26_MHZ},
7466         {38400000, REF_CLK_FREQ_38_4_MHZ},
7467         {52000000, REF_CLK_FREQ_52_MHZ},
7468         {0, REF_CLK_FREQ_INVAL},
7469 };
7470
7471 static enum ufs_ref_clk_freq
7472 ufs_get_bref_clk_from_hz(unsigned long freq)
7473 {
7474         int i;
7475
7476         for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7477                 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7478                         return ufs_ref_clk_freqs[i].val;
7479
7480         return REF_CLK_FREQ_INVAL;
7481 }
7482
7483 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7484 {
7485         unsigned long freq;
7486
7487         freq = clk_get_rate(refclk);
7488
7489         hba->dev_ref_clk_freq =
7490                 ufs_get_bref_clk_from_hz(freq);
7491
7492         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7493                 dev_err(hba->dev,
7494                 "invalid ref_clk setting = %ld\n", freq);
7495 }
7496
7497 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7498 {
7499         int err;
7500         u32 ref_clk;
7501         u32 freq = hba->dev_ref_clk_freq;
7502
7503         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7504                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7505
7506         if (err) {
7507                 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7508                         err);
7509                 goto out;
7510         }
7511
7512         if (ref_clk == freq)
7513                 goto out; /* nothing to update */
7514
7515         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7516                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7517
7518         if (err) {
7519                 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7520                         ufs_ref_clk_freqs[freq].freq_hz);
7521                 goto out;
7522         }
7523
7524         dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7525                         ufs_ref_clk_freqs[freq].freq_hz);
7526
7527 out:
7528         return err;
7529 }
7530
7531 static int ufshcd_device_params_init(struct ufs_hba *hba)
7532 {
7533         bool flag;
7534         int ret, i;
7535
7536          /* Init device descriptor sizes */
7537         for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7538                 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
7539
7540         /* Init UFS geometry descriptor related parameters */
7541         ret = ufshcd_device_geo_params_init(hba);
7542         if (ret)
7543                 goto out;
7544
7545         /* Check and apply UFS device quirks */
7546         ret = ufs_get_device_desc(hba);
7547         if (ret) {
7548                 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7549                         __func__, ret);
7550                 goto out;
7551         }
7552
7553         ufshcd_get_ref_clk_gating_wait(hba);
7554
7555         if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7556                         QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
7557                 hba->dev_info.f_power_on_wp_en = flag;
7558
7559         /* Probe maximum power mode co-supported by both UFS host and device */
7560         if (ufshcd_get_max_pwr_mode(hba))
7561                 dev_err(hba->dev,
7562                         "%s: Failed getting max supported power mode\n",
7563                         __func__);
7564 out:
7565         return ret;
7566 }
7567
7568 /**
7569  * ufshcd_add_lus - probe and add UFS logical units
7570  * @hba: per-adapter instance
7571  */
7572 static int ufshcd_add_lus(struct ufs_hba *hba)
7573 {
7574         int ret;
7575
7576         /* Add required well known logical units to scsi mid layer */
7577         ret = ufshcd_scsi_add_wlus(hba);
7578         if (ret)
7579                 goto out;
7580
7581         /* Initialize devfreq after UFS device is detected */
7582         if (ufshcd_is_clkscaling_supported(hba)) {
7583                 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7584                         &hba->pwr_info,
7585                         sizeof(struct ufs_pa_layer_attr));
7586                 hba->clk_scaling.saved_pwr_info.is_valid = true;
7587                 if (!hba->devfreq) {
7588                         ret = ufshcd_devfreq_init(hba);
7589                         if (ret)
7590                                 goto out;
7591                 }
7592
7593                 hba->clk_scaling.is_allowed = true;
7594         }
7595
7596         ufs_bsg_probe(hba);
7597         scsi_scan_host(hba->host);
7598         pm_runtime_put_sync(hba->dev);
7599
7600 out:
7601         return ret;
7602 }
7603
7604 /**
7605  * ufshcd_probe_hba - probe hba to detect device and initialize
7606  * @hba: per-adapter instance
7607  * @async: asynchronous execution or not
7608  *
7609  * Execute link-startup and verify device initialization
7610  */
7611 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
7612 {
7613         int ret;
7614         unsigned long flags;
7615         ktime_t start = ktime_get();
7616
7617         ret = ufshcd_link_startup(hba);
7618         if (ret)
7619                 goto out;
7620
7621         /* Debug counters initialization */
7622         ufshcd_clear_dbg_ufs_stats(hba);
7623
7624         /* UniPro link is active now */
7625         ufshcd_set_link_active(hba);
7626
7627         /* Verify device initialization by sending NOP OUT UPIU */
7628         ret = ufshcd_verify_dev_init(hba);
7629         if (ret)
7630                 goto out;
7631
7632         /* Initiate UFS initialization, and waiting until completion */
7633         ret = ufshcd_complete_dev_init(hba);
7634         if (ret)
7635                 goto out;
7636
7637         /*
7638          * Initialize UFS device parameters used by driver, these
7639          * parameters are associated with UFS descriptors.
7640          */
7641         if (async) {
7642                 ret = ufshcd_device_params_init(hba);
7643                 if (ret)
7644                         goto out;
7645         }
7646
7647         ufshcd_tune_unipro_params(hba);
7648
7649         /* UFS device is also active now */
7650         ufshcd_set_ufs_dev_active(hba);
7651         ufshcd_force_reset_auto_bkops(hba);
7652         hba->wlun_dev_clr_ua = true;
7653
7654         /* Gear up to HS gear if supported */
7655         if (hba->max_pwr_info.is_valid) {
7656                 /*
7657                  * Set the right value to bRefClkFreq before attempting to
7658                  * switch to HS gears.
7659                  */
7660                 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
7661                         ufshcd_set_dev_ref_clk(hba);
7662                 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
7663                 if (ret) {
7664                         dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
7665                                         __func__, ret);
7666                         goto out;
7667                 }
7668                 ufshcd_print_pwr_info(hba);
7669         }
7670
7671         /*
7672          * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
7673          * and for removable UFS card as well, hence always set the parameter.
7674          * Note: Error handler may issue the device reset hence resetting
7675          * bActiveICCLevel as well so it is always safe to set this here.
7676          */
7677         ufshcd_set_active_icc_lvl(hba);
7678
7679         ufshcd_wb_config(hba);
7680         /* Enable Auto-Hibernate if configured */
7681         ufshcd_auto_hibern8_enable(hba);
7682
7683 out:
7684         spin_lock_irqsave(hba->host->host_lock, flags);
7685         if (ret)
7686                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7687         else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
7688                 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
7689         spin_unlock_irqrestore(hba->host->host_lock, flags);
7690
7691         trace_ufshcd_init(dev_name(hba->dev), ret,
7692                 ktime_to_us(ktime_sub(ktime_get(), start)),
7693                 hba->curr_dev_pwr_mode, hba->uic_link_state);
7694         return ret;
7695 }
7696
7697 /**
7698  * ufshcd_async_scan - asynchronous execution for probing hba
7699  * @data: data pointer to pass to this function
7700  * @cookie: cookie data
7701  */
7702 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7703 {
7704         struct ufs_hba *hba = (struct ufs_hba *)data;
7705         int ret;
7706
7707         /* Initialize hba, detect and initialize UFS device */
7708         ret = ufshcd_probe_hba(hba, true);
7709         if (ret)
7710                 goto out;
7711
7712         /* Probe and add UFS logical units  */
7713         ret = ufshcd_add_lus(hba);
7714 out:
7715         /*
7716          * If we failed to initialize the device or the device is not
7717          * present, turn off the power/clocks etc.
7718          */
7719         if (ret) {
7720                 pm_runtime_put_sync(hba->dev);
7721                 ufshcd_exit_clk_scaling(hba);
7722                 ufshcd_hba_exit(hba);
7723         }
7724 }
7725
7726 static const struct attribute_group *ufshcd_driver_groups[] = {
7727         &ufs_sysfs_unit_descriptor_group,
7728         &ufs_sysfs_lun_attributes_group,
7729         NULL,
7730 };
7731
7732 static struct ufs_hba_variant_params ufs_hba_vps = {
7733         .hba_enable_delay_us            = 1000,
7734         .wb_flush_threshold             = UFS_WB_BUF_REMAIN_PERCENT(40),
7735         .devfreq_profile.polling_ms     = 100,
7736         .devfreq_profile.target         = ufshcd_devfreq_target,
7737         .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
7738         .ondemand_data.upthreshold      = 70,
7739         .ondemand_data.downdifferential = 5,
7740 };
7741
7742 static struct scsi_host_template ufshcd_driver_template = {
7743         .module                 = THIS_MODULE,
7744         .name                   = UFSHCD,
7745         .proc_name              = UFSHCD,
7746         .queuecommand           = ufshcd_queuecommand,
7747         .slave_alloc            = ufshcd_slave_alloc,
7748         .slave_configure        = ufshcd_slave_configure,
7749         .slave_destroy          = ufshcd_slave_destroy,
7750         .change_queue_depth     = ufshcd_change_queue_depth,
7751         .eh_abort_handler       = ufshcd_abort,
7752         .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7753         .eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
7754         .this_id                = -1,
7755         .sg_tablesize           = SG_ALL,
7756         .cmd_per_lun            = UFSHCD_CMD_PER_LUN,
7757         .can_queue              = UFSHCD_CAN_QUEUE,
7758         .max_segment_size       = PRDT_DATA_BYTE_COUNT_MAX,
7759         .max_host_blocked       = 1,
7760         .track_queue_depth      = 1,
7761         .sdev_groups            = ufshcd_driver_groups,
7762         .dma_boundary           = PAGE_SIZE - 1,
7763         .rpm_autosuspend_delay  = RPM_AUTOSUSPEND_DELAY_MS,
7764 };
7765
7766 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7767                                    int ua)
7768 {
7769         int ret;
7770
7771         if (!vreg)
7772                 return 0;
7773
7774         /*
7775          * "set_load" operation shall be required on those regulators
7776          * which specifically configured current limitation. Otherwise
7777          * zero max_uA may cause unexpected behavior when regulator is
7778          * enabled or set as high power mode.
7779          */
7780         if (!vreg->max_uA)
7781                 return 0;
7782
7783         ret = regulator_set_load(vreg->reg, ua);
7784         if (ret < 0) {
7785                 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7786                                 __func__, vreg->name, ua, ret);
7787         }
7788
7789         return ret;
7790 }
7791
7792 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7793                                          struct ufs_vreg *vreg)
7794 {
7795         return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
7796 }
7797
7798 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7799                                          struct ufs_vreg *vreg)
7800 {
7801         if (!vreg)
7802                 return 0;
7803
7804         return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
7805 }
7806
7807 static int ufshcd_config_vreg(struct device *dev,
7808                 struct ufs_vreg *vreg, bool on)
7809 {
7810         int ret = 0;
7811         struct regulator *reg;
7812         const char *name;
7813         int min_uV, uA_load;
7814
7815         BUG_ON(!vreg);
7816
7817         reg = vreg->reg;
7818         name = vreg->name;
7819
7820         if (regulator_count_voltages(reg) > 0) {
7821                 uA_load = on ? vreg->max_uA : 0;
7822                 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7823                 if (ret)
7824                         goto out;
7825
7826                 if (vreg->min_uV && vreg->max_uV) {
7827                         min_uV = on ? vreg->min_uV : 0;
7828                         ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7829                         if (ret)
7830                                 dev_err(dev,
7831                                         "%s: %s set voltage failed, err=%d\n",
7832                                         __func__, name, ret);
7833                 }
7834         }
7835 out:
7836         return ret;
7837 }
7838
7839 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7840 {
7841         int ret = 0;
7842
7843         if (!vreg || vreg->enabled)
7844                 goto out;
7845
7846         ret = ufshcd_config_vreg(dev, vreg, true);
7847         if (!ret)
7848                 ret = regulator_enable(vreg->reg);
7849
7850         if (!ret)
7851                 vreg->enabled = true;
7852         else
7853                 dev_err(dev, "%s: %s enable failed, err=%d\n",
7854                                 __func__, vreg->name, ret);
7855 out:
7856         return ret;
7857 }
7858
7859 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7860 {
7861         int ret = 0;
7862
7863         if (!vreg || !vreg->enabled)
7864                 goto out;
7865
7866         ret = regulator_disable(vreg->reg);
7867
7868         if (!ret) {
7869                 /* ignore errors on applying disable config */
7870                 ufshcd_config_vreg(dev, vreg, false);
7871                 vreg->enabled = false;
7872         } else {
7873                 dev_err(dev, "%s: %s disable failed, err=%d\n",
7874                                 __func__, vreg->name, ret);
7875         }
7876 out:
7877         return ret;
7878 }
7879
7880 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7881 {
7882         int ret = 0;
7883         struct device *dev = hba->dev;
7884         struct ufs_vreg_info *info = &hba->vreg_info;
7885
7886         ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7887         if (ret)
7888                 goto out;
7889
7890         ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7891         if (ret)
7892                 goto out;
7893
7894         ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7895
7896 out:
7897         if (ret) {
7898                 ufshcd_toggle_vreg(dev, info->vccq2, false);
7899                 ufshcd_toggle_vreg(dev, info->vccq, false);
7900                 ufshcd_toggle_vreg(dev, info->vcc, false);
7901         }
7902         return ret;
7903 }
7904
7905 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7906 {
7907         struct ufs_vreg_info *info = &hba->vreg_info;
7908
7909         return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
7910 }
7911
7912 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7913 {
7914         int ret = 0;
7915
7916         if (!vreg)
7917                 goto out;
7918
7919         vreg->reg = devm_regulator_get(dev, vreg->name);
7920         if (IS_ERR(vreg->reg)) {
7921                 ret = PTR_ERR(vreg->reg);
7922                 dev_err(dev, "%s: %s get failed, err=%d\n",
7923                                 __func__, vreg->name, ret);
7924         }
7925 out:
7926         return ret;
7927 }
7928
7929 static int ufshcd_init_vreg(struct ufs_hba *hba)
7930 {
7931         int ret = 0;
7932         struct device *dev = hba->dev;
7933         struct ufs_vreg_info *info = &hba->vreg_info;
7934
7935         ret = ufshcd_get_vreg(dev, info->vcc);
7936         if (ret)
7937                 goto out;
7938
7939         ret = ufshcd_get_vreg(dev, info->vccq);
7940         if (!ret)
7941                 ret = ufshcd_get_vreg(dev, info->vccq2);
7942 out:
7943         return ret;
7944 }
7945
7946 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7947 {
7948         struct ufs_vreg_info *info = &hba->vreg_info;
7949
7950         if (info)
7951                 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7952
7953         return 0;
7954 }
7955
7956 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7957                                         bool skip_ref_clk)
7958 {
7959         int ret = 0;
7960         struct ufs_clk_info *clki;
7961         struct list_head *head = &hba->clk_list_head;
7962         unsigned long flags;
7963         ktime_t start = ktime_get();
7964         bool clk_state_changed = false;
7965
7966         if (list_empty(head))
7967                 goto out;
7968
7969         ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7970         if (ret)
7971                 return ret;
7972
7973         list_for_each_entry(clki, head, list) {
7974                 if (!IS_ERR_OR_NULL(clki->clk)) {
7975                         if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7976                                 continue;
7977
7978                         clk_state_changed = on ^ clki->enabled;
7979                         if (on && !clki->enabled) {
7980                                 ret = clk_prepare_enable(clki->clk);
7981                                 if (ret) {
7982                                         dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7983                                                 __func__, clki->name, ret);
7984                                         goto out;
7985                                 }
7986                         } else if (!on && clki->enabled) {
7987                                 clk_disable_unprepare(clki->clk);
7988                         }
7989                         clki->enabled = on;
7990                         dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7991                                         clki->name, on ? "en" : "dis");
7992                 }
7993         }
7994
7995         ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7996         if (ret)
7997                 return ret;
7998
7999 out:
8000         if (ret) {
8001                 list_for_each_entry(clki, head, list) {
8002                         if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8003                                 clk_disable_unprepare(clki->clk);
8004                 }
8005         } else if (!ret && on) {
8006                 spin_lock_irqsave(hba->host->host_lock, flags);
8007                 hba->clk_gating.state = CLKS_ON;
8008                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8009                                         hba->clk_gating.state);
8010                 spin_unlock_irqrestore(hba->host->host_lock, flags);
8011         }
8012
8013         if (clk_state_changed)
8014                 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8015                         (on ? "on" : "off"),
8016                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8017         return ret;
8018 }
8019
8020 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8021 {
8022         return  __ufshcd_setup_clocks(hba, on, false);
8023 }
8024
8025 static int ufshcd_init_clocks(struct ufs_hba *hba)
8026 {
8027         int ret = 0;
8028         struct ufs_clk_info *clki;
8029         struct device *dev = hba->dev;
8030         struct list_head *head = &hba->clk_list_head;
8031
8032         if (list_empty(head))
8033                 goto out;
8034
8035         list_for_each_entry(clki, head, list) {
8036                 if (!clki->name)
8037                         continue;
8038
8039                 clki->clk = devm_clk_get(dev, clki->name);
8040                 if (IS_ERR(clki->clk)) {
8041                         ret = PTR_ERR(clki->clk);
8042                         dev_err(dev, "%s: %s clk get failed, %d\n",
8043                                         __func__, clki->name, ret);
8044                         goto out;
8045                 }
8046
8047                 /*
8048                  * Parse device ref clk freq as per device tree "ref_clk".
8049                  * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8050                  * in ufshcd_alloc_host().
8051                  */
8052                 if (!strcmp(clki->name, "ref_clk"))
8053                         ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8054
8055                 if (clki->max_freq) {
8056                         ret = clk_set_rate(clki->clk, clki->max_freq);
8057                         if (ret) {
8058                                 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8059                                         __func__, clki->name,
8060                                         clki->max_freq, ret);
8061                                 goto out;
8062                         }
8063                         clki->curr_freq = clki->max_freq;
8064                 }
8065                 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8066                                 clki->name, clk_get_rate(clki->clk));
8067         }
8068 out:
8069         return ret;
8070 }
8071
8072 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8073 {
8074         int err = 0;
8075
8076         if (!hba->vops)
8077                 goto out;
8078
8079         err = ufshcd_vops_init(hba);
8080         if (err)
8081                 goto out;
8082
8083         err = ufshcd_vops_setup_regulators(hba, true);
8084         if (err)
8085                 ufshcd_vops_exit(hba);
8086 out:
8087         if (err)
8088                 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8089                         __func__, ufshcd_get_var_name(hba), err);
8090         return err;
8091 }
8092
8093 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8094 {
8095         if (!hba->vops)
8096                 return;
8097
8098         ufshcd_vops_setup_regulators(hba, false);
8099
8100         ufshcd_vops_exit(hba);
8101 }
8102
8103 static int ufshcd_hba_init(struct ufs_hba *hba)
8104 {
8105         int err;
8106
8107         /*
8108          * Handle host controller power separately from the UFS device power
8109          * rails as it will help controlling the UFS host controller power
8110          * collapse easily which is different than UFS device power collapse.
8111          * Also, enable the host controller power before we go ahead with rest
8112          * of the initialization here.
8113          */
8114         err = ufshcd_init_hba_vreg(hba);
8115         if (err)
8116                 goto out;
8117
8118         err = ufshcd_setup_hba_vreg(hba, true);
8119         if (err)
8120                 goto out;
8121
8122         err = ufshcd_init_clocks(hba);
8123         if (err)
8124                 goto out_disable_hba_vreg;
8125
8126         err = ufshcd_setup_clocks(hba, true);
8127         if (err)
8128                 goto out_disable_hba_vreg;
8129
8130         err = ufshcd_init_vreg(hba);
8131         if (err)
8132                 goto out_disable_clks;
8133
8134         err = ufshcd_setup_vreg(hba, true);
8135         if (err)
8136                 goto out_disable_clks;
8137
8138         err = ufshcd_variant_hba_init(hba);
8139         if (err)
8140                 goto out_disable_vreg;
8141
8142         hba->is_powered = true;
8143         goto out;
8144
8145 out_disable_vreg:
8146         ufshcd_setup_vreg(hba, false);
8147 out_disable_clks:
8148         ufshcd_setup_clocks(hba, false);
8149 out_disable_hba_vreg:
8150         ufshcd_setup_hba_vreg(hba, false);
8151 out:
8152         return err;
8153 }
8154
8155 static void ufshcd_hba_exit(struct ufs_hba *hba)
8156 {
8157         if (hba->is_powered) {
8158                 ufshcd_variant_hba_exit(hba);
8159                 ufshcd_setup_vreg(hba, false);
8160                 ufshcd_suspend_clkscaling(hba);
8161                 if (ufshcd_is_clkscaling_supported(hba))
8162                         if (hba->devfreq)
8163                                 ufshcd_suspend_clkscaling(hba);
8164                 ufshcd_setup_clocks(hba, false);
8165                 ufshcd_setup_hba_vreg(hba, false);
8166                 hba->is_powered = false;
8167                 ufs_put_device_desc(hba);
8168         }
8169 }
8170
8171 static int
8172 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
8173 {
8174         unsigned char cmd[6] = {REQUEST_SENSE,
8175                                 0,
8176                                 0,
8177                                 0,
8178                                 UFS_SENSE_SIZE,
8179                                 0};
8180         char *buffer;
8181         int ret;
8182
8183         buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
8184         if (!buffer) {
8185                 ret = -ENOMEM;
8186                 goto out;
8187         }
8188
8189         ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
8190                         UFS_SENSE_SIZE, NULL, NULL,
8191                         msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
8192         if (ret)
8193                 pr_err("%s: failed with err %d\n", __func__, ret);
8194
8195         kfree(buffer);
8196 out:
8197         return ret;
8198 }
8199
8200 /**
8201  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8202  *                           power mode
8203  * @hba: per adapter instance
8204  * @pwr_mode: device power mode to set
8205  *
8206  * Returns 0 if requested power mode is set successfully
8207  * Returns non-zero if failed to set the requested power mode
8208  */
8209 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8210                                      enum ufs_dev_pwr_mode pwr_mode)
8211 {
8212         unsigned char cmd[6] = { START_STOP };
8213         struct scsi_sense_hdr sshdr;
8214         struct scsi_device *sdp;
8215         unsigned long flags;
8216         int ret;
8217
8218         spin_lock_irqsave(hba->host->host_lock, flags);
8219         sdp = hba->sdev_ufs_device;
8220         if (sdp) {
8221                 ret = scsi_device_get(sdp);
8222                 if (!ret && !scsi_device_online(sdp)) {
8223                         ret = -ENODEV;
8224                         scsi_device_put(sdp);
8225                 }
8226         } else {
8227                 ret = -ENODEV;
8228         }
8229         spin_unlock_irqrestore(hba->host->host_lock, flags);
8230
8231         if (ret)
8232                 return ret;
8233
8234         /*
8235          * If scsi commands fail, the scsi mid-layer schedules scsi error-
8236          * handling, which would wait for host to be resumed. Since we know
8237          * we are functional while we are here, skip host resume in error
8238          * handling context.
8239          */
8240         hba->host->eh_noresume = 1;
8241         if (hba->wlun_dev_clr_ua) {
8242                 ret = ufshcd_send_request_sense(hba, sdp);
8243                 if (ret)
8244                         goto out;
8245                 /* Unit attention condition is cleared now */
8246                 hba->wlun_dev_clr_ua = false;
8247         }
8248
8249         cmd[4] = pwr_mode << 4;
8250
8251         /*
8252          * Current function would be generally called from the power management
8253          * callbacks hence set the RQF_PM flag so that it doesn't resume the
8254          * already suspended childs.
8255          */
8256         ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8257                         START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8258         if (ret) {
8259                 sdev_printk(KERN_WARNING, sdp,
8260                             "START_STOP failed for power mode: %d, result %x\n",
8261                             pwr_mode, ret);
8262                 if (driver_byte(ret) == DRIVER_SENSE)
8263                         scsi_print_sense_hdr(sdp, NULL, &sshdr);
8264         }
8265
8266         if (!ret)
8267                 hba->curr_dev_pwr_mode = pwr_mode;
8268 out:
8269         scsi_device_put(sdp);
8270         hba->host->eh_noresume = 0;
8271         return ret;
8272 }
8273
8274 static int ufshcd_link_state_transition(struct ufs_hba *hba,
8275                                         enum uic_link_state req_link_state,
8276                                         int check_for_bkops)
8277 {
8278         int ret = 0;
8279
8280         if (req_link_state == hba->uic_link_state)
8281                 return 0;
8282
8283         if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8284                 ret = ufshcd_uic_hibern8_enter(hba);
8285                 if (!ret) {
8286                         ufshcd_set_link_hibern8(hba);
8287                 } else {
8288                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8289                                         __func__, ret);
8290                         goto out;
8291                 }
8292         }
8293         /*
8294          * If autobkops is enabled, link can't be turned off because
8295          * turning off the link would also turn off the device.
8296          */
8297         else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8298                  (!check_for_bkops || !hba->auto_bkops_enabled)) {
8299                 /*
8300                  * Let's make sure that link is in low power mode, we are doing
8301                  * this currently by putting the link in Hibern8. Otherway to
8302                  * put the link in low power mode is to send the DME end point
8303                  * to device and then send the DME reset command to local
8304                  * unipro. But putting the link in hibern8 is much faster.
8305                  */
8306                 ret = ufshcd_uic_hibern8_enter(hba);
8307                 if (ret) {
8308                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8309                                         __func__, ret);
8310                         goto out;
8311                 }
8312                 /*
8313                  * Change controller state to "reset state" which
8314                  * should also put the link in off/reset state
8315                  */
8316                 ufshcd_hba_stop(hba);
8317                 /*
8318                  * TODO: Check if we need any delay to make sure that
8319                  * controller is reset
8320                  */
8321                 ufshcd_set_link_off(hba);
8322         }
8323
8324 out:
8325         return ret;
8326 }
8327
8328 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8329 {
8330         bool vcc_off = false;
8331
8332         /*
8333          * It seems some UFS devices may keep drawing more than sleep current
8334          * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8335          * To avoid this situation, add 2ms delay before putting these UFS
8336          * rails in LPM mode.
8337          */
8338         if (!ufshcd_is_link_active(hba) &&
8339             hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8340                 usleep_range(2000, 2100);
8341
8342         /*
8343          * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8344          * power.
8345          *
8346          * If UFS device and link is in OFF state, all power supplies (VCC,
8347          * VCCQ, VCCQ2) can be turned off if power on write protect is not
8348          * required. If UFS link is inactive (Hibern8 or OFF state) and device
8349          * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8350          *
8351          * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8352          * in low power state which would save some power.
8353          *
8354          * If Write Booster is enabled and the device needs to flush the WB
8355          * buffer OR if bkops status is urgent for WB, keep Vcc on.
8356          */
8357         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8358             !hba->dev_info.is_lu_power_on_wp) {
8359                 ufshcd_setup_vreg(hba, false);
8360                 vcc_off = true;
8361         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8362                 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8363                 vcc_off = true;
8364                 if (!ufshcd_is_link_active(hba)) {
8365                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8366                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8367                 }
8368         }
8369
8370         /*
8371          * Some UFS devices require delay after VCC power rail is turned-off.
8372          */
8373         if (vcc_off && hba->vreg_info.vcc &&
8374                 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8375                 usleep_range(5000, 5100);
8376 }
8377
8378 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8379 {
8380         int ret = 0;
8381
8382         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8383             !hba->dev_info.is_lu_power_on_wp) {
8384                 ret = ufshcd_setup_vreg(hba, true);
8385         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8386                 if (!ret && !ufshcd_is_link_active(hba)) {
8387                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8388                         if (ret)
8389                                 goto vcc_disable;
8390                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8391                         if (ret)
8392                                 goto vccq_lpm;
8393                 }
8394                 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8395         }
8396         goto out;
8397
8398 vccq_lpm:
8399         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8400 vcc_disable:
8401         ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8402 out:
8403         return ret;
8404 }
8405
8406 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8407 {
8408         if (ufshcd_is_link_off(hba))
8409                 ufshcd_setup_hba_vreg(hba, false);
8410 }
8411
8412 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8413 {
8414         if (ufshcd_is_link_off(hba))
8415                 ufshcd_setup_hba_vreg(hba, true);
8416 }
8417
8418 /**
8419  * ufshcd_suspend - helper function for suspend operations
8420  * @hba: per adapter instance
8421  * @pm_op: desired low power operation type
8422  *
8423  * This function will try to put the UFS device and link into low power
8424  * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
8425  * (System PM level).
8426  *
8427  * If this function is called during shutdown, it will make sure that
8428  * both UFS device and UFS link is powered off.
8429  *
8430  * NOTE: UFS device & link must be active before we enter in this function.
8431  *
8432  * Returns 0 for success and non-zero for failure
8433  */
8434 static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8435 {
8436         int ret = 0;
8437         enum ufs_pm_level pm_lvl;
8438         enum ufs_dev_pwr_mode req_dev_pwr_mode;
8439         enum uic_link_state req_link_state;
8440
8441         hba->pm_op_in_progress = 1;
8442         if (!ufshcd_is_shutdown_pm(pm_op)) {
8443                 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
8444                          hba->rpm_lvl : hba->spm_lvl;
8445                 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8446                 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8447         } else {
8448                 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8449                 req_link_state = UIC_LINK_OFF_STATE;
8450         }
8451
8452         /*
8453          * If we can't transition into any of the low power modes
8454          * just gate the clocks.
8455          */
8456         ufshcd_hold(hba, false);
8457         hba->clk_gating.is_suspended = true;
8458
8459         if (hba->clk_scaling.is_allowed) {
8460                 cancel_work_sync(&hba->clk_scaling.suspend_work);
8461                 cancel_work_sync(&hba->clk_scaling.resume_work);
8462                 ufshcd_suspend_clkscaling(hba);
8463         }
8464
8465         if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8466                         req_link_state == UIC_LINK_ACTIVE_STATE) {
8467                 goto disable_clks;
8468         }
8469
8470         if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8471             (req_link_state == hba->uic_link_state))
8472                 goto enable_gating;
8473
8474         /* UFS device & link must be active before we enter in this function */
8475         if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8476                 ret = -EINVAL;
8477                 goto enable_gating;
8478         }
8479
8480         if (ufshcd_is_runtime_pm(pm_op)) {
8481                 if (ufshcd_can_autobkops_during_suspend(hba)) {
8482                         /*
8483                          * The device is idle with no requests in the queue,
8484                          * allow background operations if bkops status shows
8485                          * that performance might be impacted.
8486                          */
8487                         ret = ufshcd_urgent_bkops(hba);
8488                         if (ret)
8489                                 goto enable_gating;
8490                 } else {
8491                         /* make sure that auto bkops is disabled */
8492                         ufshcd_disable_auto_bkops(hba);
8493                 }
8494                 /*
8495                  * If device needs to do BKOP or WB buffer flush during
8496                  * Hibern8, keep device power mode as "active power mode"
8497                  * and VCC supply.
8498                  */
8499                 hba->dev_info.b_rpm_dev_flush_capable =
8500                         hba->auto_bkops_enabled ||
8501                         (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8502                         ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8503                         ufshcd_is_auto_hibern8_enabled(hba))) &&
8504                         ufshcd_wb_need_flush(hba));
8505         }
8506
8507         if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8508                 if ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
8509                     !ufshcd_is_runtime_pm(pm_op)) {
8510                         /* ensure that bkops is disabled */
8511                         ufshcd_disable_auto_bkops(hba);
8512                 }
8513
8514                 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8515                         ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8516                         if (ret)
8517                                 goto enable_gating;
8518                 }
8519         }
8520
8521         flush_work(&hba->eeh_work);
8522         ret = ufshcd_link_state_transition(hba, req_link_state, 1);
8523         if (ret)
8524                 goto set_dev_active;
8525
8526         ufshcd_vreg_set_lpm(hba);
8527
8528 disable_clks:
8529         /*
8530          * Call vendor specific suspend callback. As these callbacks may access
8531          * vendor specific host controller register space call them before the
8532          * host clocks are ON.
8533          */
8534         ret = ufshcd_vops_suspend(hba, pm_op);
8535         if (ret)
8536                 goto set_link_active;
8537         /*
8538          * Disable the host irq as host controller as there won't be any
8539          * host controller transaction expected till resume.
8540          */
8541         ufshcd_disable_irq(hba);
8542
8543         if (!ufshcd_is_link_active(hba))
8544                 ufshcd_setup_clocks(hba, false);
8545         else
8546                 /* If link is active, device ref_clk can't be switched off */
8547                 __ufshcd_setup_clocks(hba, false, true);
8548
8549         if (ufshcd_is_clkgating_allowed(hba)) {
8550                 hba->clk_gating.state = CLKS_OFF;
8551                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8552                                         hba->clk_gating.state);
8553         }
8554
8555         /* Put the host controller in low power mode if possible */
8556         ufshcd_hba_vreg_set_lpm(hba);
8557         goto out;
8558
8559 set_link_active:
8560         if (hba->clk_scaling.is_allowed)
8561                 ufshcd_resume_clkscaling(hba);
8562         ufshcd_vreg_set_hpm(hba);
8563         if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8564                 ufshcd_set_link_active(hba);
8565         else if (ufshcd_is_link_off(hba))
8566                 ufshcd_host_reset_and_restore(hba);
8567 set_dev_active:
8568         if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8569                 ufshcd_disable_auto_bkops(hba);
8570 enable_gating:
8571         if (hba->clk_scaling.is_allowed)
8572                 ufshcd_resume_clkscaling(hba);
8573         hba->clk_gating.is_suspended = false;
8574         hba->dev_info.b_rpm_dev_flush_capable = false;
8575         ufshcd_release(hba);
8576 out:
8577         if (hba->dev_info.b_rpm_dev_flush_capable) {
8578                 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8579                         msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8580         }
8581
8582         hba->pm_op_in_progress = 0;
8583
8584         if (ret)
8585                 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
8586         return ret;
8587 }
8588
8589 /**
8590  * ufshcd_resume - helper function for resume operations
8591  * @hba: per adapter instance
8592  * @pm_op: runtime PM or system PM
8593  *
8594  * This function basically brings the UFS device, UniPro link and controller
8595  * to active state.
8596  *
8597  * Returns 0 for success and non-zero for failure
8598  */
8599 static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8600 {
8601         int ret;
8602         enum uic_link_state old_link_state;
8603
8604         hba->pm_op_in_progress = 1;
8605         old_link_state = hba->uic_link_state;
8606
8607         ufshcd_hba_vreg_set_hpm(hba);
8608         /* Make sure clocks are enabled before accessing controller */
8609         ret = ufshcd_setup_clocks(hba, true);
8610         if (ret)
8611                 goto out;
8612
8613         /* enable the host irq as host controller would be active soon */
8614         ufshcd_enable_irq(hba);
8615
8616         ret = ufshcd_vreg_set_hpm(hba);
8617         if (ret)
8618                 goto disable_irq_and_vops_clks;
8619
8620         /*
8621          * Call vendor specific resume callback. As these callbacks may access
8622          * vendor specific host controller register space call them when the
8623          * host clocks are ON.
8624          */
8625         ret = ufshcd_vops_resume(hba, pm_op);
8626         if (ret)
8627                 goto disable_vreg;
8628
8629         if (ufshcd_is_link_hibern8(hba)) {
8630                 ret = ufshcd_uic_hibern8_exit(hba);
8631                 if (!ret) {
8632                         ufshcd_set_link_active(hba);
8633                 } else {
8634                         dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
8635                                         __func__, ret);
8636                         goto vendor_suspend;
8637                 }
8638         } else if (ufshcd_is_link_off(hba)) {
8639                 /*
8640                  * A full initialization of the host and the device is
8641                  * required since the link was put to off during suspend.
8642                  */
8643                 ret = ufshcd_reset_and_restore(hba);
8644                 /*
8645                  * ufshcd_reset_and_restore() should have already
8646                  * set the link state as active
8647                  */
8648                 if (ret || !ufshcd_is_link_active(hba))
8649                         goto vendor_suspend;
8650         }
8651
8652         if (!ufshcd_is_ufs_dev_active(hba)) {
8653                 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8654                 if (ret)
8655                         goto set_old_link_state;
8656         }
8657
8658         if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8659                 ufshcd_enable_auto_bkops(hba);
8660         else
8661                 /*
8662                  * If BKOPs operations are urgently needed at this moment then
8663                  * keep auto-bkops enabled or else disable it.
8664                  */
8665                 ufshcd_urgent_bkops(hba);
8666
8667         hba->clk_gating.is_suspended = false;
8668
8669         if (hba->clk_scaling.is_allowed)
8670                 ufshcd_resume_clkscaling(hba);
8671
8672         /* Enable Auto-Hibernate if configured */
8673         ufshcd_auto_hibern8_enable(hba);
8674
8675         if (hba->dev_info.b_rpm_dev_flush_capable) {
8676                 hba->dev_info.b_rpm_dev_flush_capable = false;
8677                 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
8678         }
8679
8680         /* Schedule clock gating in case of no access to UFS device yet */
8681         ufshcd_release(hba);
8682
8683         goto out;
8684
8685 set_old_link_state:
8686         ufshcd_link_state_transition(hba, old_link_state, 0);
8687 vendor_suspend:
8688         ufshcd_vops_suspend(hba, pm_op);
8689 disable_vreg:
8690         ufshcd_vreg_set_lpm(hba);
8691 disable_irq_and_vops_clks:
8692         ufshcd_disable_irq(hba);
8693         if (hba->clk_scaling.is_allowed)
8694                 ufshcd_suspend_clkscaling(hba);
8695         ufshcd_setup_clocks(hba, false);
8696         if (ufshcd_is_clkgating_allowed(hba)) {
8697                 hba->clk_gating.state = CLKS_OFF;
8698                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8699                                         hba->clk_gating.state);
8700         }
8701 out:
8702         hba->pm_op_in_progress = 0;
8703         if (ret)
8704                 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
8705         return ret;
8706 }
8707
8708 /**
8709  * ufshcd_system_suspend - system suspend routine
8710  * @hba: per adapter instance
8711  *
8712  * Check the description of ufshcd_suspend() function for more details.
8713  *
8714  * Returns 0 for success and non-zero for failure
8715  */
8716 int ufshcd_system_suspend(struct ufs_hba *hba)
8717 {
8718         int ret = 0;
8719         ktime_t start = ktime_get();
8720
8721         if (!hba || !hba->is_powered)
8722                 return 0;
8723
8724         if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8725              hba->curr_dev_pwr_mode) &&
8726             (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8727              hba->uic_link_state))
8728                 goto out;
8729
8730         if (pm_runtime_suspended(hba->dev)) {
8731                 /*
8732                  * UFS device and/or UFS link low power states during runtime
8733                  * suspend seems to be different than what is expected during
8734                  * system suspend. Hence runtime resume the devic & link and
8735                  * let the system suspend low power states to take effect.
8736                  * TODO: If resume takes longer time, we might have optimize
8737                  * it in future by not resuming everything if possible.
8738                  */
8739                 ret = ufshcd_runtime_resume(hba);
8740                 if (ret)
8741                         goto out;
8742         }
8743
8744         ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8745 out:
8746         trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8747                 ktime_to_us(ktime_sub(ktime_get(), start)),
8748                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8749         if (!ret)
8750                 hba->is_sys_suspended = true;
8751         return ret;
8752 }
8753 EXPORT_SYMBOL(ufshcd_system_suspend);
8754
8755 /**
8756  * ufshcd_system_resume - system resume routine
8757  * @hba: per adapter instance
8758  *
8759  * Returns 0 for success and non-zero for failure
8760  */
8761
8762 int ufshcd_system_resume(struct ufs_hba *hba)
8763 {
8764         int ret = 0;
8765         ktime_t start = ktime_get();
8766
8767         if (!hba)
8768                 return -EINVAL;
8769
8770         if (!hba->is_powered || pm_runtime_suspended(hba->dev))
8771                 /*
8772                  * Let the runtime resume take care of resuming
8773                  * if runtime suspended.
8774                  */
8775                 goto out;
8776         else
8777                 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8778 out:
8779         trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8780                 ktime_to_us(ktime_sub(ktime_get(), start)),
8781                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8782         if (!ret)
8783                 hba->is_sys_suspended = false;
8784         return ret;
8785 }
8786 EXPORT_SYMBOL(ufshcd_system_resume);
8787
8788 /**
8789  * ufshcd_runtime_suspend - runtime suspend routine
8790  * @hba: per adapter instance
8791  *
8792  * Check the description of ufshcd_suspend() function for more details.
8793  *
8794  * Returns 0 for success and non-zero for failure
8795  */
8796 int ufshcd_runtime_suspend(struct ufs_hba *hba)
8797 {
8798         int ret = 0;
8799         ktime_t start = ktime_get();
8800
8801         if (!hba)
8802                 return -EINVAL;
8803
8804         if (!hba->is_powered)
8805                 goto out;
8806         else
8807                 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8808 out:
8809         trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8810                 ktime_to_us(ktime_sub(ktime_get(), start)),
8811                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8812         return ret;
8813 }
8814 EXPORT_SYMBOL(ufshcd_runtime_suspend);
8815
8816 /**
8817  * ufshcd_runtime_resume - runtime resume routine
8818  * @hba: per adapter instance
8819  *
8820  * This function basically brings the UFS device, UniPro link and controller
8821  * to active state. Following operations are done in this function:
8822  *
8823  * 1. Turn on all the controller related clocks
8824  * 2. Bring the UniPro link out of Hibernate state
8825  * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8826  *    to active state.
8827  * 4. If auto-bkops is enabled on the device, disable it.
8828  *
8829  * So following would be the possible power state after this function return
8830  * successfully:
8831  *      S1: UFS device in Active state with VCC rail ON
8832  *          UniPro link in Active state
8833  *          All the UFS/UniPro controller clocks are ON
8834  *
8835  * Returns 0 for success and non-zero for failure
8836  */
8837 int ufshcd_runtime_resume(struct ufs_hba *hba)
8838 {
8839         int ret = 0;
8840         ktime_t start = ktime_get();
8841
8842         if (!hba)
8843                 return -EINVAL;
8844
8845         if (!hba->is_powered)
8846                 goto out;
8847         else
8848                 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8849 out:
8850         trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8851                 ktime_to_us(ktime_sub(ktime_get(), start)),
8852                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8853         return ret;
8854 }
8855 EXPORT_SYMBOL(ufshcd_runtime_resume);
8856
8857 int ufshcd_runtime_idle(struct ufs_hba *hba)
8858 {
8859         return 0;
8860 }
8861 EXPORT_SYMBOL(ufshcd_runtime_idle);
8862
8863 /**
8864  * ufshcd_shutdown - shutdown routine
8865  * @hba: per adapter instance
8866  *
8867  * This function would power off both UFS device and UFS link.
8868  *
8869  * Returns 0 always to allow force shutdown even in case of errors.
8870  */
8871 int ufshcd_shutdown(struct ufs_hba *hba)
8872 {
8873         int ret = 0;
8874
8875         if (!hba->is_powered)
8876                 goto out;
8877
8878         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8879                 goto out;
8880
8881         if (pm_runtime_suspended(hba->dev)) {
8882                 ret = ufshcd_runtime_resume(hba);
8883                 if (ret)
8884                         goto out;
8885         }
8886
8887         ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8888 out:
8889         if (ret)
8890                 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8891         /* allow force shutdown even in case of errors */
8892         return 0;
8893 }
8894 EXPORT_SYMBOL(ufshcd_shutdown);
8895
8896 /**
8897  * ufshcd_remove - de-allocate SCSI host and host memory space
8898  *              data structure memory
8899  * @hba: per adapter instance
8900  */
8901 void ufshcd_remove(struct ufs_hba *hba)
8902 {
8903         ufs_bsg_remove(hba);
8904         ufs_sysfs_remove_nodes(hba->dev);
8905         blk_cleanup_queue(hba->tmf_queue);
8906         blk_mq_free_tag_set(&hba->tmf_tag_set);
8907         blk_cleanup_queue(hba->cmd_queue);
8908         scsi_remove_host(hba->host);
8909         /* disable interrupts */
8910         ufshcd_disable_intr(hba, hba->intr_mask);
8911         ufshcd_hba_stop(hba);
8912
8913         ufshcd_exit_clk_scaling(hba);
8914         ufshcd_exit_clk_gating(hba);
8915         if (ufshcd_is_clkscaling_supported(hba))
8916                 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
8917         ufshcd_hba_exit(hba);
8918 }
8919 EXPORT_SYMBOL_GPL(ufshcd_remove);
8920
8921 /**
8922  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8923  * @hba: pointer to Host Bus Adapter (HBA)
8924  */
8925 void ufshcd_dealloc_host(struct ufs_hba *hba)
8926 {
8927         ufshcd_crypto_destroy_keyslot_manager(hba);
8928         scsi_host_put(hba->host);
8929 }
8930 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8931
8932 /**
8933  * ufshcd_set_dma_mask - Set dma mask based on the controller
8934  *                       addressing capability
8935  * @hba: per adapter instance
8936  *
8937  * Returns 0 for success, non-zero for failure
8938  */
8939 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8940 {
8941         if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8942                 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8943                         return 0;
8944         }
8945         return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8946 }
8947
8948 /**
8949  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
8950  * @dev: pointer to device handle
8951  * @hba_handle: driver private handle
8952  * Returns 0 on success, non-zero value on failure
8953  */
8954 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
8955 {
8956         struct Scsi_Host *host;
8957         struct ufs_hba *hba;
8958         int err = 0;
8959
8960         if (!dev) {
8961                 dev_err(dev,
8962                 "Invalid memory reference for dev is NULL\n");
8963                 err = -ENODEV;
8964                 goto out_error;
8965         }
8966
8967         host = scsi_host_alloc(&ufshcd_driver_template,
8968                                 sizeof(struct ufs_hba));
8969         if (!host) {
8970                 dev_err(dev, "scsi_host_alloc failed\n");
8971                 err = -ENOMEM;
8972                 goto out_error;
8973         }
8974         hba = shost_priv(host);
8975         hba->host = host;
8976         hba->dev = dev;
8977         *hba_handle = hba;
8978         hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
8979
8980         INIT_LIST_HEAD(&hba->clk_list_head);
8981
8982 out_error:
8983         return err;
8984 }
8985 EXPORT_SYMBOL(ufshcd_alloc_host);
8986
8987 /* This function exists because blk_mq_alloc_tag_set() requires this. */
8988 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
8989                                      const struct blk_mq_queue_data *qd)
8990 {
8991         WARN_ON_ONCE(true);
8992         return BLK_STS_NOTSUPP;
8993 }
8994
8995 static const struct blk_mq_ops ufshcd_tmf_ops = {
8996         .queue_rq = ufshcd_queue_tmf,
8997 };
8998
8999 /**
9000  * ufshcd_init - Driver initialization routine
9001  * @hba: per-adapter instance
9002  * @mmio_base: base register address
9003  * @irq: Interrupt line of device
9004  * Returns 0 on success, non-zero value on failure
9005  */
9006 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9007 {
9008         int err;
9009         struct Scsi_Host *host = hba->host;
9010         struct device *dev = hba->dev;
9011         char eh_wq_name[sizeof("ufs_eh_wq_00")];
9012
9013         if (!mmio_base) {
9014                 dev_err(hba->dev,
9015                 "Invalid memory reference for mmio_base is NULL\n");
9016                 err = -ENODEV;
9017                 goto out_error;
9018         }
9019
9020         hba->mmio_base = mmio_base;
9021         hba->irq = irq;
9022         hba->vps = &ufs_hba_vps;
9023
9024         err = ufshcd_hba_init(hba);
9025         if (err)
9026                 goto out_error;
9027
9028         /* Read capabilities registers */
9029         err = ufshcd_hba_capabilities(hba);
9030         if (err)
9031                 goto out_disable;
9032
9033         /* Get UFS version supported by the controller */
9034         hba->ufs_version = ufshcd_get_ufs_version(hba);
9035
9036         if ((hba->ufs_version != UFSHCI_VERSION_10) &&
9037             (hba->ufs_version != UFSHCI_VERSION_11) &&
9038             (hba->ufs_version != UFSHCI_VERSION_20) &&
9039             (hba->ufs_version != UFSHCI_VERSION_21))
9040                 dev_err(hba->dev, "invalid UFS version 0x%x\n",
9041                         hba->ufs_version);
9042
9043         /* Get Interrupt bit mask per version */
9044         hba->intr_mask = ufshcd_get_intr_mask(hba);
9045
9046         err = ufshcd_set_dma_mask(hba);
9047         if (err) {
9048                 dev_err(hba->dev, "set dma mask failed\n");
9049                 goto out_disable;
9050         }
9051
9052         /* Allocate memory for host memory space */
9053         err = ufshcd_memory_alloc(hba);
9054         if (err) {
9055                 dev_err(hba->dev, "Memory allocation failed\n");
9056                 goto out_disable;
9057         }
9058
9059         /* Configure LRB */
9060         ufshcd_host_memory_configure(hba);
9061
9062         host->can_queue = hba->nutrs;
9063         host->cmd_per_lun = hba->nutrs;
9064         host->max_id = UFSHCD_MAX_ID;
9065         host->max_lun = UFS_MAX_LUNS;
9066         host->max_channel = UFSHCD_MAX_CHANNEL;
9067         host->unique_id = host->host_no;
9068         host->max_cmd_len = UFS_CDB_SIZE;
9069
9070         hba->max_pwr_info.is_valid = false;
9071
9072         /* Initialize work queues */
9073         snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9074                  hba->host->host_no);
9075         hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9076         if (!hba->eh_wq) {
9077                 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9078                                 __func__);
9079                 err = -ENOMEM;
9080                 goto out_disable;
9081         }
9082         INIT_WORK(&hba->eh_work, ufshcd_err_handler);
9083         INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9084
9085         /* Initialize UIC command mutex */
9086         mutex_init(&hba->uic_cmd_mutex);
9087
9088         /* Initialize mutex for device management commands */
9089         mutex_init(&hba->dev_cmd.lock);
9090
9091         init_rwsem(&hba->clk_scaling_lock);
9092
9093         ufshcd_init_clk_gating(hba);
9094
9095         ufshcd_init_clk_scaling(hba);
9096
9097         /*
9098          * In order to avoid any spurious interrupt immediately after
9099          * registering UFS controller interrupt handler, clear any pending UFS
9100          * interrupt status and disable all the UFS interrupts.
9101          */
9102         ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9103                       REG_INTERRUPT_STATUS);
9104         ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9105         /*
9106          * Make sure that UFS interrupts are disabled and any pending interrupt
9107          * status is cleared before registering UFS interrupt handler.
9108          */
9109         mb();
9110
9111         /* IRQ registration */
9112         err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9113         if (err) {
9114                 dev_err(hba->dev, "request irq failed\n");
9115                 goto exit_gating;
9116         } else {
9117                 hba->is_irq_enabled = true;
9118         }
9119
9120         err = scsi_add_host(host, hba->dev);
9121         if (err) {
9122                 dev_err(hba->dev, "scsi_add_host failed\n");
9123                 goto exit_gating;
9124         }
9125
9126         hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9127         if (IS_ERR(hba->cmd_queue)) {
9128                 err = PTR_ERR(hba->cmd_queue);
9129                 goto out_remove_scsi_host;
9130         }
9131
9132         hba->tmf_tag_set = (struct blk_mq_tag_set) {
9133                 .nr_hw_queues   = 1,
9134                 .queue_depth    = hba->nutmrs,
9135                 .ops            = &ufshcd_tmf_ops,
9136                 .flags          = BLK_MQ_F_NO_SCHED,
9137         };
9138         err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9139         if (err < 0)
9140                 goto free_cmd_queue;
9141         hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9142         if (IS_ERR(hba->tmf_queue)) {
9143                 err = PTR_ERR(hba->tmf_queue);
9144                 goto free_tmf_tag_set;
9145         }
9146
9147         /* Reset the attached device */
9148         ufshcd_vops_device_reset(hba);
9149
9150         ufshcd_init_crypto(hba);
9151
9152         /* Host controller enable */
9153         err = ufshcd_hba_enable(hba);
9154         if (err) {
9155                 dev_err(hba->dev, "Host controller enable failed\n");
9156                 ufshcd_print_host_regs(hba);
9157                 ufshcd_print_host_state(hba);
9158                 goto free_tmf_queue;
9159         }
9160
9161         /*
9162          * Set the default power management level for runtime and system PM.
9163          * Default power saving mode is to keep UFS link in Hibern8 state
9164          * and UFS device in sleep state.
9165          */
9166         hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9167                                                 UFS_SLEEP_PWR_MODE,
9168                                                 UIC_LINK_HIBERN8_STATE);
9169         hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9170                                                 UFS_SLEEP_PWR_MODE,
9171                                                 UIC_LINK_HIBERN8_STATE);
9172
9173         INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9174                           ufshcd_rpm_dev_flush_recheck_work);
9175
9176         /* Set the default auto-hiberate idle timer value to 150 ms */
9177         if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9178                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9179                             FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9180         }
9181
9182         /* Hold auto suspend until async scan completes */
9183         pm_runtime_get_sync(dev);
9184         atomic_set(&hba->scsi_block_reqs_cnt, 0);
9185         /*
9186          * We are assuming that device wasn't put in sleep/power-down
9187          * state exclusively during the boot stage before kernel.
9188          * This assumption helps avoid doing link startup twice during
9189          * ufshcd_probe_hba().
9190          */
9191         ufshcd_set_ufs_dev_active(hba);
9192
9193         async_schedule(ufshcd_async_scan, hba);
9194         ufs_sysfs_add_nodes(hba->dev);
9195
9196         return 0;
9197
9198 free_tmf_queue:
9199         blk_cleanup_queue(hba->tmf_queue);
9200 free_tmf_tag_set:
9201         blk_mq_free_tag_set(&hba->tmf_tag_set);
9202 free_cmd_queue:
9203         blk_cleanup_queue(hba->cmd_queue);
9204 out_remove_scsi_host:
9205         scsi_remove_host(hba->host);
9206 exit_gating:
9207         ufshcd_exit_clk_scaling(hba);
9208         ufshcd_exit_clk_gating(hba);
9209 out_disable:
9210         hba->is_irq_enabled = false;
9211         ufshcd_hba_exit(hba);
9212 out_error:
9213         return err;
9214 }
9215 EXPORT_SYMBOL_GPL(ufshcd_init);
9216
9217 MODULE_AUTHOR("Santosh Yaragnavi <[email protected]>");
9218 MODULE_AUTHOR("Vinayak Holikatti <[email protected]>");
9219 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9220 MODULE_LICENSE("GPL");
9221 MODULE_VERSION(UFSHCD_DRIVER_VERSION);