drivers/scsi/ufs/ufs-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/acpi.h>
   7 #include <linux/time.h>
   8 #include <linux/of.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/phy/phy.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/reset-controller.h>
  13 #include <linux/devfreq.h>
  14
  15 #include "ufshcd.h"
  16 #include "ufshcd-pltfrm.h"
  17 #include "unipro.h"
  18 #include "ufs-qcom.h"
  19 #include "ufshci.h"
  20 #include "ufs_quirks.h"
  21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  22         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  23
  24 enum {
  25         TSTBUS_UAWM,
  26         TSTBUS_UARM,
  27         TSTBUS_TXUC,
  28         TSTBUS_RXUC,
  29         TSTBUS_DFC,
  30         TSTBUS_TRLUT,
  31         TSTBUS_TMRLUT,
  32         TSTBUS_OCSC,
  33         TSTBUS_UTP_HCI,
  34         TSTBUS_COMBINED,
  35         TSTBUS_WRAPPER,
  36         TSTBUS_UNIPRO,
  37         TSTBUS_MAX,
  38 };
  39
  40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  41
  42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  44                                                        u32 clk_cycles);
  45
  46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  47 {
  48         return container_of(rcd, struct ufs_qcom_host, rcdev);
  49 }
  50
  51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  52                                        const char *prefix, void *priv)
  53 {
  54         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  55 }
  56
  57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  58 {
  59         int err = 0;
  60
  61         err = ufshcd_dme_get(hba,
  62                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  63         if (err)
  64                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  65                                 __func__, err);
  66
  67         return err;
  68 }
  69
  70 static int ufs_qcom_host_clk_get(struct device *dev,
  71                 const char *name, struct clk **clk_out, bool optional)
  72 {
  73         struct clk *clk;
  74         int err = 0;
  75
  76         clk = devm_clk_get(dev, name);
  77         if (!IS_ERR(clk)) {
  78                 *clk_out = clk;
  79                 return 0;
  80         }
  81
  82         err = PTR_ERR(clk);
  83
  84         if (optional && err == -ENOENT) {
  85                 *clk_out = NULL;
  86                 return 0;
  87         }
  88
  89         if (err != -EPROBE_DEFER)
  90                 dev_err(dev, "failed to get %s err %d\n", name, err);
  91
  92         return err;
  93 }
  94
  95 static int ufs_qcom_host_clk_enable(struct device *dev,
  96                 const char *name, struct clk *clk)
  97 {
  98         int err = 0;
  99
 100         err = clk_prepare_enable(clk);
 101         if (err)
 102                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 103
 104         return err;
 105 }
 106
 107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 108 {
 109         if (!host->is_lane_clks_enabled)
 110                 return;
 111
 112         clk_disable_unprepare(host->tx_l1_sync_clk);
 113         clk_disable_unprepare(host->tx_l0_sync_clk);
 114         clk_disable_unprepare(host->rx_l1_sync_clk);
 115         clk_disable_unprepare(host->rx_l0_sync_clk);
 116
 117         host->is_lane_clks_enabled = false;
 118 }
 119
 120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 121 {
 122         int err = 0;
 123         struct device *dev = host->hba->dev;
 124
 125         if (host->is_lane_clks_enabled)
 126                 return 0;
 127
 128         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 129                 host->rx_l0_sync_clk);
 130         if (err)
 131                 goto out;
 132
 133         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 134                 host->tx_l0_sync_clk);
 135         if (err)
 136                 goto disable_rx_l0;
 137
 138         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 139                         host->rx_l1_sync_clk);
 140         if (err)
 141                 goto disable_tx_l0;
 142
 143         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 144                         host->tx_l1_sync_clk);
 145         if (err)
 146                 goto disable_rx_l1;
 147
 148         host->is_lane_clks_enabled = true;
 149         goto out;
 150
 151 disable_rx_l1:
 152         clk_disable_unprepare(host->rx_l1_sync_clk);
 153 disable_tx_l0:
 154         clk_disable_unprepare(host->tx_l0_sync_clk);
 155 disable_rx_l0:
 156         clk_disable_unprepare(host->rx_l0_sync_clk);
 157 out:
 158         return err;
 159 }
 160
 161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 162 {
 163         int err = 0;
 164         struct device *dev = host->hba->dev;
 165
 166         if (has_acpi_companion(dev))
 167                 return 0;
 168
 169         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 170                                         &host->rx_l0_sync_clk, false);
 171         if (err)
 172                 goto out;
 173
 174         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 175                                         &host->tx_l0_sync_clk, false);
 176         if (err)
 177                 goto out;
 178
 179         /* In case of single lane per direction, don't read lane1 clocks */
 180         if (host->hba->lanes_per_direction > 1) {
 181                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 182                         &host->rx_l1_sync_clk, false);
 183                 if (err)
 184                         goto out;
 185
 186                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 187                         &host->tx_l1_sync_clk, true);
 188         }
 189 out:
 190         return err;
 191 }
 192
 193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 194 {
 195         u32 tx_lanes;
 196
 197         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 198 }
 199
 200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 201 {
 202         int err;
 203         u32 tx_fsm_val = 0;
 204         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 205
 206         do {
 207                 err = ufshcd_dme_get(hba,
 208                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 209                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 210                                 &tx_fsm_val);
 211                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 212                         break;
 213
 214                 /* sleep for max. 200us */
 215                 usleep_range(100, 200);
 216         } while (time_before(jiffies, timeout));
 217
 218         /*
 219          * we might have scheduled out for long during polling so
 220          * check the state again.
 221          */
 222         if (time_after(jiffies, timeout))
 223                 err = ufshcd_dme_get(hba,
 224                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 225                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 226                                 &tx_fsm_val);
 227
 228         if (err) {
 229                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 230                                 __func__, err);
 231         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 232                 err = tx_fsm_val;
 233                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 234                                 __func__, err);
 235         }
 236
 237         return err;
 238 }
 239
 240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 241 {
 242         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 243                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 244                    REG_UFS_CFG1);
 245         /* make sure above configuration is applied before we return */
 246         mb();
 247 }
 248
 249 /*
 250  * ufs_qcom_host_reset - reset host controller and PHY
 251  */
 252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
 253 {
 254         int ret = 0;
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256
 257         if (!host->core_reset) {
 258                 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
 259                 goto out;
 260         }
 261
 262         ret = reset_control_assert(host->core_reset);
 263         if (ret) {
 264                 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
 265                                  __func__, ret);
 266                 goto out;
 267         }
 268
 269         /*
 270          * The hardware requirement for delay between assert/deassert
 271          * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
 272          * ~125us (4/32768). To be on the safe side add 200us delay.
 273          */
 274         usleep_range(200, 210);
 275
 276         ret = reset_control_deassert(host->core_reset);
 277         if (ret)
 278                 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
 279                                  __func__, ret);
 280
 281         usleep_range(1000, 1100);
 282
 283 out:
 284         return ret;
 285 }
 286
 287 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 288 {
 289         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 290         struct phy *phy = host->generic_phy;
 291         int ret = 0;
 292         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 293                                                         ? true : false;
 294
 295         /* Reset UFS Host Controller and PHY */
 296         ret = ufs_qcom_host_reset(hba);
 297         if (ret)
 298                 dev_warn(hba->dev, "%s: host reset returned %d\n",
 299                                   __func__, ret);
 300
 301         if (is_rate_B)
 302                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 303
 304         /* phy initialization - calibrate the phy */
 305         ret = phy_init(phy);
 306         if (ret) {
 307                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 308                         __func__, ret);
 309                 goto out;
 310         }
 311
 312         /* power on phy - start serdes and phy's power and clocks */
 313         ret = phy_power_on(phy);
 314         if (ret) {
 315                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 316                         __func__, ret);
 317                 goto out_disable_phy;
 318         }
 319
 320         ufs_qcom_select_unipro_mode(host);
 321
 322         return 0;
 323
 324 out_disable_phy:
 325         phy_exit(phy);
 326 out:
 327         return ret;
 328 }
 329
 330 /*
 331  * The UTP controller has a number of internal clock gating cells (CGCs).
 332  * Internal hardware sub-modules within the UTP controller control the CGCs.
 333  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 334  * in a specific operation, UTP controller CGCs are by default disabled and
 335  * this function enables them (after every UFS link startup) to save some power
 336  * leakage.
 337  */
 338 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 339 {
 340         ufshcd_writel(hba,
 341                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 342                 REG_UFS_CFG2);
 343
 344         /* Ensure that HW clock gating is enabled before next operations */
 345         mb();
 346 }
 347
 348 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 349                                       enum ufs_notify_change_status status)
 350 {
 351         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 352         int err = 0;
 353
 354         switch (status) {
 355         case PRE_CHANGE:
 356                 ufs_qcom_power_up_sequence(hba);
 357                 /*
 358                  * The PHY PLL output is the source of tx/rx lane symbol
 359                  * clocks, hence, enable the lane clocks only after PHY
 360                  * is initialized.
 361                  */
 362                 err = ufs_qcom_enable_lane_clks(host);
 363                 break;
 364         case POST_CHANGE:
 365                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 366                 err = ufs_qcom_check_hibern8(hba);
 367                 ufs_qcom_enable_hw_clk_gating(hba);
 368                 ufs_qcom_ice_enable(host);
 369                 break;
 370         default:
 371                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 372                 err = -EINVAL;
 373                 break;
 374         }
 375         return err;
 376 }
 377
 378 /*
 379  * Returns zero for success and non-zero in case of a failure
 380  */
 381 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 382                                u32 hs, u32 rate, bool update_link_startup_timer)
 383 {
 384         int ret = 0;
 385         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 386         struct ufs_clk_info *clki;
 387         u32 core_clk_period_in_ns;
 388         u32 tx_clk_cycles_per_us = 0;
 389         unsigned long core_clk_rate = 0;
 390         u32 core_clk_cycles_per_us = 0;
 391
 392         static u32 pwm_fr_table[][2] = {
 393                 {UFS_PWM_G1, 0x1},
 394                 {UFS_PWM_G2, 0x1},
 395                 {UFS_PWM_G3, 0x1},
 396                 {UFS_PWM_G4, 0x1},
 397         };
 398
 399         static u32 hs_fr_table_rA[][2] = {
 400                 {UFS_HS_G1, 0x1F},
 401                 {UFS_HS_G2, 0x3e},
 402                 {UFS_HS_G3, 0x7D},
 403         };
 404
 405         static u32 hs_fr_table_rB[][2] = {
 406                 {UFS_HS_G1, 0x24},
 407                 {UFS_HS_G2, 0x49},
 408                 {UFS_HS_G3, 0x92},
 409         };
 410
 411         /*
 412          * The Qunipro controller does not use following registers:
 413          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 414          * UFS_REG_PA_LINK_STARTUP_TIMER
 415          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 416          * Aggregation logic.
 417         */
 418         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 419                 goto out;
 420
 421         if (gear == 0) {
 422                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 423                 goto out_error;
 424         }
 425
 426         list_for_each_entry(clki, &hba->clk_list_head, list) {
 427                 if (!strcmp(clki->name, "core_clk"))
 428                         core_clk_rate = clk_get_rate(clki->clk);
 429         }
 430
 431         /* If frequency is smaller than 1MHz, set to 1MHz */
 432         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 433                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 434
 435         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 436         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 437                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 438                 /*
 439                  * make sure above write gets applied before we return from
 440                  * this function.
 441                  */
 442                 mb();
 443         }
 444
 445         if (ufs_qcom_cap_qunipro(host))
 446                 goto out;
 447
 448         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 449         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 450         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 451
 452         switch (hs) {
 453         case FASTAUTO_MODE:
 454         case FAST_MODE:
 455                 if (rate == PA_HS_MODE_A) {
 456                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 457                                 dev_err(hba->dev,
 458                                         "%s: index %d exceeds table size %zu\n",
 459                                         __func__, gear,
 460                                         ARRAY_SIZE(hs_fr_table_rA));
 461                                 goto out_error;
 462                         }
 463                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 464                 } else if (rate == PA_HS_MODE_B) {
 465                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 466                                 dev_err(hba->dev,
 467                                         "%s: index %d exceeds table size %zu\n",
 468                                         __func__, gear,
 469                                         ARRAY_SIZE(hs_fr_table_rB));
 470                                 goto out_error;
 471                         }
 472                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 473                 } else {
 474                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 475                                 __func__, rate);
 476                         goto out_error;
 477                 }
 478                 break;
 479         case SLOWAUTO_MODE:
 480         case SLOW_MODE:
 481                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 482                         dev_err(hba->dev,
 483                                         "%s: index %d exceeds table size %zu\n",
 484                                         __func__, gear,
 485                                         ARRAY_SIZE(pwm_fr_table));
 486                         goto out_error;
 487                 }
 488                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 489                 break;
 490         case UNCHANGED:
 491         default:
 492                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 493                 goto out_error;
 494         }
 495
 496         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 497             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 498                 /* this register 2 fields shall be written at once */
 499                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 500                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 501                 /*
 502                  * make sure above write gets applied before we return from
 503                  * this function.
 504                  */
 505                 mb();
 506         }
 507
 508         if (update_link_startup_timer) {
 509                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 510                               REG_UFS_PA_LINK_STARTUP_TIMER);
 511                 /*
 512                  * make sure that this configuration is applied before
 513                  * we return
 514                  */
 515                 mb();
 516         }
 517         goto out;
 518
 519 out_error:
 520         ret = -EINVAL;
 521 out:
 522         return ret;
 523 }
 524
 525 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 526                                         enum ufs_notify_change_status status)
 527 {
 528         int err = 0;
 529         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 530
 531         switch (status) {
 532         case PRE_CHANGE:
 533                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 534                                         0, true)) {
 535                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 536                                 __func__);
 537                         err = -EINVAL;
 538                         goto out;
 539                 }
 540
 541                 if (ufs_qcom_cap_qunipro(host))
 542                         /*
 543                          * set unipro core clock cycles to 150 & clear clock
 544                          * divider
 545                          */
 546                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 547                                                                           150);
 548
 549                 /*
 550                  * Some UFS devices (and may be host) have issues if LCC is
 551                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 552                  * before link startup which will make sure that both host
 553                  * and device TX LCC are disabled once link startup is
 554                  * completed.
 555                  */
 556                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 557                         err = ufshcd_disable_host_tx_lcc(hba);
 558
 559                 break;
 560         case POST_CHANGE:
 561                 ufs_qcom_link_startup_post_change(hba);
 562                 break;
 563         default:
 564                 break;
 565         }
 566
 567 out:
 568         return err;
 569 }
 570
 571 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 572 {
 573         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 574         struct phy *phy = host->generic_phy;
 575
 576         if (ufs_qcom_is_link_off(hba)) {
 577                 /*
 578                  * Disable the tx/rx lane symbol clocks before PHY is
 579                  * powered down as the PLL source should be disabled
 580                  * after downstream clocks are disabled.
 581                  */
 582                 ufs_qcom_disable_lane_clks(host);
 583                 phy_power_off(phy);
 584
 585         } else if (!ufs_qcom_is_link_active(hba)) {
 586                 ufs_qcom_disable_lane_clks(host);
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 593 {
 594         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 595         struct phy *phy = host->generic_phy;
 596         int err;
 597
 598         if (ufs_qcom_is_link_off(hba)) {
 599                 err = phy_power_on(phy);
 600                 if (err) {
 601                         dev_err(hba->dev, "%s: failed PHY power on: %d\n",
 602                                 __func__, err);
 603                         return err;
 604                 }
 605
 606                 err = ufs_qcom_enable_lane_clks(host);
 607                 if (err)
 608                         return err;
 609
 610         } else if (!ufs_qcom_is_link_active(hba)) {
 611                 err = ufs_qcom_enable_lane_clks(host);
 612                 if (err)
 613                         return err;
 614         }
 615
 616         err = ufs_qcom_ice_resume(host);
 617         if (err)
 618                 return err;
 619
 620         hba->is_sys_suspended = false;
 621         return 0;
 622 }
 623
 624 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 625 {
 626         if (host->dev_ref_clk_ctrl_mmio &&
 627             (enable ^ host->is_dev_ref_clk_enabled)) {
 628                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 629
 630                 if (enable)
 631                         temp |= host->dev_ref_clk_en_mask;
 632                 else
 633                         temp &= ~host->dev_ref_clk_en_mask;
 634
 635                 /*
 636                  * If we are here to disable this clock it might be immediately
 637                  * after entering into hibern8 in which case we need to make
 638                  * sure that device ref_clk is active for specific time after
 639                  * hibern8 enter.
 640                  */
 641                 if (!enable) {
 642                         unsigned long gating_wait;
 643
 644                         gating_wait = host->hba->dev_info.clk_gating_wait_us;
 645                         if (!gating_wait) {
 646                                 udelay(1);
 647                         } else {
 648                                 /*
 649                                  * bRefClkGatingWaitTime defines the minimum
 650                                  * time for which the reference clock is
 651                                  * required by device during transition from
 652                                  * HS-MODE to LS-MODE or HIBERN8 state. Give it
 653                                  * more delay to be on the safe side.
 654                                  */
 655                                 gating_wait += 10;
 656                                 usleep_range(gating_wait, gating_wait + 10);
 657                         }
 658                 }
 659
 660                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 661
 662                 /* ensure that ref_clk is enabled/disabled before we return */
 663                 wmb();
 664
 665                 /*
 666                  * If we call hibern8 exit after this, we need to make sure that
 667                  * device ref_clk is stable for at least 1us before the hibern8
 668                  * exit command.
 669                  */
 670                 if (enable)
 671                         udelay(1);
 672
 673                 host->is_dev_ref_clk_enabled = enable;
 674         }
 675 }
 676
 677 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 678                                 enum ufs_notify_change_status status,
 679                                 struct ufs_pa_layer_attr *dev_max_params,
 680                                 struct ufs_pa_layer_attr *dev_req_params)
 681 {
 682         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 683         struct ufs_dev_params ufs_qcom_cap;
 684         int ret = 0;
 685
 686         if (!dev_req_params) {
 687                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 688                 ret = -EINVAL;
 689                 goto out;
 690         }
 691
 692         switch (status) {
 693         case PRE_CHANGE:
 694                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 695                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 696                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 697                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 698                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 699                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 700                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 701                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 702                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 703                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 704                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 705                 ufs_qcom_cap.desired_working_mode =
 706                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 707
 708                 if (host->hw_ver.major == 0x1) {
 709                         /*
 710                          * HS-G3 operations may not reliably work on legacy QCOM
 711                          * UFS host controller hardware even though capability
 712                          * exchange during link startup phase may end up
 713                          * negotiating maximum supported gear as G3.
 714                          * Hence downgrade the maximum supported gear to HS-G2.
 715                          */
 716                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 717                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 718                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 719                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 720                 }
 721
 722                 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
 723                                                dev_max_params,
 724                                                dev_req_params);
 725                 if (ret) {
 726                         pr_err("%s: failed to determine capabilities\n",
 727                                         __func__);
 728                         goto out;
 729                 }
 730
 731                 /* enable the device ref clock before changing to HS mode */
 732                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 733                         ufshcd_is_hs_mode(dev_req_params))
 734                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 735
 736                 if (host->hw_ver.major >= 0x4) {
 737                         if (dev_req_params->gear_tx == UFS_HS_G4) {
 738                                 /* INITIAL ADAPT */
 739                                 ufshcd_dme_set(hba,
 740                                                UIC_ARG_MIB(PA_TXHSADAPTTYPE),
 741                                                PA_INITIAL_ADAPT);
 742                         } else {
 743                                 /* NO ADAPT */
 744                                 ufshcd_dme_set(hba,
 745                                                UIC_ARG_MIB(PA_TXHSADAPTTYPE),
 746                                                PA_NO_ADAPT);
 747                         }
 748                 }
 749                 break;
 750         case POST_CHANGE:
 751                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 752                                         dev_req_params->pwr_rx,
 753                                         dev_req_params->hs_rate, false)) {
 754                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 755                                 __func__);
 756                         /*
 757                          * we return error code at the end of the routine,
 758                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 759                          * and bus voting as usual
 760                          */
 761                         ret = -EINVAL;
 762                 }
 763
 764                 /* cache the power mode parameters to use internally */
 765                 memcpy(&host->dev_req_params,
 766                                 dev_req_params, sizeof(*dev_req_params));
 767
 768                 /* disable the device ref clock if entered PWM mode */
 769                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 770                         !ufshcd_is_hs_mode(dev_req_params))
 771                         ufs_qcom_dev_ref_clk_ctrl(host, false);
 772                 break;
 773         default:
 774                 ret = -EINVAL;
 775                 break;
 776         }
 777 out:
 778         return ret;
 779 }
 780
 781 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
 782 {
 783         int err;
 784         u32 pa_vs_config_reg1;
 785
 786         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 787                              &pa_vs_config_reg1);
 788         if (err)
 789                 goto out;
 790
 791         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
 792         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 793                             (pa_vs_config_reg1 | (1 << 12)));
 794
 795 out:
 796         return err;
 797 }
 798
 799 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
 800 {
 801         int err = 0;
 802
 803         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
 804                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
 805
 806         if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
 807                 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
 808
 809         return err;
 810 }
 811
 812 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
 813 {
 814         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 815
 816         if (host->hw_ver.major == 0x1)
 817                 return UFSHCI_VERSION_11;
 818         else
 819                 return UFSHCI_VERSION_20;
 820 }
 821
 822 /**
 823  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
 824  * @hba: host controller instance
 825  *
 826  * QCOM UFS host controller might have some non standard behaviours (quirks)
 827  * than what is specified by UFSHCI specification. Advertise all such
 828  * quirks to standard UFS host controller driver so standard takes them into
 829  * account.
 830  */
 831 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 832 {
 833         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 834
 835         if (host->hw_ver.major == 0x01) {
 836                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 837                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
 838                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
 839
 840                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
 841                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
 842
 843                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
 844         }
 845
 846         if (host->hw_ver.major == 0x2) {
 847                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
 848
 849                 if (!ufs_qcom_cap_qunipro(host))
 850                         /* Legacy UniPro mode still need following quirks */
 851                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 852                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
 853                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
 854         }
 855 }
 856
 857 static void ufs_qcom_set_caps(struct ufs_hba *hba)
 858 {
 859         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 860
 861         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
 862         hba->caps |= UFSHCD_CAP_CLK_SCALING;
 863         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
 864         hba->caps |= UFSHCD_CAP_WB_EN;
 865         hba->caps |= UFSHCD_CAP_CRYPTO;
 866
 867         if (host->hw_ver.major >= 0x2) {
 868                 host->caps = UFS_QCOM_CAP_QUNIPRO |
 869                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
 870         }
 871 }
 872
 873 /**
 874  * ufs_qcom_setup_clocks - enables/disable clocks
 875  * @hba: host controller instance
 876  * @on: If true, enable clocks else disable them.
 877  * @status: PRE_CHANGE or POST_CHANGE notify
 878  *
 879  * Returns 0 on success, non-zero on failure.
 880  */
 881 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 882                                  enum ufs_notify_change_status status)
 883 {
 884         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 885         int err = 0;
 886
 887         /*
 888          * In case ufs_qcom_init() is not yet done, simply ignore.
 889          * This ufs_qcom_setup_clocks() shall be called from
 890          * ufs_qcom_init() after init is done.
 891          */
 892         if (!host)
 893                 return 0;
 894
 895         switch (status) {
 896         case PRE_CHANGE:
 897                 if (!on) {
 898                         if (!ufs_qcom_is_link_active(hba)) {
 899                                 /* disable device ref_clk */
 900                                 ufs_qcom_dev_ref_clk_ctrl(host, false);
 901                         }
 902                 }
 903                 break;
 904         case POST_CHANGE:
 905                 if (on) {
 906                         /* enable the device ref clock for HS mode*/
 907                         if (ufshcd_is_hs_mode(&hba->pwr_info))
 908                                 ufs_qcom_dev_ref_clk_ctrl(host, true);
 909                 }
 910                 break;
 911         }
 912
 913         return err;
 914 }
 915
 916 static int
 917 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
 918 {
 919         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
 920
 921         /* Currently this code only knows about a single reset. */
 922         WARN_ON(id);
 923         ufs_qcom_assert_reset(host->hba);
 924         /* provide 1ms delay to let the reset pulse propagate. */
 925         usleep_range(1000, 1100);
 926         return 0;
 927 }
 928
 929 static int
 930 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
 931 {
 932         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
 933
 934         /* Currently this code only knows about a single reset. */
 935         WARN_ON(id);
 936         ufs_qcom_deassert_reset(host->hba);
 937
 938         /*
 939          * after reset deassertion, phy will need all ref clocks,
 940          * voltage, current to settle down before starting serdes.
 941          */
 942         usleep_range(1000, 1100);
 943         return 0;
 944 }
 945
 946 static const struct reset_control_ops ufs_qcom_reset_ops = {
 947         .assert = ufs_qcom_reset_assert,
 948         .deassert = ufs_qcom_reset_deassert,
 949 };
 950
 951 #define ANDROID_BOOT_DEV_MAX    30
 952 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
 953
 954 #ifndef MODULE
 955 static int __init get_android_boot_dev(char *str)
 956 {
 957         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
 958         return 1;
 959 }
 960 __setup("androidboot.bootdevice=", get_android_boot_dev);
 961 #endif
 962
 963 /**
 964  * ufs_qcom_init - bind phy with controller
 965  * @hba: host controller instance
 966  *
 967  * Binds PHY with controller and powers up PHY enabling clocks
 968  * and regulators.
 969  *
 970  * Returns -EPROBE_DEFER if binding fails, returns negative error
 971  * on phy power up failure and returns zero on success.
 972  */
 973 static int ufs_qcom_init(struct ufs_hba *hba)
 974 {
 975         int err;
 976         struct device *dev = hba->dev;
 977         struct platform_device *pdev = to_platform_device(dev);
 978         struct ufs_qcom_host *host;
 979         struct resource *res;
 980
 981         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
 982                 return -ENODEV;
 983
 984         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 985         if (!host) {
 986                 err = -ENOMEM;
 987                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
 988                 goto out;
 989         }
 990
 991         /* Make a two way bind between the qcom host and the hba */
 992         host->hba = hba;
 993         ufshcd_set_variant(hba, host);
 994
 995         /* Setup the reset control of HCI */
 996         host->core_reset = devm_reset_control_get(hba->dev, "rst");
 997         if (IS_ERR(host->core_reset)) {
 998                 err = PTR_ERR(host->core_reset);
 999                 dev_warn(dev, "Failed to get reset control %d\n", err);
1000                 host->core_reset = NULL;
1001                 err = 0;
1002         }
1003
1004         /* Fire up the reset controller. Failure here is non-fatal. */
1005         host->rcdev.of_node = dev->of_node;
1006         host->rcdev.ops = &ufs_qcom_reset_ops;
1007         host->rcdev.owner = dev->driver->owner;
1008         host->rcdev.nr_resets = 1;
1009         err = devm_reset_controller_register(dev, &host->rcdev);
1010         if (err) {
1011                 dev_warn(dev, "Failed to register reset controller\n");
1012                 err = 0;
1013         }
1014
1015         /*
1016          * voting/devoting device ref_clk source is time consuming hence
1017          * skip devoting it during aggressive clock gating. This clock
1018          * will still be gated off during runtime suspend.
1019          */
1020         host->generic_phy = devm_phy_get(dev, "ufsphy");
1021
1022         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1023                 /*
1024                  * UFS driver might be probed before the phy driver does.
1025                  * In that case we would like to return EPROBE_DEFER code.
1026                  */
1027                 err = -EPROBE_DEFER;
1028                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1029                         __func__, err);
1030                 goto out_variant_clear;
1031         } else if (IS_ERR(host->generic_phy)) {
1032                 if (has_acpi_companion(dev)) {
1033                         host->generic_phy = NULL;
1034                 } else {
1035                         err = PTR_ERR(host->generic_phy);
1036                         dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1037                         goto out_variant_clear;
1038                 }
1039         }
1040
1041         host->device_reset = devm_gpiod_get_optional(dev, "reset",
1042                                                      GPIOD_OUT_HIGH);
1043         if (IS_ERR(host->device_reset)) {
1044                 err = PTR_ERR(host->device_reset);
1045                 if (err != -EPROBE_DEFER)
1046                         dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1047                 goto out_variant_clear;
1048         }
1049
1050         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1051                 &host->hw_ver.minor, &host->hw_ver.step);
1052
1053         /*
1054          * for newer controllers, device reference clock control bit has
1055          * moved inside UFS controller register address space itself.
1056          */
1057         if (host->hw_ver.major >= 0x02) {
1058                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1059                 host->dev_ref_clk_en_mask = BIT(26);
1060         } else {
1061                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1062                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1063                                                    "dev_ref_clk_ctrl_mem");
1064                 if (res) {
1065                         host->dev_ref_clk_ctrl_mmio =
1066                                         devm_ioremap_resource(dev, res);
1067                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1068                                 dev_warn(dev,
1069                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1070                                         __func__,
1071                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1072                                 host->dev_ref_clk_ctrl_mmio = NULL;
1073                         }
1074                         host->dev_ref_clk_en_mask = BIT(5);
1075                 }
1076         }
1077
1078         err = ufs_qcom_init_lane_clks(host);
1079         if (err)
1080                 goto out_variant_clear;
1081
1082         ufs_qcom_set_caps(hba);
1083         ufs_qcom_advertise_quirks(hba);
1084
1085         err = ufs_qcom_ice_init(host);
1086         if (err)
1087                 goto out_variant_clear;
1088
1089         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1090
1091         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1092                 ufs_qcom_hosts[hba->dev->id] = host;
1093
1094         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1095         ufs_qcom_get_default_testbus_cfg(host);
1096         err = ufs_qcom_testbus_config(host);
1097         if (err) {
1098                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1099                                 __func__, err);
1100                 err = 0;
1101         }
1102
1103         goto out;
1104
1105 out_variant_clear:
1106         ufshcd_set_variant(hba, NULL);
1107 out:
1108         return err;
1109 }
1110
1111 static void ufs_qcom_exit(struct ufs_hba *hba)
1112 {
1113         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1114
1115         ufs_qcom_disable_lane_clks(host);
1116         phy_power_off(host->generic_phy);
1117         phy_exit(host->generic_phy);
1118 }
1119
1120 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1121                                                        u32 clk_cycles)
1122 {
1123         int err;
1124         u32 core_clk_ctrl_reg;
1125
1126         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1127                 return -EINVAL;
1128
1129         err = ufshcd_dme_get(hba,
1130                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1131                             &core_clk_ctrl_reg);
1132         if (err)
1133                 goto out;
1134
1135         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1136         core_clk_ctrl_reg |= clk_cycles;
1137
1138         /* Clear CORE_CLK_DIV_EN */
1139         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1140
1141         err = ufshcd_dme_set(hba,
1142                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1143                             core_clk_ctrl_reg);
1144 out:
1145         return err;
1146 }
1147
1148 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1149 {
1150         /* nothing to do as of now */
1151         return 0;
1152 }
1153
1154 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1155 {
1156         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1157
1158         if (!ufs_qcom_cap_qunipro(host))
1159                 return 0;
1160
1161         /* set unipro core clock cycles to 150 and clear clock divider */
1162         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1163 }
1164
1165 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1166 {
1167         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1168         int err;
1169         u32 core_clk_ctrl_reg;
1170
1171         if (!ufs_qcom_cap_qunipro(host))
1172                 return 0;
1173
1174         err = ufshcd_dme_get(hba,
1175                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1176                             &core_clk_ctrl_reg);
1177
1178         /* make sure CORE_CLK_DIV_EN is cleared */
1179         if (!err &&
1180             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1181                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1182                 err = ufshcd_dme_set(hba,
1183                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1184                                     core_clk_ctrl_reg);
1185         }
1186
1187         return err;
1188 }
1189
1190 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1191 {
1192         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1193
1194         if (!ufs_qcom_cap_qunipro(host))
1195                 return 0;
1196
1197         /* set unipro core clock cycles to 75 and clear clock divider */
1198         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1199 }
1200
1201 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1202                 bool scale_up, enum ufs_notify_change_status status)
1203 {
1204         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1205         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1206         int err = 0;
1207
1208         if (status == PRE_CHANGE) {
1209                 if (scale_up)
1210                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1211                 else
1212                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1213         } else {
1214                 if (scale_up)
1215                         err = ufs_qcom_clk_scale_up_post_change(hba);
1216                 else
1217                         err = ufs_qcom_clk_scale_down_post_change(hba);
1218
1219                 if (err || !dev_req_params)
1220                         goto out;
1221
1222                 ufs_qcom_cfg_timers(hba,
1223                                     dev_req_params->gear_rx,
1224                                     dev_req_params->pwr_rx,
1225                                     dev_req_params->hs_rate,
1226                                     false);
1227         }
1228
1229 out:
1230         return err;
1231 }
1232
1233 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1234                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1235                 int offset, int num_regs, const char *str, void *priv))
1236 {
1237         u32 reg;
1238         struct ufs_qcom_host *host;
1239
1240         if (unlikely(!hba)) {
1241                 pr_err("%s: hba is NULL\n", __func__);
1242                 return;
1243         }
1244         if (unlikely(!print_fn)) {
1245                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1246                 return;
1247         }
1248
1249         host = ufshcd_get_variant(hba);
1250         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1251                 return;
1252
1253         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1254         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1255
1256         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1257         reg |= UTP_DBG_RAMS_EN;
1258         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1259
1260         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1261         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1262
1263         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1264         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1265
1266         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1267         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1268
1269         /* clear bit 17 - UTP_DBG_RAMS_EN */
1270         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1271
1272         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1273         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1274
1275         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1276         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1277
1278         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1279         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1280
1281         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1282         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1283
1284         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1285         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1286
1287         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1288         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1289
1290         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1291         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1292 }
1293
1294 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1295 {
1296         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1297                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1298                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1299                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1300         } else {
1301                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1302                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1303         }
1304 }
1305
1306 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1307 {
1308         /* provide a legal default configuration */
1309         host->testbus.select_major = TSTBUS_UNIPRO;
1310         host->testbus.select_minor = 37;
1311 }
1312
1313 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1314 {
1315         if (host->testbus.select_major >= TSTBUS_MAX) {
1316                 dev_err(host->hba->dev,
1317                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1318                         __func__, host->testbus.select_major);
1319                 return false;
1320         }
1321
1322         return true;
1323 }
1324
1325 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1326 {
1327         int reg;
1328         int offset;
1329         u32 mask = TEST_BUS_SUB_SEL_MASK;
1330
1331         if (!host)
1332                 return -EINVAL;
1333
1334         if (!ufs_qcom_testbus_cfg_is_ok(host))
1335                 return -EPERM;
1336
1337         switch (host->testbus.select_major) {
1338         case TSTBUS_UAWM:
1339                 reg = UFS_TEST_BUS_CTRL_0;
1340                 offset = 24;
1341                 break;
1342         case TSTBUS_UARM:
1343                 reg = UFS_TEST_BUS_CTRL_0;
1344                 offset = 16;
1345                 break;
1346         case TSTBUS_TXUC:
1347                 reg = UFS_TEST_BUS_CTRL_0;
1348                 offset = 8;
1349                 break;
1350         case TSTBUS_RXUC:
1351                 reg = UFS_TEST_BUS_CTRL_0;
1352                 offset = 0;
1353                 break;
1354         case TSTBUS_DFC:
1355                 reg = UFS_TEST_BUS_CTRL_1;
1356                 offset = 24;
1357                 break;
1358         case TSTBUS_TRLUT:
1359                 reg = UFS_TEST_BUS_CTRL_1;
1360                 offset = 16;
1361                 break;
1362         case TSTBUS_TMRLUT:
1363                 reg = UFS_TEST_BUS_CTRL_1;
1364                 offset = 8;
1365                 break;
1366         case TSTBUS_OCSC:
1367                 reg = UFS_TEST_BUS_CTRL_1;
1368                 offset = 0;
1369                 break;
1370         case TSTBUS_WRAPPER:
1371                 reg = UFS_TEST_BUS_CTRL_2;
1372                 offset = 16;
1373                 break;
1374         case TSTBUS_COMBINED:
1375                 reg = UFS_TEST_BUS_CTRL_2;
1376                 offset = 8;
1377                 break;
1378         case TSTBUS_UTP_HCI:
1379                 reg = UFS_TEST_BUS_CTRL_2;
1380                 offset = 0;
1381                 break;
1382         case TSTBUS_UNIPRO:
1383                 reg = UFS_UNIPRO_CFG;
1384                 offset = 20;
1385                 mask = 0xFFF;
1386                 break;
1387         /*
1388          * No need for a default case, since
1389          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1390          * is legal
1391          */
1392         }
1393         mask <<= offset;
1394         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1395                     (u32)host->testbus.select_major << 19,
1396                     REG_UFS_CFG1);
1397         ufshcd_rmwl(host->hba, mask,
1398                     (u32)host->testbus.select_minor << offset,
1399                     reg);
1400         ufs_qcom_enable_test_bus(host);
1401         /*
1402          * Make sure the test bus configuration is
1403          * committed before returning.
1404          */
1405         mb();
1406
1407         return 0;
1408 }
1409
1410 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1411 {
1412         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1413                          "HCI Vendor Specific Registers ");
1414
1415         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1416 }
1417
1418 /**
1419  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1420  * @hba: per-adapter instance
1421  *
1422  * Toggles the (optional) reset line to reset the attached device.
1423  */
1424 static void ufs_qcom_device_reset(struct ufs_hba *hba)
1425 {
1426         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1427
1428         /* reset gpio is optional */
1429         if (!host->device_reset)
1430                 return;
1431
1432         /*
1433          * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1434          * be on the safe side.
1435          */
1436         gpiod_set_value_cansleep(host->device_reset, 1);
1437         usleep_range(10, 15);
1438
1439         gpiod_set_value_cansleep(host->device_reset, 0);
1440         usleep_range(10, 15);
1441 }
1442
1443 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1444 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1445                                           struct devfreq_dev_profile *p,
1446                                           void *data)
1447 {
1448         static struct devfreq_simple_ondemand_data *d;
1449
1450         if (!data)
1451                 return;
1452
1453         d = (struct devfreq_simple_ondemand_data *)data;
1454         p->polling_ms = 60;
1455         d->upthreshold = 70;
1456         d->downdifferential = 5;
1457 }
1458 #else
1459 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1460                                           struct devfreq_dev_profile *p,
1461                                           void *data)
1462 {
1463 }
1464 #endif
1465
1466 /*
1467  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1468  *
1469  * The variant operations configure the necessary controller and PHY
1470  * handshake during initialization.
1471  */
1472 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1473         .name                   = "qcom",
1474         .init                   = ufs_qcom_init,
1475         .exit                   = ufs_qcom_exit,
1476         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1477         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1478         .setup_clocks           = ufs_qcom_setup_clocks,
1479         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1480         .link_startup_notify    = ufs_qcom_link_startup_notify,
1481         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1482         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1483         .suspend                = ufs_qcom_suspend,
1484         .resume                 = ufs_qcom_resume,
1485         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1486         .device_reset           = ufs_qcom_device_reset,
1487         .config_scaling_param = ufs_qcom_config_scaling_param,
1488         .program_key            = ufs_qcom_ice_program_key,
1489 };
1490
1491 /**
1492  * ufs_qcom_probe - probe routine of the driver
1493  * @pdev: pointer to Platform device handle
1494  *
1495  * Return zero for success and non-zero for failure
1496  */
1497 static int ufs_qcom_probe(struct platform_device *pdev)
1498 {
1499         int err;
1500         struct device *dev = &pdev->dev;
1501
1502         /* Perform generic probe */
1503         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1504         if (err)
1505                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1506
1507         return err;
1508 }
1509
1510 /**
1511  * ufs_qcom_remove - set driver_data of the device to NULL
1512  * @pdev: pointer to platform device handle
1513  *
1514  * Always returns 0
1515  */
1516 static int ufs_qcom_remove(struct platform_device *pdev)
1517 {
1518         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1519
1520         pm_runtime_get_sync(&(pdev)->dev);
1521         ufshcd_remove(hba);
1522         return 0;
1523 }
1524
1525 static const struct of_device_id ufs_qcom_of_match[] = {
1526         { .compatible = "qcom,ufshc"},
1527         {},
1528 };
1529 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1530
1531 #ifdef CONFIG_ACPI
1532 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1533         { "QCOM24A5" },
1534         { },
1535 };
1536 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1537 #endif
1538
1539 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1540         .suspend        = ufshcd_pltfrm_suspend,
1541         .resume         = ufshcd_pltfrm_resume,
1542         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1543         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1544         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1545 };
1546
1547 static struct platform_driver ufs_qcom_pltform = {
1548         .probe  = ufs_qcom_probe,
1549         .remove = ufs_qcom_remove,
1550         .shutdown = ufshcd_pltfrm_shutdown,
1551         .driver = {
1552                 .name   = "ufshcd-qcom",
1553                 .pm     = &ufs_qcom_pm_ops,
1554                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1555                 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1556         },
1557 };
1558 module_platform_driver(ufs_qcom_pltform);
1559
1560 MODULE_LICENSE("GPL v2");