drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         drm_gem_object_release(&bo->gem_base);
  64         amdgpu_bo_unref(&bo->parent);
  65         if (!list_empty(&bo->shadow_list)) {
  66                 mutex_lock(&adev->shadow_list_lock);
  67                 list_del_init(&bo->shadow_list);
  68                 mutex_unlock(&adev->shadow_list_lock);
  69         }
  70         kfree(bo->metadata);
  71         kfree(bo);
  72 }
  73
  74 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  75 {
  76         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  77                 return true;
  78         return false;
  79 }
  80
  81 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  82 {
  83         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  84         struct ttm_placement *placement = &abo->placement;
  85         struct ttm_place *places = abo->placements;
  86         u64 flags = abo->flags;
  87         u32 c = 0;
  88
  89         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  90                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  91
  92                 places[c].fpfn = 0;
  93                 places[c].lpfn = 0;
  94                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  95                         TTM_PL_FLAG_VRAM;
  96
  97                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  98                         places[c].lpfn = visible_pfn;
  99                 else
 100                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 101
 102                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 103                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 104                 c++;
 105         }
 106
 107         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 108                 places[c].fpfn = 0;
 109                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 110                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 111                 else
 112                         places[c].lpfn = 0;
 113                 places[c].flags = TTM_PL_FLAG_TT;
 114                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 115                         places[c].flags |= TTM_PL_FLAG_WC |
 116                                 TTM_PL_FLAG_UNCACHED;
 117                 else
 118                         places[c].flags |= TTM_PL_FLAG_CACHED;
 119                 c++;
 120         }
 121
 122         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 123                 places[c].fpfn = 0;
 124                 places[c].lpfn = 0;
 125                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 126                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 127                         places[c].flags |= TTM_PL_FLAG_WC |
 128                                 TTM_PL_FLAG_UNCACHED;
 129                 else
 130                         places[c].flags |= TTM_PL_FLAG_CACHED;
 131                 c++;
 132         }
 133
 134         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 135                 places[c].fpfn = 0;
 136                 places[c].lpfn = 0;
 137                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 138                 c++;
 139         }
 140
 141         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 142                 places[c].fpfn = 0;
 143                 places[c].lpfn = 0;
 144                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 145                 c++;
 146         }
 147
 148         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 149                 places[c].fpfn = 0;
 150                 places[c].lpfn = 0;
 151                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 152                 c++;
 153         }
 154
 155         if (!c) {
 156                 places[c].fpfn = 0;
 157                 places[c].lpfn = 0;
 158                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 159                 c++;
 160         }
 161
 162         placement->num_placement = c;
 163         placement->placement = places;
 164
 165         placement->num_busy_placement = c;
 166         placement->busy_placement = places;
 167 }
 168
 169 /**
 170  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 171  *
 172  * @adev: amdgpu device object
 173  * @size: size for the new BO
 174  * @align: alignment for the new BO
 175  * @domain: where to place it
 176  * @bo_ptr: resulting BO
 177  * @gpu_addr: GPU addr of the pinned BO
 178  * @cpu_addr: optional CPU address mapping
 179  *
 180  * Allocates and pins a BO for kernel internal use, and returns it still
 181  * reserved.
 182  *
 183  * Returns 0 on success, negative error code otherwise.
 184  */
 185 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 186                               unsigned long size, int align,
 187                               u32 domain, struct amdgpu_bo **bo_ptr,
 188                               u64 *gpu_addr, void **cpu_addr)
 189 {
 190         bool free = false;
 191         int r;
 192
 193         if (!*bo_ptr) {
 194                 r = amdgpu_bo_create(adev, size, align, true, domain,
 195                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 196                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 197                                      NULL, NULL, bo_ptr);
 198                 if (r) {
 199                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 200                                 r);
 201                         return r;
 202                 }
 203                 free = true;
 204         }
 205
 206         r = amdgpu_bo_reserve(*bo_ptr, false);
 207         if (r) {
 208                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 209                 goto error_free;
 210         }
 211
 212         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 213         if (r) {
 214                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 215                 goto error_unreserve;
 216         }
 217
 218         if (cpu_addr) {
 219                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 220                 if (r) {
 221                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 222                         goto error_unreserve;
 223                 }
 224         }
 225
 226         return 0;
 227
 228 error_unreserve:
 229         amdgpu_bo_unreserve(*bo_ptr);
 230
 231 error_free:
 232         if (free)
 233                 amdgpu_bo_unref(bo_ptr);
 234
 235         return r;
 236 }
 237
 238 /**
 239  * amdgpu_bo_create_kernel - create BO for kernel use
 240  *
 241  * @adev: amdgpu device object
 242  * @size: size for the new BO
 243  * @align: alignment for the new BO
 244  * @domain: where to place it
 245  * @bo_ptr: resulting BO
 246  * @gpu_addr: GPU addr of the pinned BO
 247  * @cpu_addr: optional CPU address mapping
 248  *
 249  * Allocates and pins a BO for kernel internal use.
 250  *
 251  * Returns 0 on success, negative error code otherwise.
 252  */
 253 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 254                             unsigned long size, int align,
 255                             u32 domain, struct amdgpu_bo **bo_ptr,
 256                             u64 *gpu_addr, void **cpu_addr)
 257 {
 258         int r;
 259
 260         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 261                                       gpu_addr, cpu_addr);
 262
 263         if (r)
 264                 return r;
 265
 266         amdgpu_bo_unreserve(*bo_ptr);
 267
 268         return 0;
 269 }
 270
 271 /**
 272  * amdgpu_bo_free_kernel - free BO for kernel use
 273  *
 274  * @bo: amdgpu BO to free
 275  *
 276  * unmaps and unpin a BO for kernel internal use.
 277  */
 278 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 279                            void **cpu_addr)
 280 {
 281         if (*bo == NULL)
 282                 return;
 283
 284         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 285                 if (cpu_addr)
 286                         amdgpu_bo_kunmap(*bo);
 287
 288                 amdgpu_bo_unpin(*bo);
 289                 amdgpu_bo_unreserve(*bo);
 290         }
 291         amdgpu_bo_unref(bo);
 292
 293         if (gpu_addr)
 294                 *gpu_addr = 0;
 295
 296         if (cpu_addr)
 297                 *cpu_addr = NULL;
 298 }
 299
 300 /* Validate bo size is bit bigger then the request domain */
 301 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 302                                           unsigned long size, u32 domain)
 303 {
 304         struct ttm_mem_type_manager *man = NULL;
 305
 306         /*
 307          * If GTT is part of requested domains the check must succeed to
 308          * allow fall back to GTT
 309          */
 310         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 311                 man = &adev->mman.bdev.man[TTM_PL_TT];
 312
 313                 if (size < (man->size << PAGE_SHIFT))
 314                         return true;
 315                 else
 316                         goto fail;
 317         }
 318
 319         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 320                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 321
 322                 if (size < (man->size << PAGE_SHIFT))
 323                         return true;
 324                 else
 325                         goto fail;
 326         }
 327
 328
 329         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 330         return true;
 331
 332 fail:
 333         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 334                   man->size << PAGE_SHIFT);
 335         return false;
 336 }
 337
 338 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 339                                unsigned long size, int byte_align,
 340                                bool kernel, u32 domain, u64 flags,
 341                                struct sg_table *sg,
 342                                struct reservation_object *resv,
 343                                struct amdgpu_bo **bo_ptr)
 344 {
 345         struct ttm_operation_ctx ctx = {
 346                 .interruptible = !kernel,
 347                 .no_wait_gpu = false,
 348                 .resv = resv,
 349                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 350         };
 351         struct amdgpu_bo *bo;
 352         enum ttm_bo_type type;
 353         unsigned long page_align;
 354         size_t acc_size;
 355         int r;
 356
 357         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 358         size = ALIGN(size, PAGE_SIZE);
 359
 360         if (!amdgpu_bo_validate_size(adev, size, domain))
 361                 return -ENOMEM;
 362
 363         if (kernel) {
 364                 type = ttm_bo_type_kernel;
 365         } else if (sg) {
 366                 type = ttm_bo_type_sg;
 367         } else {
 368                 type = ttm_bo_type_device;
 369         }
 370         *bo_ptr = NULL;
 371
 372         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 373                                        sizeof(struct amdgpu_bo));
 374
 375         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 376         if (bo == NULL)
 377                 return -ENOMEM;
 378         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 379         INIT_LIST_HEAD(&bo->shadow_list);
 380         INIT_LIST_HEAD(&bo->va);
 381         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 382                                          AMDGPU_GEM_DOMAIN_GTT |
 383                                          AMDGPU_GEM_DOMAIN_CPU |
 384                                          AMDGPU_GEM_DOMAIN_GDS |
 385                                          AMDGPU_GEM_DOMAIN_GWS |
 386                                          AMDGPU_GEM_DOMAIN_OA);
 387         bo->allowed_domains = bo->preferred_domains;
 388         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 389                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 390
 391         bo->flags = flags;
 392
 393 #ifdef CONFIG_X86_32
 394         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 395          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 396          */
 397         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 398 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 399         /* Don't try to enable write-combining when it can't work, or things
 400          * may be slow
 401          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 402          */
 403
 404 #ifndef CONFIG_COMPILE_TEST
 405 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 406          thanks to write-combining
 407 #endif
 408
 409         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 410                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 411                               "better performance thanks to write-combining\n");
 412         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 413 #else
 414         /* For architectures that don't support WC memory,
 415          * mask out the WC flag from the BO
 416          */
 417         if (!drm_arch_can_wc_memory())
 418                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 419 #endif
 420
 421         bo->tbo.bdev = &adev->mman.bdev;
 422         amdgpu_ttm_placement_from_domain(bo, domain);
 423
 424         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 425                                  &bo->placement, page_align, &ctx, acc_size,
 426                                  sg, resv, &amdgpu_ttm_bo_destroy);
 427         if (unlikely(r != 0))
 428                 return r;
 429
 430         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 431             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 432             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 433                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 434                                              ctx.bytes_moved);
 435         else
 436                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 437
 438         if (kernel)
 439                 bo->tbo.priority = 1;
 440
 441         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 442             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 443                 struct dma_fence *fence;
 444
 445                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 446                 if (unlikely(r))
 447                         goto fail_unreserve;
 448
 449                 amdgpu_bo_fence(bo, fence, false);
 450                 dma_fence_put(bo->tbo.moving);
 451                 bo->tbo.moving = dma_fence_get(fence);
 452                 dma_fence_put(fence);
 453         }
 454         if (!resv)
 455                 amdgpu_bo_unreserve(bo);
 456         *bo_ptr = bo;
 457
 458         trace_amdgpu_bo_create(bo);
 459
 460         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 461         if (type == ttm_bo_type_device)
 462                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 463
 464         return 0;
 465
 466 fail_unreserve:
 467         if (!resv)
 468                 ww_mutex_unlock(&bo->tbo.resv->lock);
 469         amdgpu_bo_unref(&bo);
 470         return r;
 471 }
 472
 473 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 474                                    unsigned long size, int byte_align,
 475                                    struct amdgpu_bo *bo)
 476 {
 477         int r;
 478
 479         if (bo->shadow)
 480                 return 0;
 481
 482         r = amdgpu_bo_do_create(adev, size, byte_align, true,
 483                                 AMDGPU_GEM_DOMAIN_GTT,
 484                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 485                                 AMDGPU_GEM_CREATE_SHADOW,
 486                                 NULL, bo->tbo.resv,
 487                                 &bo->shadow);
 488         if (!r) {
 489                 bo->shadow->parent = amdgpu_bo_ref(bo);
 490                 mutex_lock(&adev->shadow_list_lock);
 491                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 492                 mutex_unlock(&adev->shadow_list_lock);
 493         }
 494
 495         return r;
 496 }
 497
 498 int amdgpu_bo_create(struct amdgpu_device *adev,
 499                      unsigned long size, int byte_align,
 500                      bool kernel, u32 domain, u64 flags,
 501                      struct sg_table *sg,
 502                      struct reservation_object *resv,
 503                      struct amdgpu_bo **bo_ptr)
 504 {
 505         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 506         int r;
 507
 508         r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
 509                                 parent_flags, sg, resv, bo_ptr);
 510         if (r)
 511                 return r;
 512
 513         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 514                 if (!resv)
 515                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 516                                                         NULL));
 517
 518                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 519
 520                 if (!resv)
 521                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 522
 523                 if (r)
 524                         amdgpu_bo_unref(bo_ptr);
 525         }
 526
 527         return r;
 528 }
 529
 530 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 531                                struct amdgpu_ring *ring,
 532                                struct amdgpu_bo *bo,
 533                                struct reservation_object *resv,
 534                                struct dma_fence **fence,
 535                                bool direct)
 536
 537 {
 538         struct amdgpu_bo *shadow = bo->shadow;
 539         uint64_t bo_addr, shadow_addr;
 540         int r;
 541
 542         if (!shadow)
 543                 return -EINVAL;
 544
 545         bo_addr = amdgpu_bo_gpu_offset(bo);
 546         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 547
 548         r = reservation_object_reserve_shared(bo->tbo.resv);
 549         if (r)
 550                 goto err;
 551
 552         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 553                                amdgpu_bo_size(bo), resv, fence,
 554                                direct, false);
 555         if (!r)
 556                 amdgpu_bo_fence(bo, *fence, true);
 557
 558 err:
 559         return r;
 560 }
 561
 562 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 563 {
 564         struct ttm_operation_ctx ctx = { false, false };
 565         uint32_t domain;
 566         int r;
 567
 568         if (bo->pin_count)
 569                 return 0;
 570
 571         domain = bo->preferred_domains;
 572
 573 retry:
 574         amdgpu_ttm_placement_from_domain(bo, domain);
 575         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 576         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 577                 domain = bo->allowed_domains;
 578                 goto retry;
 579         }
 580
 581         return r;
 582 }
 583
 584 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 585                                   struct amdgpu_ring *ring,
 586                                   struct amdgpu_bo *bo,
 587                                   struct reservation_object *resv,
 588                                   struct dma_fence **fence,
 589                                   bool direct)
 590
 591 {
 592         struct amdgpu_bo *shadow = bo->shadow;
 593         uint64_t bo_addr, shadow_addr;
 594         int r;
 595
 596         if (!shadow)
 597                 return -EINVAL;
 598
 599         bo_addr = amdgpu_bo_gpu_offset(bo);
 600         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 601
 602         r = reservation_object_reserve_shared(bo->tbo.resv);
 603         if (r)
 604                 goto err;
 605
 606         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 607                                amdgpu_bo_size(bo), resv, fence,
 608                                direct, false);
 609         if (!r)
 610                 amdgpu_bo_fence(bo, *fence, true);
 611
 612 err:
 613         return r;
 614 }
 615
 616 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 617 {
 618         void *kptr;
 619         long r;
 620
 621         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 622                 return -EPERM;
 623
 624         kptr = amdgpu_bo_kptr(bo);
 625         if (kptr) {
 626                 if (ptr)
 627                         *ptr = kptr;
 628                 return 0;
 629         }
 630
 631         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 632                                                 MAX_SCHEDULE_TIMEOUT);
 633         if (r < 0)
 634                 return r;
 635
 636         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 637         if (r)
 638                 return r;
 639
 640         if (ptr)
 641                 *ptr = amdgpu_bo_kptr(bo);
 642
 643         return 0;
 644 }
 645
 646 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 647 {
 648         bool is_iomem;
 649
 650         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 651 }
 652
 653 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 654 {
 655         if (bo->kmap.bo)
 656                 ttm_bo_kunmap(&bo->kmap);
 657 }
 658
 659 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 660 {
 661         if (bo == NULL)
 662                 return NULL;
 663
 664         ttm_bo_reference(&bo->tbo);
 665         return bo;
 666 }
 667
 668 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 669 {
 670         struct ttm_buffer_object *tbo;
 671
 672         if ((*bo) == NULL)
 673                 return;
 674
 675         tbo = &((*bo)->tbo);
 676         ttm_bo_unref(&tbo);
 677         if (tbo == NULL)
 678                 *bo = NULL;
 679 }
 680
 681 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 682                              u64 min_offset, u64 max_offset,
 683                              u64 *gpu_addr)
 684 {
 685         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 686         struct ttm_operation_ctx ctx = { false, false };
 687         int r, i;
 688
 689         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 690                 return -EPERM;
 691
 692         if (WARN_ON_ONCE(min_offset > max_offset))
 693                 return -EINVAL;
 694
 695         /* A shared bo cannot be migrated to VRAM */
 696         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 697                 return -EINVAL;
 698
 699         if (bo->pin_count) {
 700                 uint32_t mem_type = bo->tbo.mem.mem_type;
 701
 702                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 703                         return -EINVAL;
 704
 705                 bo->pin_count++;
 706                 if (gpu_addr)
 707                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 708
 709                 if (max_offset != 0) {
 710                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 711                         WARN_ON_ONCE(max_offset <
 712                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 713                 }
 714
 715                 return 0;
 716         }
 717
 718         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 719         /* force to pin into visible video ram */
 720         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 721                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 722         amdgpu_ttm_placement_from_domain(bo, domain);
 723         for (i = 0; i < bo->placement.num_placement; i++) {
 724                 unsigned fpfn, lpfn;
 725
 726                 fpfn = min_offset >> PAGE_SHIFT;
 727                 lpfn = max_offset >> PAGE_SHIFT;
 728
 729                 if (fpfn > bo->placements[i].fpfn)
 730                         bo->placements[i].fpfn = fpfn;
 731                 if (!bo->placements[i].lpfn ||
 732                     (lpfn && lpfn < bo->placements[i].lpfn))
 733                         bo->placements[i].lpfn = lpfn;
 734                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 735         }
 736
 737         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 738         if (unlikely(r)) {
 739                 dev_err(adev->dev, "%p pin failed\n", bo);
 740                 goto error;
 741         }
 742
 743         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 744         if (unlikely(r)) {
 745                 dev_err(adev->dev, "%p bind failed\n", bo);
 746                 goto error;
 747         }
 748
 749         bo->pin_count = 1;
 750         if (gpu_addr != NULL)
 751                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 752
 753         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 754         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 755                 adev->vram_pin_size += amdgpu_bo_size(bo);
 756                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 757                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 758         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 759                 adev->gart_pin_size += amdgpu_bo_size(bo);
 760         }
 761
 762 error:
 763         return r;
 764 }
 765
 766 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 767 {
 768         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 769 }
 770
 771 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 772 {
 773         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 774         struct ttm_operation_ctx ctx = { false, false };
 775         int r, i;
 776
 777         if (!bo->pin_count) {
 778                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 779                 return 0;
 780         }
 781         bo->pin_count--;
 782         if (bo->pin_count)
 783                 return 0;
 784         for (i = 0; i < bo->placement.num_placement; i++) {
 785                 bo->placements[i].lpfn = 0;
 786                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 787         }
 788         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 789         if (unlikely(r)) {
 790                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 791                 goto error;
 792         }
 793
 794         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 795                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 796                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 797                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 798         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 799                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 800         }
 801
 802 error:
 803         return r;
 804 }
 805
 806 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 807 {
 808         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 809         if (0 && (adev->flags & AMD_IS_APU)) {
 810                 /* Useless to evict on IGP chips */
 811                 return 0;
 812         }
 813         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 814 }
 815
 816 static const char *amdgpu_vram_names[] = {
 817         "UNKNOWN",
 818         "GDDR1",
 819         "DDR2",
 820         "GDDR3",
 821         "GDDR4",
 822         "GDDR5",
 823         "HBM",
 824         "DDR3"
 825 };
 826
 827 int amdgpu_bo_init(struct amdgpu_device *adev)
 828 {
 829         /* reserve PAT memory space to WC for VRAM */
 830         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 831                                    adev->gmc.aper_size);
 832
 833         /* Add an MTRR for the VRAM */
 834         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 835                                               adev->gmc.aper_size);
 836         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 837                  adev->gmc.mc_vram_size >> 20,
 838                  (unsigned long long)adev->gmc.aper_size >> 20);
 839         DRM_INFO("RAM width %dbits %s\n",
 840                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 841         return amdgpu_ttm_init(adev);
 842 }
 843
 844 void amdgpu_bo_fini(struct amdgpu_device *adev)
 845 {
 846         amdgpu_ttm_fini(adev);
 847         arch_phys_wc_del(adev->gmc.vram_mtrr);
 848         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 849 }
 850
 851 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 852                              struct vm_area_struct *vma)
 853 {
 854         return ttm_fbdev_mmap(vma, &bo->tbo);
 855 }
 856
 857 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 858 {
 859         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 860
 861         if (adev->family <= AMDGPU_FAMILY_CZ &&
 862             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 863                 return -EINVAL;
 864
 865         bo->tiling_flags = tiling_flags;
 866         return 0;
 867 }
 868
 869 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 870 {
 871         lockdep_assert_held(&bo->tbo.resv->lock.base);
 872
 873         if (tiling_flags)
 874                 *tiling_flags = bo->tiling_flags;
 875 }
 876
 877 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 878                             uint32_t metadata_size, uint64_t flags)
 879 {
 880         void *buffer;
 881
 882         if (!metadata_size) {
 883                 if (bo->metadata_size) {
 884                         kfree(bo->metadata);
 885                         bo->metadata = NULL;
 886                         bo->metadata_size = 0;
 887                 }
 888                 return 0;
 889         }
 890
 891         if (metadata == NULL)
 892                 return -EINVAL;
 893
 894         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 895         if (buffer == NULL)
 896                 return -ENOMEM;
 897
 898         kfree(bo->metadata);
 899         bo->metadata_flags = flags;
 900         bo->metadata = buffer;
 901         bo->metadata_size = metadata_size;
 902
 903         return 0;
 904 }
 905
 906 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 907                            size_t buffer_size, uint32_t *metadata_size,
 908                            uint64_t *flags)
 909 {
 910         if (!buffer && !metadata_size)
 911                 return -EINVAL;
 912
 913         if (buffer) {
 914                 if (buffer_size < bo->metadata_size)
 915                         return -EINVAL;
 916
 917                 if (bo->metadata_size)
 918                         memcpy(buffer, bo->metadata, bo->metadata_size);
 919         }
 920
 921         if (metadata_size)
 922                 *metadata_size = bo->metadata_size;
 923         if (flags)
 924                 *flags = bo->metadata_flags;
 925
 926         return 0;
 927 }
 928
 929 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 930                            bool evict,
 931                            struct ttm_mem_reg *new_mem)
 932 {
 933         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 934         struct amdgpu_bo *abo;
 935         struct ttm_mem_reg *old_mem = &bo->mem;
 936
 937         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 938                 return;
 939
 940         abo = ttm_to_amdgpu_bo(bo);
 941         amdgpu_vm_bo_invalidate(adev, abo, evict);
 942
 943         amdgpu_bo_kunmap(abo);
 944
 945         /* remember the eviction */
 946         if (evict)
 947                 atomic64_inc(&adev->num_evictions);
 948
 949         /* update statistics */
 950         if (!new_mem)
 951                 return;
 952
 953         /* move_notify is called before move happens */
 954         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 955 }
 956
 957 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 958 {
 959         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 960         struct ttm_operation_ctx ctx = { false, false };
 961         struct amdgpu_bo *abo;
 962         unsigned long offset, size;
 963         int r;
 964
 965         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 966                 return 0;
 967
 968         abo = ttm_to_amdgpu_bo(bo);
 969
 970         /* Remember that this BO was accessed by the CPU */
 971         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 972
 973         if (bo->mem.mem_type != TTM_PL_VRAM)
 974                 return 0;
 975
 976         size = bo->mem.num_pages << PAGE_SHIFT;
 977         offset = bo->mem.start << PAGE_SHIFT;
 978         if ((offset + size) <= adev->gmc.visible_vram_size)
 979                 return 0;
 980
 981         /* Can't move a pinned BO to visible VRAM */
 982         if (abo->pin_count > 0)
 983                 return -EINVAL;
 984
 985         /* hurrah the memory is not visible ! */
 986         atomic64_inc(&adev->num_vram_cpu_page_faults);
 987         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 988                                          AMDGPU_GEM_DOMAIN_GTT);
 989
 990         /* Avoid costly evictions; only set GTT as a busy placement */
 991         abo->placement.num_busy_placement = 1;
 992         abo->placement.busy_placement = &abo->placements[1];
 993
 994         r = ttm_bo_validate(bo, &abo->placement, &ctx);
 995         if (unlikely(r != 0))
 996                 return r;
 997
 998         offset = bo->mem.start << PAGE_SHIFT;
 999         /* this should never happen */
1000         if (bo->mem.mem_type == TTM_PL_VRAM &&
1001             (offset + size) > adev->gmc.visible_vram_size)
1002                 return -EINVAL;
1003
1004         return 0;
1005 }
1006
1007 /**
1008  * amdgpu_bo_fence - add fence to buffer object
1009  *
1010  * @bo: buffer object in question
1011  * @fence: fence to add
1012  * @shared: true if fence should be added shared
1013  *
1014  */
1015 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1016                      bool shared)
1017 {
1018         struct reservation_object *resv = bo->tbo.resv;
1019
1020         if (shared)
1021                 reservation_object_add_shared_fence(resv, fence);
1022         else
1023                 reservation_object_add_excl_fence(resv, fence);
1024 }
1025
1026 /**
1027  * amdgpu_bo_gpu_offset - return GPU offset of bo
1028  * @bo: amdgpu object for which we query the offset
1029  *
1030  * Returns current GPU offset of the object.
1031  *
1032  * Note: object should either be pinned or reserved when calling this
1033  * function, it might be useful to add check for this for debugging.
1034  */
1035 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1036 {
1037         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1038         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1039                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1040         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1041                      !bo->pin_count);
1042         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1043         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1044                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1045
1046         return bo->tbo.offset;
1047 }