drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drm_cache.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v9_0.h"
  27 #include "amdgpu_atomfirmware.h"
  28
  29 #include "hdp/hdp_4_0_offset.h"
  30 #include "hdp/hdp_4_0_sh_mask.h"
  31 #include "gc/gc_9_0_sh_mask.h"
  32 #include "dce/dce_12_0_offset.h"
  33 #include "dce/dce_12_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "mmhub/mmhub_1_0_offset.h"
  36 #include "athub/athub_1_0_offset.h"
  37 #include "oss/osssys_4_0_offset.h"
  38
  39 #include "soc15.h"
  40 #include "soc15_common.h"
  41 #include "umc/umc_6_0_sh_mask.h"
  42
  43 #include "gfxhub_v1_0.h"
  44 #include "mmhub_v1_0.h"
  45
  46 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  47 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  48 //DF_CS_AON0_DramBaseAddress0
  49 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  50 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  51 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  52 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  53 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  54 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  55 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  56 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  57 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  58 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  59
  60 /* add these here since we already include dce12 headers and these are for DCN */
  61 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  63 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  67
  68 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  69 #define AMDGPU_NUM_OF_VMIDS                     8
  70
  71 static const u32 golden_settings_vega10_hdp[] =
  72 {
  73         0xf64, 0x0fffffff, 0x00000000,
  74         0xf65, 0x0fffffff, 0x00000000,
  75         0xf66, 0x0fffffff, 0x00000000,
  76         0xf67, 0x0fffffff, 0x00000000,
  77         0xf68, 0x0fffffff, 0x00000000,
  78         0xf6a, 0x0fffffff, 0x00000000,
  79         0xf6b, 0x0fffffff, 0x00000000,
  80         0xf6c, 0x0fffffff, 0x00000000,
  81         0xf6d, 0x0fffffff, 0x00000000,
  82         0xf6e, 0x0fffffff, 0x00000000,
  83 };
  84
  85 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  86 {
  87         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  88         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  89 };
  90
  91 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  92 {
  93         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  94         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  95 };
  96
  97 /* Ecc related register addresses, (BASE + reg offset) */
  98 /* Universal Memory Controller caps (may be fused). */
  99 /* UMCCH:UmcLocalCap */
 100 #define UMCLOCALCAPS_ADDR0      (0x00014306 + 0x00000000)
 101 #define UMCLOCALCAPS_ADDR1      (0x00014306 + 0x00000800)
 102 #define UMCLOCALCAPS_ADDR2      (0x00014306 + 0x00001000)
 103 #define UMCLOCALCAPS_ADDR3      (0x00014306 + 0x00001800)
 104 #define UMCLOCALCAPS_ADDR4      (0x00054306 + 0x00000000)
 105 #define UMCLOCALCAPS_ADDR5      (0x00054306 + 0x00000800)
 106 #define UMCLOCALCAPS_ADDR6      (0x00054306 + 0x00001000)
 107 #define UMCLOCALCAPS_ADDR7      (0x00054306 + 0x00001800)
 108 #define UMCLOCALCAPS_ADDR8      (0x00094306 + 0x00000000)
 109 #define UMCLOCALCAPS_ADDR9      (0x00094306 + 0x00000800)
 110 #define UMCLOCALCAPS_ADDR10     (0x00094306 + 0x00001000)
 111 #define UMCLOCALCAPS_ADDR11     (0x00094306 + 0x00001800)
 112 #define UMCLOCALCAPS_ADDR12     (0x000d4306 + 0x00000000)
 113 #define UMCLOCALCAPS_ADDR13     (0x000d4306 + 0x00000800)
 114 #define UMCLOCALCAPS_ADDR14     (0x000d4306 + 0x00001000)
 115 #define UMCLOCALCAPS_ADDR15     (0x000d4306 + 0x00001800)
 116
 117 /* Universal Memory Controller Channel config. */
 118 /* UMCCH:UMC_CONFIG */
 119 #define UMCCH_UMC_CONFIG_ADDR0  (0x00014040 + 0x00000000)
 120 #define UMCCH_UMC_CONFIG_ADDR1  (0x00014040 + 0x00000800)
 121 #define UMCCH_UMC_CONFIG_ADDR2  (0x00014040 + 0x00001000)
 122 #define UMCCH_UMC_CONFIG_ADDR3  (0x00014040 + 0x00001800)
 123 #define UMCCH_UMC_CONFIG_ADDR4  (0x00054040 + 0x00000000)
 124 #define UMCCH_UMC_CONFIG_ADDR5  (0x00054040 + 0x00000800)
 125 #define UMCCH_UMC_CONFIG_ADDR6  (0x00054040 + 0x00001000)
 126 #define UMCCH_UMC_CONFIG_ADDR7  (0x00054040 + 0x00001800)
 127 #define UMCCH_UMC_CONFIG_ADDR8  (0x00094040 + 0x00000000)
 128 #define UMCCH_UMC_CONFIG_ADDR9  (0x00094040 + 0x00000800)
 129 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
 130 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
 131 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
 132 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
 133 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
 134 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
 135
 136 /* Universal Memory Controller Channel Ecc config. */
 137 /* UMCCH:EccCtrl */
 138 #define UMCCH_ECCCTRL_ADDR0     (0x00014053 + 0x00000000)
 139 #define UMCCH_ECCCTRL_ADDR1     (0x00014053 + 0x00000800)
 140 #define UMCCH_ECCCTRL_ADDR2     (0x00014053 + 0x00001000)
 141 #define UMCCH_ECCCTRL_ADDR3     (0x00014053 + 0x00001800)
 142 #define UMCCH_ECCCTRL_ADDR4     (0x00054053 + 0x00000000)
 143 #define UMCCH_ECCCTRL_ADDR5     (0x00054053 + 0x00000800)
 144 #define UMCCH_ECCCTRL_ADDR6     (0x00054053 + 0x00001000)
 145 #define UMCCH_ECCCTRL_ADDR7     (0x00054053 + 0x00001800)
 146 #define UMCCH_ECCCTRL_ADDR8     (0x00094053 + 0x00000000)
 147 #define UMCCH_ECCCTRL_ADDR9     (0x00094053 + 0x00000800)
 148 #define UMCCH_ECCCTRL_ADDR10    (0x00094053 + 0x00001000)
 149 #define UMCCH_ECCCTRL_ADDR11    (0x00094053 + 0x00001800)
 150 #define UMCCH_ECCCTRL_ADDR12    (0x000d4053 + 0x00000000)
 151 #define UMCCH_ECCCTRL_ADDR13    (0x000d4053 + 0x00000800)
 152 #define UMCCH_ECCCTRL_ADDR14    (0x000d4053 + 0x00001000)
 153 #define UMCCH_ECCCTRL_ADDR15    (0x000d4053 + 0x00001800)
 154
 155 static const uint32_t ecc_umclocalcap_addrs[] = {
 156         UMCLOCALCAPS_ADDR0,
 157         UMCLOCALCAPS_ADDR1,
 158         UMCLOCALCAPS_ADDR2,
 159         UMCLOCALCAPS_ADDR3,
 160         UMCLOCALCAPS_ADDR4,
 161         UMCLOCALCAPS_ADDR5,
 162         UMCLOCALCAPS_ADDR6,
 163         UMCLOCALCAPS_ADDR7,
 164         UMCLOCALCAPS_ADDR8,
 165         UMCLOCALCAPS_ADDR9,
 166         UMCLOCALCAPS_ADDR10,
 167         UMCLOCALCAPS_ADDR11,
 168         UMCLOCALCAPS_ADDR12,
 169         UMCLOCALCAPS_ADDR13,
 170         UMCLOCALCAPS_ADDR14,
 171         UMCLOCALCAPS_ADDR15,
 172 };
 173
 174 static const uint32_t ecc_umcch_umc_config_addrs[] = {
 175         UMCCH_UMC_CONFIG_ADDR0,
 176         UMCCH_UMC_CONFIG_ADDR1,
 177         UMCCH_UMC_CONFIG_ADDR2,
 178         UMCCH_UMC_CONFIG_ADDR3,
 179         UMCCH_UMC_CONFIG_ADDR4,
 180         UMCCH_UMC_CONFIG_ADDR5,
 181         UMCCH_UMC_CONFIG_ADDR6,
 182         UMCCH_UMC_CONFIG_ADDR7,
 183         UMCCH_UMC_CONFIG_ADDR8,
 184         UMCCH_UMC_CONFIG_ADDR9,
 185         UMCCH_UMC_CONFIG_ADDR10,
 186         UMCCH_UMC_CONFIG_ADDR11,
 187         UMCCH_UMC_CONFIG_ADDR12,
 188         UMCCH_UMC_CONFIG_ADDR13,
 189         UMCCH_UMC_CONFIG_ADDR14,
 190         UMCCH_UMC_CONFIG_ADDR15,
 191 };
 192
 193 static const uint32_t ecc_umcch_eccctrl_addrs[] = {
 194         UMCCH_ECCCTRL_ADDR0,
 195         UMCCH_ECCCTRL_ADDR1,
 196         UMCCH_ECCCTRL_ADDR2,
 197         UMCCH_ECCCTRL_ADDR3,
 198         UMCCH_ECCCTRL_ADDR4,
 199         UMCCH_ECCCTRL_ADDR5,
 200         UMCCH_ECCCTRL_ADDR6,
 201         UMCCH_ECCCTRL_ADDR7,
 202         UMCCH_ECCCTRL_ADDR8,
 203         UMCCH_ECCCTRL_ADDR9,
 204         UMCCH_ECCCTRL_ADDR10,
 205         UMCCH_ECCCTRL_ADDR11,
 206         UMCCH_ECCCTRL_ADDR12,
 207         UMCCH_ECCCTRL_ADDR13,
 208         UMCCH_ECCCTRL_ADDR14,
 209         UMCCH_ECCCTRL_ADDR15,
 210 };
 211
 212 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 213                                         struct amdgpu_irq_src *src,
 214                                         unsigned type,
 215                                         enum amdgpu_interrupt_state state)
 216 {
 217         struct amdgpu_vmhub *hub;
 218         u32 tmp, reg, bits, i, j;
 219
 220         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 221                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 222                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 223                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 224                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 225                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 226                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 227
 228         switch (state) {
 229         case AMDGPU_IRQ_STATE_DISABLE:
 230                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 231                         hub = &adev->vmhub[j];
 232                         for (i = 0; i < 16; i++) {
 233                                 reg = hub->vm_context0_cntl + i;
 234                                 tmp = RREG32(reg);
 235                                 tmp &= ~bits;
 236                                 WREG32(reg, tmp);
 237                         }
 238                 }
 239                 break;
 240         case AMDGPU_IRQ_STATE_ENABLE:
 241                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 242                         hub = &adev->vmhub[j];
 243                         for (i = 0; i < 16; i++) {
 244                                 reg = hub->vm_context0_cntl + i;
 245                                 tmp = RREG32(reg);
 246                                 tmp |= bits;
 247                                 WREG32(reg, tmp);
 248                         }
 249                 }
 250         default:
 251                 break;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 258                                 struct amdgpu_irq_src *source,
 259                                 struct amdgpu_iv_entry *entry)
 260 {
 261         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 262         uint32_t status = 0;
 263         u64 addr;
 264
 265         addr = (u64)entry->src_data[0] << 12;
 266         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 267
 268         if (!amdgpu_sriov_vf(adev)) {
 269                 status = RREG32(hub->vm_l2_pro_fault_status);
 270                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 271         }
 272
 273         if (printk_ratelimit()) {
 274                 dev_err(adev->dev,
 275                         "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
 276                         entry->vmid_src ? "mmhub" : "gfxhub",
 277                         entry->src_id, entry->ring_id, entry->vmid,
 278                         entry->pasid);
 279                 dev_err(adev->dev, "  at page 0x%016llx from %d\n",
 280                         addr, entry->client_id);
 281                 if (!amdgpu_sriov_vf(adev))
 282                         dev_err(adev->dev,
 283                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 284                                 status);
 285         }
 286
 287         return 0;
 288 }
 289
 290 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 291         .set = gmc_v9_0_vm_fault_interrupt_state,
 292         .process = gmc_v9_0_process_interrupt,
 293 };
 294
 295 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 296 {
 297         adev->gmc.vm_fault.num_types = 1;
 298         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 299 }
 300
 301 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
 302 {
 303         u32 req = 0;
 304
 305         /* invalidate using legacy mode on vmid*/
 306         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 307                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 308         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
 309         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 310         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 311         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 312         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 313         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 314         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 315                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 316
 317         return req;
 318 }
 319
 320 /*
 321  * GART
 322  * VMID 0 is the physical GPU addresses as used by the kernel.
 323  * VMIDs 1-15 are used for userspace clients and are handled
 324  * by the amdgpu vm/hsa code.
 325  */
 326
 327 /**
 328  * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
 329  *
 330  * @adev: amdgpu_device pointer
 331  * @vmid: vm instance to flush
 332  *
 333  * Flush the TLB for the requested page table.
 334  */
 335 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 336                                         uint32_t vmid)
 337 {
 338         /* Use register 17 for GART */
 339         const unsigned eng = 17;
 340         unsigned i, j;
 341
 342         spin_lock(&adev->gmc.invalidate_lock);
 343
 344         for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
 345                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
 346                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
 347
 348                 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 349
 350                 /* Busy wait for ACK.*/
 351                 for (j = 0; j < 100; j++) {
 352                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 353                         tmp &= 1 << vmid;
 354                         if (tmp)
 355                                 break;
 356                         cpu_relax();
 357                 }
 358                 if (j < 100)
 359                         continue;
 360
 361                 /* Wait for ACK with a delay.*/
 362                 for (j = 0; j < adev->usec_timeout; j++) {
 363                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 364                         tmp &= 1 << vmid;
 365                         if (tmp)
 366                                 break;
 367                         udelay(1);
 368                 }
 369                 if (j < adev->usec_timeout)
 370                         continue;
 371
 372                 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 373         }
 374
 375         spin_unlock(&adev->gmc.invalidate_lock);
 376 }
 377
 378 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 379                                             unsigned vmid, uint64_t pd_addr)
 380 {
 381         struct amdgpu_device *adev = ring->adev;
 382         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 383         uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
 384         uint64_t flags = AMDGPU_PTE_VALID;
 385         unsigned eng = ring->vm_inv_eng;
 386
 387         amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
 388         pd_addr |= flags;
 389
 390         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 391                               lower_32_bits(pd_addr));
 392
 393         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 394                               upper_32_bits(pd_addr));
 395
 396         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 397                                             hub->vm_inv_eng0_ack + eng,
 398                                             req, 1 << vmid);
 399
 400         return pd_addr;
 401 }
 402
 403 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 404                                         unsigned pasid)
 405 {
 406         struct amdgpu_device *adev = ring->adev;
 407         uint32_t reg;
 408
 409         if (ring->funcs->vmhub == AMDGPU_GFXHUB)
 410                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 411         else
 412                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 413
 414         amdgpu_ring_emit_wreg(ring, reg, pasid);
 415 }
 416
 417 /**
 418  * gmc_v9_0_set_pte_pde - update the page tables using MMIO
 419  *
 420  * @adev: amdgpu_device pointer
 421  * @cpu_pt_addr: cpu address of the page table
 422  * @gpu_page_idx: entry in the page table to update
 423  * @addr: dst addr to write into pte/pde
 424  * @flags: access flags
 425  *
 426  * Update the page tables using the CPU.
 427  */
 428 static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 429                                 uint32_t gpu_page_idx, uint64_t addr,
 430                                 uint64_t flags)
 431 {
 432         void __iomem *ptr = (void *)cpu_pt_addr;
 433         uint64_t value;
 434
 435         /*
 436          * PTE format on VEGA 10:
 437          * 63:59 reserved
 438          * 58:57 mtype
 439          * 56 F
 440          * 55 L
 441          * 54 P
 442          * 53 SW
 443          * 52 T
 444          * 50:48 reserved
 445          * 47:12 4k physical page base address
 446          * 11:7 fragment
 447          * 6 write
 448          * 5 read
 449          * 4 exe
 450          * 3 Z
 451          * 2 snooped
 452          * 1 system
 453          * 0 valid
 454          *
 455          * PDE format on VEGA 10:
 456          * 63:59 block fragment size
 457          * 58:55 reserved
 458          * 54 P
 459          * 53:48 reserved
 460          * 47:6 physical base address of PD or PTE
 461          * 5:3 reserved
 462          * 2 C
 463          * 1 system
 464          * 0 valid
 465          */
 466
 467         /*
 468          * The following is for PTE only. GART does not have PDEs.
 469         */
 470         value = addr & 0x0000FFFFFFFFF000ULL;
 471         value |= flags;
 472         writeq(value, ptr + (gpu_page_idx * 8));
 473         return 0;
 474 }
 475
 476 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 477                                                 uint32_t flags)
 478
 479 {
 480         uint64_t pte_flag = 0;
 481
 482         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 483                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 484         if (flags & AMDGPU_VM_PAGE_READABLE)
 485                 pte_flag |= AMDGPU_PTE_READABLE;
 486         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 487                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 488
 489         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 490         case AMDGPU_VM_MTYPE_DEFAULT:
 491                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 492                 break;
 493         case AMDGPU_VM_MTYPE_NC:
 494                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 495                 break;
 496         case AMDGPU_VM_MTYPE_WC:
 497                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
 498                 break;
 499         case AMDGPU_VM_MTYPE_CC:
 500                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
 501                 break;
 502         case AMDGPU_VM_MTYPE_UC:
 503                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
 504                 break;
 505         default:
 506                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 507                 break;
 508         }
 509
 510         if (flags & AMDGPU_VM_PAGE_PRT)
 511                 pte_flag |= AMDGPU_PTE_PRT;
 512
 513         return pte_flag;
 514 }
 515
 516 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 517                                 uint64_t *addr, uint64_t *flags)
 518 {
 519         if (!(*flags & AMDGPU_PDE_PTE))
 520                 *addr = adev->vm_manager.vram_base_offset + *addr -
 521                         adev->gmc.vram_start;
 522         BUG_ON(*addr & 0xFFFF00000000003FULL);
 523
 524         if (!adev->gmc.translate_further)
 525                 return;
 526
 527         if (level == AMDGPU_VM_PDB1) {
 528                 /* Set the block fragment size */
 529                 if (!(*flags & AMDGPU_PDE_PTE))
 530                         *flags |= AMDGPU_PDE_BFS(0x9);
 531
 532         } else if (level == AMDGPU_VM_PDB0) {
 533                 if (*flags & AMDGPU_PDE_PTE)
 534                         *flags &= ~AMDGPU_PDE_PTE;
 535                 else
 536                         *flags |= AMDGPU_PTE_TF;
 537         }
 538 }
 539
 540 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 541         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 542         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 543         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 544         .set_pte_pde = gmc_v9_0_set_pte_pde,
 545         .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 546         .get_vm_pde = gmc_v9_0_get_vm_pde
 547 };
 548
 549 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 550 {
 551         if (adev->gmc.gmc_funcs == NULL)
 552                 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 553 }
 554
 555 static int gmc_v9_0_early_init(void *handle)
 556 {
 557         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 558
 559         gmc_v9_0_set_gmc_funcs(adev);
 560         gmc_v9_0_set_irq_funcs(adev);
 561
 562         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 563         adev->gmc.shared_aperture_end =
 564                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 565         adev->gmc.private_aperture_start =
 566                 adev->gmc.shared_aperture_end + 1;
 567         adev->gmc.private_aperture_end =
 568                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 569
 570         return 0;
 571 }
 572
 573 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
 574 {
 575         uint32_t reg_val;
 576         uint32_t reg_addr;
 577         uint32_t field_val;
 578         size_t i;
 579         uint32_t fv2;
 580         size_t lost_sheep;
 581
 582         DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
 583
 584         lost_sheep = 0;
 585         for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
 586                 reg_addr = ecc_umclocalcap_addrs[i];
 587                 DRM_DEBUG("ecc: "
 588                           "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
 589                           i, reg_addr);
 590                 reg_val = RREG32(reg_addr);
 591                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
 592                                           EccDis);
 593                 DRM_DEBUG("ecc: "
 594                           "reg_val: 0x%08x, "
 595                           "EccDis: 0x%08x, ",
 596                           reg_val, field_val);
 597                 if (field_val) {
 598                         DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
 599                         ++lost_sheep;
 600                 }
 601         }
 602
 603         for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
 604                 reg_addr = ecc_umcch_umc_config_addrs[i];
 605                 DRM_DEBUG("ecc: "
 606                           "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
 607                           i, reg_addr);
 608                 reg_val = RREG32(reg_addr);
 609                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
 610                                           DramReady);
 611                 DRM_DEBUG("ecc: "
 612                           "reg_val: 0x%08x, "
 613                           "DramReady: 0x%08x\n",
 614                           reg_val, field_val);
 615
 616                 if (!field_val) {
 617                         DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
 618                         ++lost_sheep;
 619                 }
 620         }
 621
 622         for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
 623                 reg_addr = ecc_umcch_eccctrl_addrs[i];
 624                 DRM_DEBUG("ecc: "
 625                           "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
 626                           i, reg_addr);
 627                 reg_val = RREG32(reg_addr);
 628                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
 629                                           WrEccEn);
 630                 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
 631                                     RdEccEn);
 632                 DRM_DEBUG("ecc: "
 633                           "reg_val: 0x%08x, "
 634                           "WrEccEn: 0x%08x, "
 635                           "RdEccEn: 0x%08x\n",
 636                           reg_val, field_val, fv2);
 637
 638                 if (!field_val) {
 639                         DRM_DEBUG("ecc: WrEccEn is not set\n");
 640                         ++lost_sheep;
 641                 }
 642                 if (!fv2) {
 643                         DRM_DEBUG("ecc: RdEccEn is not set\n");
 644                         ++lost_sheep;
 645                 }
 646         }
 647
 648         DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
 649         return lost_sheep == 0;
 650 }
 651
 652 static int gmc_v9_0_late_init(void *handle)
 653 {
 654         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 655         /*
 656          * The latest engine allocation on gfx9 is:
 657          * Engine 0, 1: idle
 658          * Engine 2, 3: firmware
 659          * Engine 4~13: amdgpu ring, subject to change when ring number changes
 660          * Engine 14~15: idle
 661          * Engine 16: kfd tlb invalidation
 662          * Engine 17: Gart flushes
 663          */
 664         unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
 665         unsigned i;
 666         int r;
 667
 668         /*
 669          * TODO - Uncomment once GART corruption issue is fixed.
 670          */
 671         /* amdgpu_bo_late_init(adev); */
 672
 673         for(i = 0; i < adev->num_rings; ++i) {
 674                 struct amdgpu_ring *ring = adev->rings[i];
 675                 unsigned vmhub = ring->funcs->vmhub;
 676
 677                 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
 678                 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
 679                          ring->idx, ring->name, ring->vm_inv_eng,
 680                          ring->funcs->vmhub);
 681         }
 682
 683         /* Engine 16 is used for KFD and 17 for GART flushes */
 684         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
 685                 BUG_ON(vm_inv_eng[i] > 16);
 686
 687         if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
 688                 r = gmc_v9_0_ecc_available(adev);
 689                 if (r == 1) {
 690                         DRM_INFO("ECC is active.\n");
 691                 } else if (r == 0) {
 692                         DRM_INFO("ECC is not present.\n");
 693                 } else {
 694                         DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
 695                         return r;
 696                 }
 697         }
 698
 699         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 700 }
 701
 702 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 703                                         struct amdgpu_gmc *mc)
 704 {
 705         u64 base = 0;
 706         if (!amdgpu_sriov_vf(adev))
 707                 base = mmhub_v1_0_get_fb_location(adev);
 708         amdgpu_device_vram_location(adev, &adev->gmc, base);
 709         amdgpu_device_gart_location(adev, mc);
 710         /* base offset of vram pages */
 711         if (adev->flags & AMD_IS_APU)
 712                 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 713         else
 714                 adev->vm_manager.vram_base_offset = 0;
 715 }
 716
 717 /**
 718  * gmc_v9_0_mc_init - initialize the memory controller driver params
 719  *
 720  * @adev: amdgpu_device pointer
 721  *
 722  * Look up the amount of vram, vram width, and decide how to place
 723  * vram and gart within the GPU's physical address space.
 724  * Returns 0 for success.
 725  */
 726 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 727 {
 728         int chansize, numchan;
 729         int r;
 730
 731         if (amdgpu_emu_mode != 1)
 732                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 733         if (!adev->gmc.vram_width) {
 734                 /* hbm memory channel size */
 735                 if (adev->flags & AMD_IS_APU)
 736                         chansize = 64;
 737                 else
 738                         chansize = 128;
 739
 740                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
 741                 adev->gmc.vram_width = numchan * chansize;
 742         }
 743
 744         /* size in MB on si */
 745         adev->gmc.mc_vram_size =
 746                 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 747         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 748
 749         if (!(adev->flags & AMD_IS_APU)) {
 750                 r = amdgpu_device_resize_fb_bar(adev);
 751                 if (r)
 752                         return r;
 753         }
 754         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 755         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 756
 757 #ifdef CONFIG_X86_64
 758         if (adev->flags & AMD_IS_APU) {
 759                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 760                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 761         }
 762 #endif
 763         /* In case the PCI BAR is larger than the actual amount of vram */
 764         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 765         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 766                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 767
 768         /* set the gart size */
 769         if (amdgpu_gart_size == -1) {
 770                 switch (adev->asic_type) {
 771                 case CHIP_VEGA10:  /* all engines support GPUVM */
 772                 case CHIP_VEGA12:  /* all engines support GPUVM */
 773                 default:
 774                         adev->gmc.gart_size = 512ULL << 20;
 775                         break;
 776                 case CHIP_RAVEN:   /* DCE SG support */
 777                         adev->gmc.gart_size = 1024ULL << 20;
 778                         break;
 779                 }
 780         } else {
 781                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 782         }
 783
 784         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 785
 786         return 0;
 787 }
 788
 789 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 790 {
 791         int r;
 792
 793         if (adev->gart.robj) {
 794                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 795                 return 0;
 796         }
 797         /* Initialize common gart structure */
 798         r = amdgpu_gart_init(adev);
 799         if (r)
 800                 return r;
 801         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 802         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
 803                                  AMDGPU_PTE_EXECUTABLE;
 804         return amdgpu_gart_table_vram_alloc(adev);
 805 }
 806
 807 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 808 {
 809 #if 0
 810         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 811 #endif
 812         unsigned size;
 813
 814         /*
 815          * TODO Remove once GART corruption is resolved
 816          * Check related code in gmc_v9_0_sw_fini
 817          * */
 818         size = 9 * 1024 * 1024;
 819
 820 #if 0
 821         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 822                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 823         } else {
 824                 u32 viewport;
 825
 826                 switch (adev->asic_type) {
 827                 case CHIP_RAVEN:
 828                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 829                         size = (REG_GET_FIELD(viewport,
 830                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 831                                 REG_GET_FIELD(viewport,
 832                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
 833                                 4);
 834                         break;
 835                 case CHIP_VEGA10:
 836                 case CHIP_VEGA12:
 837                 default:
 838                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
 839                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 840                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 841                                 4);
 842                         break;
 843                 }
 844         }
 845         /* return 0 if the pre-OS buffer uses up most of vram */
 846         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 847                 return 0;
 848
 849 #endif
 850         return size;
 851 }
 852
 853 static int gmc_v9_0_sw_init(void *handle)
 854 {
 855         int r;
 856         int dma_bits;
 857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 858
 859         gfxhub_v1_0_init(adev);
 860         mmhub_v1_0_init(adev);
 861
 862         spin_lock_init(&adev->gmc.invalidate_lock);
 863
 864         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
 865         switch (adev->asic_type) {
 866         case CHIP_RAVEN:
 867                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
 868                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 869                 } else {
 870                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
 871                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
 872                         adev->gmc.translate_further =
 873                                 adev->vm_manager.num_level > 1;
 874                 }
 875                 break;
 876         case CHIP_VEGA10:
 877         case CHIP_VEGA12:
 878                 /*
 879                  * To fulfill 4-level page support,
 880                  * vm size is 256TB (48bit), maximum size of Vega10,
 881                  * block size 512 (9bit)
 882                  */
 883                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 884                 break;
 885         default:
 886                 break;
 887         }
 888
 889         /* This interrupt is VMC page fault.*/
 890         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,
 891                                 &adev->gmc.vm_fault);
 892         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,
 893                                 &adev->gmc.vm_fault);
 894
 895         if (r)
 896                 return r;
 897
 898         /* Set the internal MC address mask
 899          * This is the max address of the GPU's
 900          * internal address space.
 901          */
 902         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 903
 904         /* set DMA mask + need_dma32 flags.
 905          * PCIE - can handle 44-bits.
 906          * IGP - can handle 44-bits
 907          * PCI - dma32 for legacy pci gart, 44 bits on vega10
 908          */
 909         adev->need_dma32 = false;
 910         dma_bits = adev->need_dma32 ? 32 : 44;
 911         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 912         if (r) {
 913                 adev->need_dma32 = true;
 914                 dma_bits = 32;
 915                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 916         }
 917         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 918         if (r) {
 919                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 920                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 921         }
 922         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 923
 924         r = gmc_v9_0_mc_init(adev);
 925         if (r)
 926                 return r;
 927
 928         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
 929
 930         /* Memory manager */
 931         r = amdgpu_bo_init(adev);
 932         if (r)
 933                 return r;
 934
 935         r = gmc_v9_0_gart_init(adev);
 936         if (r)
 937                 return r;
 938
 939         /*
 940          * number of VMs
 941          * VMID 0 is reserved for System
 942          * amdgpu graphics/compute will use VMIDs 1-7
 943          * amdkfd will use VMIDs 8-15
 944          */
 945         adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 946         adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 947
 948         amdgpu_vm_manager_init(adev);
 949
 950         return 0;
 951 }
 952
 953 /**
 954  * gmc_v9_0_gart_fini - vm fini callback
 955  *
 956  * @adev: amdgpu_device pointer
 957  *
 958  * Tears down the driver GART/VM setup (CIK).
 959  */
 960 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
 961 {
 962         amdgpu_gart_table_vram_free(adev);
 963         amdgpu_gart_fini(adev);
 964 }
 965
 966 static int gmc_v9_0_sw_fini(void *handle)
 967 {
 968         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 969
 970         amdgpu_gem_force_release(adev);
 971         amdgpu_vm_manager_fini(adev);
 972         gmc_v9_0_gart_fini(adev);
 973
 974         /*
 975         * TODO:
 976         * Currently there is a bug where some memory client outside
 977         * of the driver writes to first 8M of VRAM on S3 resume,
 978         * this overrides GART which by default gets placed in first 8M and
 979         * causes VM_FAULTS once GTT is accessed.
 980         * Keep the stolen memory reservation until the while this is not solved.
 981         * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 982         */
 983         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
 984
 985         amdgpu_bo_fini(adev);
 986
 987         return 0;
 988 }
 989
 990 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
 991 {
 992
 993         switch (adev->asic_type) {
 994         case CHIP_VEGA10:
 995                 soc15_program_register_sequence(adev,
 996                                                 golden_settings_mmhub_1_0_0,
 997                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
 998                 soc15_program_register_sequence(adev,
 999                                                 golden_settings_athub_1_0_0,
1000                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1001                 break;
1002         case CHIP_VEGA12:
1003                 break;
1004         case CHIP_RAVEN:
1005                 soc15_program_register_sequence(adev,
1006                                                 golden_settings_athub_1_0_0,
1007                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1008                 break;
1009         default:
1010                 break;
1011         }
1012 }
1013
1014 /**
1015  * gmc_v9_0_gart_enable - gart enable
1016  *
1017  * @adev: amdgpu_device pointer
1018  */
1019 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1020 {
1021         int r;
1022         bool value;
1023         u32 tmp;
1024
1025         amdgpu_device_program_register_sequence(adev,
1026                                                 golden_settings_vega10_hdp,
1027                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1028
1029         if (adev->gart.robj == NULL) {
1030                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1031                 return -EINVAL;
1032         }
1033         r = amdgpu_gart_table_vram_pin(adev);
1034         if (r)
1035                 return r;
1036
1037         switch (adev->asic_type) {
1038         case CHIP_RAVEN:
1039                 mmhub_v1_0_initialize_power_gating(adev);
1040                 mmhub_v1_0_update_power_gating(adev, true);
1041                 break;
1042         default:
1043                 break;
1044         }
1045
1046         r = gfxhub_v1_0_gart_enable(adev);
1047         if (r)
1048                 return r;
1049
1050         r = mmhub_v1_0_gart_enable(adev);
1051         if (r)
1052                 return r;
1053
1054         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1055
1056         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1057         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1058
1059         /* After HDP is initialized, flush HDP.*/
1060         adev->nbio_funcs->hdp_flush(adev, NULL);
1061
1062         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1063                 value = false;
1064         else
1065                 value = true;
1066
1067         gfxhub_v1_0_set_fault_enable_default(adev, value);
1068         mmhub_v1_0_set_fault_enable_default(adev, value);
1069         gmc_v9_0_flush_gpu_tlb(adev, 0);
1070
1071         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1072                  (unsigned)(adev->gmc.gart_size >> 20),
1073                  (unsigned long long)adev->gart.table_addr);
1074         adev->gart.ready = true;
1075         return 0;
1076 }
1077
1078 static int gmc_v9_0_hw_init(void *handle)
1079 {
1080         int r;
1081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082
1083         /* The sequence of these two function calls matters.*/
1084         gmc_v9_0_init_golden_registers(adev);
1085
1086         if (adev->mode_info.num_crtc) {
1087                 /* Lockout access through VGA aperture*/
1088                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1089
1090                 /* disable VGA render */
1091                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1092         }
1093
1094         r = gmc_v9_0_gart_enable(adev);
1095
1096         return r;
1097 }
1098
1099 /**
1100  * gmc_v9_0_gart_disable - gart disable
1101  *
1102  * @adev: amdgpu_device pointer
1103  *
1104  * This disables all VM page table.
1105  */
1106 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1107 {
1108         gfxhub_v1_0_gart_disable(adev);
1109         mmhub_v1_0_gart_disable(adev);
1110         amdgpu_gart_table_vram_unpin(adev);
1111 }
1112
1113 static int gmc_v9_0_hw_fini(void *handle)
1114 {
1115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1116
1117         if (amdgpu_sriov_vf(adev)) {
1118                 /* full access mode, so don't touch any GMC register */
1119                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1120                 return 0;
1121         }
1122
1123         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1124         gmc_v9_0_gart_disable(adev);
1125
1126         return 0;
1127 }
1128
1129 static int gmc_v9_0_suspend(void *handle)
1130 {
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133         return gmc_v9_0_hw_fini(adev);
1134 }
1135
1136 static int gmc_v9_0_resume(void *handle)
1137 {
1138         int r;
1139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140
1141         r = gmc_v9_0_hw_init(adev);
1142         if (r)
1143                 return r;
1144
1145         amdgpu_vmid_reset_all(adev);
1146
1147         return 0;
1148 }
1149
1150 static bool gmc_v9_0_is_idle(void *handle)
1151 {
1152         /* MC is always ready in GMC v9.*/
1153         return true;
1154 }
1155
1156 static int gmc_v9_0_wait_for_idle(void *handle)
1157 {
1158         /* There is no need to wait for MC idle in GMC v9.*/
1159         return 0;
1160 }
1161
1162 static int gmc_v9_0_soft_reset(void *handle)
1163 {
1164         /* XXX for emulation.*/
1165         return 0;
1166 }
1167
1168 static int gmc_v9_0_set_clockgating_state(void *handle,
1169                                         enum amd_clockgating_state state)
1170 {
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
1173         return mmhub_v1_0_set_clockgating(adev, state);
1174 }
1175
1176 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1177 {
1178         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1179
1180         mmhub_v1_0_get_clockgating(adev, flags);
1181 }
1182
1183 static int gmc_v9_0_set_powergating_state(void *handle,
1184                                         enum amd_powergating_state state)
1185 {
1186         return 0;
1187 }
1188
1189 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1190         .name = "gmc_v9_0",
1191         .early_init = gmc_v9_0_early_init,
1192         .late_init = gmc_v9_0_late_init,
1193         .sw_init = gmc_v9_0_sw_init,
1194         .sw_fini = gmc_v9_0_sw_fini,
1195         .hw_init = gmc_v9_0_hw_init,
1196         .hw_fini = gmc_v9_0_hw_fini,
1197         .suspend = gmc_v9_0_suspend,
1198         .resume = gmc_v9_0_resume,
1199         .is_idle = gmc_v9_0_is_idle,
1200         .wait_for_idle = gmc_v9_0_wait_for_idle,
1201         .soft_reset = gmc_v9_0_soft_reset,
1202         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1203         .set_powergating_state = gmc_v9_0_set_powergating_state,
1204         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1205 };
1206
1207 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1208 {
1209         .type = AMD_IP_BLOCK_TYPE_GMC,
1210         .major = 9,
1211         .minor = 0,
1212         .rev = 0,
1213         .funcs = &gmc_v9_0_ip_funcs,
1214 };