drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         if (bo->gem_base.import_attach)
  64                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->gem_base);
  66         amdgpu_bo_unref(&bo->parent);
  67         if (!list_empty(&bo->shadow_list)) {
  68                 mutex_lock(&adev->shadow_list_lock);
  69                 list_del_init(&bo->shadow_list);
  70                 mutex_unlock(&adev->shadow_list_lock);
  71         }
  72         kfree(bo->metadata);
  73         kfree(bo);
  74 }
  75
  76 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  77 {
  78         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  79                 return true;
  80         return false;
  81 }
  82
  83 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  84 {
  85         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  86         struct ttm_placement *placement = &abo->placement;
  87         struct ttm_place *places = abo->placements;
  88         u64 flags = abo->flags;
  89         u32 c = 0;
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  92                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  93
  94                 places[c].fpfn = 0;
  95                 places[c].lpfn = 0;
  96                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  97                         TTM_PL_FLAG_VRAM;
  98
  99                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 100                         places[c].lpfn = visible_pfn;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 103
 104                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 105                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 110                 places[c].fpfn = 0;
 111                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 112                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 113                 else
 114                         places[c].lpfn = 0;
 115                 places[c].flags = TTM_PL_FLAG_TT;
 116                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 117                         places[c].flags |= TTM_PL_FLAG_WC |
 118                                 TTM_PL_FLAG_UNCACHED;
 119                 else
 120                         places[c].flags |= TTM_PL_FLAG_CACHED;
 121                 c++;
 122         }
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 125                 places[c].fpfn = 0;
 126                 places[c].lpfn = 0;
 127                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 128                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 129                         places[c].flags |= TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED;
 131                 else
 132                         places[c].flags |= TTM_PL_FLAG_CACHED;
 133                 c++;
 134         }
 135
 136         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 137                 places[c].fpfn = 0;
 138                 places[c].lpfn = 0;
 139                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 140                 c++;
 141         }
 142
 143         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 144                 places[c].fpfn = 0;
 145                 places[c].lpfn = 0;
 146                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 147                 c++;
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 151                 places[c].fpfn = 0;
 152                 places[c].lpfn = 0;
 153                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 154                 c++;
 155         }
 156
 157         if (!c) {
 158                 places[c].fpfn = 0;
 159                 places[c].lpfn = 0;
 160                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 161                 c++;
 162         }
 163
 164         placement->num_placement = c;
 165         placement->placement = places;
 166
 167         placement->num_busy_placement = c;
 168         placement->busy_placement = places;
 169 }
 170
 171 /**
 172  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 173  *
 174  * @adev: amdgpu device object
 175  * @size: size for the new BO
 176  * @align: alignment for the new BO
 177  * @domain: where to place it
 178  * @bo_ptr: used to initialize BOs in structures
 179  * @gpu_addr: GPU addr of the pinned BO
 180  * @cpu_addr: optional CPU address mapping
 181  *
 182  * Allocates and pins a BO for kernel internal use, and returns it still
 183  * reserved.
 184  *
 185  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 186  *
 187  * Returns 0 on success, negative error code otherwise.
 188  */
 189 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 190                               unsigned long size, int align,
 191                               u32 domain, struct amdgpu_bo **bo_ptr,
 192                               u64 *gpu_addr, void **cpu_addr)
 193 {
 194         bool free = false;
 195         int r;
 196
 197         if (!*bo_ptr) {
 198                 r = amdgpu_bo_create(adev, size, align, domain,
 199                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 200                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 201                                      ttm_bo_type_kernel, NULL, bo_ptr);
 202                 if (r) {
 203                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 204                                 r);
 205                         return r;
 206                 }
 207                 free = true;
 208         }
 209
 210         r = amdgpu_bo_reserve(*bo_ptr, false);
 211         if (r) {
 212                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 213                 goto error_free;
 214         }
 215
 216         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 217         if (r) {
 218                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 219                 goto error_unreserve;
 220         }
 221
 222         if (cpu_addr) {
 223                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 224                 if (r) {
 225                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 226                         goto error_unreserve;
 227                 }
 228         }
 229
 230         return 0;
 231
 232 error_unreserve:
 233         amdgpu_bo_unreserve(*bo_ptr);
 234
 235 error_free:
 236         if (free)
 237                 amdgpu_bo_unref(bo_ptr);
 238
 239         return r;
 240 }
 241
 242 /**
 243  * amdgpu_bo_create_kernel - create BO for kernel use
 244  *
 245  * @adev: amdgpu device object
 246  * @size: size for the new BO
 247  * @align: alignment for the new BO
 248  * @domain: where to place it
 249  * @bo_ptr:  used to initialize BOs in structures
 250  * @gpu_addr: GPU addr of the pinned BO
 251  * @cpu_addr: optional CPU address mapping
 252  *
 253  * Allocates and pins a BO for kernel internal use.
 254  *
 255  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 256  *
 257  * Returns 0 on success, negative error code otherwise.
 258  */
 259 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 260                             unsigned long size, int align,
 261                             u32 domain, struct amdgpu_bo **bo_ptr,
 262                             u64 *gpu_addr, void **cpu_addr)
 263 {
 264         int r;
 265
 266         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 267                                       gpu_addr, cpu_addr);
 268
 269         if (r)
 270                 return r;
 271
 272         amdgpu_bo_unreserve(*bo_ptr);
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * amdgpu_bo_free_kernel - free BO for kernel use
 279  *
 280  * @bo: amdgpu BO to free
 281  *
 282  * unmaps and unpin a BO for kernel internal use.
 283  */
 284 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 285                            void **cpu_addr)
 286 {
 287         if (*bo == NULL)
 288                 return;
 289
 290         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 291                 if (cpu_addr)
 292                         amdgpu_bo_kunmap(*bo);
 293
 294                 amdgpu_bo_unpin(*bo);
 295                 amdgpu_bo_unreserve(*bo);
 296         }
 297         amdgpu_bo_unref(bo);
 298
 299         if (gpu_addr)
 300                 *gpu_addr = 0;
 301
 302         if (cpu_addr)
 303                 *cpu_addr = NULL;
 304 }
 305
 306 /* Validate bo size is bit bigger then the request domain */
 307 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 308                                           unsigned long size, u32 domain)
 309 {
 310         struct ttm_mem_type_manager *man = NULL;
 311
 312         /*
 313          * If GTT is part of requested domains the check must succeed to
 314          * allow fall back to GTT
 315          */
 316         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 317                 man = &adev->mman.bdev.man[TTM_PL_TT];
 318
 319                 if (size < (man->size << PAGE_SHIFT))
 320                         return true;
 321                 else
 322                         goto fail;
 323         }
 324
 325         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 326                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 327
 328                 if (size < (man->size << PAGE_SHIFT))
 329                         return true;
 330                 else
 331                         goto fail;
 332         }
 333
 334
 335         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 336         return true;
 337
 338 fail:
 339         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 340                   man->size << PAGE_SHIFT);
 341         return false;
 342 }
 343
 344 static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
 345                                int byte_align, u32 domain,
 346                                u64 flags, enum ttm_bo_type type,
 347                                struct reservation_object *resv,
 348                                struct amdgpu_bo **bo_ptr)
 349 {
 350         struct ttm_operation_ctx ctx = {
 351                 .interruptible = (type != ttm_bo_type_kernel),
 352                 .no_wait_gpu = false,
 353                 .resv = resv,
 354                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 355         };
 356         struct amdgpu_bo *bo;
 357         unsigned long page_align;
 358         size_t acc_size;
 359         u32 domains, preferred_domains, allowed_domains;
 360         int r;
 361
 362         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 363         size = ALIGN(size, PAGE_SIZE);
 364
 365         if (!amdgpu_bo_validate_size(adev, size, domain))
 366                 return -ENOMEM;
 367
 368         *bo_ptr = NULL;
 369
 370         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 371                                        sizeof(struct amdgpu_bo));
 372
 373         preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 374                                       AMDGPU_GEM_DOMAIN_GTT |
 375                                       AMDGPU_GEM_DOMAIN_CPU |
 376                                       AMDGPU_GEM_DOMAIN_GDS |
 377                                       AMDGPU_GEM_DOMAIN_GWS |
 378                                       AMDGPU_GEM_DOMAIN_OA);
 379         allowed_domains = preferred_domains;
 380         if (type != ttm_bo_type_kernel &&
 381             allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 382                 allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 383         domains = preferred_domains;
 384 retry:
 385         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 386         if (bo == NULL)
 387                 return -ENOMEM;
 388         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 389         INIT_LIST_HEAD(&bo->shadow_list);
 390         INIT_LIST_HEAD(&bo->va);
 391         bo->preferred_domains = preferred_domains;
 392         bo->allowed_domains = allowed_domains;
 393
 394         bo->flags = flags;
 395
 396 #ifdef CONFIG_X86_32
 397         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 398          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 399          */
 400         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 401 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 402         /* Don't try to enable write-combining when it can't work, or things
 403          * may be slow
 404          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 405          */
 406
 407 #ifndef CONFIG_COMPILE_TEST
 408 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 409          thanks to write-combining
 410 #endif
 411
 412         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 413                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 414                               "better performance thanks to write-combining\n");
 415         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 416 #else
 417         /* For architectures that don't support WC memory,
 418          * mask out the WC flag from the BO
 419          */
 420         if (!drm_arch_can_wc_memory())
 421                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 422 #endif
 423
 424         bo->tbo.bdev = &adev->mman.bdev;
 425         amdgpu_ttm_placement_from_domain(bo, domains);
 426         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 427                                  &bo->placement, page_align, &ctx, acc_size,
 428                                  NULL, resv, &amdgpu_ttm_bo_destroy);
 429         if (unlikely(r && r != -ERESTARTSYS) && type == ttm_bo_type_device &&
 430             !(flags & AMDGPU_GEM_CREATE_NO_FALLBACK)) {
 431                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 432                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 433                         goto retry;
 434                 } else if (domains != allowed_domains) {
 435                         domains = allowed_domains;
 436                         goto retry;
 437                 }
 438         }
 439         if (unlikely(r))
 440                 return r;
 441
 442         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 443             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 444             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 445                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 446                                              ctx.bytes_moved);
 447         else
 448                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 449
 450         if (type == ttm_bo_type_kernel)
 451                 bo->tbo.priority = 1;
 452
 453         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 454             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 455                 struct dma_fence *fence;
 456
 457                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 458                 if (unlikely(r))
 459                         goto fail_unreserve;
 460
 461                 amdgpu_bo_fence(bo, fence, false);
 462                 dma_fence_put(bo->tbo.moving);
 463                 bo->tbo.moving = dma_fence_get(fence);
 464                 dma_fence_put(fence);
 465         }
 466         if (!resv)
 467                 amdgpu_bo_unreserve(bo);
 468         *bo_ptr = bo;
 469
 470         trace_amdgpu_bo_create(bo);
 471
 472         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 473         if (type == ttm_bo_type_device)
 474                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 475
 476         return 0;
 477
 478 fail_unreserve:
 479         if (!resv)
 480                 ww_mutex_unlock(&bo->tbo.resv->lock);
 481         amdgpu_bo_unref(&bo);
 482         return r;
 483 }
 484
 485 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 486                                    unsigned long size, int byte_align,
 487                                    struct amdgpu_bo *bo)
 488 {
 489         int r;
 490
 491         if (bo->shadow)
 492                 return 0;
 493
 494         r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
 495                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 496                                 AMDGPU_GEM_CREATE_SHADOW,
 497                                 ttm_bo_type_kernel,
 498                                 bo->tbo.resv, &bo->shadow);
 499         if (!r) {
 500                 bo->shadow->parent = amdgpu_bo_ref(bo);
 501                 mutex_lock(&adev->shadow_list_lock);
 502                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 503                 mutex_unlock(&adev->shadow_list_lock);
 504         }
 505
 506         return r;
 507 }
 508
 509 int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
 510                      int byte_align, u32 domain,
 511                      u64 flags, enum ttm_bo_type type,
 512                      struct reservation_object *resv,
 513                      struct amdgpu_bo **bo_ptr)
 514 {
 515         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 516         int r;
 517
 518         r = amdgpu_bo_do_create(adev, size, byte_align, domain,
 519                                 parent_flags, type, resv, bo_ptr);
 520         if (r)
 521                 return r;
 522
 523         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 524                 if (!resv)
 525                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 526                                                         NULL));
 527
 528                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 529
 530                 if (!resv)
 531                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 532
 533                 if (r)
 534                         amdgpu_bo_unref(bo_ptr);
 535         }
 536
 537         return r;
 538 }
 539
 540 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 541                                struct amdgpu_ring *ring,
 542                                struct amdgpu_bo *bo,
 543                                struct reservation_object *resv,
 544                                struct dma_fence **fence,
 545                                bool direct)
 546
 547 {
 548         struct amdgpu_bo *shadow = bo->shadow;
 549         uint64_t bo_addr, shadow_addr;
 550         int r;
 551
 552         if (!shadow)
 553                 return -EINVAL;
 554
 555         bo_addr = amdgpu_bo_gpu_offset(bo);
 556         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 557
 558         r = reservation_object_reserve_shared(bo->tbo.resv);
 559         if (r)
 560                 goto err;
 561
 562         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 563                                amdgpu_bo_size(bo), resv, fence,
 564                                direct, false);
 565         if (!r)
 566                 amdgpu_bo_fence(bo, *fence, true);
 567
 568 err:
 569         return r;
 570 }
 571
 572 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 573 {
 574         struct ttm_operation_ctx ctx = { false, false };
 575         uint32_t domain;
 576         int r;
 577
 578         if (bo->pin_count)
 579                 return 0;
 580
 581         domain = bo->preferred_domains;
 582
 583 retry:
 584         amdgpu_ttm_placement_from_domain(bo, domain);
 585         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 586         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 587                 domain = bo->allowed_domains;
 588                 goto retry;
 589         }
 590
 591         return r;
 592 }
 593
 594 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 595                                   struct amdgpu_ring *ring,
 596                                   struct amdgpu_bo *bo,
 597                                   struct reservation_object *resv,
 598                                   struct dma_fence **fence,
 599                                   bool direct)
 600
 601 {
 602         struct amdgpu_bo *shadow = bo->shadow;
 603         uint64_t bo_addr, shadow_addr;
 604         int r;
 605
 606         if (!shadow)
 607                 return -EINVAL;
 608
 609         bo_addr = amdgpu_bo_gpu_offset(bo);
 610         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 611
 612         r = reservation_object_reserve_shared(bo->tbo.resv);
 613         if (r)
 614                 goto err;
 615
 616         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 617                                amdgpu_bo_size(bo), resv, fence,
 618                                direct, false);
 619         if (!r)
 620                 amdgpu_bo_fence(bo, *fence, true);
 621
 622 err:
 623         return r;
 624 }
 625
 626 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 627 {
 628         void *kptr;
 629         long r;
 630
 631         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 632                 return -EPERM;
 633
 634         kptr = amdgpu_bo_kptr(bo);
 635         if (kptr) {
 636                 if (ptr)
 637                         *ptr = kptr;
 638                 return 0;
 639         }
 640
 641         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 642                                                 MAX_SCHEDULE_TIMEOUT);
 643         if (r < 0)
 644                 return r;
 645
 646         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 647         if (r)
 648                 return r;
 649
 650         if (ptr)
 651                 *ptr = amdgpu_bo_kptr(bo);
 652
 653         return 0;
 654 }
 655
 656 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 657 {
 658         bool is_iomem;
 659
 660         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 661 }
 662
 663 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 664 {
 665         if (bo->kmap.bo)
 666                 ttm_bo_kunmap(&bo->kmap);
 667 }
 668
 669 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 670 {
 671         if (bo == NULL)
 672                 return NULL;
 673
 674         ttm_bo_reference(&bo->tbo);
 675         return bo;
 676 }
 677
 678 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 679 {
 680         struct ttm_buffer_object *tbo;
 681
 682         if ((*bo) == NULL)
 683                 return;
 684
 685         tbo = &((*bo)->tbo);
 686         ttm_bo_unref(&tbo);
 687         if (tbo == NULL)
 688                 *bo = NULL;
 689 }
 690
 691 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 692                              u64 min_offset, u64 max_offset,
 693                              u64 *gpu_addr)
 694 {
 695         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 696         struct ttm_operation_ctx ctx = { false, false };
 697         int r, i;
 698
 699         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 700                 return -EPERM;
 701
 702         if (WARN_ON_ONCE(min_offset > max_offset))
 703                 return -EINVAL;
 704
 705         /* A shared bo cannot be migrated to VRAM */
 706         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 707                 return -EINVAL;
 708
 709         if (bo->pin_count) {
 710                 uint32_t mem_type = bo->tbo.mem.mem_type;
 711
 712                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 713                         return -EINVAL;
 714
 715                 bo->pin_count++;
 716                 if (gpu_addr)
 717                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 718
 719                 if (max_offset != 0) {
 720                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 721                         WARN_ON_ONCE(max_offset <
 722                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 723                 }
 724
 725                 return 0;
 726         }
 727
 728         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 729         /* force to pin into visible video ram */
 730         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 731                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 732         amdgpu_ttm_placement_from_domain(bo, domain);
 733         for (i = 0; i < bo->placement.num_placement; i++) {
 734                 unsigned fpfn, lpfn;
 735
 736                 fpfn = min_offset >> PAGE_SHIFT;
 737                 lpfn = max_offset >> PAGE_SHIFT;
 738
 739                 if (fpfn > bo->placements[i].fpfn)
 740                         bo->placements[i].fpfn = fpfn;
 741                 if (!bo->placements[i].lpfn ||
 742                     (lpfn && lpfn < bo->placements[i].lpfn))
 743                         bo->placements[i].lpfn = lpfn;
 744                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 745         }
 746
 747         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 748         if (unlikely(r)) {
 749                 dev_err(adev->dev, "%p pin failed\n", bo);
 750                 goto error;
 751         }
 752
 753         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 754         if (unlikely(r)) {
 755                 dev_err(adev->dev, "%p bind failed\n", bo);
 756                 goto error;
 757         }
 758
 759         bo->pin_count = 1;
 760         if (gpu_addr != NULL)
 761                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 762
 763         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 764         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 765                 adev->vram_pin_size += amdgpu_bo_size(bo);
 766                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 767                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 768         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 769                 adev->gart_pin_size += amdgpu_bo_size(bo);
 770         }
 771
 772 error:
 773         return r;
 774 }
 775
 776 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 777 {
 778         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 779 }
 780
 781 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 782 {
 783         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 784         struct ttm_operation_ctx ctx = { false, false };
 785         int r, i;
 786
 787         if (!bo->pin_count) {
 788                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 789                 return 0;
 790         }
 791         bo->pin_count--;
 792         if (bo->pin_count)
 793                 return 0;
 794         for (i = 0; i < bo->placement.num_placement; i++) {
 795                 bo->placements[i].lpfn = 0;
 796                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 797         }
 798         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 799         if (unlikely(r)) {
 800                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 801                 goto error;
 802         }
 803
 804         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 805                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 806                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 807                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 808         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 809                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 810         }
 811
 812 error:
 813         return r;
 814 }
 815
 816 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 817 {
 818         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 819         if (0 && (adev->flags & AMD_IS_APU)) {
 820                 /* Useless to evict on IGP chips */
 821                 return 0;
 822         }
 823         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 824 }
 825
 826 static const char *amdgpu_vram_names[] = {
 827         "UNKNOWN",
 828         "GDDR1",
 829         "DDR2",
 830         "GDDR3",
 831         "GDDR4",
 832         "GDDR5",
 833         "HBM",
 834         "DDR3",
 835         "DDR4",
 836 };
 837
 838 int amdgpu_bo_init(struct amdgpu_device *adev)
 839 {
 840         /* reserve PAT memory space to WC for VRAM */
 841         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 842                                    adev->gmc.aper_size);
 843
 844         /* Add an MTRR for the VRAM */
 845         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 846                                               adev->gmc.aper_size);
 847         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 848                  adev->gmc.mc_vram_size >> 20,
 849                  (unsigned long long)adev->gmc.aper_size >> 20);
 850         DRM_INFO("RAM width %dbits %s\n",
 851                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 852         return amdgpu_ttm_init(adev);
 853 }
 854
 855 int amdgpu_bo_late_init(struct amdgpu_device *adev)
 856 {
 857         amdgpu_ttm_late_init(adev);
 858
 859         return 0;
 860 }
 861
 862 void amdgpu_bo_fini(struct amdgpu_device *adev)
 863 {
 864         amdgpu_ttm_fini(adev);
 865         arch_phys_wc_del(adev->gmc.vram_mtrr);
 866         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 867 }
 868
 869 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 870                              struct vm_area_struct *vma)
 871 {
 872         return ttm_fbdev_mmap(vma, &bo->tbo);
 873 }
 874
 875 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 876 {
 877         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 878
 879         if (adev->family <= AMDGPU_FAMILY_CZ &&
 880             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 881                 return -EINVAL;
 882
 883         bo->tiling_flags = tiling_flags;
 884         return 0;
 885 }
 886
 887 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 888 {
 889         lockdep_assert_held(&bo->tbo.resv->lock.base);
 890
 891         if (tiling_flags)
 892                 *tiling_flags = bo->tiling_flags;
 893 }
 894
 895 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 896                             uint32_t metadata_size, uint64_t flags)
 897 {
 898         void *buffer;
 899
 900         if (!metadata_size) {
 901                 if (bo->metadata_size) {
 902                         kfree(bo->metadata);
 903                         bo->metadata = NULL;
 904                         bo->metadata_size = 0;
 905                 }
 906                 return 0;
 907         }
 908
 909         if (metadata == NULL)
 910                 return -EINVAL;
 911
 912         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 913         if (buffer == NULL)
 914                 return -ENOMEM;
 915
 916         kfree(bo->metadata);
 917         bo->metadata_flags = flags;
 918         bo->metadata = buffer;
 919         bo->metadata_size = metadata_size;
 920
 921         return 0;
 922 }
 923
 924 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 925                            size_t buffer_size, uint32_t *metadata_size,
 926                            uint64_t *flags)
 927 {
 928         if (!buffer && !metadata_size)
 929                 return -EINVAL;
 930
 931         if (buffer) {
 932                 if (buffer_size < bo->metadata_size)
 933                         return -EINVAL;
 934
 935                 if (bo->metadata_size)
 936                         memcpy(buffer, bo->metadata, bo->metadata_size);
 937         }
 938
 939         if (metadata_size)
 940                 *metadata_size = bo->metadata_size;
 941         if (flags)
 942                 *flags = bo->metadata_flags;
 943
 944         return 0;
 945 }
 946
 947 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 948                            bool evict,
 949                            struct ttm_mem_reg *new_mem)
 950 {
 951         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 952         struct amdgpu_bo *abo;
 953         struct ttm_mem_reg *old_mem = &bo->mem;
 954
 955         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 956                 return;
 957
 958         abo = ttm_to_amdgpu_bo(bo);
 959         amdgpu_vm_bo_invalidate(adev, abo, evict);
 960
 961         amdgpu_bo_kunmap(abo);
 962
 963         /* remember the eviction */
 964         if (evict)
 965                 atomic64_inc(&adev->num_evictions);
 966
 967         /* update statistics */
 968         if (!new_mem)
 969                 return;
 970
 971         /* move_notify is called before move happens */
 972         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 973 }
 974
 975 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 976 {
 977         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 978         struct ttm_operation_ctx ctx = { false, false };
 979         struct amdgpu_bo *abo;
 980         unsigned long offset, size;
 981         int r;
 982
 983         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 984                 return 0;
 985
 986         abo = ttm_to_amdgpu_bo(bo);
 987
 988         /* Remember that this BO was accessed by the CPU */
 989         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 990
 991         if (bo->mem.mem_type != TTM_PL_VRAM)
 992                 return 0;
 993
 994         size = bo->mem.num_pages << PAGE_SHIFT;
 995         offset = bo->mem.start << PAGE_SHIFT;
 996         if ((offset + size) <= adev->gmc.visible_vram_size)
 997                 return 0;
 998
 999         /* Can't move a pinned BO to visible VRAM */
1000         if (abo->pin_count > 0)
1001                 return -EINVAL;
1002
1003         /* hurrah the memory is not visible ! */
1004         atomic64_inc(&adev->num_vram_cpu_page_faults);
1005         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1006                                          AMDGPU_GEM_DOMAIN_GTT);
1007
1008         /* Avoid costly evictions; only set GTT as a busy placement */
1009         abo->placement.num_busy_placement = 1;
1010         abo->placement.busy_placement = &abo->placements[1];
1011
1012         r = ttm_bo_validate(bo, &abo->placement, &ctx);
1013         if (unlikely(r != 0))
1014                 return r;
1015
1016         offset = bo->mem.start << PAGE_SHIFT;
1017         /* this should never happen */
1018         if (bo->mem.mem_type == TTM_PL_VRAM &&
1019             (offset + size) > adev->gmc.visible_vram_size)
1020                 return -EINVAL;
1021
1022         return 0;
1023 }
1024
1025 /**
1026  * amdgpu_bo_fence - add fence to buffer object
1027  *
1028  * @bo: buffer object in question
1029  * @fence: fence to add
1030  * @shared: true if fence should be added shared
1031  *
1032  */
1033 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1034                      bool shared)
1035 {
1036         struct reservation_object *resv = bo->tbo.resv;
1037
1038         if (shared)
1039                 reservation_object_add_shared_fence(resv, fence);
1040         else
1041                 reservation_object_add_excl_fence(resv, fence);
1042 }
1043
1044 /**
1045  * amdgpu_bo_gpu_offset - return GPU offset of bo
1046  * @bo: amdgpu object for which we query the offset
1047  *
1048  * Returns current GPU offset of the object.
1049  *
1050  * Note: object should either be pinned or reserved when calling this
1051  * function, it might be useful to add check for this for debugging.
1052  */
1053 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1054 {
1055         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1056         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1057                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1058         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1059                      !bo->pin_count);
1060         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1061         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1062                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1063
1064         return bo->tbo.offset;
1065 }