drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41 #include "amdgpu_atombios.h"
  42
  43
  44 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  45 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int gmc_v8_0_wait_for_idle(void *handle);
  47
  48 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  50 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  52
  53 static const u32 golden_settings_tonga_a11[] =
  54 {
  55         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  56         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  57         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  58         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  60         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  61         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62 };
  63
  64 static const u32 tonga_mgcg_cgcg_init[] =
  65 {
  66         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  67 };
  68
  69 static const u32 golden_settings_fiji_a10[] =
  70 {
  71         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  73         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  74         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75 };
  76
  77 static const u32 fiji_mgcg_cgcg_init[] =
  78 {
  79         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  80 };
  81
  82 static const u32 golden_settings_polaris11_a11[] =
  83 {
  84         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  86         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  87         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  88 };
  89
  90 static const u32 golden_settings_polaris10_a11[] =
  91 {
  92         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  93         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  95         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  96         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  97 };
  98
  99 static const u32 cz_mgcg_cgcg_init[] =
 100 {
 101         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 102 };
 103
 104 static const u32 stoney_mgcg_cgcg_init[] =
 105 {
 106         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 107         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 108 };
 109
 110 static const u32 golden_settings_stoney_common[] =
 111 {
 112         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 113         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 114 };
 115
 116 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 117 {
 118         switch (adev->asic_type) {
 119         case CHIP_FIJI:
 120                 amdgpu_program_register_sequence(adev,
 121                                                  fiji_mgcg_cgcg_init,
 122                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 123                 amdgpu_program_register_sequence(adev,
 124                                                  golden_settings_fiji_a10,
 125                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 126                 break;
 127         case CHIP_TONGA:
 128                 amdgpu_program_register_sequence(adev,
 129                                                  tonga_mgcg_cgcg_init,
 130                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 131                 amdgpu_program_register_sequence(adev,
 132                                                  golden_settings_tonga_a11,
 133                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 134                 break;
 135         case CHIP_POLARIS11:
 136         case CHIP_POLARIS12:
 137                 amdgpu_program_register_sequence(adev,
 138                                                  golden_settings_polaris11_a11,
 139                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 140                 break;
 141         case CHIP_POLARIS10:
 142                 amdgpu_program_register_sequence(adev,
 143                                                  golden_settings_polaris10_a11,
 144                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 145                 break;
 146         case CHIP_CARRIZO:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  cz_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 150                 break;
 151         case CHIP_STONEY:
 152                 amdgpu_program_register_sequence(adev,
 153                                                  stoney_mgcg_cgcg_init,
 154                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 155                 amdgpu_program_register_sequence(adev,
 156                                                  golden_settings_stoney_common,
 157                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 158                 break;
 159         default:
 160                 break;
 161         }
 162 }
 163
 164 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 165 {
 166         u32 blackout;
 167
 168         gmc_v8_0_wait_for_idle(adev);
 169
 170         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 171         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 172                 /* Block CPU access */
 173                 WREG32(mmBIF_FB_EN, 0);
 174                 /* blackout the MC */
 175                 blackout = REG_SET_FIELD(blackout,
 176                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 177                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 178         }
 179         /* wait for the MC to settle */
 180         udelay(100);
 181 }
 182
 183 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 184 {
 185         u32 tmp;
 186
 187         /* unblackout the MC */
 188         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 189         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 190         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 191         /* allow CPU access */
 192         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 193         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 194         WREG32(mmBIF_FB_EN, tmp);
 195 }
 196
 197 /**
 198  * gmc_v8_0_init_microcode - load ucode images from disk
 199  *
 200  * @adev: amdgpu_device pointer
 201  *
 202  * Use the firmware interface to load the ucode images into
 203  * the driver (not loaded into hw).
 204  * Returns 0 on success, error on failure.
 205  */
 206 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 207 {
 208         const char *chip_name;
 209         char fw_name[30];
 210         int err;
 211
 212         DRM_DEBUG("\n");
 213
 214         switch (adev->asic_type) {
 215         case CHIP_TONGA:
 216                 chip_name = "tonga";
 217                 break;
 218         case CHIP_POLARIS11:
 219                 chip_name = "polaris11";
 220                 break;
 221         case CHIP_POLARIS10:
 222                 chip_name = "polaris10";
 223                 break;
 224         case CHIP_POLARIS12:
 225                 chip_name = "polaris12";
 226                 break;
 227         case CHIP_FIJI:
 228         case CHIP_CARRIZO:
 229         case CHIP_STONEY:
 230                 return 0;
 231         default: BUG();
 232         }
 233
 234         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 235         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 236         if (err)
 237                 goto out;
 238         err = amdgpu_ucode_validate(adev->mc.fw);
 239
 240 out:
 241         if (err) {
 242                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 243                 release_firmware(adev->mc.fw);
 244                 adev->mc.fw = NULL;
 245         }
 246         return err;
 247 }
 248
 249 /**
 250  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 251  *
 252  * @adev: amdgpu_device pointer
 253  *
 254  * Load the GDDR MC ucode into the hw (CIK).
 255  * Returns 0 on success, error on failure.
 256  */
 257 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 258 {
 259         const struct mc_firmware_header_v1_0 *hdr;
 260         const __le32 *fw_data = NULL;
 261         const __le32 *io_mc_regs = NULL;
 262         u32 running;
 263         int i, ucode_size, regs_size;
 264
 265         /* Skip MC ucode loading on SR-IOV capable boards.
 266          * vbios does this for us in asic_init in that case.
 267          * Skip MC ucode loading on VF, because hypervisor will do that
 268          * for this adaptor.
 269          */
 270         if (amdgpu_sriov_bios(adev))
 271                 return 0;
 272
 273         if (!adev->mc.fw)
 274                 return -EINVAL;
 275
 276         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 277         amdgpu_ucode_print_mc_hdr(&hdr->header);
 278
 279         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 280         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 281         io_mc_regs = (const __le32 *)
 282                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 283         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 284         fw_data = (const __le32 *)
 285                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 286
 287         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 288
 289         if (running == 0) {
 290                 /* reset the engine and set to writable */
 291                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 292                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 293
 294                 /* load mc io regs */
 295                 for (i = 0; i < regs_size; i++) {
 296                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 297                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 298                 }
 299                 /* load the MC ucode */
 300                 for (i = 0; i < ucode_size; i++)
 301                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 302
 303                 /* put the engine back into the active state */
 304                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 305                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 306                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 307
 308                 /* wait for training to complete */
 309                 for (i = 0; i < adev->usec_timeout; i++) {
 310                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 311                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 312                                 break;
 313                         udelay(1);
 314                 }
 315                 for (i = 0; i < adev->usec_timeout; i++) {
 316                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 317                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 318                                 break;
 319                         udelay(1);
 320                 }
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 327 {
 328         const struct mc_firmware_header_v1_0 *hdr;
 329         const __le32 *fw_data = NULL;
 330         const __le32 *io_mc_regs = NULL;
 331         u32 data, vbios_version;
 332         int i, ucode_size, regs_size;
 333
 334         /* Skip MC ucode loading on SR-IOV capable boards.
 335          * vbios does this for us in asic_init in that case.
 336          * Skip MC ucode loading on VF, because hypervisor will do that
 337          * for this adaptor.
 338          */
 339         if (amdgpu_sriov_bios(adev))
 340                 return 0;
 341
 342         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 343         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 344         vbios_version = data & 0xf;
 345
 346         if (vbios_version == 0)
 347                 return 0;
 348
 349         if (!adev->mc.fw)
 350                 return -EINVAL;
 351
 352         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 353         amdgpu_ucode_print_mc_hdr(&hdr->header);
 354
 355         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 356         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 357         io_mc_regs = (const __le32 *)
 358                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 359         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 360         fw_data = (const __le32 *)
 361                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 362
 363         data = RREG32(mmMC_SEQ_MISC0);
 364         data &= ~(0x40);
 365         WREG32(mmMC_SEQ_MISC0, data);
 366
 367         /* load mc io regs */
 368         for (i = 0; i < regs_size; i++) {
 369                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 370                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 371         }
 372
 373         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 374         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 375
 376         /* load the MC ucode */
 377         for (i = 0; i < ucode_size; i++)
 378                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 379
 380         /* put the engine back into the active state */
 381         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 382         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 383         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 384
 385         /* wait for training to complete */
 386         for (i = 0; i < adev->usec_timeout; i++) {
 387                 data = RREG32(mmMC_SEQ_MISC0);
 388                 if (data & 0x80)
 389                         break;
 390                 udelay(1);
 391         }
 392
 393         return 0;
 394 }
 395
 396 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 397                                        struct amdgpu_mc *mc)
 398 {
 399         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 400         base <<= 24;
 401
 402         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 403                 /* leave room for at least 1024M GTT */
 404                 dev_warn(adev->dev, "limiting VRAM\n");
 405                 mc->real_vram_size = 0xFFC0000000ULL;
 406                 mc->mc_vram_size = 0xFFC0000000ULL;
 407         }
 408         amdgpu_vram_location(adev, &adev->mc, base);
 409         amdgpu_gart_location(adev, mc);
 410 }
 411
 412 /**
 413  * gmc_v8_0_mc_program - program the GPU memory controller
 414  *
 415  * @adev: amdgpu_device pointer
 416  *
 417  * Set the location of vram, gart, and AGP in the GPU's
 418  * physical address space (CIK).
 419  */
 420 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 421 {
 422         u32 tmp;
 423         int i, j;
 424
 425         /* Initialize HDP */
 426         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 427                 WREG32((0xb05 + j), 0x00000000);
 428                 WREG32((0xb06 + j), 0x00000000);
 429                 WREG32((0xb07 + j), 0x00000000);
 430                 WREG32((0xb08 + j), 0x00000000);
 431                 WREG32((0xb09 + j), 0x00000000);
 432         }
 433         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 434
 435         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 436                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 437         }
 438         /* Update configuration */
 439         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 440                adev->mc.vram_start >> 12);
 441         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 442                adev->mc.vram_end >> 12);
 443         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 444                adev->vram_scratch.gpu_addr >> 12);
 445         WREG32(mmMC_VM_AGP_BASE, 0);
 446         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 447         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 448         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 449                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 450         }
 451
 452         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 453
 454         tmp = RREG32(mmHDP_MISC_CNTL);
 455         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 456         WREG32(mmHDP_MISC_CNTL, tmp);
 457
 458         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 459         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 460 }
 461
 462 /**
 463  * gmc_v8_0_mc_init - initialize the memory controller driver params
 464  *
 465  * @adev: amdgpu_device pointer
 466  *
 467  * Look up the amount of vram, vram width, and decide how to place
 468  * vram and gart within the GPU's physical address space (CIK).
 469  * Returns 0 for success.
 470  */
 471 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 472 {
 473         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 474         if (!adev->mc.vram_width) {
 475                 u32 tmp;
 476                 int chansize, numchan;
 477
 478                 /* Get VRAM informations */
 479                 tmp = RREG32(mmMC_ARB_RAMCFG);
 480                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 481                         chansize = 64;
 482                 } else {
 483                         chansize = 32;
 484                 }
 485                 tmp = RREG32(mmMC_SHARED_CHMAP);
 486                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 487                 case 0:
 488                 default:
 489                         numchan = 1;
 490                         break;
 491                 case 1:
 492                         numchan = 2;
 493                         break;
 494                 case 2:
 495                         numchan = 4;
 496                         break;
 497                 case 3:
 498                         numchan = 8;
 499                         break;
 500                 case 4:
 501                         numchan = 3;
 502                         break;
 503                 case 5:
 504                         numchan = 6;
 505                         break;
 506                 case 6:
 507                         numchan = 10;
 508                         break;
 509                 case 7:
 510                         numchan = 12;
 511                         break;
 512                 case 8:
 513                         numchan = 16;
 514                         break;
 515                 }
 516                 adev->mc.vram_width = numchan * chansize;
 517         }
 518         /* Could aper size report 0 ? */
 519         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 520         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 521         /* size in MB on si */
 522         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 523         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 524
 525 #ifdef CONFIG_X86_64
 526         if (adev->flags & AMD_IS_APU) {
 527                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 528                 adev->mc.aper_size = adev->mc.real_vram_size;
 529         }
 530 #endif
 531
 532         /* In case the PCI BAR is larger than the actual amount of vram */
 533         adev->mc.visible_vram_size = adev->mc.aper_size;
 534         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 535                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 536
 537         amdgpu_gart_set_defaults(adev);
 538         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 539
 540         return 0;
 541 }
 542
 543 /*
 544  * GART
 545  * VMID 0 is the physical GPU addresses as used by the kernel.
 546  * VMIDs 1-15 are used for userspace clients and are handled
 547  * by the amdgpu vm/hsa code.
 548  */
 549
 550 /**
 551  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 552  *
 553  * @adev: amdgpu_device pointer
 554  * @vmid: vm instance to flush
 555  *
 556  * Flush the TLB for the requested page table (CIK).
 557  */
 558 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 559                                         uint32_t vmid)
 560 {
 561         /* flush hdp cache */
 562         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 563
 564         /* bits 0-15 are the VM contexts0-15 */
 565         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 566 }
 567
 568 /**
 569  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 570  *
 571  * @adev: amdgpu_device pointer
 572  * @cpu_pt_addr: cpu address of the page table
 573  * @gpu_page_idx: entry in the page table to update
 574  * @addr: dst addr to write into pte/pde
 575  * @flags: access flags
 576  *
 577  * Update the page tables using the CPU.
 578  */
 579 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 580                                      void *cpu_pt_addr,
 581                                      uint32_t gpu_page_idx,
 582                                      uint64_t addr,
 583                                      uint64_t flags)
 584 {
 585         void __iomem *ptr = (void *)cpu_pt_addr;
 586         uint64_t value;
 587
 588         /*
 589          * PTE format on VI:
 590          * 63:40 reserved
 591          * 39:12 4k physical page base address
 592          * 11:7 fragment
 593          * 6 write
 594          * 5 read
 595          * 4 exe
 596          * 3 reserved
 597          * 2 snooped
 598          * 1 system
 599          * 0 valid
 600          *
 601          * PDE format on VI:
 602          * 63:59 block fragment size
 603          * 58:40 reserved
 604          * 39:1 physical base address of PTE
 605          * bits 5:1 must be 0.
 606          * 0 valid
 607          */
 608         value = addr & 0x000000FFFFFFF000ULL;
 609         value |= flags;
 610         writeq(value, ptr + (gpu_page_idx * 8));
 611
 612         return 0;
 613 }
 614
 615 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 616                                           uint32_t flags)
 617 {
 618         uint64_t pte_flag = 0;
 619
 620         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 621                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 622         if (flags & AMDGPU_VM_PAGE_READABLE)
 623                 pte_flag |= AMDGPU_PTE_READABLE;
 624         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 625                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 626         if (flags & AMDGPU_VM_PAGE_PRT)
 627                 pte_flag |= AMDGPU_PTE_PRT;
 628
 629         return pte_flag;
 630 }
 631
 632 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 633 {
 634         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 635         return addr;
 636 }
 637
 638 /**
 639  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 640  *
 641  * @adev: amdgpu_device pointer
 642  * @value: true redirects VM faults to the default page
 643  */
 644 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 645                                               bool value)
 646 {
 647         u32 tmp;
 648
 649         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 650         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 651                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 652         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 653                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 654         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 655                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 656         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 657                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 659                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 660         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 661                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 662         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 663                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 664         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 665 }
 666
 667 /**
 668  * gmc_v8_0_set_prt - set PRT VM fault
 669  *
 670  * @adev: amdgpu_device pointer
 671  * @enable: enable/disable VM fault handling for PRT
 672 */
 673 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 674 {
 675         u32 tmp;
 676
 677         if (enable && !adev->mc.prt_warning) {
 678                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 679                 adev->mc.prt_warning = true;
 680         }
 681
 682         tmp = RREG32(mmVM_PRT_CNTL);
 683         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 684                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 685         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 686                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 687         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 688                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 689         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 690                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 691         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 692                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 693         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 694                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 695         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 696                             MASK_PDE0_FAULT, enable);
 697         WREG32(mmVM_PRT_CNTL, tmp);
 698
 699         if (enable) {
 700                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 701                 uint32_t high = adev->vm_manager.max_pfn;
 702
 703                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 704                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 705                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 706                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 707                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 708                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 709                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 710                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 711         } else {
 712                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 713                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 714                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 715                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 716                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 717                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 718                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 719                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 720         }
 721 }
 722
 723 /**
 724  * gmc_v8_0_gart_enable - gart enable
 725  *
 726  * @adev: amdgpu_device pointer
 727  *
 728  * This sets up the TLBs, programs the page tables for VMID0,
 729  * sets up the hw for VMIDs 1-15 which are allocated on
 730  * demand, and sets up the global locations for the LDS, GDS,
 731  * and GPUVM for FSA64 clients (CIK).
 732  * Returns 0 for success, errors for failure.
 733  */
 734 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 735 {
 736         int r, i;
 737         u32 tmp;
 738
 739         if (adev->gart.robj == NULL) {
 740                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 741                 return -EINVAL;
 742         }
 743         r = amdgpu_gart_table_vram_pin(adev);
 744         if (r)
 745                 return r;
 746         /* Setup TLB control */
 747         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 748         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 749         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 750         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 751         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 752         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 753         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 754         /* Setup L2 cache */
 755         tmp = RREG32(mmVM_L2_CNTL);
 756         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 757         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 758         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 759         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 760         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 761         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 762         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 763         WREG32(mmVM_L2_CNTL, tmp);
 764         tmp = RREG32(mmVM_L2_CNTL2);
 765         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 766         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 767         WREG32(mmVM_L2_CNTL2, tmp);
 768         tmp = RREG32(mmVM_L2_CNTL3);
 769         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 770         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 771         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 772         WREG32(mmVM_L2_CNTL3, tmp);
 773         /* XXX: set to enable PTE/PDE in system memory */
 774         tmp = RREG32(mmVM_L2_CNTL4);
 775         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 776         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 777         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 778         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 779         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 780         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 781         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 782         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 783         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 784         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 785         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 786         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 787         WREG32(mmVM_L2_CNTL4, tmp);
 788         /* setup context0 */
 789         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 790         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 791         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 792         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 793                         (u32)(adev->dummy_page.addr >> 12));
 794         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 795         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 796         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 797         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 798         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 799         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 800
 801         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 802         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 803         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 804
 805         /* empty context1-15 */
 806         /* FIXME start with 4G, once using 2 level pt switch to full
 807          * vm size space
 808          */
 809         /* set vm size, must be a multiple of 4 */
 810         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 811         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 812         for (i = 1; i < 16; i++) {
 813                 if (i < 8)
 814                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 815                                adev->gart.table_addr >> 12);
 816                 else
 817                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 818                                adev->gart.table_addr >> 12);
 819         }
 820
 821         /* enable context1-15 */
 822         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 823                (u32)(adev->dummy_page.addr >> 12));
 824         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 825         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 826         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 827         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 828         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 829         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 831         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 832         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 833         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 834         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 835         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 836                             adev->vm_manager.block_size - 9);
 837         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 838         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 839                 gmc_v8_0_set_fault_enable_default(adev, false);
 840         else
 841                 gmc_v8_0_set_fault_enable_default(adev, true);
 842
 843         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 844         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 845                  (unsigned)(adev->mc.gart_size >> 20),
 846                  (unsigned long long)adev->gart.table_addr);
 847         adev->gart.ready = true;
 848         return 0;
 849 }
 850
 851 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 852 {
 853         int r;
 854
 855         if (adev->gart.robj) {
 856                 WARN(1, "R600 PCIE GART already initialized\n");
 857                 return 0;
 858         }
 859         /* Initialize common gart structure */
 860         r = amdgpu_gart_init(adev);
 861         if (r)
 862                 return r;
 863         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 864         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 865         return amdgpu_gart_table_vram_alloc(adev);
 866 }
 867
 868 /**
 869  * gmc_v8_0_gart_disable - gart disable
 870  *
 871  * @adev: amdgpu_device pointer
 872  *
 873  * This disables all VM page table (CIK).
 874  */
 875 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 876 {
 877         u32 tmp;
 878
 879         /* Disable all tables */
 880         WREG32(mmVM_CONTEXT0_CNTL, 0);
 881         WREG32(mmVM_CONTEXT1_CNTL, 0);
 882         /* Setup TLB control */
 883         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 884         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 885         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 886         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 887         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 888         /* Setup L2 cache */
 889         tmp = RREG32(mmVM_L2_CNTL);
 890         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 891         WREG32(mmVM_L2_CNTL, tmp);
 892         WREG32(mmVM_L2_CNTL2, 0);
 893         amdgpu_gart_table_vram_unpin(adev);
 894 }
 895
 896 /**
 897  * gmc_v8_0_gart_fini - vm fini callback
 898  *
 899  * @adev: amdgpu_device pointer
 900  *
 901  * Tears down the driver GART/VM setup (CIK).
 902  */
 903 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 904 {
 905         amdgpu_gart_table_vram_free(adev);
 906         amdgpu_gart_fini(adev);
 907 }
 908
 909 /**
 910  * gmc_v8_0_vm_decode_fault - print human readable fault info
 911  *
 912  * @adev: amdgpu_device pointer
 913  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 914  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 915  *
 916  * Print human readable fault information (CIK).
 917  */
 918 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 919                                      u32 status, u32 addr, u32 mc_client)
 920 {
 921         u32 mc_id;
 922         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 923         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 924                                         PROTECTIONS);
 925         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 926                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 927
 928         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 929                               MEMORY_CLIENT_ID);
 930
 931         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 932                protections, vmid, addr,
 933                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 934                              MEMORY_CLIENT_RW) ?
 935                "write" : "read", block, mc_client, mc_id);
 936 }
 937
 938 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 939 {
 940         switch (mc_seq_vram_type) {
 941         case MC_SEQ_MISC0__MT__GDDR1:
 942                 return AMDGPU_VRAM_TYPE_GDDR1;
 943         case MC_SEQ_MISC0__MT__DDR2:
 944                 return AMDGPU_VRAM_TYPE_DDR2;
 945         case MC_SEQ_MISC0__MT__GDDR3:
 946                 return AMDGPU_VRAM_TYPE_GDDR3;
 947         case MC_SEQ_MISC0__MT__GDDR4:
 948                 return AMDGPU_VRAM_TYPE_GDDR4;
 949         case MC_SEQ_MISC0__MT__GDDR5:
 950                 return AMDGPU_VRAM_TYPE_GDDR5;
 951         case MC_SEQ_MISC0__MT__HBM:
 952                 return AMDGPU_VRAM_TYPE_HBM;
 953         case MC_SEQ_MISC0__MT__DDR3:
 954                 return AMDGPU_VRAM_TYPE_DDR3;
 955         default:
 956                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 957         }
 958 }
 959
 960 static int gmc_v8_0_early_init(void *handle)
 961 {
 962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 963
 964         gmc_v8_0_set_gart_funcs(adev);
 965         gmc_v8_0_set_irq_funcs(adev);
 966
 967         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 968         adev->mc.shared_aperture_end =
 969                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 970         adev->mc.private_aperture_start =
 971                 adev->mc.shared_aperture_end + 1;
 972         adev->mc.private_aperture_end =
 973                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 974
 975         return 0;
 976 }
 977
 978 static int gmc_v8_0_late_init(void *handle)
 979 {
 980         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 981
 982         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 983                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 984         else
 985                 return 0;
 986 }
 987
 988 #define mmMC_SEQ_MISC0_FIJI 0xA71
 989
 990 static int gmc_v8_0_sw_init(void *handle)
 991 {
 992         int r;
 993         int dma_bits;
 994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 995
 996         if (adev->flags & AMD_IS_APU) {
 997                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 998         } else {
 999                 u32 tmp;
1000
1001                 if (adev->asic_type == CHIP_FIJI)
1002                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1003                 else
1004                         tmp = RREG32(mmMC_SEQ_MISC0);
1005                 tmp &= MC_SEQ_MISC0__MT__MASK;
1006                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1007         }
1008
1009         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1010         if (r)
1011                 return r;
1012
1013         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1014         if (r)
1015                 return r;
1016
1017         /* Adjust VM size here.
1018          * Currently set to 4GB ((1 << 20) 4k pages).
1019          * Max GPUVM size for cayman and SI is 40 bits.
1020          */
1021         amdgpu_vm_adjust_size(adev, 64);
1022         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1023
1024         /* Set the internal MC address mask
1025          * This is the max address of the GPU's
1026          * internal address space.
1027          */
1028         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1029
1030         adev->mc.stolen_size = 256 * 1024;
1031
1032         /* set DMA mask + need_dma32 flags.
1033          * PCIE - can handle 40-bits.
1034          * IGP - can handle 40-bits
1035          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1036          */
1037         adev->need_dma32 = false;
1038         dma_bits = adev->need_dma32 ? 32 : 40;
1039         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1040         if (r) {
1041                 adev->need_dma32 = true;
1042                 dma_bits = 32;
1043                 pr_warn("amdgpu: No suitable DMA available\n");
1044         }
1045         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1046         if (r) {
1047                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1048                 pr_warn("amdgpu: No coherent DMA available\n");
1049         }
1050
1051         r = gmc_v8_0_init_microcode(adev);
1052         if (r) {
1053                 DRM_ERROR("Failed to load mc firmware!\n");
1054                 return r;
1055         }
1056
1057         r = gmc_v8_0_mc_init(adev);
1058         if (r)
1059                 return r;
1060
1061         /* Memory manager */
1062         r = amdgpu_bo_init(adev);
1063         if (r)
1064                 return r;
1065
1066         r = gmc_v8_0_gart_init(adev);
1067         if (r)
1068                 return r;
1069
1070         /*
1071          * number of VMs
1072          * VMID 0 is reserved for System
1073          * amdgpu graphics/compute will use VMIDs 1-7
1074          * amdkfd will use VMIDs 8-15
1075          */
1076         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1077         adev->vm_manager.num_level = 1;
1078         amdgpu_vm_manager_init(adev);
1079
1080         /* base offset of vram pages */
1081         if (adev->flags & AMD_IS_APU) {
1082                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1083
1084                 tmp <<= 22;
1085                 adev->vm_manager.vram_base_offset = tmp;
1086         } else {
1087                 adev->vm_manager.vram_base_offset = 0;
1088         }
1089
1090         return 0;
1091 }
1092
1093 static int gmc_v8_0_sw_fini(void *handle)
1094 {
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097         amdgpu_vm_manager_fini(adev);
1098         gmc_v8_0_gart_fini(adev);
1099         amdgpu_gem_force_release(adev);
1100         amdgpu_bo_fini(adev);
1101
1102         return 0;
1103 }
1104
1105 static int gmc_v8_0_hw_init(void *handle)
1106 {
1107         int r;
1108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109
1110         gmc_v8_0_init_golden_registers(adev);
1111
1112         gmc_v8_0_mc_program(adev);
1113
1114         if (adev->asic_type == CHIP_TONGA) {
1115                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1116                 if (r) {
1117                         DRM_ERROR("Failed to load MC firmware!\n");
1118                         return r;
1119                 }
1120         } else if (adev->asic_type == CHIP_POLARIS11 ||
1121                         adev->asic_type == CHIP_POLARIS10 ||
1122                         adev->asic_type == CHIP_POLARIS12) {
1123                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1124                 if (r) {
1125                         DRM_ERROR("Failed to load MC firmware!\n");
1126                         return r;
1127                 }
1128         }
1129
1130         r = gmc_v8_0_gart_enable(adev);
1131         if (r)
1132                 return r;
1133
1134         return r;
1135 }
1136
1137 static int gmc_v8_0_hw_fini(void *handle)
1138 {
1139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140
1141         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1142         gmc_v8_0_gart_disable(adev);
1143
1144         return 0;
1145 }
1146
1147 static int gmc_v8_0_suspend(void *handle)
1148 {
1149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1150
1151         gmc_v8_0_hw_fini(adev);
1152
1153         return 0;
1154 }
1155
1156 static int gmc_v8_0_resume(void *handle)
1157 {
1158         int r;
1159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160
1161         r = gmc_v8_0_hw_init(adev);
1162         if (r)
1163                 return r;
1164
1165         amdgpu_vm_reset_all_ids(adev);
1166
1167         return 0;
1168 }
1169
1170 static bool gmc_v8_0_is_idle(void *handle)
1171 {
1172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173         u32 tmp = RREG32(mmSRBM_STATUS);
1174
1175         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1176                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1177                 return false;
1178
1179         return true;
1180 }
1181
1182 static int gmc_v8_0_wait_for_idle(void *handle)
1183 {
1184         unsigned i;
1185         u32 tmp;
1186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187
1188         for (i = 0; i < adev->usec_timeout; i++) {
1189                 /* read MC_STATUS */
1190                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1191                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1192                                                SRBM_STATUS__MCC_BUSY_MASK |
1193                                                SRBM_STATUS__MCD_BUSY_MASK |
1194                                                SRBM_STATUS__VMC_BUSY_MASK |
1195                                                SRBM_STATUS__VMC1_BUSY_MASK);
1196                 if (!tmp)
1197                         return 0;
1198                 udelay(1);
1199         }
1200         return -ETIMEDOUT;
1201
1202 }
1203
1204 static bool gmc_v8_0_check_soft_reset(void *handle)
1205 {
1206         u32 srbm_soft_reset = 0;
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208         u32 tmp = RREG32(mmSRBM_STATUS);
1209
1210         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1211                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1212                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1213
1214         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1215                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1216                 if (!(adev->flags & AMD_IS_APU))
1217                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1218                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1219         }
1220         if (srbm_soft_reset) {
1221                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1222                 return true;
1223         } else {
1224                 adev->mc.srbm_soft_reset = 0;
1225                 return false;
1226         }
1227 }
1228
1229 static int gmc_v8_0_pre_soft_reset(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         if (!adev->mc.srbm_soft_reset)
1234                 return 0;
1235
1236         gmc_v8_0_mc_stop(adev);
1237         if (gmc_v8_0_wait_for_idle(adev)) {
1238                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int gmc_v8_0_soft_reset(void *handle)
1245 {
1246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247         u32 srbm_soft_reset;
1248
1249         if (!adev->mc.srbm_soft_reset)
1250                 return 0;
1251         srbm_soft_reset = adev->mc.srbm_soft_reset;
1252
1253         if (srbm_soft_reset) {
1254                 u32 tmp;
1255
1256                 tmp = RREG32(mmSRBM_SOFT_RESET);
1257                 tmp |= srbm_soft_reset;
1258                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1259                 WREG32(mmSRBM_SOFT_RESET, tmp);
1260                 tmp = RREG32(mmSRBM_SOFT_RESET);
1261
1262                 udelay(50);
1263
1264                 tmp &= ~srbm_soft_reset;
1265                 WREG32(mmSRBM_SOFT_RESET, tmp);
1266                 tmp = RREG32(mmSRBM_SOFT_RESET);
1267
1268                 /* Wait a little for things to settle down */
1269                 udelay(50);
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int gmc_v8_0_post_soft_reset(void *handle)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279         if (!adev->mc.srbm_soft_reset)
1280                 return 0;
1281
1282         gmc_v8_0_mc_resume(adev);
1283         return 0;
1284 }
1285
1286 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1287                                              struct amdgpu_irq_src *src,
1288                                              unsigned type,
1289                                              enum amdgpu_interrupt_state state)
1290 {
1291         u32 tmp;
1292         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1293                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1294                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1295                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1296                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1297                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1298                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1299
1300         switch (state) {
1301         case AMDGPU_IRQ_STATE_DISABLE:
1302                 /* system context */
1303                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1304                 tmp &= ~bits;
1305                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1306                 /* VMs */
1307                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1308                 tmp &= ~bits;
1309                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1310                 break;
1311         case AMDGPU_IRQ_STATE_ENABLE:
1312                 /* system context */
1313                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1314                 tmp |= bits;
1315                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1316                 /* VMs */
1317                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1318                 tmp |= bits;
1319                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1320                 break;
1321         default:
1322                 break;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1329                                       struct amdgpu_irq_src *source,
1330                                       struct amdgpu_iv_entry *entry)
1331 {
1332         u32 addr, status, mc_client;
1333
1334         if (amdgpu_sriov_vf(adev)) {
1335                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1336                         entry->src_id, entry->src_data[0]);
1337                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1338                 return 0;
1339         }
1340
1341         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1342         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1343         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1344         /* reset addr and status */
1345         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1346
1347         if (!addr && !status)
1348                 return 0;
1349
1350         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1351                 gmc_v8_0_set_fault_enable_default(adev, false);
1352
1353         if (printk_ratelimit()) {
1354                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1355                         entry->src_id, entry->src_data[0]);
1356                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1357                         addr);
1358                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1359                         status);
1360                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1367                                                      bool enable)
1368 {
1369         uint32_t data;
1370
1371         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1372                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1373                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1374                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1375
1376                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1377                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1378                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1379
1380                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1381                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1382                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1383
1384                 data = RREG32(mmMC_XPB_CLK_GAT);
1385                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1386                 WREG32(mmMC_XPB_CLK_GAT, data);
1387
1388                 data = RREG32(mmATC_MISC_CG);
1389                 data |= ATC_MISC_CG__ENABLE_MASK;
1390                 WREG32(mmATC_MISC_CG, data);
1391
1392                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1393                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1394                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1395
1396                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1397                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1398                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1399
1400                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1401                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1402                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1403
1404                 data = RREG32(mmVM_L2_CG);
1405                 data |= VM_L2_CG__ENABLE_MASK;
1406                 WREG32(mmVM_L2_CG, data);
1407         } else {
1408                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1409                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1410                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1411
1412                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1413                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1414                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1415
1416                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1417                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1418                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1419
1420                 data = RREG32(mmMC_XPB_CLK_GAT);
1421                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1422                 WREG32(mmMC_XPB_CLK_GAT, data);
1423
1424                 data = RREG32(mmATC_MISC_CG);
1425                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1426                 WREG32(mmATC_MISC_CG, data);
1427
1428                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1429                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1430                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1431
1432                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1433                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1434                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1435
1436                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1437                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1438                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1439
1440                 data = RREG32(mmVM_L2_CG);
1441                 data &= ~VM_L2_CG__ENABLE_MASK;
1442                 WREG32(mmVM_L2_CG, data);
1443         }
1444 }
1445
1446 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1447                                        bool enable)
1448 {
1449         uint32_t data;
1450
1451         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1452                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1453                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1454                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1455
1456                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1457                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1458                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1459
1460                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1461                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1462                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1463
1464                 data = RREG32(mmMC_XPB_CLK_GAT);
1465                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1466                 WREG32(mmMC_XPB_CLK_GAT, data);
1467
1468                 data = RREG32(mmATC_MISC_CG);
1469                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1470                 WREG32(mmATC_MISC_CG, data);
1471
1472                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1473                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1474                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1475
1476                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1477                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1478                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1479
1480                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1481                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1482                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1483
1484                 data = RREG32(mmVM_L2_CG);
1485                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1486                 WREG32(mmVM_L2_CG, data);
1487         } else {
1488                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1489                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1490                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1491
1492                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1493                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1494                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1495
1496                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1497                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1498                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1499
1500                 data = RREG32(mmMC_XPB_CLK_GAT);
1501                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1502                 WREG32(mmMC_XPB_CLK_GAT, data);
1503
1504                 data = RREG32(mmATC_MISC_CG);
1505                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1506                 WREG32(mmATC_MISC_CG, data);
1507
1508                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1509                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1510                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1511
1512                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1513                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1514                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1515
1516                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1517                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1518                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1519
1520                 data = RREG32(mmVM_L2_CG);
1521                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1522                 WREG32(mmVM_L2_CG, data);
1523         }
1524 }
1525
1526 static int gmc_v8_0_set_clockgating_state(void *handle,
1527                                           enum amd_clockgating_state state)
1528 {
1529         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531         if (amdgpu_sriov_vf(adev))
1532                 return 0;
1533
1534         switch (adev->asic_type) {
1535         case CHIP_FIJI:
1536                 fiji_update_mc_medium_grain_clock_gating(adev,
1537                                 state == AMD_CG_STATE_GATE);
1538                 fiji_update_mc_light_sleep(adev,
1539                                 state == AMD_CG_STATE_GATE);
1540                 break;
1541         default:
1542                 break;
1543         }
1544         return 0;
1545 }
1546
1547 static int gmc_v8_0_set_powergating_state(void *handle,
1548                                           enum amd_powergating_state state)
1549 {
1550         return 0;
1551 }
1552
1553 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1554 {
1555         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1556         int data;
1557
1558         if (amdgpu_sriov_vf(adev))
1559                 *flags = 0;
1560
1561         /* AMD_CG_SUPPORT_MC_MGCG */
1562         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1563         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1564                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1565
1566         /* AMD_CG_SUPPORT_MC_LS */
1567         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1568                 *flags |= AMD_CG_SUPPORT_MC_LS;
1569 }
1570
1571 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1572         .name = "gmc_v8_0",
1573         .early_init = gmc_v8_0_early_init,
1574         .late_init = gmc_v8_0_late_init,
1575         .sw_init = gmc_v8_0_sw_init,
1576         .sw_fini = gmc_v8_0_sw_fini,
1577         .hw_init = gmc_v8_0_hw_init,
1578         .hw_fini = gmc_v8_0_hw_fini,
1579         .suspend = gmc_v8_0_suspend,
1580         .resume = gmc_v8_0_resume,
1581         .is_idle = gmc_v8_0_is_idle,
1582         .wait_for_idle = gmc_v8_0_wait_for_idle,
1583         .check_soft_reset = gmc_v8_0_check_soft_reset,
1584         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1585         .soft_reset = gmc_v8_0_soft_reset,
1586         .post_soft_reset = gmc_v8_0_post_soft_reset,
1587         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1588         .set_powergating_state = gmc_v8_0_set_powergating_state,
1589         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1590 };
1591
1592 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1593         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1594         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1595         .set_prt = gmc_v8_0_set_prt,
1596         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1597         .get_vm_pde = gmc_v8_0_get_vm_pde
1598 };
1599
1600 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1601         .set = gmc_v8_0_vm_fault_interrupt_state,
1602         .process = gmc_v8_0_process_interrupt,
1603 };
1604
1605 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1606 {
1607         if (adev->gart.gart_funcs == NULL)
1608                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1609 }
1610
1611 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1612 {
1613         adev->mc.vm_fault.num_types = 1;
1614         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1615 }
1616
1617 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1618 {
1619         .type = AMD_IP_BLOCK_TYPE_GMC,
1620         .major = 8,
1621         .minor = 0,
1622         .rev = 0,
1623         .funcs = &gmc_v8_0_ip_funcs,
1624 };
1625
1626 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1627 {
1628         .type = AMD_IP_BLOCK_TYPE_GMC,
1629         .major = 8,
1630         .minor = 1,
1631         .rev = 0,
1632         .funcs = &gmc_v8_0_ip_funcs,
1633 };
1634
1635 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1636 {
1637         .type = AMD_IP_BLOCK_TYPE_GMC,
1638         .major = 8,
1639         .minor = 5,
1640         .rev = 0,
1641         .funcs = &gmc_v8_0_ip_funcs,
1642 };