drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v6_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gmc/gmc_6_0_d.h"
  34 #include "gmc/gmc_6_0_sh_mask.h"
  35 #include "dce/dce_6_0_d.h"
  36 #include "dce/dce_6_0_sh_mask.h"
  37 #include "si_enums.h"
  38
  39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
  40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int gmc_v6_0_wait_for_idle(void *handle);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
  44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
  45 MODULE_FIRMWARE("radeon/verde_mc.bin");
  46 MODULE_FIRMWARE("radeon/oland_mc.bin");
  47 MODULE_FIRMWARE("radeon/si58_mc.bin");
  48
  49 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  50 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  51 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  52 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  53 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  54 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  55 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  56 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  57
  58
  59 static const u32 crtc_offsets[6] =
  60 {
  61         SI_CRTC0_REGISTER_OFFSET,
  62         SI_CRTC1_REGISTER_OFFSET,
  63         SI_CRTC2_REGISTER_OFFSET,
  64         SI_CRTC3_REGISTER_OFFSET,
  65         SI_CRTC4_REGISTER_OFFSET,
  66         SI_CRTC5_REGISTER_OFFSET
  67 };
  68
  69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  70 {
  71         u32 blackout;
  72
  73         gmc_v6_0_wait_for_idle((void *)adev);
  74
  75         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  76         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  77                 /* Block CPU access */
  78                 WREG32(mmBIF_FB_EN, 0);
  79                 /* blackout the MC */
  80                 blackout = REG_SET_FIELD(blackout,
  81                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  82                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  83         }
  84         /* wait for the MC to settle */
  85         udelay(100);
  86
  87 }
  88
  89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  90 {
  91         u32 tmp;
  92
  93         /* unblackout the MC */
  94         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  95         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  96         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
  97         /* allow CPU access */
  98         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
  99         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 100         WREG32(mmBIF_FB_EN, tmp);
 101 }
 102
 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 104 {
 105         const char *chip_name;
 106         char fw_name[30];
 107         int err;
 108         bool is_58_fw = false;
 109
 110         DRM_DEBUG("\n");
 111
 112         switch (adev->asic_type) {
 113         case CHIP_TAHITI:
 114                 chip_name = "tahiti";
 115                 break;
 116         case CHIP_PITCAIRN:
 117                 chip_name = "pitcairn";
 118                 break;
 119         case CHIP_VERDE:
 120                 chip_name = "verde";
 121                 break;
 122         case CHIP_OLAND:
 123                 chip_name = "oland";
 124                 break;
 125         case CHIP_HAINAN:
 126                 chip_name = "hainan";
 127                 break;
 128         default: BUG();
 129         }
 130
 131         /* this memory configuration requires special firmware */
 132         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 133                 is_58_fw = true;
 134
 135         if (is_58_fw)
 136                 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
 137         else
 138                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 139         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 140         if (err)
 141                 goto out;
 142
 143         err = amdgpu_ucode_validate(adev->mc.fw);
 144
 145 out:
 146         if (err) {
 147                 dev_err(adev->dev,
 148                        "si_mc: Failed to load firmware \"%s\"\n",
 149                        fw_name);
 150                 release_firmware(adev->mc.fw);
 151                 adev->mc.fw = NULL;
 152         }
 153         return err;
 154 }
 155
 156 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 157 {
 158         const __le32 *new_fw_data = NULL;
 159         u32 running;
 160         const __le32 *new_io_mc_regs = NULL;
 161         int i, regs_size, ucode_size;
 162         const struct mc_firmware_header_v1_0 *hdr;
 163
 164         if (!adev->mc.fw)
 165                 return -EINVAL;
 166
 167         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 168
 169         amdgpu_ucode_print_mc_hdr(&hdr->header);
 170
 171         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 172         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 173         new_io_mc_regs = (const __le32 *)
 174                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 175         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 176         new_fw_data = (const __le32 *)
 177                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 178
 179         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 180
 181         if (running == 0) {
 182
 183                 /* reset the engine and set to writable */
 184                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 185                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 186
 187                 /* load mc io regs */
 188                 for (i = 0; i < regs_size; i++) {
 189                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 190                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 191                 }
 192                 /* load the MC ucode */
 193                 for (i = 0; i < ucode_size; i++) {
 194                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 195                 }
 196
 197                 /* put the engine back into the active state */
 198                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 199                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 201
 202                 /* wait for training to complete */
 203                 for (i = 0; i < adev->usec_timeout; i++) {
 204                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 205                                 break;
 206                         udelay(1);
 207                 }
 208                 for (i = 0; i < adev->usec_timeout; i++) {
 209                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 210                                 break;
 211                         udelay(1);
 212                 }
 213
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 220                                        struct amdgpu_mc *mc)
 221 {
 222         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 223         base <<= 24;
 224
 225         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 226                 dev_warn(adev->dev, "limiting VRAM\n");
 227                 mc->real_vram_size = 0xFFC0000000ULL;
 228                 mc->mc_vram_size = 0xFFC0000000ULL;
 229         }
 230         amdgpu_vram_location(adev, &adev->mc, base);
 231         amdgpu_gart_location(adev, mc);
 232 }
 233
 234 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 235 {
 236         int i, j;
 237
 238         /* Initialize HDP */
 239         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 240                 WREG32((0xb05 + j), 0x00000000);
 241                 WREG32((0xb06 + j), 0x00000000);
 242                 WREG32((0xb07 + j), 0x00000000);
 243                 WREG32((0xb08 + j), 0x00000000);
 244                 WREG32((0xb09 + j), 0x00000000);
 245         }
 246         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 247
 248         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 249                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 250         }
 251
 252         WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
 253         /* Update configuration */
 254         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 255                adev->mc.vram_start >> 12);
 256         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 257                adev->mc.vram_end >> 12);
 258         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 259                adev->vram_scratch.gpu_addr >> 12);
 260         WREG32(mmMC_VM_AGP_BASE, 0);
 261         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 262         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 263
 264         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 265                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 266         }
 267 }
 268
 269 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 270 {
 271
 272         u32 tmp;
 273         int chansize, numchan;
 274
 275         tmp = RREG32(mmMC_ARB_RAMCFG);
 276         if (tmp & (1 << 11)) {
 277                 chansize = 16;
 278         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 279                 chansize = 64;
 280         } else {
 281                 chansize = 32;
 282         }
 283         tmp = RREG32(mmMC_SHARED_CHMAP);
 284         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 285         case 0:
 286         default:
 287                 numchan = 1;
 288                 break;
 289         case 1:
 290                 numchan = 2;
 291                 break;
 292         case 2:
 293                 numchan = 4;
 294                 break;
 295         case 3:
 296                 numchan = 8;
 297                 break;
 298         case 4:
 299                 numchan = 3;
 300                 break;
 301         case 5:
 302                 numchan = 6;
 303                 break;
 304         case 6:
 305                 numchan = 10;
 306                 break;
 307         case 7:
 308                 numchan = 12;
 309                 break;
 310         case 8:
 311                 numchan = 16;
 312                 break;
 313         }
 314         adev->mc.vram_width = numchan * chansize;
 315         /* Could aper size report 0 ? */
 316         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 317         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 318         /* size in MB on si */
 319         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 320         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 321         adev->mc.visible_vram_size = adev->mc.aper_size;
 322
 323         amdgpu_gart_set_defaults(adev);
 324         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 325
 326         return 0;
 327 }
 328
 329 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 330                                         uint32_t vmid)
 331 {
 332         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 333
 334         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 335 }
 336
 337 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 338                                      void *cpu_pt_addr,
 339                                      uint32_t gpu_page_idx,
 340                                      uint64_t addr,
 341                                      uint64_t flags)
 342 {
 343         void __iomem *ptr = (void *)cpu_pt_addr;
 344         uint64_t value;
 345
 346         value = addr & 0xFFFFFFFFFFFFF000ULL;
 347         value |= flags;
 348         writeq(value, ptr + (gpu_page_idx * 8));
 349
 350         return 0;
 351 }
 352
 353 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
 354                                           uint32_t flags)
 355 {
 356         uint64_t pte_flag = 0;
 357
 358         if (flags & AMDGPU_VM_PAGE_READABLE)
 359                 pte_flag |= AMDGPU_PTE_READABLE;
 360         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 361                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 362         if (flags & AMDGPU_VM_PAGE_PRT)
 363                 pte_flag |= AMDGPU_PTE_PRT;
 364
 365         return pte_flag;
 366 }
 367
 368 static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 369 {
 370         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 371         return addr;
 372 }
 373
 374 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 375                                               bool value)
 376 {
 377         u32 tmp;
 378
 379         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 380         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 381                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 382         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 383                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 384         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 385                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 386         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 387                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 388         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 389                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 390         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 391                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 392         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 393 }
 394
 395  /**
 396    + * gmc_v8_0_set_prt - set PRT VM fault
 397    + *
 398    + * @adev: amdgpu_device pointer
 399    + * @enable: enable/disable VM fault handling for PRT
 400    +*/
 401 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 402 {
 403         u32 tmp;
 404
 405         if (enable && !adev->mc.prt_warning) {
 406                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 407                 adev->mc.prt_warning = true;
 408         }
 409
 410         tmp = RREG32(mmVM_PRT_CNTL);
 411         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 412                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 413                             enable);
 414         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 415                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 416                             enable);
 417         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 418                             L2_CACHE_STORE_INVALID_ENTRIES,
 419                             enable);
 420         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 421                             L1_TLB_STORE_INVALID_ENTRIES,
 422                             enable);
 423         WREG32(mmVM_PRT_CNTL, tmp);
 424
 425         if (enable) {
 426                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 427                 uint32_t high = adev->vm_manager.max_pfn;
 428
 429                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 430                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 431                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 432                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 433                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 434                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 435                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 436                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 437         } else {
 438                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 439                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 440                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 441                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 442                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 443                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 444                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 445                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 446         }
 447 }
 448
 449 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 450 {
 451         int r, i;
 452
 453         if (adev->gart.robj == NULL) {
 454                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 455                 return -EINVAL;
 456         }
 457         r = amdgpu_gart_table_vram_pin(adev);
 458         if (r)
 459                 return r;
 460         /* Setup TLB control */
 461         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 462                (0xA << 7) |
 463                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 464                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 465                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 466                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 467                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 468         /* Setup L2 cache */
 469         WREG32(mmVM_L2_CNTL,
 470                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 471                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 472                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 473                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 474                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 475                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 476         WREG32(mmVM_L2_CNTL2,
 477                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 478                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 479         WREG32(mmVM_L2_CNTL3,
 480                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 481                (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 482                (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 483         /* setup context0 */
 484         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 485         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 486         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 487         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 488                         (u32)(adev->dummy_page.addr >> 12));
 489         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 490         WREG32(mmVM_CONTEXT0_CNTL,
 491                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 492                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 493                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 494
 495         WREG32(0x575, 0);
 496         WREG32(0x576, 0);
 497         WREG32(0x577, 0);
 498
 499         /* empty context1-15 */
 500         /* set vm size, must be a multiple of 4 */
 501         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 502         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 503         /* Assign the pt base to something valid for now; the pts used for
 504          * the VMs are determined by the application and setup and assigned
 505          * on the fly in the vm part of radeon_gart.c
 506          */
 507         for (i = 1; i < 16; i++) {
 508                 if (i < 8)
 509                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 510                                adev->gart.table_addr >> 12);
 511                 else
 512                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 513                                adev->gart.table_addr >> 12);
 514         }
 515
 516         /* enable context1-15 */
 517         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 518                (u32)(adev->dummy_page.addr >> 12));
 519         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 520         WREG32(mmVM_CONTEXT1_CNTL,
 521                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 522                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 523                ((adev->vm_manager.block_size - 9)
 524                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 525         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 526                 gmc_v6_0_set_fault_enable_default(adev, false);
 527         else
 528                 gmc_v6_0_set_fault_enable_default(adev, true);
 529
 530         gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
 531         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 532                  (unsigned)(adev->mc.gart_size >> 20),
 533                  (unsigned long long)adev->gart.table_addr);
 534         adev->gart.ready = true;
 535         return 0;
 536 }
 537
 538 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 539 {
 540         int r;
 541
 542         if (adev->gart.robj) {
 543                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 544                 return 0;
 545         }
 546         r = amdgpu_gart_init(adev);
 547         if (r)
 548                 return r;
 549         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 550         adev->gart.gart_pte_flags = 0;
 551         return amdgpu_gart_table_vram_alloc(adev);
 552 }
 553
 554 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 555 {
 556         /*unsigned i;
 557
 558         for (i = 1; i < 16; ++i) {
 559                 uint32_t reg;
 560                 if (i < 8)
 561                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 562                 else
 563                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 564                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 565         }*/
 566
 567         /* Disable all tables */
 568         WREG32(mmVM_CONTEXT0_CNTL, 0);
 569         WREG32(mmVM_CONTEXT1_CNTL, 0);
 570         /* Setup TLB control */
 571         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 572                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 573                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 574         /* Setup L2 cache */
 575         WREG32(mmVM_L2_CNTL,
 576                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 577                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 578                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 579                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 580         WREG32(mmVM_L2_CNTL2, 0);
 581         WREG32(mmVM_L2_CNTL3,
 582                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 583                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 584         amdgpu_gart_table_vram_unpin(adev);
 585 }
 586
 587 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
 588 {
 589         amdgpu_gart_table_vram_free(adev);
 590         amdgpu_gart_fini(adev);
 591 }
 592
 593 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 594                                      u32 status, u32 addr, u32 mc_client)
 595 {
 596         u32 mc_id;
 597         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 598         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 599                                         PROTECTIONS);
 600         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 601                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 602
 603         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 604                               MEMORY_CLIENT_ID);
 605
 606         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 607                protections, vmid, addr,
 608                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 609                              MEMORY_CLIENT_RW) ?
 610                "write" : "read", block, mc_client, mc_id);
 611 }
 612
 613 /*
 614 static const u32 mc_cg_registers[] = {
 615         MC_HUB_MISC_HUB_CG,
 616         MC_HUB_MISC_SIP_CG,
 617         MC_HUB_MISC_VM_CG,
 618         MC_XPB_CLK_GAT,
 619         ATC_MISC_CG,
 620         MC_CITF_MISC_WR_CG,
 621         MC_CITF_MISC_RD_CG,
 622         MC_CITF_MISC_VM_CG,
 623         VM_L2_CG,
 624 };
 625
 626 static const u32 mc_cg_ls_en[] = {
 627         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 628         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 629         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 630         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 631         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 632         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 633         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 634         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 635         VM_L2_CG__MEM_LS_ENABLE_MASK,
 636 };
 637
 638 static const u32 mc_cg_en[] = {
 639         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 640         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 641         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 642         MC_XPB_CLK_GAT__ENABLE_MASK,
 643         ATC_MISC_CG__ENABLE_MASK,
 644         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 645         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 646         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 647         VM_L2_CG__ENABLE_MASK,
 648 };
 649
 650 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 651                                   bool enable)
 652 {
 653         int i;
 654         u32 orig, data;
 655
 656         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 657                 orig = data = RREG32(mc_cg_registers[i]);
 658                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 659                         data |= mc_cg_ls_en[i];
 660                 else
 661                         data &= ~mc_cg_ls_en[i];
 662                 if (data != orig)
 663                         WREG32(mc_cg_registers[i], data);
 664         }
 665 }
 666
 667 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 668                                     bool enable)
 669 {
 670         int i;
 671         u32 orig, data;
 672
 673         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 674                 orig = data = RREG32(mc_cg_registers[i]);
 675                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 676                         data |= mc_cg_en[i];
 677                 else
 678                         data &= ~mc_cg_en[i];
 679                 if (data != orig)
 680                         WREG32(mc_cg_registers[i], data);
 681         }
 682 }
 683
 684 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 685                                      bool enable)
 686 {
 687         u32 orig, data;
 688
 689         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 690
 691         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 692                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 693                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 694                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 695                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 696         } else {
 697                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 698                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 699                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 700                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 701         }
 702
 703         if (orig != data)
 704                 WREG32_PCIE(ixPCIE_CNTL2, data);
 705 }
 706
 707 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 708                                      bool enable)
 709 {
 710         u32 orig, data;
 711
 712         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 713
 714         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 715                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 716         else
 717                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 718
 719         if (orig != data)
 720                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 721 }
 722
 723 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 724                                    bool enable)
 725 {
 726         u32 orig, data;
 727
 728         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 729
 730         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 731                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 732         else
 733                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 734
 735         if (orig != data)
 736                 WREG32(mmHDP_MEM_POWER_LS, data);
 737 }
 738 */
 739
 740 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 741 {
 742         switch (mc_seq_vram_type) {
 743         case MC_SEQ_MISC0__MT__GDDR1:
 744                 return AMDGPU_VRAM_TYPE_GDDR1;
 745         case MC_SEQ_MISC0__MT__DDR2:
 746                 return AMDGPU_VRAM_TYPE_DDR2;
 747         case MC_SEQ_MISC0__MT__GDDR3:
 748                 return AMDGPU_VRAM_TYPE_GDDR3;
 749         case MC_SEQ_MISC0__MT__GDDR4:
 750                 return AMDGPU_VRAM_TYPE_GDDR4;
 751         case MC_SEQ_MISC0__MT__GDDR5:
 752                 return AMDGPU_VRAM_TYPE_GDDR5;
 753         case MC_SEQ_MISC0__MT__DDR3:
 754                 return AMDGPU_VRAM_TYPE_DDR3;
 755         default:
 756                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 757         }
 758 }
 759
 760 static int gmc_v6_0_early_init(void *handle)
 761 {
 762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 763
 764         gmc_v6_0_set_gart_funcs(adev);
 765         gmc_v6_0_set_irq_funcs(adev);
 766
 767         return 0;
 768 }
 769
 770 static int gmc_v6_0_late_init(void *handle)
 771 {
 772         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 773
 774         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 775                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 776         else
 777                 return 0;
 778 }
 779
 780 static int gmc_v6_0_sw_init(void *handle)
 781 {
 782         int r;
 783         int dma_bits;
 784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 785
 786         if (adev->flags & AMD_IS_APU) {
 787                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 788         } else {
 789                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 790                 tmp &= MC_SEQ_MISC0__MT__MASK;
 791                 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 792         }
 793
 794         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 795         if (r)
 796                 return r;
 797
 798         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 799         if (r)
 800                 return r;
 801
 802         amdgpu_vm_adjust_size(adev, 64);
 803         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 804
 805         adev->mc.mc_mask = 0xffffffffffULL;
 806
 807         adev->mc.stolen_size = 256 * 1024;
 808
 809         adev->need_dma32 = false;
 810         dma_bits = adev->need_dma32 ? 32 : 40;
 811         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 812         if (r) {
 813                 adev->need_dma32 = true;
 814                 dma_bits = 32;
 815                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 816         }
 817         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 818         if (r) {
 819                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 820                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 821         }
 822
 823         r = gmc_v6_0_init_microcode(adev);
 824         if (r) {
 825                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 826                 return r;
 827         }
 828
 829         r = gmc_v6_0_mc_init(adev);
 830         if (r)
 831                 return r;
 832
 833         r = amdgpu_bo_init(adev);
 834         if (r)
 835                 return r;
 836
 837         r = gmc_v6_0_gart_init(adev);
 838         if (r)
 839                 return r;
 840
 841         /*
 842          * number of VMs
 843          * VMID 0 is reserved for System
 844          * amdgpu graphics/compute will use VMIDs 1-7
 845          * amdkfd will use VMIDs 8-15
 846          */
 847         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 848         adev->vm_manager.num_level = 1;
 849         amdgpu_vm_manager_init(adev);
 850
 851         /* base offset of vram pages */
 852         if (adev->flags & AMD_IS_APU) {
 853                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 854
 855                 tmp <<= 22;
 856                 adev->vm_manager.vram_base_offset = tmp;
 857         } else {
 858                 adev->vm_manager.vram_base_offset = 0;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int gmc_v6_0_sw_fini(void *handle)
 865 {
 866         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 867
 868         amdgpu_vm_manager_fini(adev);
 869         gmc_v6_0_gart_fini(adev);
 870         amdgpu_gem_force_release(adev);
 871         amdgpu_bo_fini(adev);
 872
 873         return 0;
 874 }
 875
 876 static int gmc_v6_0_hw_init(void *handle)
 877 {
 878         int r;
 879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880
 881         gmc_v6_0_mc_program(adev);
 882
 883         if (!(adev->flags & AMD_IS_APU)) {
 884                 r = gmc_v6_0_mc_load_microcode(adev);
 885                 if (r) {
 886                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 887                         return r;
 888                 }
 889         }
 890
 891         r = gmc_v6_0_gart_enable(adev);
 892         if (r)
 893                 return r;
 894
 895         return r;
 896 }
 897
 898 static int gmc_v6_0_hw_fini(void *handle)
 899 {
 900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 901
 902         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 903         gmc_v6_0_gart_disable(adev);
 904
 905         return 0;
 906 }
 907
 908 static int gmc_v6_0_suspend(void *handle)
 909 {
 910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 911
 912         gmc_v6_0_hw_fini(adev);
 913
 914         return 0;
 915 }
 916
 917 static int gmc_v6_0_resume(void *handle)
 918 {
 919         int r;
 920         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 921
 922         r = gmc_v6_0_hw_init(adev);
 923         if (r)
 924                 return r;
 925
 926         amdgpu_vm_reset_all_ids(adev);
 927
 928         return 0;
 929 }
 930
 931 static bool gmc_v6_0_is_idle(void *handle)
 932 {
 933         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 934         u32 tmp = RREG32(mmSRBM_STATUS);
 935
 936         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 937                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 938                 return false;
 939
 940         return true;
 941 }
 942
 943 static int gmc_v6_0_wait_for_idle(void *handle)
 944 {
 945         unsigned i;
 946         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 947
 948         for (i = 0; i < adev->usec_timeout; i++) {
 949                 if (gmc_v6_0_is_idle(handle))
 950                         return 0;
 951                 udelay(1);
 952         }
 953         return -ETIMEDOUT;
 954
 955 }
 956
 957 static int gmc_v6_0_soft_reset(void *handle)
 958 {
 959         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 960         u32 srbm_soft_reset = 0;
 961         u32 tmp = RREG32(mmSRBM_STATUS);
 962
 963         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 964                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 965                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 966
 967         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 968                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
 969                 if (!(adev->flags & AMD_IS_APU))
 970                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 971                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 972         }
 973
 974         if (srbm_soft_reset) {
 975                 gmc_v6_0_mc_stop(adev);
 976                 if (gmc_v6_0_wait_for_idle(adev)) {
 977                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
 978                 }
 979
 980
 981                 tmp = RREG32(mmSRBM_SOFT_RESET);
 982                 tmp |= srbm_soft_reset;
 983                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 984                 WREG32(mmSRBM_SOFT_RESET, tmp);
 985                 tmp = RREG32(mmSRBM_SOFT_RESET);
 986
 987                 udelay(50);
 988
 989                 tmp &= ~srbm_soft_reset;
 990                 WREG32(mmSRBM_SOFT_RESET, tmp);
 991                 tmp = RREG32(mmSRBM_SOFT_RESET);
 992
 993                 udelay(50);
 994
 995                 gmc_v6_0_mc_resume(adev);
 996                 udelay(50);
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1003                                              struct amdgpu_irq_src *src,
1004                                              unsigned type,
1005                                              enum amdgpu_interrupt_state state)
1006 {
1007         u32 tmp;
1008         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1009                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1010                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1011                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1012                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1013                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1014
1015         switch (state) {
1016         case AMDGPU_IRQ_STATE_DISABLE:
1017                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1018                 tmp &= ~bits;
1019                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1020                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1021                 tmp &= ~bits;
1022                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1023                 break;
1024         case AMDGPU_IRQ_STATE_ENABLE:
1025                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1026                 tmp |= bits;
1027                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1028                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1029                 tmp |= bits;
1030                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1031                 break;
1032         default:
1033                 break;
1034         }
1035
1036         return 0;
1037 }
1038
1039 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1040                                       struct amdgpu_irq_src *source,
1041                                       struct amdgpu_iv_entry *entry)
1042 {
1043         u32 addr, status;
1044
1045         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1046         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1047         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1048
1049         if (!addr && !status)
1050                 return 0;
1051
1052         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1053                 gmc_v6_0_set_fault_enable_default(adev, false);
1054
1055         if (printk_ratelimit()) {
1056                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1057                         entry->src_id, entry->src_data[0]);
1058                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1059                         addr);
1060                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1061                         status);
1062                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1063         }
1064
1065         return 0;
1066 }
1067
1068 static int gmc_v6_0_set_clockgating_state(void *handle,
1069                                           enum amd_clockgating_state state)
1070 {
1071         return 0;
1072 }
1073
1074 static int gmc_v6_0_set_powergating_state(void *handle,
1075                                           enum amd_powergating_state state)
1076 {
1077         return 0;
1078 }
1079
1080 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1081         .name = "gmc_v6_0",
1082         .early_init = gmc_v6_0_early_init,
1083         .late_init = gmc_v6_0_late_init,
1084         .sw_init = gmc_v6_0_sw_init,
1085         .sw_fini = gmc_v6_0_sw_fini,
1086         .hw_init = gmc_v6_0_hw_init,
1087         .hw_fini = gmc_v6_0_hw_fini,
1088         .suspend = gmc_v6_0_suspend,
1089         .resume = gmc_v6_0_resume,
1090         .is_idle = gmc_v6_0_is_idle,
1091         .wait_for_idle = gmc_v6_0_wait_for_idle,
1092         .soft_reset = gmc_v6_0_soft_reset,
1093         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1094         .set_powergating_state = gmc_v6_0_set_powergating_state,
1095 };
1096
1097 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1098         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1099         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1100         .set_prt = gmc_v6_0_set_prt,
1101         .get_vm_pde = gmc_v6_0_get_vm_pde,
1102         .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1103 };
1104
1105 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1106         .set = gmc_v6_0_vm_fault_interrupt_state,
1107         .process = gmc_v6_0_process_interrupt,
1108 };
1109
1110 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1111 {
1112         if (adev->gart.gart_funcs == NULL)
1113                 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1114 }
1115
1116 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1117 {
1118         adev->mc.vm_fault.num_types = 1;
1119         adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1120 }
1121
1122 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1123 {
1124         .type = AMD_IP_BLOCK_TYPE_GMC,
1125         .major = 6,
1126         .minor = 0,
1127         .rev = 0,
1128         .funcs = &gmc_v6_0_ip_funcs,
1129 };