drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  51                              struct ttm_mem_reg *mem, unsigned num_pages,
  52                              uint64_t offset, unsigned window,
  53                              struct amdgpu_ring *ring,
  54                              uint64_t *addr);
  55
  56 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  57 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  58
  59 /*
  60  * Global memory.
  61  */
  62 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  63 {
  64         return ttm_mem_global_init(ref->object);
  65 }
  66
  67 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  68 {
  69         ttm_mem_global_release(ref->object);
  70 }
  71
  72 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  73 {
  74         struct drm_global_reference *global_ref;
  75         struct amdgpu_ring *ring;
  76         struct amd_sched_rq *rq;
  77         int r;
  78
  79         adev->mman.mem_global_referenced = false;
  80         global_ref = &adev->mman.mem_global_ref;
  81         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  82         global_ref->size = sizeof(struct ttm_mem_global);
  83         global_ref->init = &amdgpu_ttm_mem_global_init;
  84         global_ref->release = &amdgpu_ttm_mem_global_release;
  85         r = drm_global_item_ref(global_ref);
  86         if (r) {
  87                 DRM_ERROR("Failed setting up TTM memory accounting "
  88                           "subsystem.\n");
  89                 goto error_mem;
  90         }
  91
  92         adev->mman.bo_global_ref.mem_glob =
  93                 adev->mman.mem_global_ref.object;
  94         global_ref = &adev->mman.bo_global_ref.ref;
  95         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  96         global_ref->size = sizeof(struct ttm_bo_global);
  97         global_ref->init = &ttm_bo_global_init;
  98         global_ref->release = &ttm_bo_global_release;
  99         r = drm_global_item_ref(global_ref);
 100         if (r) {
 101                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 102                 goto error_bo;
 103         }
 104
 105         mutex_init(&adev->mman.gtt_window_lock);
 106
 107         ring = adev->mman.buffer_funcs_ring;
 108         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 109         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 110                                   rq, amdgpu_sched_jobs);
 111         if (r) {
 112                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 113                 goto error_entity;
 114         }
 115
 116         adev->mman.mem_global_referenced = true;
 117
 118         return 0;
 119
 120 error_entity:
 121         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 122 error_bo:
 123         drm_global_item_unref(&adev->mman.mem_global_ref);
 124 error_mem:
 125         return r;
 126 }
 127
 128 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 129 {
 130         if (adev->mman.mem_global_referenced) {
 131                 amd_sched_entity_fini(adev->mman.entity.sched,
 132                                       &adev->mman.entity);
 133                 mutex_destroy(&adev->mman.gtt_window_lock);
 134                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 135                 drm_global_item_unref(&adev->mman.mem_global_ref);
 136                 adev->mman.mem_global_referenced = false;
 137         }
 138 }
 139
 140 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 141 {
 142         return 0;
 143 }
 144
 145 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 146                                 struct ttm_mem_type_manager *man)
 147 {
 148         struct amdgpu_device *adev;
 149
 150         adev = amdgpu_ttm_adev(bdev);
 151
 152         switch (type) {
 153         case TTM_PL_SYSTEM:
 154                 /* System memory */
 155                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                 man->available_caching = TTM_PL_MASK_CACHING;
 157                 man->default_caching = TTM_PL_FLAG_CACHED;
 158                 break;
 159         case TTM_PL_TT:
 160                 man->func = &amdgpu_gtt_mgr_func;
 161                 man->gpu_offset = adev->mc.gart_start;
 162                 man->available_caching = TTM_PL_MASK_CACHING;
 163                 man->default_caching = TTM_PL_FLAG_CACHED;
 164                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 165                 break;
 166         case TTM_PL_VRAM:
 167                 /* "On-card" video ram */
 168                 man->func = &amdgpu_vram_mgr_func;
 169                 man->gpu_offset = adev->mc.vram_start;
 170                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 171                              TTM_MEMTYPE_FLAG_MAPPABLE;
 172                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 173                 man->default_caching = TTM_PL_FLAG_WC;
 174                 break;
 175         case AMDGPU_PL_GDS:
 176         case AMDGPU_PL_GWS:
 177         case AMDGPU_PL_OA:
 178                 /* On-chip GDS memory*/
 179                 man->func = &ttm_bo_manager_func;
 180                 man->gpu_offset = 0;
 181                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 182                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 183                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 184                 break;
 185         default:
 186                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 187                 return -EINVAL;
 188         }
 189         return 0;
 190 }
 191
 192 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 193                                 struct ttm_placement *placement)
 194 {
 195         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 196         struct amdgpu_bo *abo;
 197         static const struct ttm_place placements = {
 198                 .fpfn = 0,
 199                 .lpfn = 0,
 200                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 201         };
 202
 203         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 204                 placement->placement = &placements;
 205                 placement->busy_placement = &placements;
 206                 placement->num_placement = 1;
 207                 placement->num_busy_placement = 1;
 208                 return;
 209         }
 210         abo = container_of(bo, struct amdgpu_bo, tbo);
 211         switch (bo->mem.mem_type) {
 212         case TTM_PL_VRAM:
 213                 if (adev->mman.buffer_funcs &&
 214                     adev->mman.buffer_funcs_ring &&
 215                     adev->mman.buffer_funcs_ring->ready == false) {
 216                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 217                 } else {
 218                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 219                 }
 220                 break;
 221         case TTM_PL_TT:
 222         default:
 223                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 224         }
 225         *placement = abo->placement;
 226 }
 227
 228 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 229 {
 230         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 231
 232         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 233                 return -EPERM;
 234         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 235                                           filp->private_data);
 236 }
 237
 238 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 239                              struct ttm_mem_reg *new_mem)
 240 {
 241         struct ttm_mem_reg *old_mem = &bo->mem;
 242
 243         BUG_ON(old_mem->mm_node != NULL);
 244         *old_mem = *new_mem;
 245         new_mem->mm_node = NULL;
 246 }
 247
 248 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 249                                     struct drm_mm_node *mm_node,
 250                                     struct ttm_mem_reg *mem)
 251 {
 252         uint64_t addr = 0;
 253
 254         if (mem->mem_type != TTM_PL_TT ||
 255             amdgpu_gtt_mgr_is_allocated(mem)) {
 256                 addr = mm_node->start << PAGE_SHIFT;
 257                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 258         }
 259         return addr;
 260 }
 261
 262 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 263                             bool evict, bool no_wait_gpu,
 264                             struct ttm_mem_reg *new_mem,
 265                             struct ttm_mem_reg *old_mem)
 266 {
 267         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 268         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 269
 270         struct drm_mm_node *old_mm, *new_mm;
 271         uint64_t old_start, old_size, new_start, new_size;
 272         unsigned long num_pages;
 273         struct dma_fence *fence = NULL;
 274         int r;
 275
 276         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 277
 278         if (!ring->ready) {
 279                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 280                 return -EINVAL;
 281         }
 282
 283         old_mm = old_mem->mm_node;
 284         old_size = old_mm->size;
 285         old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
 286
 287         new_mm = new_mem->mm_node;
 288         new_size = new_mm->size;
 289         new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
 290
 291         num_pages = new_mem->num_pages;
 292         mutex_lock(&adev->mman.gtt_window_lock);
 293         while (num_pages) {
 294                 unsigned long cur_pages = min(min(old_size, new_size),
 295                                               (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
 296                 uint64_t from = old_start, to = new_start;
 297                 struct dma_fence *next;
 298
 299                 if (old_mem->mem_type == TTM_PL_TT &&
 300                     !amdgpu_gtt_mgr_is_allocated(old_mem)) {
 301                         r = amdgpu_map_buffer(bo, old_mem, cur_pages,
 302                                               old_start, 0, ring, &from);
 303                         if (r)
 304                                 goto error;
 305                 }
 306
 307                 if (new_mem->mem_type == TTM_PL_TT &&
 308                     !amdgpu_gtt_mgr_is_allocated(new_mem)) {
 309                         r = amdgpu_map_buffer(bo, new_mem, cur_pages,
 310                                               new_start, 1, ring, &to);
 311                         if (r)
 312                                 goto error;
 313                 }
 314
 315                 r = amdgpu_copy_buffer(ring, from, to,
 316                                        cur_pages * PAGE_SIZE,
 317                                        bo->resv, &next, false, true);
 318                 if (r)
 319                         goto error;
 320
 321                 dma_fence_put(fence);
 322                 fence = next;
 323
 324                 num_pages -= cur_pages;
 325                 if (!num_pages)
 326                         break;
 327
 328                 old_size -= cur_pages;
 329                 if (!old_size) {
 330                         old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
 331                         old_size = old_mm->size;
 332                 } else {
 333                         old_start += cur_pages * PAGE_SIZE;
 334                 }
 335
 336                 new_size -= cur_pages;
 337                 if (!new_size) {
 338                         new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
 339                         new_size = new_mm->size;
 340                 } else {
 341                         new_start += cur_pages * PAGE_SIZE;
 342                 }
 343         }
 344         mutex_unlock(&adev->mman.gtt_window_lock);
 345
 346         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 347         dma_fence_put(fence);
 348         return r;
 349
 350 error:
 351         mutex_unlock(&adev->mman.gtt_window_lock);
 352
 353         if (fence)
 354                 dma_fence_wait(fence, false);
 355         dma_fence_put(fence);
 356         return r;
 357 }
 358
 359 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 360                                 bool evict, bool interruptible,
 361                                 bool no_wait_gpu,
 362                                 struct ttm_mem_reg *new_mem)
 363 {
 364         struct amdgpu_device *adev;
 365         struct ttm_mem_reg *old_mem = &bo->mem;
 366         struct ttm_mem_reg tmp_mem;
 367         struct ttm_place placements;
 368         struct ttm_placement placement;
 369         int r;
 370
 371         adev = amdgpu_ttm_adev(bo->bdev);
 372         tmp_mem = *new_mem;
 373         tmp_mem.mm_node = NULL;
 374         placement.num_placement = 1;
 375         placement.placement = &placements;
 376         placement.num_busy_placement = 1;
 377         placement.busy_placement = &placements;
 378         placements.fpfn = 0;
 379         placements.lpfn = 0;
 380         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 381         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 382                              interruptible, no_wait_gpu);
 383         if (unlikely(r)) {
 384                 return r;
 385         }
 386
 387         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 388         if (unlikely(r)) {
 389                 goto out_cleanup;
 390         }
 391
 392         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 393         if (unlikely(r)) {
 394                 goto out_cleanup;
 395         }
 396         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 397         if (unlikely(r)) {
 398                 goto out_cleanup;
 399         }
 400         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 401 out_cleanup:
 402         ttm_bo_mem_put(bo, &tmp_mem);
 403         return r;
 404 }
 405
 406 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 407                                 bool evict, bool interruptible,
 408                                 bool no_wait_gpu,
 409                                 struct ttm_mem_reg *new_mem)
 410 {
 411         struct amdgpu_device *adev;
 412         struct ttm_mem_reg *old_mem = &bo->mem;
 413         struct ttm_mem_reg tmp_mem;
 414         struct ttm_placement placement;
 415         struct ttm_place placements;
 416         int r;
 417
 418         adev = amdgpu_ttm_adev(bo->bdev);
 419         tmp_mem = *new_mem;
 420         tmp_mem.mm_node = NULL;
 421         placement.num_placement = 1;
 422         placement.placement = &placements;
 423         placement.num_busy_placement = 1;
 424         placement.busy_placement = &placements;
 425         placements.fpfn = 0;
 426         placements.lpfn = 0;
 427         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 428         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 429                              interruptible, no_wait_gpu);
 430         if (unlikely(r)) {
 431                 return r;
 432         }
 433         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 434         if (unlikely(r)) {
 435                 goto out_cleanup;
 436         }
 437         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 438         if (unlikely(r)) {
 439                 goto out_cleanup;
 440         }
 441 out_cleanup:
 442         ttm_bo_mem_put(bo, &tmp_mem);
 443         return r;
 444 }
 445
 446 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 447                         bool evict, bool interruptible,
 448                         bool no_wait_gpu,
 449                         struct ttm_mem_reg *new_mem)
 450 {
 451         struct amdgpu_device *adev;
 452         struct amdgpu_bo *abo;
 453         struct ttm_mem_reg *old_mem = &bo->mem;
 454         int r;
 455
 456         /* Can't move a pinned BO */
 457         abo = container_of(bo, struct amdgpu_bo, tbo);
 458         if (WARN_ON_ONCE(abo->pin_count > 0))
 459                 return -EINVAL;
 460
 461         adev = amdgpu_ttm_adev(bo->bdev);
 462
 463         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 464                 amdgpu_move_null(bo, new_mem);
 465                 return 0;
 466         }
 467         if ((old_mem->mem_type == TTM_PL_TT &&
 468              new_mem->mem_type == TTM_PL_SYSTEM) ||
 469             (old_mem->mem_type == TTM_PL_SYSTEM &&
 470              new_mem->mem_type == TTM_PL_TT)) {
 471                 /* bind is enough */
 472                 amdgpu_move_null(bo, new_mem);
 473                 return 0;
 474         }
 475         if (adev->mman.buffer_funcs == NULL ||
 476             adev->mman.buffer_funcs_ring == NULL ||
 477             !adev->mman.buffer_funcs_ring->ready) {
 478                 /* use memcpy */
 479                 goto memcpy;
 480         }
 481
 482         if (old_mem->mem_type == TTM_PL_VRAM &&
 483             new_mem->mem_type == TTM_PL_SYSTEM) {
 484                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 485                                         no_wait_gpu, new_mem);
 486         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 487                    new_mem->mem_type == TTM_PL_VRAM) {
 488                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 489                                             no_wait_gpu, new_mem);
 490         } else {
 491                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 492         }
 493
 494         if (r) {
 495 memcpy:
 496                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 497                 if (r) {
 498                         return r;
 499                 }
 500         }
 501
 502         /* update statistics */
 503         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 504         return 0;
 505 }
 506
 507 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 508 {
 509         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 510         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 511
 512         mem->bus.addr = NULL;
 513         mem->bus.offset = 0;
 514         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 515         mem->bus.base = 0;
 516         mem->bus.is_iomem = false;
 517         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 518                 return -EINVAL;
 519         switch (mem->mem_type) {
 520         case TTM_PL_SYSTEM:
 521                 /* system memory */
 522                 return 0;
 523         case TTM_PL_TT:
 524                 break;
 525         case TTM_PL_VRAM:
 526                 mem->bus.offset = mem->start << PAGE_SHIFT;
 527                 /* check if it's visible */
 528                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 529                         return -EINVAL;
 530                 mem->bus.base = adev->mc.aper_base;
 531                 mem->bus.is_iomem = true;
 532                 break;
 533         default:
 534                 return -EINVAL;
 535         }
 536         return 0;
 537 }
 538
 539 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 540 {
 541 }
 542
 543 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 544                                            unsigned long page_offset)
 545 {
 546         struct drm_mm_node *mm = bo->mem.mm_node;
 547         uint64_t size = mm->size;
 548         uint64_t offset = page_offset;
 549
 550         page_offset = do_div(offset, size);
 551         mm += offset;
 552         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 553 }
 554
 555 /*
 556  * TTM backend functions.
 557  */
 558 struct amdgpu_ttm_gup_task_list {
 559         struct list_head        list;
 560         struct task_struct      *task;
 561 };
 562
 563 struct amdgpu_ttm_tt {
 564         struct ttm_dma_tt       ttm;
 565         struct amdgpu_device    *adev;
 566         u64                     offset;
 567         uint64_t                userptr;
 568         struct mm_struct        *usermm;
 569         uint32_t                userflags;
 570         spinlock_t              guptasklock;
 571         struct list_head        guptasks;
 572         atomic_t                mmu_invalidations;
 573         struct list_head        list;
 574 };
 575
 576 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 577 {
 578         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 579         unsigned int flags = 0;
 580         unsigned pinned = 0;
 581         int r;
 582
 583         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 584                 flags |= FOLL_WRITE;
 585
 586         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 587                 /* check that we only use anonymous memory
 588                    to prevent problems with writeback */
 589                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 590                 struct vm_area_struct *vma;
 591
 592                 vma = find_vma(gtt->usermm, gtt->userptr);
 593                 if (!vma || vma->vm_file || vma->vm_end < end)
 594                         return -EPERM;
 595         }
 596
 597         do {
 598                 unsigned num_pages = ttm->num_pages - pinned;
 599                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 600                 struct page **p = pages + pinned;
 601                 struct amdgpu_ttm_gup_task_list guptask;
 602
 603                 guptask.task = current;
 604                 spin_lock(&gtt->guptasklock);
 605                 list_add(&guptask.list, &gtt->guptasks);
 606                 spin_unlock(&gtt->guptasklock);
 607
 608                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 609
 610                 spin_lock(&gtt->guptasklock);
 611                 list_del(&guptask.list);
 612                 spin_unlock(&gtt->guptasklock);
 613
 614                 if (r < 0)
 615                         goto release_pages;
 616
 617                 pinned += r;
 618
 619         } while (pinned < ttm->num_pages);
 620
 621         return 0;
 622
 623 release_pages:
 624         release_pages(pages, pinned, 0);
 625         return r;
 626 }
 627
 628 /* prepare the sg table with the user pages */
 629 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 630 {
 631         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 632         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 633         unsigned nents;
 634         int r;
 635
 636         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 637         enum dma_data_direction direction = write ?
 638                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 639
 640         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 641                                       ttm->num_pages << PAGE_SHIFT,
 642                                       GFP_KERNEL);
 643         if (r)
 644                 goto release_sg;
 645
 646         r = -ENOMEM;
 647         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 648         if (nents != ttm->sg->nents)
 649                 goto release_sg;
 650
 651         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 652                                          gtt->ttm.dma_address, ttm->num_pages);
 653
 654         return 0;
 655
 656 release_sg:
 657         kfree(ttm->sg);
 658         return r;
 659 }
 660
 661 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 662 {
 663         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 664         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 665         struct sg_page_iter sg_iter;
 666
 667         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 668         enum dma_data_direction direction = write ?
 669                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 670
 671         /* double check that we don't free the table twice */
 672         if (!ttm->sg->sgl)
 673                 return;
 674
 675         /* free the sg table and pages again */
 676         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 677
 678         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 679                 struct page *page = sg_page_iter_page(&sg_iter);
 680                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 681                         set_page_dirty(page);
 682
 683                 mark_page_accessed(page);
 684                 put_page(page);
 685         }
 686
 687         sg_free_table(ttm->sg);
 688 }
 689
 690 static int amdgpu_ttm_do_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
 691 {
 692         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 693         uint64_t flags;
 694         int r;
 695
 696         spin_lock(&gtt->adev->gtt_list_lock);
 697         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, mem);
 698         gtt->offset = (u64)mem->start << PAGE_SHIFT;
 699         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 700                 ttm->pages, gtt->ttm.dma_address, flags);
 701
 702         if (r) {
 703                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 704                           ttm->num_pages, gtt->offset);
 705                 goto error_gart_bind;
 706         }
 707
 708         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 709 error_gart_bind:
 710         spin_unlock(&gtt->adev->gtt_list_lock);
 711         return r;
 712
 713 }
 714
 715 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 716                                    struct ttm_mem_reg *bo_mem)
 717 {
 718         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 719         int r;
 720
 721         if (gtt->userptr) {
 722                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 723                 if (r) {
 724                         DRM_ERROR("failed to pin userptr\n");
 725                         return r;
 726                 }
 727         }
 728         if (!ttm->num_pages) {
 729                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 730                      ttm->num_pages, bo_mem, ttm);
 731         }
 732
 733         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 734             bo_mem->mem_type == AMDGPU_PL_GWS ||
 735             bo_mem->mem_type == AMDGPU_PL_OA)
 736                 return -EINVAL;
 737
 738         if (amdgpu_gtt_mgr_is_allocated(bo_mem))
 739             r = amdgpu_ttm_do_bind(ttm, bo_mem);
 740
 741         return r;
 742 }
 743
 744 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 745 {
 746         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 747
 748         return gtt && !list_empty(&gtt->list);
 749 }
 750
 751 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 752 {
 753         struct ttm_tt *ttm = bo->ttm;
 754         int r;
 755
 756         if (!ttm || amdgpu_ttm_is_bound(ttm))
 757                 return 0;
 758
 759         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 760                                  NULL, bo_mem);
 761         if (r) {
 762                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 763                 return r;
 764         }
 765
 766         return amdgpu_ttm_do_bind(ttm, bo_mem);
 767 }
 768
 769 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 770 {
 771         struct amdgpu_ttm_tt *gtt, *tmp;
 772         struct ttm_mem_reg bo_mem;
 773         uint64_t flags;
 774         int r;
 775
 776         bo_mem.mem_type = TTM_PL_TT;
 777         spin_lock(&adev->gtt_list_lock);
 778         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 779                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 780                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 781                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 782                                      flags);
 783                 if (r) {
 784                         spin_unlock(&adev->gtt_list_lock);
 785                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 786                                   gtt->ttm.ttm.num_pages, gtt->offset);
 787                         return r;
 788                 }
 789         }
 790         spin_unlock(&adev->gtt_list_lock);
 791         return 0;
 792 }
 793
 794 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 795 {
 796         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 797         int r;
 798
 799         if (gtt->userptr)
 800                 amdgpu_ttm_tt_unpin_userptr(ttm);
 801
 802         if (!amdgpu_ttm_is_bound(ttm))
 803                 return 0;
 804
 805         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 806         spin_lock(&gtt->adev->gtt_list_lock);
 807         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 808         if (r) {
 809                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 810                           gtt->ttm.ttm.num_pages, gtt->offset);
 811                 goto error_unbind;
 812         }
 813         list_del_init(&gtt->list);
 814 error_unbind:
 815         spin_unlock(&gtt->adev->gtt_list_lock);
 816         return r;
 817 }
 818
 819 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 820 {
 821         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 822
 823         ttm_dma_tt_fini(&gtt->ttm);
 824         kfree(gtt);
 825 }
 826
 827 static struct ttm_backend_func amdgpu_backend_func = {
 828         .bind = &amdgpu_ttm_backend_bind,
 829         .unbind = &amdgpu_ttm_backend_unbind,
 830         .destroy = &amdgpu_ttm_backend_destroy,
 831 };
 832
 833 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 834                                     unsigned long size, uint32_t page_flags,
 835                                     struct page *dummy_read_page)
 836 {
 837         struct amdgpu_device *adev;
 838         struct amdgpu_ttm_tt *gtt;
 839
 840         adev = amdgpu_ttm_adev(bdev);
 841
 842         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 843         if (gtt == NULL) {
 844                 return NULL;
 845         }
 846         gtt->ttm.ttm.func = &amdgpu_backend_func;
 847         gtt->adev = adev;
 848         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 849                 kfree(gtt);
 850                 return NULL;
 851         }
 852         INIT_LIST_HEAD(&gtt->list);
 853         return &gtt->ttm.ttm;
 854 }
 855
 856 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 857 {
 858         struct amdgpu_device *adev;
 859         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 860         unsigned i;
 861         int r;
 862         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 863
 864         if (ttm->state != tt_unpopulated)
 865                 return 0;
 866
 867         if (gtt && gtt->userptr) {
 868                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 869                 if (!ttm->sg)
 870                         return -ENOMEM;
 871
 872                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 873                 ttm->state = tt_unbound;
 874                 return 0;
 875         }
 876
 877         if (slave && ttm->sg) {
 878                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 879                                                  gtt->ttm.dma_address, ttm->num_pages);
 880                 ttm->state = tt_unbound;
 881                 return 0;
 882         }
 883
 884         adev = amdgpu_ttm_adev(ttm->bdev);
 885
 886 #ifdef CONFIG_SWIOTLB
 887         if (swiotlb_nr_tbl()) {
 888                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 889         }
 890 #endif
 891
 892         r = ttm_pool_populate(ttm);
 893         if (r) {
 894                 return r;
 895         }
 896
 897         for (i = 0; i < ttm->num_pages; i++) {
 898                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 899                                                        0, PAGE_SIZE,
 900                                                        PCI_DMA_BIDIRECTIONAL);
 901                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 902                         while (i--) {
 903                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 904                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 905                                 gtt->ttm.dma_address[i] = 0;
 906                         }
 907                         ttm_pool_unpopulate(ttm);
 908                         return -EFAULT;
 909                 }
 910         }
 911         return 0;
 912 }
 913
 914 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 915 {
 916         struct amdgpu_device *adev;
 917         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 918         unsigned i;
 919         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 920
 921         if (gtt && gtt->userptr) {
 922                 kfree(ttm->sg);
 923                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 924                 return;
 925         }
 926
 927         if (slave)
 928                 return;
 929
 930         adev = amdgpu_ttm_adev(ttm->bdev);
 931
 932 #ifdef CONFIG_SWIOTLB
 933         if (swiotlb_nr_tbl()) {
 934                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 935                 return;
 936         }
 937 #endif
 938
 939         for (i = 0; i < ttm->num_pages; i++) {
 940                 if (gtt->ttm.dma_address[i]) {
 941                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 942                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 943                 }
 944         }
 945
 946         ttm_pool_unpopulate(ttm);
 947 }
 948
 949 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 950                               uint32_t flags)
 951 {
 952         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 953
 954         if (gtt == NULL)
 955                 return -EINVAL;
 956
 957         gtt->userptr = addr;
 958         gtt->usermm = current->mm;
 959         gtt->userflags = flags;
 960         spin_lock_init(&gtt->guptasklock);
 961         INIT_LIST_HEAD(&gtt->guptasks);
 962         atomic_set(&gtt->mmu_invalidations, 0);
 963
 964         return 0;
 965 }
 966
 967 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 968 {
 969         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 970
 971         if (gtt == NULL)
 972                 return NULL;
 973
 974         return gtt->usermm;
 975 }
 976
 977 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 978                                   unsigned long end)
 979 {
 980         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 981         struct amdgpu_ttm_gup_task_list *entry;
 982         unsigned long size;
 983
 984         if (gtt == NULL || !gtt->userptr)
 985                 return false;
 986
 987         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 988         if (gtt->userptr > end || gtt->userptr + size <= start)
 989                 return false;
 990
 991         spin_lock(&gtt->guptasklock);
 992         list_for_each_entry(entry, &gtt->guptasks, list) {
 993                 if (entry->task == current) {
 994                         spin_unlock(&gtt->guptasklock);
 995                         return false;
 996                 }
 997         }
 998         spin_unlock(&gtt->guptasklock);
 999
1000         atomic_inc(&gtt->mmu_invalidations);
1001
1002         return true;
1003 }
1004
1005 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1006                                        int *last_invalidated)
1007 {
1008         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1009         int prev_invalidated = *last_invalidated;
1010
1011         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1012         return prev_invalidated != *last_invalidated;
1013 }
1014
1015 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1016 {
1017         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1018
1019         if (gtt == NULL)
1020                 return false;
1021
1022         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1023 }
1024
1025 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1026                                  struct ttm_mem_reg *mem)
1027 {
1028         uint64_t flags = 0;
1029
1030         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1031                 flags |= AMDGPU_PTE_VALID;
1032
1033         if (mem && mem->mem_type == TTM_PL_TT) {
1034                 flags |= AMDGPU_PTE_SYSTEM;
1035
1036                 if (ttm->caching_state == tt_cached)
1037                         flags |= AMDGPU_PTE_SNOOPED;
1038         }
1039
1040         flags |= adev->gart.gart_pte_flags;
1041         flags |= AMDGPU_PTE_READABLE;
1042
1043         if (!amdgpu_ttm_tt_is_readonly(ttm))
1044                 flags |= AMDGPU_PTE_WRITEABLE;
1045
1046         return flags;
1047 }
1048
1049 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1050                                             const struct ttm_place *place)
1051 {
1052         unsigned long num_pages = bo->mem.num_pages;
1053         struct drm_mm_node *node = bo->mem.mm_node;
1054
1055         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1056                 return ttm_bo_eviction_valuable(bo, place);
1057
1058         switch (bo->mem.mem_type) {
1059         case TTM_PL_TT:
1060                 return true;
1061
1062         case TTM_PL_VRAM:
1063                 /* Check each drm MM node individually */
1064                 while (num_pages) {
1065                         if (place->fpfn < (node->start + node->size) &&
1066                             !(place->lpfn && place->lpfn <= node->start))
1067                                 return true;
1068
1069                         num_pages -= node->size;
1070                         ++node;
1071                 }
1072                 break;
1073
1074         default:
1075                 break;
1076         }
1077
1078         return ttm_bo_eviction_valuable(bo, place);
1079 }
1080
1081 static struct ttm_bo_driver amdgpu_bo_driver = {
1082         .ttm_tt_create = &amdgpu_ttm_tt_create,
1083         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1084         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1085         .invalidate_caches = &amdgpu_invalidate_caches,
1086         .init_mem_type = &amdgpu_init_mem_type,
1087         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1088         .evict_flags = &amdgpu_evict_flags,
1089         .move = &amdgpu_bo_move,
1090         .verify_access = &amdgpu_verify_access,
1091         .move_notify = &amdgpu_bo_move_notify,
1092         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1093         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1094         .io_mem_free = &amdgpu_ttm_io_mem_free,
1095         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1096 };
1097
1098 int amdgpu_ttm_init(struct amdgpu_device *adev)
1099 {
1100         int r;
1101
1102         r = amdgpu_ttm_global_init(adev);
1103         if (r) {
1104                 return r;
1105         }
1106         /* No others user of address space so set it to 0 */
1107         r = ttm_bo_device_init(&adev->mman.bdev,
1108                                adev->mman.bo_global_ref.ref.object,
1109                                &amdgpu_bo_driver,
1110                                adev->ddev->anon_inode->i_mapping,
1111                                DRM_FILE_PAGE_OFFSET,
1112                                adev->need_dma32);
1113         if (r) {
1114                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1115                 return r;
1116         }
1117         adev->mman.initialized = true;
1118         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1119                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1120         if (r) {
1121                 DRM_ERROR("Failed initializing VRAM heap.\n");
1122                 return r;
1123         }
1124         /* Change the size here instead of the init above so only lpfn is affected */
1125         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1126
1127         r = amdgpu_bo_create(adev, adev->mc.stolen_size, PAGE_SIZE, true,
1128                              AMDGPU_GEM_DOMAIN_VRAM,
1129                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1130                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1131                              NULL, NULL, &adev->stollen_vga_memory);
1132         if (r) {
1133                 return r;
1134         }
1135         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1136         if (r)
1137                 return r;
1138         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1139         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1140         if (r) {
1141                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1142                 return r;
1143         }
1144         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1145                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1146         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1147                                 adev->mc.gart_size >> PAGE_SHIFT);
1148         if (r) {
1149                 DRM_ERROR("Failed initializing GTT heap.\n");
1150                 return r;
1151         }
1152         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1153                  (unsigned)(adev->mc.gart_size / (1024 * 1024)));
1154
1155         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1156         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1157         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1158         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1159         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1160         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1161         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1162         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1163         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1164         /* GDS Memory */
1165         if (adev->gds.mem.total_size) {
1166                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1167                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1168                 if (r) {
1169                         DRM_ERROR("Failed initializing GDS heap.\n");
1170                         return r;
1171                 }
1172         }
1173
1174         /* GWS */
1175         if (adev->gds.gws.total_size) {
1176                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1177                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1178                 if (r) {
1179                         DRM_ERROR("Failed initializing gws heap.\n");
1180                         return r;
1181                 }
1182         }
1183
1184         /* OA */
1185         if (adev->gds.oa.total_size) {
1186                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1187                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1188                 if (r) {
1189                         DRM_ERROR("Failed initializing oa heap.\n");
1190                         return r;
1191                 }
1192         }
1193
1194         r = amdgpu_ttm_debugfs_init(adev);
1195         if (r) {
1196                 DRM_ERROR("Failed to init debugfs\n");
1197                 return r;
1198         }
1199         return 0;
1200 }
1201
1202 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1203 {
1204         int r;
1205
1206         if (!adev->mman.initialized)
1207                 return;
1208         amdgpu_ttm_debugfs_fini(adev);
1209         if (adev->stollen_vga_memory) {
1210                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, true);
1211                 if (r == 0) {
1212                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1213                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1214                 }
1215                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1216         }
1217         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1218         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1219         if (adev->gds.mem.total_size)
1220                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1221         if (adev->gds.gws.total_size)
1222                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1223         if (adev->gds.oa.total_size)
1224                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1225         ttm_bo_device_release(&adev->mman.bdev);
1226         amdgpu_gart_fini(adev);
1227         amdgpu_ttm_global_fini(adev);
1228         adev->mman.initialized = false;
1229         DRM_INFO("amdgpu: ttm finalized\n");
1230 }
1231
1232 /* this should only be called at bootup or when userspace
1233  * isn't running */
1234 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1235 {
1236         struct ttm_mem_type_manager *man;
1237
1238         if (!adev->mman.initialized)
1239                 return;
1240
1241         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1242         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1243         man->size = size >> PAGE_SHIFT;
1244 }
1245
1246 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1247 {
1248         struct drm_file *file_priv;
1249         struct amdgpu_device *adev;
1250
1251         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1252                 return -EINVAL;
1253
1254         file_priv = filp->private_data;
1255         adev = file_priv->minor->dev->dev_private;
1256         if (adev == NULL)
1257                 return -EINVAL;
1258
1259         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1260 }
1261
1262 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1263                              struct ttm_mem_reg *mem, unsigned num_pages,
1264                              uint64_t offset, unsigned window,
1265                              struct amdgpu_ring *ring,
1266                              uint64_t *addr)
1267 {
1268         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1269         struct amdgpu_device *adev = ring->adev;
1270         struct ttm_tt *ttm = bo->ttm;
1271         struct amdgpu_job *job;
1272         unsigned num_dw, num_bytes;
1273         dma_addr_t *dma_address;
1274         struct dma_fence *fence;
1275         uint64_t src_addr, dst_addr;
1276         uint64_t flags;
1277         int r;
1278
1279         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1280                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1281
1282         *addr = adev->mc.gart_start;
1283         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1284                 AMDGPU_GPU_PAGE_SIZE;
1285
1286         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1287         while (num_dw & 0x7)
1288                 num_dw++;
1289
1290         num_bytes = num_pages * 8;
1291
1292         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1293         if (r)
1294                 return r;
1295
1296         src_addr = num_dw * 4;
1297         src_addr += job->ibs[0].gpu_addr;
1298
1299         dst_addr = adev->gart.table_addr;
1300         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1301         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1302                                 dst_addr, num_bytes);
1303
1304         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1305         WARN_ON(job->ibs[0].length_dw > num_dw);
1306
1307         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1308         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1309         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1310                             &job->ibs[0].ptr[num_dw]);
1311         if (r)
1312                 goto error_free;
1313
1314         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1315                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1316         if (r)
1317                 goto error_free;
1318
1319         dma_fence_put(fence);
1320
1321         return r;
1322
1323 error_free:
1324         amdgpu_job_free(job);
1325         return r;
1326 }
1327
1328 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1329                        uint64_t dst_offset, uint32_t byte_count,
1330                        struct reservation_object *resv,
1331                        struct dma_fence **fence, bool direct_submit,
1332                        bool vm_needs_flush)
1333 {
1334         struct amdgpu_device *adev = ring->adev;
1335         struct amdgpu_job *job;
1336
1337         uint32_t max_bytes;
1338         unsigned num_loops, num_dw;
1339         unsigned i;
1340         int r;
1341
1342         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1343         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1344         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1345
1346         /* for IB padding */
1347         while (num_dw & 0x7)
1348                 num_dw++;
1349
1350         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1351         if (r)
1352                 return r;
1353
1354         job->vm_needs_flush = vm_needs_flush;
1355         if (resv) {
1356                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1357                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1358                 if (r) {
1359                         DRM_ERROR("sync failed (%d).\n", r);
1360                         goto error_free;
1361                 }
1362         }
1363
1364         for (i = 0; i < num_loops; i++) {
1365                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1366
1367                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1368                                         dst_offset, cur_size_in_bytes);
1369
1370                 src_offset += cur_size_in_bytes;
1371                 dst_offset += cur_size_in_bytes;
1372                 byte_count -= cur_size_in_bytes;
1373         }
1374
1375         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1376         WARN_ON(job->ibs[0].length_dw > num_dw);
1377         if (direct_submit) {
1378                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1379                                        NULL, fence);
1380                 job->fence = dma_fence_get(*fence);
1381                 if (r)
1382                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1383                 amdgpu_job_free(job);
1384         } else {
1385                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1386                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1387                 if (r)
1388                         goto error_free;
1389         }
1390
1391         return r;
1392
1393 error_free:
1394         amdgpu_job_free(job);
1395         return r;
1396 }
1397
1398 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1399                        uint32_t src_data,
1400                        struct reservation_object *resv,
1401                        struct dma_fence **fence)
1402 {
1403         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1404         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1405         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1406
1407         struct drm_mm_node *mm_node;
1408         unsigned long num_pages;
1409         unsigned int num_loops, num_dw;
1410
1411         struct amdgpu_job *job;
1412         int r;
1413
1414         if (!ring->ready) {
1415                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1416                 return -EINVAL;
1417         }
1418
1419         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1420                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1421                 if (r)
1422                         return r;
1423         }
1424
1425         num_pages = bo->tbo.num_pages;
1426         mm_node = bo->tbo.mem.mm_node;
1427         num_loops = 0;
1428         while (num_pages) {
1429                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1430
1431                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1432                 num_pages -= mm_node->size;
1433                 ++mm_node;
1434         }
1435         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1436
1437         /* for IB padding */
1438         num_dw += 64;
1439
1440         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1441         if (r)
1442                 return r;
1443
1444         if (resv) {
1445                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1446                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1447                 if (r) {
1448                         DRM_ERROR("sync failed (%d).\n", r);
1449                         goto error_free;
1450                 }
1451         }
1452
1453         num_pages = bo->tbo.num_pages;
1454         mm_node = bo->tbo.mem.mm_node;
1455
1456         while (num_pages) {
1457                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1458                 uint64_t dst_addr;
1459
1460                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1461                 while (byte_count) {
1462                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1463
1464                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1465                                                 dst_addr, cur_size_in_bytes);
1466
1467                         dst_addr += cur_size_in_bytes;
1468                         byte_count -= cur_size_in_bytes;
1469                 }
1470
1471                 num_pages -= mm_node->size;
1472                 ++mm_node;
1473         }
1474
1475         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1476         WARN_ON(job->ibs[0].length_dw > num_dw);
1477         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1478                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1479         if (r)
1480                 goto error_free;
1481
1482         return 0;
1483
1484 error_free:
1485         amdgpu_job_free(job);
1486         return r;
1487 }
1488
1489 #if defined(CONFIG_DEBUG_FS)
1490
1491 extern void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager
1492                                  *man);
1493 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1494 {
1495         struct drm_info_node *node = (struct drm_info_node *)m->private;
1496         unsigned ttm_pl = *(int *)node->info_ent->data;
1497         struct drm_device *dev = node->minor->dev;
1498         struct amdgpu_device *adev = dev->dev_private;
1499         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1500         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1501         struct drm_printer p = drm_seq_file_printer(m);
1502
1503         spin_lock(&glob->lru_lock);
1504         drm_mm_print(mm, &p);
1505         spin_unlock(&glob->lru_lock);
1506         switch (ttm_pl) {
1507         case TTM_PL_VRAM:
1508                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1509                            adev->mman.bdev.man[ttm_pl].size,
1510                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1511                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1512                 break;
1513         case TTM_PL_TT:
1514                 amdgpu_gtt_mgr_print(m, &adev->mman.bdev.man[TTM_PL_TT]);
1515                 break;
1516         }
1517         return 0;
1518 }
1519
1520 static int ttm_pl_vram = TTM_PL_VRAM;
1521 static int ttm_pl_tt = TTM_PL_TT;
1522
1523 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1524         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1525         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1526         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1527 #ifdef CONFIG_SWIOTLB
1528         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1529 #endif
1530 };
1531
1532 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1533                                     size_t size, loff_t *pos)
1534 {
1535         struct amdgpu_device *adev = file_inode(f)->i_private;
1536         ssize_t result = 0;
1537         int r;
1538
1539         if (size & 0x3 || *pos & 0x3)
1540                 return -EINVAL;
1541
1542         if (*pos >= adev->mc.mc_vram_size)
1543                 return -ENXIO;
1544
1545         while (size) {
1546                 unsigned long flags;
1547                 uint32_t value;
1548
1549                 if (*pos >= adev->mc.mc_vram_size)
1550                         return result;
1551
1552                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1553                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1554                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1555                 value = RREG32(mmMM_DATA);
1556                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1557
1558                 r = put_user(value, (uint32_t *)buf);
1559                 if (r)
1560                         return r;
1561
1562                 result += 4;
1563                 buf += 4;
1564                 *pos += 4;
1565                 size -= 4;
1566         }
1567
1568         return result;
1569 }
1570
1571 static const struct file_operations amdgpu_ttm_vram_fops = {
1572         .owner = THIS_MODULE,
1573         .read = amdgpu_ttm_vram_read,
1574         .llseek = default_llseek
1575 };
1576
1577 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1578
1579 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1580                                    size_t size, loff_t *pos)
1581 {
1582         struct amdgpu_device *adev = file_inode(f)->i_private;
1583         ssize_t result = 0;
1584         int r;
1585
1586         while (size) {
1587                 loff_t p = *pos / PAGE_SIZE;
1588                 unsigned off = *pos & ~PAGE_MASK;
1589                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1590                 struct page *page;
1591                 void *ptr;
1592
1593                 if (p >= adev->gart.num_cpu_pages)
1594                         return result;
1595
1596                 page = adev->gart.pages[p];
1597                 if (page) {
1598                         ptr = kmap(page);
1599                         ptr += off;
1600
1601                         r = copy_to_user(buf, ptr, cur_size);
1602                         kunmap(adev->gart.pages[p]);
1603                 } else
1604                         r = clear_user(buf, cur_size);
1605
1606                 if (r)
1607                         return -EFAULT;
1608
1609                 result += cur_size;
1610                 buf += cur_size;
1611                 *pos += cur_size;
1612                 size -= cur_size;
1613         }
1614
1615         return result;
1616 }
1617
1618 static const struct file_operations amdgpu_ttm_gtt_fops = {
1619         .owner = THIS_MODULE,
1620         .read = amdgpu_ttm_gtt_read,
1621         .llseek = default_llseek
1622 };
1623
1624 #endif
1625
1626 #endif
1627
1628 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1629 {
1630 #if defined(CONFIG_DEBUG_FS)
1631         unsigned count;
1632
1633         struct drm_minor *minor = adev->ddev->primary;
1634         struct dentry *ent, *root = minor->debugfs_root;
1635
1636         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1637                                   adev, &amdgpu_ttm_vram_fops);
1638         if (IS_ERR(ent))
1639                 return PTR_ERR(ent);
1640         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1641         adev->mman.vram = ent;
1642
1643 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1644         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1645                                   adev, &amdgpu_ttm_gtt_fops);
1646         if (IS_ERR(ent))
1647                 return PTR_ERR(ent);
1648         i_size_write(ent->d_inode, adev->mc.gart_size);
1649         adev->mman.gtt = ent;
1650
1651 #endif
1652         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1653
1654 #ifdef CONFIG_SWIOTLB
1655         if (!swiotlb_nr_tbl())
1656                 --count;
1657 #endif
1658
1659         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1660 #else
1661
1662         return 0;
1663 #endif
1664 }
1665
1666 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1667 {
1668 #if defined(CONFIG_DEBUG_FS)
1669
1670         debugfs_remove(adev->mman.vram);
1671         adev->mman.vram = NULL;
1672
1673 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1674         debugfs_remove(adev->mman.gtt);
1675         adev->mman.gtt = NULL;
1676 #endif
1677
1678 #endif
1679 }