drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35
  36 #include "gmc/gmc_8_1_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "gca/gfx_8_0_d.h"
  46 #include "gca/gfx_8_0_sh_mask.h"
  47
  48 #include "smu/smu_7_1_1_d.h"
  49 #include "smu/smu_7_1_1_sh_mask.h"
  50
  51 #include "uvd/uvd_5_0_d.h"
  52 #include "uvd/uvd_5_0_sh_mask.h"
  53
  54 #include "vce/vce_3_0_d.h"
  55 #include "vce/vce_3_0_sh_mask.h"
  56
  57 #include "dce/dce_10_0_d.h"
  58 #include "dce/dce_10_0_sh_mask.h"
  59
  60 #include "vid.h"
  61 #include "vi.h"
  62 #include "gmc_v8_0.h"
  63 #include "gmc_v7_0.h"
  64 #include "gfx_v8_0.h"
  65 #include "sdma_v2_4.h"
  66 #include "sdma_v3_0.h"
  67 #include "dce_v10_0.h"
  68 #include "dce_v11_0.h"
  69 #include "iceland_ih.h"
  70 #include "tonga_ih.h"
  71 #include "cz_ih.h"
  72 #include "uvd_v5_0.h"
  73 #include "uvd_v6_0.h"
  74 #include "vce_v3_0.h"
  75 #if defined(CONFIG_DRM_AMD_ACP)
  76 #include "amdgpu_acp.h"
  77 #endif
  78 #include "dce_virtual.h"
  79 #include "mxgpu_vi.h"
  80 #include "amdgpu_dm.h"
  81
  82 /*
  83  * Indirect registers accessor
  84  */
  85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  86 {
  87         unsigned long flags;
  88         u32 r;
  89
  90         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  91         WREG32_NO_KIQ(mmPCIE_INDEX, reg);
  92         (void)RREG32_NO_KIQ(mmPCIE_INDEX);
  93         r = RREG32_NO_KIQ(mmPCIE_DATA);
  94         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  95         return r;
  96 }
  97
  98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  99 {
 100         unsigned long flags;
 101
 102         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 103         WREG32_NO_KIQ(mmPCIE_INDEX, reg);
 104         (void)RREG32_NO_KIQ(mmPCIE_INDEX);
 105         WREG32_NO_KIQ(mmPCIE_DATA, v);
 106         (void)RREG32_NO_KIQ(mmPCIE_DATA);
 107         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 108 }
 109
 110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 111 {
 112         unsigned long flags;
 113         u32 r;
 114
 115         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 116         WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
 117         r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
 118         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 119         return r;
 120 }
 121
 122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 123 {
 124         unsigned long flags;
 125
 126         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 127         WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
 128         WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
 129         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 130 }
 131
 132 /* smu_8_0_d.h */
 133 #define mmMP0PUB_IND_INDEX                                                      0x180
 134 #define mmMP0PUB_IND_DATA                                                       0x181
 135
 136 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 137 {
 138         unsigned long flags;
 139         u32 r;
 140
 141         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 142         WREG32(mmMP0PUB_IND_INDEX, (reg));
 143         r = RREG32(mmMP0PUB_IND_DATA);
 144         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 145         return r;
 146 }
 147
 148 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 153         WREG32(mmMP0PUB_IND_INDEX, (reg));
 154         WREG32(mmMP0PUB_IND_DATA, (v));
 155         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 156 }
 157
 158 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 164         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 165         r = RREG32(mmUVD_CTX_DATA);
 166         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 167         return r;
 168 }
 169
 170 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 171 {
 172         unsigned long flags;
 173
 174         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 175         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 176         WREG32(mmUVD_CTX_DATA, (v));
 177         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 178 }
 179
 180 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 181 {
 182         unsigned long flags;
 183         u32 r;
 184
 185         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 186         WREG32(mmDIDT_IND_INDEX, (reg));
 187         r = RREG32(mmDIDT_IND_DATA);
 188         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 189         return r;
 190 }
 191
 192 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 193 {
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 197         WREG32(mmDIDT_IND_INDEX, (reg));
 198         WREG32(mmDIDT_IND_DATA, (v));
 199         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 200 }
 201
 202 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 203 {
 204         unsigned long flags;
 205         u32 r;
 206
 207         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 208         WREG32(mmGC_CAC_IND_INDEX, (reg));
 209         r = RREG32(mmGC_CAC_IND_DATA);
 210         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 211         return r;
 212 }
 213
 214 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 215 {
 216         unsigned long flags;
 217
 218         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 219         WREG32(mmGC_CAC_IND_INDEX, (reg));
 220         WREG32(mmGC_CAC_IND_DATA, (v));
 221         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 222 }
 223
 224
 225 static const u32 tonga_mgcg_cgcg_init[] =
 226 {
 227         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 228         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 229         mmPCIE_DATA, 0x000f0000, 0x00000000,
 230         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 231         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 232         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 233         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 234 };
 235
 236 static const u32 fiji_mgcg_cgcg_init[] =
 237 {
 238         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 239         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 240         mmPCIE_DATA, 0x000f0000, 0x00000000,
 241         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 242         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 243         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 244         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 245 };
 246
 247 static const u32 iceland_mgcg_cgcg_init[] =
 248 {
 249         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 250         mmPCIE_DATA, 0x000f0000, 0x00000000,
 251         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 252         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 253         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 254 };
 255
 256 static const u32 cz_mgcg_cgcg_init[] =
 257 {
 258         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 259         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 260         mmPCIE_DATA, 0x000f0000, 0x00000000,
 261         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 262         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 263 };
 264
 265 static const u32 stoney_mgcg_cgcg_init[] =
 266 {
 267         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 268         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 269         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 270 };
 271
 272 static void vi_init_golden_registers(struct amdgpu_device *adev)
 273 {
 274         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 275         mutex_lock(&adev->grbm_idx_mutex);
 276
 277         if (amdgpu_sriov_vf(adev)) {
 278                 xgpu_vi_init_golden_registers(adev);
 279                 mutex_unlock(&adev->grbm_idx_mutex);
 280                 return;
 281         }
 282
 283         switch (adev->asic_type) {
 284         case CHIP_TOPAZ:
 285                 amdgpu_device_program_register_sequence(adev,
 286                                                         iceland_mgcg_cgcg_init,
 287                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 288                 break;
 289         case CHIP_FIJI:
 290                 amdgpu_device_program_register_sequence(adev,
 291                                                         fiji_mgcg_cgcg_init,
 292                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 293                 break;
 294         case CHIP_TONGA:
 295                 amdgpu_device_program_register_sequence(adev,
 296                                                         tonga_mgcg_cgcg_init,
 297                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 298                 break;
 299         case CHIP_CARRIZO:
 300                 amdgpu_device_program_register_sequence(adev,
 301                                                         cz_mgcg_cgcg_init,
 302                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 303                 break;
 304         case CHIP_STONEY:
 305                 amdgpu_device_program_register_sequence(adev,
 306                                                         stoney_mgcg_cgcg_init,
 307                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 308                 break;
 309         case CHIP_POLARIS10:
 310         case CHIP_POLARIS11:
 311         case CHIP_POLARIS12:
 312         case CHIP_VEGAM:
 313         default:
 314                 break;
 315         }
 316         mutex_unlock(&adev->grbm_idx_mutex);
 317 }
 318
 319 /**
 320  * vi_get_xclk - get the xclk
 321  *
 322  * @adev: amdgpu_device pointer
 323  *
 324  * Returns the reference clock used by the gfx engine
 325  * (VI).
 326  */
 327 static u32 vi_get_xclk(struct amdgpu_device *adev)
 328 {
 329         u32 reference_clock = adev->clock.spll.reference_freq;
 330         u32 tmp;
 331
 332         if (adev->flags & AMD_IS_APU)
 333                 return reference_clock;
 334
 335         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 336         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 337                 return 1000;
 338
 339         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 340         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 341                 return reference_clock / 4;
 342
 343         return reference_clock;
 344 }
 345
 346 /**
 347  * vi_srbm_select - select specific register instances
 348  *
 349  * @adev: amdgpu_device pointer
 350  * @me: selected ME (micro engine)
 351  * @pipe: pipe
 352  * @queue: queue
 353  * @vmid: VMID
 354  *
 355  * Switches the currently active registers instances.  Some
 356  * registers are instanced per VMID, others are instanced per
 357  * me/pipe/queue combination.
 358  */
 359 void vi_srbm_select(struct amdgpu_device *adev,
 360                      u32 me, u32 pipe, u32 queue, u32 vmid)
 361 {
 362         u32 srbm_gfx_cntl = 0;
 363         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 364         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 365         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 366         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 367         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 368 }
 369
 370 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 371 {
 372         /* todo */
 373 }
 374
 375 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 376 {
 377         u32 bus_cntl;
 378         u32 d1vga_control = 0;
 379         u32 d2vga_control = 0;
 380         u32 vga_render_control = 0;
 381         u32 rom_cntl;
 382         bool r;
 383
 384         bus_cntl = RREG32(mmBUS_CNTL);
 385         if (adev->mode_info.num_crtc) {
 386                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 387                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 388                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 389         }
 390         rom_cntl = RREG32_SMC(ixROM_CNTL);
 391
 392         /* enable the rom */
 393         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 394         if (adev->mode_info.num_crtc) {
 395                 /* Disable VGA mode */
 396                 WREG32(mmD1VGA_CONTROL,
 397                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 398                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 399                 WREG32(mmD2VGA_CONTROL,
 400                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 401                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 402                 WREG32(mmVGA_RENDER_CONTROL,
 403                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 404         }
 405         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 406
 407         r = amdgpu_read_bios(adev);
 408
 409         /* restore regs */
 410         WREG32(mmBUS_CNTL, bus_cntl);
 411         if (adev->mode_info.num_crtc) {
 412                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 413                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 414                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 415         }
 416         WREG32_SMC(ixROM_CNTL, rom_cntl);
 417         return r;
 418 }
 419
 420 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 421                                   u8 *bios, u32 length_bytes)
 422 {
 423         u32 *dw_ptr;
 424         unsigned long flags;
 425         u32 i, length_dw;
 426
 427         if (bios == NULL)
 428                 return false;
 429         if (length_bytes == 0)
 430                 return false;
 431         /* APU vbios image is part of sbios image */
 432         if (adev->flags & AMD_IS_APU)
 433                 return false;
 434
 435         dw_ptr = (u32 *)bios;
 436         length_dw = ALIGN(length_bytes, 4) / 4;
 437         /* take the smc lock since we are using the smc index */
 438         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 439         /* set rom index to 0 */
 440         WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
 441         WREG32(mmSMC_IND_DATA_11, 0);
 442         /* set index to data for continous read */
 443         WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
 444         for (i = 0; i < length_dw; i++)
 445                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
 446         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 447
 448         return true;
 449 }
 450
 451 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 452         {mmGRBM_STATUS},
 453         {mmGRBM_STATUS2},
 454         {mmGRBM_STATUS_SE0},
 455         {mmGRBM_STATUS_SE1},
 456         {mmGRBM_STATUS_SE2},
 457         {mmGRBM_STATUS_SE3},
 458         {mmSRBM_STATUS},
 459         {mmSRBM_STATUS2},
 460         {mmSRBM_STATUS3},
 461         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
 462         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
 463         {mmCP_STAT},
 464         {mmCP_STALLED_STAT1},
 465         {mmCP_STALLED_STAT2},
 466         {mmCP_STALLED_STAT3},
 467         {mmCP_CPF_BUSY_STAT},
 468         {mmCP_CPF_STALLED_STAT1},
 469         {mmCP_CPF_STATUS},
 470         {mmCP_CPC_BUSY_STAT},
 471         {mmCP_CPC_STALLED_STAT1},
 472         {mmCP_CPC_STATUS},
 473         {mmGB_ADDR_CONFIG},
 474         {mmMC_ARB_RAMCFG},
 475         {mmGB_TILE_MODE0},
 476         {mmGB_TILE_MODE1},
 477         {mmGB_TILE_MODE2},
 478         {mmGB_TILE_MODE3},
 479         {mmGB_TILE_MODE4},
 480         {mmGB_TILE_MODE5},
 481         {mmGB_TILE_MODE6},
 482         {mmGB_TILE_MODE7},
 483         {mmGB_TILE_MODE8},
 484         {mmGB_TILE_MODE9},
 485         {mmGB_TILE_MODE10},
 486         {mmGB_TILE_MODE11},
 487         {mmGB_TILE_MODE12},
 488         {mmGB_TILE_MODE13},
 489         {mmGB_TILE_MODE14},
 490         {mmGB_TILE_MODE15},
 491         {mmGB_TILE_MODE16},
 492         {mmGB_TILE_MODE17},
 493         {mmGB_TILE_MODE18},
 494         {mmGB_TILE_MODE19},
 495         {mmGB_TILE_MODE20},
 496         {mmGB_TILE_MODE21},
 497         {mmGB_TILE_MODE22},
 498         {mmGB_TILE_MODE23},
 499         {mmGB_TILE_MODE24},
 500         {mmGB_TILE_MODE25},
 501         {mmGB_TILE_MODE26},
 502         {mmGB_TILE_MODE27},
 503         {mmGB_TILE_MODE28},
 504         {mmGB_TILE_MODE29},
 505         {mmGB_TILE_MODE30},
 506         {mmGB_TILE_MODE31},
 507         {mmGB_MACROTILE_MODE0},
 508         {mmGB_MACROTILE_MODE1},
 509         {mmGB_MACROTILE_MODE2},
 510         {mmGB_MACROTILE_MODE3},
 511         {mmGB_MACROTILE_MODE4},
 512         {mmGB_MACROTILE_MODE5},
 513         {mmGB_MACROTILE_MODE6},
 514         {mmGB_MACROTILE_MODE7},
 515         {mmGB_MACROTILE_MODE8},
 516         {mmGB_MACROTILE_MODE9},
 517         {mmGB_MACROTILE_MODE10},
 518         {mmGB_MACROTILE_MODE11},
 519         {mmGB_MACROTILE_MODE12},
 520         {mmGB_MACROTILE_MODE13},
 521         {mmGB_MACROTILE_MODE14},
 522         {mmGB_MACROTILE_MODE15},
 523         {mmCC_RB_BACKEND_DISABLE, true},
 524         {mmGC_USER_RB_BACKEND_DISABLE, true},
 525         {mmGB_BACKEND_MAP, false},
 526         {mmPA_SC_RASTER_CONFIG, true},
 527         {mmPA_SC_RASTER_CONFIG_1, true},
 528 };
 529
 530 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 531                                       bool indexed, u32 se_num,
 532                                       u32 sh_num, u32 reg_offset)
 533 {
 534         if (indexed) {
 535                 uint32_t val;
 536                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
 537                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
 538
 539                 switch (reg_offset) {
 540                 case mmCC_RB_BACKEND_DISABLE:
 541                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
 542                 case mmGC_USER_RB_BACKEND_DISABLE:
 543                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
 544                 case mmPA_SC_RASTER_CONFIG:
 545                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
 546                 case mmPA_SC_RASTER_CONFIG_1:
 547                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
 548                 }
 549
 550                 mutex_lock(&adev->grbm_idx_mutex);
 551                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 552                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 553
 554                 val = RREG32(reg_offset);
 555
 556                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 557                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 558                 mutex_unlock(&adev->grbm_idx_mutex);
 559                 return val;
 560         } else {
 561                 unsigned idx;
 562
 563                 switch (reg_offset) {
 564                 case mmGB_ADDR_CONFIG:
 565                         return adev->gfx.config.gb_addr_config;
 566                 case mmMC_ARB_RAMCFG:
 567                         return adev->gfx.config.mc_arb_ramcfg;
 568                 case mmGB_TILE_MODE0:
 569                 case mmGB_TILE_MODE1:
 570                 case mmGB_TILE_MODE2:
 571                 case mmGB_TILE_MODE3:
 572                 case mmGB_TILE_MODE4:
 573                 case mmGB_TILE_MODE5:
 574                 case mmGB_TILE_MODE6:
 575                 case mmGB_TILE_MODE7:
 576                 case mmGB_TILE_MODE8:
 577                 case mmGB_TILE_MODE9:
 578                 case mmGB_TILE_MODE10:
 579                 case mmGB_TILE_MODE11:
 580                 case mmGB_TILE_MODE12:
 581                 case mmGB_TILE_MODE13:
 582                 case mmGB_TILE_MODE14:
 583                 case mmGB_TILE_MODE15:
 584                 case mmGB_TILE_MODE16:
 585                 case mmGB_TILE_MODE17:
 586                 case mmGB_TILE_MODE18:
 587                 case mmGB_TILE_MODE19:
 588                 case mmGB_TILE_MODE20:
 589                 case mmGB_TILE_MODE21:
 590                 case mmGB_TILE_MODE22:
 591                 case mmGB_TILE_MODE23:
 592                 case mmGB_TILE_MODE24:
 593                 case mmGB_TILE_MODE25:
 594                 case mmGB_TILE_MODE26:
 595                 case mmGB_TILE_MODE27:
 596                 case mmGB_TILE_MODE28:
 597                 case mmGB_TILE_MODE29:
 598                 case mmGB_TILE_MODE30:
 599                 case mmGB_TILE_MODE31:
 600                         idx = (reg_offset - mmGB_TILE_MODE0);
 601                         return adev->gfx.config.tile_mode_array[idx];
 602                 case mmGB_MACROTILE_MODE0:
 603                 case mmGB_MACROTILE_MODE1:
 604                 case mmGB_MACROTILE_MODE2:
 605                 case mmGB_MACROTILE_MODE3:
 606                 case mmGB_MACROTILE_MODE4:
 607                 case mmGB_MACROTILE_MODE5:
 608                 case mmGB_MACROTILE_MODE6:
 609                 case mmGB_MACROTILE_MODE7:
 610                 case mmGB_MACROTILE_MODE8:
 611                 case mmGB_MACROTILE_MODE9:
 612                 case mmGB_MACROTILE_MODE10:
 613                 case mmGB_MACROTILE_MODE11:
 614                 case mmGB_MACROTILE_MODE12:
 615                 case mmGB_MACROTILE_MODE13:
 616                 case mmGB_MACROTILE_MODE14:
 617                 case mmGB_MACROTILE_MODE15:
 618                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
 619                         return adev->gfx.config.macrotile_mode_array[idx];
 620                 default:
 621                         return RREG32(reg_offset);
 622                 }
 623         }
 624 }
 625
 626 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 627                             u32 sh_num, u32 reg_offset, u32 *value)
 628 {
 629         uint32_t i;
 630
 631         *value = 0;
 632         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 633                 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
 634
 635                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 636                         continue;
 637
 638                 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
 639                                                reg_offset);
 640                 return 0;
 641         }
 642         return -EINVAL;
 643 }
 644
 645 /**
 646  * vi_asic_pci_config_reset - soft reset GPU
 647  *
 648  * @adev: amdgpu_device pointer
 649  *
 650  * Use PCI Config method to reset the GPU.
 651  *
 652  * Returns 0 for success.
 653  */
 654 static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
 655 {
 656         u32 i;
 657         int r = -EINVAL;
 658
 659         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 660
 661         /* disable BM */
 662         pci_clear_master(adev->pdev);
 663         /* reset */
 664         amdgpu_device_pci_config_reset(adev);
 665
 666         udelay(100);
 667
 668         /* wait for asic to come out of reset */
 669         for (i = 0; i < adev->usec_timeout; i++) {
 670                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
 671                         /* enable BM */
 672                         pci_set_master(adev->pdev);
 673                         adev->has_hw_reset = true;
 674                         r = 0;
 675                         break;
 676                 }
 677                 udelay(1);
 678         }
 679
 680         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 681
 682         return r;
 683 }
 684
 685 static bool vi_asic_supports_baco(struct amdgpu_device *adev)
 686 {
 687         switch (adev->asic_type) {
 688         case CHIP_FIJI:
 689         case CHIP_TONGA:
 690         case CHIP_POLARIS10:
 691         case CHIP_POLARIS11:
 692         case CHIP_POLARIS12:
 693         case CHIP_TOPAZ:
 694                 return amdgpu_dpm_is_baco_supported(adev);
 695         default:
 696                 return false;
 697         }
 698 }
 699
 700 static enum amd_reset_method
 701 vi_asic_reset_method(struct amdgpu_device *adev)
 702 {
 703         bool baco_reset;
 704
 705         if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
 706             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 707                 return amdgpu_reset_method;
 708
 709         if (amdgpu_reset_method != -1)
 710                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 711                                   amdgpu_reset_method);
 712
 713         switch (adev->asic_type) {
 714         case CHIP_FIJI:
 715         case CHIP_TONGA:
 716         case CHIP_POLARIS10:
 717         case CHIP_POLARIS11:
 718         case CHIP_POLARIS12:
 719         case CHIP_TOPAZ:
 720                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 721                 break;
 722         default:
 723                 baco_reset = false;
 724                 break;
 725         }
 726
 727         if (baco_reset)
 728                 return AMD_RESET_METHOD_BACO;
 729         else
 730                 return AMD_RESET_METHOD_LEGACY;
 731 }
 732
 733 /**
 734  * vi_asic_reset - soft reset GPU
 735  *
 736  * @adev: amdgpu_device pointer
 737  *
 738  * Look up which blocks are hung and attempt
 739  * to reset them.
 740  * Returns 0 for success.
 741  */
 742 static int vi_asic_reset(struct amdgpu_device *adev)
 743 {
 744         int r;
 745
 746         if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 747                 dev_info(adev->dev, "BACO reset\n");
 748                 r = amdgpu_dpm_baco_reset(adev);
 749         } else {
 750                 dev_info(adev->dev, "PCI CONFIG reset\n");
 751                 r = vi_asic_pci_config_reset(adev);
 752         }
 753
 754         return r;
 755 }
 756
 757 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
 758 {
 759         return RREG32(mmCONFIG_MEMSIZE);
 760 }
 761
 762 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 763                         u32 cntl_reg, u32 status_reg)
 764 {
 765         int r, i;
 766         struct atom_clock_dividers dividers;
 767         uint32_t tmp;
 768
 769         r = amdgpu_atombios_get_clock_dividers(adev,
 770                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 771                                                clock, false, &dividers);
 772         if (r)
 773                 return r;
 774
 775         tmp = RREG32_SMC(cntl_reg);
 776
 777         if (adev->flags & AMD_IS_APU)
 778                 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
 779         else
 780                 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
 781                                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
 782         tmp |= dividers.post_divider;
 783         WREG32_SMC(cntl_reg, tmp);
 784
 785         for (i = 0; i < 100; i++) {
 786                 tmp = RREG32_SMC(status_reg);
 787                 if (adev->flags & AMD_IS_APU) {
 788                         if (tmp & 0x10000)
 789                                 break;
 790                 } else {
 791                         if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
 792                                 break;
 793                 }
 794                 mdelay(10);
 795         }
 796         if (i == 100)
 797                 return -ETIMEDOUT;
 798         return 0;
 799 }
 800
 801 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
 802 #define ixGNB_CLK1_STATUS   0xD822010C
 803 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
 804 #define ixGNB_CLK2_STATUS   0xD822012C
 805 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
 806 #define ixGNB_CLK3_STATUS   0xD822014C
 807
 808 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 809 {
 810         int r;
 811
 812         if (adev->flags & AMD_IS_APU) {
 813                 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
 814                 if (r)
 815                         return r;
 816
 817                 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
 818                 if (r)
 819                         return r;
 820         } else {
 821                 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 822                 if (r)
 823                         return r;
 824
 825                 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 826                 if (r)
 827                         return r;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 834 {
 835         int r, i;
 836         struct atom_clock_dividers dividers;
 837         u32 tmp;
 838         u32 reg_ctrl;
 839         u32 reg_status;
 840         u32 status_mask;
 841         u32 reg_mask;
 842
 843         if (adev->flags & AMD_IS_APU) {
 844                 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
 845                 reg_status = ixGNB_CLK3_STATUS;
 846                 status_mask = 0x00010000;
 847                 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 848         } else {
 849                 reg_ctrl = ixCG_ECLK_CNTL;
 850                 reg_status = ixCG_ECLK_STATUS;
 851                 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
 852                 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 853         }
 854
 855         r = amdgpu_atombios_get_clock_dividers(adev,
 856                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 857                                                ecclk, false, &dividers);
 858         if (r)
 859                 return r;
 860
 861         for (i = 0; i < 100; i++) {
 862                 if (RREG32_SMC(reg_status) & status_mask)
 863                         break;
 864                 mdelay(10);
 865         }
 866
 867         if (i == 100)
 868                 return -ETIMEDOUT;
 869
 870         tmp = RREG32_SMC(reg_ctrl);
 871         tmp &= ~reg_mask;
 872         tmp |= dividers.post_divider;
 873         WREG32_SMC(reg_ctrl, tmp);
 874
 875         for (i = 0; i < 100; i++) {
 876                 if (RREG32_SMC(reg_status) & status_mask)
 877                         break;
 878                 mdelay(10);
 879         }
 880
 881         if (i == 100)
 882                 return -ETIMEDOUT;
 883
 884         return 0;
 885 }
 886
 887 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
 888 {
 889         if (pci_is_root_bus(adev->pdev->bus))
 890                 return;
 891
 892         if (amdgpu_pcie_gen2 == 0)
 893                 return;
 894
 895         if (adev->flags & AMD_IS_APU)
 896                 return;
 897
 898         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 899                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 900                 return;
 901
 902         /* todo */
 903 }
 904
 905 static void vi_program_aspm(struct amdgpu_device *adev)
 906 {
 907
 908         if (amdgpu_aspm == 0)
 909                 return;
 910
 911         /* todo */
 912 }
 913
 914 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
 915                                         bool enable)
 916 {
 917         u32 tmp;
 918
 919         /* not necessary on CZ */
 920         if (adev->flags & AMD_IS_APU)
 921                 return;
 922
 923         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
 924         if (enable)
 925                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
 926         else
 927                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
 928
 929         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
 930 }
 931
 932 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
 933 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
 934 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
 935
 936 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 937 {
 938         if (adev->flags & AMD_IS_APU)
 939                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
 940                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
 941         else
 942                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
 943                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
 944 }
 945
 946 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 947 {
 948         if (!ring || !ring->funcs->emit_wreg) {
 949                 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
 950                 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
 951         } else {
 952                 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
 953         }
 954 }
 955
 956 static void vi_invalidate_hdp(struct amdgpu_device *adev,
 957                               struct amdgpu_ring *ring)
 958 {
 959         if (!ring || !ring->funcs->emit_wreg) {
 960                 WREG32(mmHDP_DEBUG0, 1);
 961                 RREG32(mmHDP_DEBUG0);
 962         } else {
 963                 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
 964         }
 965 }
 966
 967 static bool vi_need_full_reset(struct amdgpu_device *adev)
 968 {
 969         switch (adev->asic_type) {
 970         case CHIP_CARRIZO:
 971         case CHIP_STONEY:
 972                 /* CZ has hang issues with full reset at the moment */
 973                 return false;
 974         case CHIP_FIJI:
 975         case CHIP_TONGA:
 976                 /* XXX: soft reset should work on fiji and tonga */
 977                 return true;
 978         case CHIP_POLARIS10:
 979         case CHIP_POLARIS11:
 980         case CHIP_POLARIS12:
 981         case CHIP_TOPAZ:
 982         default:
 983                 /* change this when we support soft reset */
 984                 return true;
 985         }
 986 }
 987
 988 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 989                               uint64_t *count1)
 990 {
 991         uint32_t perfctr = 0;
 992         uint64_t cnt0_of, cnt1_of;
 993         int tmp;
 994
 995         /* This reports 0 on APUs, so return to avoid writing/reading registers
 996          * that may or may not be different from their GPU counterparts
 997          */
 998         if (adev->flags & AMD_IS_APU)
 999                 return;
1000
1001         /* Set the 2 events that we wish to watch, defined above */
1002         /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1003         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1004         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1005
1006         /* Write to enable desired perf counters */
1007         WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1008         /* Zero out and enable the perf counters
1009          * Write 0x5:
1010          * Bit 0 = Start all counters(1)
1011          * Bit 2 = Global counter reset enable(1)
1012          */
1013         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1014
1015         msleep(1000);
1016
1017         /* Load the shadow and disable the perf counters
1018          * Write 0x2:
1019          * Bit 0 = Stop counters(0)
1020          * Bit 1 = Load the shadow counters(1)
1021          */
1022         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1023
1024         /* Read register values to get any >32bit overflow */
1025         tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1026         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1027         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1028
1029         /* Get the values and add the overflow */
1030         *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1031         *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1032 }
1033
1034 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1035 {
1036         uint64_t nak_r, nak_g;
1037
1038         /* Get the number of NAKs received and generated */
1039         nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1040         nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1041
1042         /* Add the total number of NAKs, i.e the number of replays */
1043         return (nak_r + nak_g);
1044 }
1045
1046 static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1047 {
1048         u32 clock_cntl, pc;
1049
1050         if (adev->flags & AMD_IS_APU)
1051                 return false;
1052
1053         /* check if the SMC is already running */
1054         clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1055         pc = RREG32_SMC(ixSMC_PC_C);
1056         if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1057             (0x20100 <= pc))
1058                 return true;
1059
1060         return false;
1061 }
1062
1063 static void vi_pre_asic_init(struct amdgpu_device *adev)
1064 {
1065 }
1066
1067 static const struct amdgpu_asic_funcs vi_asic_funcs =
1068 {
1069         .read_disabled_bios = &vi_read_disabled_bios,
1070         .read_bios_from_rom = &vi_read_bios_from_rom,
1071         .read_register = &vi_read_register,
1072         .reset = &vi_asic_reset,
1073         .reset_method = &vi_asic_reset_method,
1074         .set_vga_state = &vi_vga_set_state,
1075         .get_xclk = &vi_get_xclk,
1076         .set_uvd_clocks = &vi_set_uvd_clocks,
1077         .set_vce_clocks = &vi_set_vce_clocks,
1078         .get_config_memsize = &vi_get_config_memsize,
1079         .flush_hdp = &vi_flush_hdp,
1080         .invalidate_hdp = &vi_invalidate_hdp,
1081         .need_full_reset = &vi_need_full_reset,
1082         .init_doorbell_index = &legacy_doorbell_index_init,
1083         .get_pcie_usage = &vi_get_pcie_usage,
1084         .need_reset_on_init = &vi_need_reset_on_init,
1085         .get_pcie_replay_count = &vi_get_pcie_replay_count,
1086         .supports_baco = &vi_asic_supports_baco,
1087         .pre_asic_init = &vi_pre_asic_init,
1088 };
1089
1090 #define CZ_REV_BRISTOL(rev)      \
1091         ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1092
1093 static int vi_common_early_init(void *handle)
1094 {
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097         if (adev->flags & AMD_IS_APU) {
1098                 adev->smc_rreg = &cz_smc_rreg;
1099                 adev->smc_wreg = &cz_smc_wreg;
1100         } else {
1101                 adev->smc_rreg = &vi_smc_rreg;
1102                 adev->smc_wreg = &vi_smc_wreg;
1103         }
1104         adev->pcie_rreg = &vi_pcie_rreg;
1105         adev->pcie_wreg = &vi_pcie_wreg;
1106         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1107         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1108         adev->didt_rreg = &vi_didt_rreg;
1109         adev->didt_wreg = &vi_didt_wreg;
1110         adev->gc_cac_rreg = &vi_gc_cac_rreg;
1111         adev->gc_cac_wreg = &vi_gc_cac_wreg;
1112
1113         adev->asic_funcs = &vi_asic_funcs;
1114
1115         adev->rev_id = vi_get_rev_id(adev);
1116         adev->external_rev_id = 0xFF;
1117         switch (adev->asic_type) {
1118         case CHIP_TOPAZ:
1119                 adev->cg_flags = 0;
1120                 adev->pg_flags = 0;
1121                 adev->external_rev_id = 0x1;
1122                 break;
1123         case CHIP_FIJI:
1124                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1125                         AMD_CG_SUPPORT_GFX_MGLS |
1126                         AMD_CG_SUPPORT_GFX_RLC_LS |
1127                         AMD_CG_SUPPORT_GFX_CP_LS |
1128                         AMD_CG_SUPPORT_GFX_CGTS |
1129                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1130                         AMD_CG_SUPPORT_GFX_CGCG |
1131                         AMD_CG_SUPPORT_GFX_CGLS |
1132                         AMD_CG_SUPPORT_SDMA_MGCG |
1133                         AMD_CG_SUPPORT_SDMA_LS |
1134                         AMD_CG_SUPPORT_BIF_LS |
1135                         AMD_CG_SUPPORT_HDP_MGCG |
1136                         AMD_CG_SUPPORT_HDP_LS |
1137                         AMD_CG_SUPPORT_ROM_MGCG |
1138                         AMD_CG_SUPPORT_MC_MGCG |
1139                         AMD_CG_SUPPORT_MC_LS |
1140                         AMD_CG_SUPPORT_UVD_MGCG;
1141                 adev->pg_flags = 0;
1142                 adev->external_rev_id = adev->rev_id + 0x3c;
1143                 break;
1144         case CHIP_TONGA:
1145                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1146                         AMD_CG_SUPPORT_GFX_CGCG |
1147                         AMD_CG_SUPPORT_GFX_CGLS |
1148                         AMD_CG_SUPPORT_SDMA_MGCG |
1149                         AMD_CG_SUPPORT_SDMA_LS |
1150                         AMD_CG_SUPPORT_BIF_LS |
1151                         AMD_CG_SUPPORT_HDP_MGCG |
1152                         AMD_CG_SUPPORT_HDP_LS |
1153                         AMD_CG_SUPPORT_ROM_MGCG |
1154                         AMD_CG_SUPPORT_MC_MGCG |
1155                         AMD_CG_SUPPORT_MC_LS |
1156                         AMD_CG_SUPPORT_DRM_LS |
1157                         AMD_CG_SUPPORT_UVD_MGCG;
1158                 adev->pg_flags = 0;
1159                 adev->external_rev_id = adev->rev_id + 0x14;
1160                 break;
1161         case CHIP_POLARIS11:
1162                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1163                         AMD_CG_SUPPORT_GFX_RLC_LS |
1164                         AMD_CG_SUPPORT_GFX_CP_LS |
1165                         AMD_CG_SUPPORT_GFX_CGCG |
1166                         AMD_CG_SUPPORT_GFX_CGLS |
1167                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1168                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1169                         AMD_CG_SUPPORT_SDMA_MGCG |
1170                         AMD_CG_SUPPORT_SDMA_LS |
1171                         AMD_CG_SUPPORT_BIF_MGCG |
1172                         AMD_CG_SUPPORT_BIF_LS |
1173                         AMD_CG_SUPPORT_HDP_MGCG |
1174                         AMD_CG_SUPPORT_HDP_LS |
1175                         AMD_CG_SUPPORT_ROM_MGCG |
1176                         AMD_CG_SUPPORT_MC_MGCG |
1177                         AMD_CG_SUPPORT_MC_LS |
1178                         AMD_CG_SUPPORT_DRM_LS |
1179                         AMD_CG_SUPPORT_UVD_MGCG |
1180                         AMD_CG_SUPPORT_VCE_MGCG;
1181                 adev->pg_flags = 0;
1182                 adev->external_rev_id = adev->rev_id + 0x5A;
1183                 break;
1184         case CHIP_POLARIS10:
1185                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1186                         AMD_CG_SUPPORT_GFX_RLC_LS |
1187                         AMD_CG_SUPPORT_GFX_CP_LS |
1188                         AMD_CG_SUPPORT_GFX_CGCG |
1189                         AMD_CG_SUPPORT_GFX_CGLS |
1190                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1191                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1192                         AMD_CG_SUPPORT_SDMA_MGCG |
1193                         AMD_CG_SUPPORT_SDMA_LS |
1194                         AMD_CG_SUPPORT_BIF_MGCG |
1195                         AMD_CG_SUPPORT_BIF_LS |
1196                         AMD_CG_SUPPORT_HDP_MGCG |
1197                         AMD_CG_SUPPORT_HDP_LS |
1198                         AMD_CG_SUPPORT_ROM_MGCG |
1199                         AMD_CG_SUPPORT_MC_MGCG |
1200                         AMD_CG_SUPPORT_MC_LS |
1201                         AMD_CG_SUPPORT_DRM_LS |
1202                         AMD_CG_SUPPORT_UVD_MGCG |
1203                         AMD_CG_SUPPORT_VCE_MGCG;
1204                 adev->pg_flags = 0;
1205                 adev->external_rev_id = adev->rev_id + 0x50;
1206                 break;
1207         case CHIP_POLARIS12:
1208                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1209                         AMD_CG_SUPPORT_GFX_RLC_LS |
1210                         AMD_CG_SUPPORT_GFX_CP_LS |
1211                         AMD_CG_SUPPORT_GFX_CGCG |
1212                         AMD_CG_SUPPORT_GFX_CGLS |
1213                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1214                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1215                         AMD_CG_SUPPORT_SDMA_MGCG |
1216                         AMD_CG_SUPPORT_SDMA_LS |
1217                         AMD_CG_SUPPORT_BIF_MGCG |
1218                         AMD_CG_SUPPORT_BIF_LS |
1219                         AMD_CG_SUPPORT_HDP_MGCG |
1220                         AMD_CG_SUPPORT_HDP_LS |
1221                         AMD_CG_SUPPORT_ROM_MGCG |
1222                         AMD_CG_SUPPORT_MC_MGCG |
1223                         AMD_CG_SUPPORT_MC_LS |
1224                         AMD_CG_SUPPORT_DRM_LS |
1225                         AMD_CG_SUPPORT_UVD_MGCG |
1226                         AMD_CG_SUPPORT_VCE_MGCG;
1227                 adev->pg_flags = 0;
1228                 adev->external_rev_id = adev->rev_id + 0x64;
1229                 break;
1230         case CHIP_VEGAM:
1231                 adev->cg_flags = 0;
1232                         /*AMD_CG_SUPPORT_GFX_MGCG |
1233                         AMD_CG_SUPPORT_GFX_RLC_LS |
1234                         AMD_CG_SUPPORT_GFX_CP_LS |
1235                         AMD_CG_SUPPORT_GFX_CGCG |
1236                         AMD_CG_SUPPORT_GFX_CGLS |
1237                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1238                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1239                         AMD_CG_SUPPORT_SDMA_MGCG |
1240                         AMD_CG_SUPPORT_SDMA_LS |
1241                         AMD_CG_SUPPORT_BIF_MGCG |
1242                         AMD_CG_SUPPORT_BIF_LS |
1243                         AMD_CG_SUPPORT_HDP_MGCG |
1244                         AMD_CG_SUPPORT_HDP_LS |
1245                         AMD_CG_SUPPORT_ROM_MGCG |
1246                         AMD_CG_SUPPORT_MC_MGCG |
1247                         AMD_CG_SUPPORT_MC_LS |
1248                         AMD_CG_SUPPORT_DRM_LS |
1249                         AMD_CG_SUPPORT_UVD_MGCG |
1250                         AMD_CG_SUPPORT_VCE_MGCG;*/
1251                 adev->pg_flags = 0;
1252                 adev->external_rev_id = adev->rev_id + 0x6E;
1253                 break;
1254         case CHIP_CARRIZO:
1255                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1256                         AMD_CG_SUPPORT_GFX_MGCG |
1257                         AMD_CG_SUPPORT_GFX_MGLS |
1258                         AMD_CG_SUPPORT_GFX_RLC_LS |
1259                         AMD_CG_SUPPORT_GFX_CP_LS |
1260                         AMD_CG_SUPPORT_GFX_CGTS |
1261                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1262                         AMD_CG_SUPPORT_GFX_CGCG |
1263                         AMD_CG_SUPPORT_GFX_CGLS |
1264                         AMD_CG_SUPPORT_BIF_LS |
1265                         AMD_CG_SUPPORT_HDP_MGCG |
1266                         AMD_CG_SUPPORT_HDP_LS |
1267                         AMD_CG_SUPPORT_SDMA_MGCG |
1268                         AMD_CG_SUPPORT_SDMA_LS |
1269                         AMD_CG_SUPPORT_VCE_MGCG;
1270                 /* rev0 hardware requires workarounds to support PG */
1271                 adev->pg_flags = 0;
1272                 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1273                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1274                                 AMD_PG_SUPPORT_GFX_PIPELINE |
1275                                 AMD_PG_SUPPORT_CP |
1276                                 AMD_PG_SUPPORT_UVD |
1277                                 AMD_PG_SUPPORT_VCE;
1278                 }
1279                 adev->external_rev_id = adev->rev_id + 0x1;
1280                 break;
1281         case CHIP_STONEY:
1282                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1283                         AMD_CG_SUPPORT_GFX_MGCG |
1284                         AMD_CG_SUPPORT_GFX_MGLS |
1285                         AMD_CG_SUPPORT_GFX_RLC_LS |
1286                         AMD_CG_SUPPORT_GFX_CP_LS |
1287                         AMD_CG_SUPPORT_GFX_CGTS |
1288                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1289                         AMD_CG_SUPPORT_GFX_CGLS |
1290                         AMD_CG_SUPPORT_BIF_LS |
1291                         AMD_CG_SUPPORT_HDP_MGCG |
1292                         AMD_CG_SUPPORT_HDP_LS |
1293                         AMD_CG_SUPPORT_SDMA_MGCG |
1294                         AMD_CG_SUPPORT_SDMA_LS |
1295                         AMD_CG_SUPPORT_VCE_MGCG;
1296                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1297                         AMD_PG_SUPPORT_GFX_SMG |
1298                         AMD_PG_SUPPORT_GFX_PIPELINE |
1299                         AMD_PG_SUPPORT_CP |
1300                         AMD_PG_SUPPORT_UVD |
1301                         AMD_PG_SUPPORT_VCE;
1302                 adev->external_rev_id = adev->rev_id + 0x61;
1303                 break;
1304         default:
1305                 /* FIXME: not supported yet */
1306                 return -EINVAL;
1307         }
1308
1309         if (amdgpu_sriov_vf(adev)) {
1310                 amdgpu_virt_init_setting(adev);
1311                 xgpu_vi_mailbox_set_irq_funcs(adev);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int vi_common_late_init(void *handle)
1318 {
1319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320
1321         if (amdgpu_sriov_vf(adev))
1322                 xgpu_vi_mailbox_get_irq(adev);
1323
1324         return 0;
1325 }
1326
1327 static int vi_common_sw_init(void *handle)
1328 {
1329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331         if (amdgpu_sriov_vf(adev))
1332                 xgpu_vi_mailbox_add_irq_id(adev);
1333
1334         return 0;
1335 }
1336
1337 static int vi_common_sw_fini(void *handle)
1338 {
1339         return 0;
1340 }
1341
1342 static int vi_common_hw_init(void *handle)
1343 {
1344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345
1346         /* move the golden regs per IP block */
1347         vi_init_golden_registers(adev);
1348         /* enable pcie gen2/3 link */
1349         vi_pcie_gen3_enable(adev);
1350         /* enable aspm */
1351         vi_program_aspm(adev);
1352         /* enable the doorbell aperture */
1353         vi_enable_doorbell_aperture(adev, true);
1354
1355         return 0;
1356 }
1357
1358 static int vi_common_hw_fini(void *handle)
1359 {
1360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361
1362         /* enable the doorbell aperture */
1363         vi_enable_doorbell_aperture(adev, false);
1364
1365         if (amdgpu_sriov_vf(adev))
1366                 xgpu_vi_mailbox_put_irq(adev);
1367
1368         return 0;
1369 }
1370
1371 static int vi_common_suspend(void *handle)
1372 {
1373         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374
1375         return vi_common_hw_fini(adev);
1376 }
1377
1378 static int vi_common_resume(void *handle)
1379 {
1380         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1381
1382         return vi_common_hw_init(adev);
1383 }
1384
1385 static bool vi_common_is_idle(void *handle)
1386 {
1387         return true;
1388 }
1389
1390 static int vi_common_wait_for_idle(void *handle)
1391 {
1392         return 0;
1393 }
1394
1395 static int vi_common_soft_reset(void *handle)
1396 {
1397         return 0;
1398 }
1399
1400 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1401                                                    bool enable)
1402 {
1403         uint32_t temp, data;
1404
1405         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1406
1407         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1408                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1409                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1410                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1411         else
1412                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1413                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1414                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1415
1416         if (temp != data)
1417                 WREG32_PCIE(ixPCIE_CNTL2, data);
1418 }
1419
1420 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1421                                                     bool enable)
1422 {
1423         uint32_t temp, data;
1424
1425         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1426
1427         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1428                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1429         else
1430                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1431
1432         if (temp != data)
1433                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1434 }
1435
1436 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1437                                       bool enable)
1438 {
1439         uint32_t temp, data;
1440
1441         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1442
1443         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1444                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1445         else
1446                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1447
1448         if (temp != data)
1449                 WREG32(mmHDP_MEM_POWER_LS, data);
1450 }
1451
1452 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1453                                       bool enable)
1454 {
1455         uint32_t temp, data;
1456
1457         temp = data = RREG32(0x157a);
1458
1459         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1460                 data |= 1;
1461         else
1462                 data &= ~1;
1463
1464         if (temp != data)
1465                 WREG32(0x157a, data);
1466 }
1467
1468
1469 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1470                                                     bool enable)
1471 {
1472         uint32_t temp, data;
1473
1474         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1475
1476         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1477                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1478                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1479         else
1480                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1481                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1482
1483         if (temp != data)
1484                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1485 }
1486
1487 static int vi_common_set_clockgating_state_by_smu(void *handle,
1488                                            enum amd_clockgating_state state)
1489 {
1490         uint32_t msg_id, pp_state = 0;
1491         uint32_t pp_support_state = 0;
1492         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1493
1494         if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1495                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1496                         pp_support_state = PP_STATE_SUPPORT_LS;
1497                         pp_state = PP_STATE_LS;
1498                 }
1499                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1500                         pp_support_state |= PP_STATE_SUPPORT_CG;
1501                         pp_state |= PP_STATE_CG;
1502                 }
1503                 if (state == AMD_CG_STATE_UNGATE)
1504                         pp_state = 0;
1505                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1506                                PP_BLOCK_SYS_MC,
1507                                pp_support_state,
1508                                pp_state);
1509                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1510         }
1511
1512         if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1513                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1514                         pp_support_state = PP_STATE_SUPPORT_LS;
1515                         pp_state = PP_STATE_LS;
1516                 }
1517                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1518                         pp_support_state |= PP_STATE_SUPPORT_CG;
1519                         pp_state |= PP_STATE_CG;
1520                 }
1521                 if (state == AMD_CG_STATE_UNGATE)
1522                         pp_state = 0;
1523                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1524                                PP_BLOCK_SYS_SDMA,
1525                                pp_support_state,
1526                                pp_state);
1527                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1528         }
1529
1530         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1531                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1532                         pp_support_state = PP_STATE_SUPPORT_LS;
1533                         pp_state = PP_STATE_LS;
1534                 }
1535                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1536                         pp_support_state |= PP_STATE_SUPPORT_CG;
1537                         pp_state |= PP_STATE_CG;
1538                 }
1539                 if (state == AMD_CG_STATE_UNGATE)
1540                         pp_state = 0;
1541                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1542                                PP_BLOCK_SYS_HDP,
1543                                pp_support_state,
1544                                pp_state);
1545                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1546         }
1547
1548
1549         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1550                 if (state == AMD_CG_STATE_UNGATE)
1551                         pp_state = 0;
1552                 else
1553                         pp_state = PP_STATE_LS;
1554
1555                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1556                                PP_BLOCK_SYS_BIF,
1557                                PP_STATE_SUPPORT_LS,
1558                                 pp_state);
1559                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1560         }
1561         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1562                 if (state == AMD_CG_STATE_UNGATE)
1563                         pp_state = 0;
1564                 else
1565                         pp_state = PP_STATE_CG;
1566
1567                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1568                                PP_BLOCK_SYS_BIF,
1569                                PP_STATE_SUPPORT_CG,
1570                                pp_state);
1571                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1572         }
1573
1574         if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1575
1576                 if (state == AMD_CG_STATE_UNGATE)
1577                         pp_state = 0;
1578                 else
1579                         pp_state = PP_STATE_LS;
1580
1581                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1582                                PP_BLOCK_SYS_DRM,
1583                                PP_STATE_SUPPORT_LS,
1584                                pp_state);
1585                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1586         }
1587
1588         if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1589
1590                 if (state == AMD_CG_STATE_UNGATE)
1591                         pp_state = 0;
1592                 else
1593                         pp_state = PP_STATE_CG;
1594
1595                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1596                                PP_BLOCK_SYS_ROM,
1597                                PP_STATE_SUPPORT_CG,
1598                                pp_state);
1599                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1600         }
1601         return 0;
1602 }
1603
1604 static int vi_common_set_clockgating_state(void *handle,
1605                                            enum amd_clockgating_state state)
1606 {
1607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608
1609         if (amdgpu_sriov_vf(adev))
1610                 return 0;
1611
1612         switch (adev->asic_type) {
1613         case CHIP_FIJI:
1614                 vi_update_bif_medium_grain_light_sleep(adev,
1615                                 state == AMD_CG_STATE_GATE);
1616                 vi_update_hdp_medium_grain_clock_gating(adev,
1617                                 state == AMD_CG_STATE_GATE);
1618                 vi_update_hdp_light_sleep(adev,
1619                                 state == AMD_CG_STATE_GATE);
1620                 vi_update_rom_medium_grain_clock_gating(adev,
1621                                 state == AMD_CG_STATE_GATE);
1622                 break;
1623         case CHIP_CARRIZO:
1624         case CHIP_STONEY:
1625                 vi_update_bif_medium_grain_light_sleep(adev,
1626                                 state == AMD_CG_STATE_GATE);
1627                 vi_update_hdp_medium_grain_clock_gating(adev,
1628                                 state == AMD_CG_STATE_GATE);
1629                 vi_update_hdp_light_sleep(adev,
1630                                 state == AMD_CG_STATE_GATE);
1631                 vi_update_drm_light_sleep(adev,
1632                                 state == AMD_CG_STATE_GATE);
1633                 break;
1634         case CHIP_TONGA:
1635         case CHIP_POLARIS10:
1636         case CHIP_POLARIS11:
1637         case CHIP_POLARIS12:
1638         case CHIP_VEGAM:
1639                 vi_common_set_clockgating_state_by_smu(adev, state);
1640                 break;
1641         default:
1642                 break;
1643         }
1644         return 0;
1645 }
1646
1647 static int vi_common_set_powergating_state(void *handle,
1648                                             enum amd_powergating_state state)
1649 {
1650         return 0;
1651 }
1652
1653 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1654 {
1655         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1656         int data;
1657
1658         if (amdgpu_sriov_vf(adev))
1659                 *flags = 0;
1660
1661         /* AMD_CG_SUPPORT_BIF_LS */
1662         data = RREG32_PCIE(ixPCIE_CNTL2);
1663         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1664                 *flags |= AMD_CG_SUPPORT_BIF_LS;
1665
1666         /* AMD_CG_SUPPORT_HDP_LS */
1667         data = RREG32(mmHDP_MEM_POWER_LS);
1668         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1669                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1670
1671         /* AMD_CG_SUPPORT_HDP_MGCG */
1672         data = RREG32(mmHDP_HOST_PATH_CNTL);
1673         if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1674                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1675
1676         /* AMD_CG_SUPPORT_ROM_MGCG */
1677         data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1678         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1679                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1680 }
1681
1682 static const struct amd_ip_funcs vi_common_ip_funcs = {
1683         .name = "vi_common",
1684         .early_init = vi_common_early_init,
1685         .late_init = vi_common_late_init,
1686         .sw_init = vi_common_sw_init,
1687         .sw_fini = vi_common_sw_fini,
1688         .hw_init = vi_common_hw_init,
1689         .hw_fini = vi_common_hw_fini,
1690         .suspend = vi_common_suspend,
1691         .resume = vi_common_resume,
1692         .is_idle = vi_common_is_idle,
1693         .wait_for_idle = vi_common_wait_for_idle,
1694         .soft_reset = vi_common_soft_reset,
1695         .set_clockgating_state = vi_common_set_clockgating_state,
1696         .set_powergating_state = vi_common_set_powergating_state,
1697         .get_clockgating_state = vi_common_get_clockgating_state,
1698 };
1699
1700 static const struct amdgpu_ip_block_version vi_common_ip_block =
1701 {
1702         .type = AMD_IP_BLOCK_TYPE_COMMON,
1703         .major = 1,
1704         .minor = 0,
1705         .rev = 0,
1706         .funcs = &vi_common_ip_funcs,
1707 };
1708
1709 void vi_set_virt_ops(struct amdgpu_device *adev)
1710 {
1711         adev->virt.ops = &xgpu_vi_virt_ops;
1712 }
1713
1714 int vi_set_ip_blocks(struct amdgpu_device *adev)
1715 {
1716         switch (adev->asic_type) {
1717         case CHIP_TOPAZ:
1718                 /* topaz has no DCE, UVD, VCE */
1719                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1720                 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1721                 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1722                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1723                 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1724                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1725                 if (adev->enable_virtual_display)
1726                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1727                 break;
1728         case CHIP_FIJI:
1729                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1730                 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1731                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1732                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1733                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1734                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1735                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1736                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1737 #if defined(CONFIG_DRM_AMD_DC)
1738                 else if (amdgpu_device_has_dc_support(adev))
1739                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1740 #endif
1741                 else
1742                         amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1743                 if (!amdgpu_sriov_vf(adev)) {
1744                         amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1745                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1746                 }
1747                 break;
1748         case CHIP_TONGA:
1749                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1750                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1751                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1752                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1753                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1754                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1755                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1756                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1757 #if defined(CONFIG_DRM_AMD_DC)
1758                 else if (amdgpu_device_has_dc_support(adev))
1759                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1760 #endif
1761                 else
1762                         amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1763                 if (!amdgpu_sriov_vf(adev)) {
1764                         amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1765                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1766                 }
1767                 break;
1768         case CHIP_POLARIS10:
1769         case CHIP_POLARIS11:
1770         case CHIP_POLARIS12:
1771         case CHIP_VEGAM:
1772                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1773                 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1774                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1775                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1776                 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1777                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1778                 if (adev->enable_virtual_display)
1779                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1780 #if defined(CONFIG_DRM_AMD_DC)
1781                 else if (amdgpu_device_has_dc_support(adev))
1782                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1783 #endif
1784                 else
1785                         amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1786                 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1787                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1788                 break;
1789         case CHIP_CARRIZO:
1790                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1791                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1792                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1793                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1794                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1795                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1796                 if (adev->enable_virtual_display)
1797                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1798 #if defined(CONFIG_DRM_AMD_DC)
1799                 else if (amdgpu_device_has_dc_support(adev))
1800                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1801 #endif
1802                 else
1803                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1804                 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1805                 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1806 #if defined(CONFIG_DRM_AMD_ACP)
1807                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1808 #endif
1809                 break;
1810         case CHIP_STONEY:
1811                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1812                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1813                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1814                 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1815                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1816                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1817                 if (adev->enable_virtual_display)
1818                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1819 #if defined(CONFIG_DRM_AMD_DC)
1820                 else if (amdgpu_device_has_dc_support(adev))
1821                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1822 #endif
1823                 else
1824                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1825                 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1826                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1827 #if defined(CONFIG_DRM_AMD_ACP)
1828                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1829 #endif
1830                 break;
1831         default:
1832                 /* FIXME: not supported yet */
1833                 return -EINVAL;
1834         }
1835
1836         return 0;
1837 }
1838
1839 void legacy_doorbell_index_init(struct amdgpu_device *adev)
1840 {
1841         adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1842         adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1843         adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1844         adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1845         adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1846         adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1847         adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1848         adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1849         adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1850         adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1851         adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1852         adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1853         adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1854         adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1855 }