drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  33 {
  34         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  35                                                 firmwareinfo);
  36         uint16_t data_offset;
  37
  38         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  39                                           NULL, NULL, &data_offset)) {
  40                 struct atom_firmware_info_v3_1 *firmware_info =
  41                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  42                                                            data_offset);
  43
  44                 if (le32_to_cpu(firmware_info->firmware_capability) &
  45                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  46                         return true;
  47         }
  48         return false;
  49 }
  50
  51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  52 {
  53         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  54                                                 firmwareinfo);
  55         uint16_t data_offset;
  56
  57         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  58                                           NULL, NULL, &data_offset)) {
  59                 struct atom_firmware_info_v3_1 *firmware_info =
  60                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  61                                                            data_offset);
  62
  63                 adev->bios_scratch_reg_offset =
  64                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  65         }
  66 }
  67
  68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  69 {
  70         struct atom_context *ctx = adev->mode_info.atom_context;
  71         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  72                                                 vram_usagebyfirmware);
  73         struct vram_usagebyfirmware_v2_1 *firmware_usage;
  74         uint32_t start_addr, size;
  75         uint16_t data_offset;
  76         int usage_bytes = 0;
  77
  78         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  79                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  81                           le32_to_cpu(firmware_usage->start_address_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  84
  85                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  86                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  87
  88                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  89                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  90                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  91                         /* Firmware request VRAM reservation for SR-IOV */
  92                         adev->mman.fw_vram_usage_start_offset = (start_addr &
  93                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  94                         adev->mman.fw_vram_usage_size = size << 10;
  95                         /* Use the default scratch size */
  96                         usage_bytes = 0;
  97                 } else {
  98                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  99                 }
 100         }
 101         ctx->scratch_size_bytes = 0;
 102         if (usage_bytes == 0)
 103                 usage_bytes = 20 * 1024;
 104         /* allocate some scratch memory */
 105         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 106         if (!ctx->scratch)
 107                 return -ENOMEM;
 108         ctx->scratch_size_bytes = usage_bytes;
 109         return 0;
 110 }
 111
 112 union igp_info {
 113         struct atom_integrated_system_info_v1_11 v11;
 114         struct atom_integrated_system_info_v1_12 v12;
 115         struct atom_integrated_system_info_v2_1 v21;
 116 };
 117
 118 union umc_info {
 119         struct atom_umc_info_v3_1 v31;
 120 };
 121
 122 union vram_info {
 123         struct atom_vram_info_header_v2_3 v23;
 124         struct atom_vram_info_header_v2_4 v24;
 125         struct atom_vram_info_header_v2_5 v25;
 126 };
 127
 128 union vram_module {
 129         struct atom_vram_module_v9 v9;
 130         struct atom_vram_module_v10 v10;
 131         struct atom_vram_module_v11 v11;
 132 };
 133
 134 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 135                                               int atom_mem_type)
 136 {
 137         int vram_type;
 138
 139         if (adev->flags & AMD_IS_APU) {
 140                 switch (atom_mem_type) {
 141                 case Ddr2MemType:
 142                 case LpDdr2MemType:
 143                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 144                         break;
 145                 case Ddr3MemType:
 146                 case LpDdr3MemType:
 147                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 148                         break;
 149                 case Ddr4MemType:
 150                 case LpDdr4MemType:
 151                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 152                         break;
 153                 case Ddr5MemType:
 154                 case LpDdr5MemType:
 155                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 156                         break;
 157                 default:
 158                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 159                         break;
 160                 }
 161         } else {
 162                 switch (atom_mem_type) {
 163                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 164                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 165                         break;
 166                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 167                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 168                         break;
 169                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 170                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 171                         break;
 172                 default:
 173                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 174                         break;
 175                 }
 176         }
 177
 178         return vram_type;
 179 }
 180
 181
 182 int
 183 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 184                                   int *vram_width, int *vram_type,
 185                                   int *vram_vendor)
 186 {
 187         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 188         int index, i = 0;
 189         u16 data_offset, size;
 190         union igp_info *igp_info;
 191         union vram_info *vram_info;
 192         union vram_module *vram_module;
 193         u8 frev, crev;
 194         u8 mem_type;
 195         u8 mem_vendor;
 196         u32 mem_channel_number;
 197         u32 mem_channel_width;
 198         u32 module_id;
 199
 200         if (adev->flags & AMD_IS_APU)
 201                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 202                                                     integratedsysteminfo);
 203         else
 204                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 205                                                     vram_info);
 206
 207         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 208                                           index, &size,
 209                                           &frev, &crev, &data_offset)) {
 210                 if (adev->flags & AMD_IS_APU) {
 211                         igp_info = (union igp_info *)
 212                                 (mode_info->atom_context->bios + data_offset);
 213                         switch (frev) {
 214                         case 1:
 215                                 switch (crev) {
 216                                 case 11:
 217                                 case 12:
 218                                         mem_channel_number = igp_info->v11.umachannelnumber;
 219                                         if (!mem_channel_number)
 220                                                 mem_channel_number = 1;
 221                                         /* channel width is 64 */
 222                                         if (vram_width)
 223                                                 *vram_width = mem_channel_number * 64;
 224                                         mem_type = igp_info->v11.memorytype;
 225                                         if (vram_type)
 226                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 227                                         break;
 228                                 default:
 229                                         return -EINVAL;
 230                                 }
 231                                 break;
 232                         case 2:
 233                                 switch (crev) {
 234                                 case 1:
 235                                 case 2:
 236                                         mem_channel_number = igp_info->v21.umachannelnumber;
 237                                         if (!mem_channel_number)
 238                                                 mem_channel_number = 1;
 239                                         /* channel width is 64 */
 240                                         if (vram_width)
 241                                                 *vram_width = mem_channel_number * 64;
 242                                         mem_type = igp_info->v21.memorytype;
 243                                         if (vram_type)
 244                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 245                                         break;
 246                                 default:
 247                                         return -EINVAL;
 248                                 }
 249                                 break;
 250                         default:
 251                                 return -EINVAL;
 252                         }
 253                 } else {
 254                         vram_info = (union vram_info *)
 255                                 (mode_info->atom_context->bios + data_offset);
 256                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 257                         switch (crev) {
 258                         case 3:
 259                                 if (module_id > vram_info->v23.vram_module_num)
 260                                         module_id = 0;
 261                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 262                                 while (i < module_id) {
 263                                         vram_module = (union vram_module *)
 264                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 265                                         i++;
 266                                 }
 267                                 mem_type = vram_module->v9.memory_type;
 268                                 if (vram_type)
 269                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 270                                 mem_channel_number = vram_module->v9.channel_num;
 271                                 mem_channel_width = vram_module->v9.channel_width;
 272                                 if (vram_width)
 273                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 274                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 275                                 if (vram_vendor)
 276                                         *vram_vendor = mem_vendor;
 277                                 break;
 278                         case 4:
 279                                 if (module_id > vram_info->v24.vram_module_num)
 280                                         module_id = 0;
 281                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 282                                 while (i < module_id) {
 283                                         vram_module = (union vram_module *)
 284                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 285                                         i++;
 286                                 }
 287                                 mem_type = vram_module->v10.memory_type;
 288                                 if (vram_type)
 289                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 290                                 mem_channel_number = vram_module->v10.channel_num;
 291                                 mem_channel_width = vram_module->v10.channel_width;
 292                                 if (vram_width)
 293                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 294                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 295                                 if (vram_vendor)
 296                                         *vram_vendor = mem_vendor;
 297                                 break;
 298                         case 5:
 299                                 if (module_id > vram_info->v25.vram_module_num)
 300                                         module_id = 0;
 301                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 302                                 while (i < module_id) {
 303                                         vram_module = (union vram_module *)
 304                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 305                                         i++;
 306                                 }
 307                                 mem_type = vram_module->v11.memory_type;
 308                                 if (vram_type)
 309                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 310                                 mem_channel_number = vram_module->v11.channel_num;
 311                                 mem_channel_width = vram_module->v11.channel_width;
 312                                 if (vram_width)
 313                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 314                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 315                                 if (vram_vendor)
 316                                         *vram_vendor = mem_vendor;
 317                                 break;
 318                         default:
 319                                 return -EINVAL;
 320                         }
 321                 }
 322
 323         }
 324
 325         return 0;
 326 }
 327
 328 /*
 329  * Return true if vbios enabled ecc by default, if umc info table is available
 330  * or false if ecc is not enabled or umc info table is not available
 331  */
 332 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 333 {
 334         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 335         int index;
 336         u16 data_offset, size;
 337         union umc_info *umc_info;
 338         u8 frev, crev;
 339         bool ecc_default_enabled = false;
 340
 341         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 342                         umc_info);
 343
 344         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 345                                 index, &size, &frev, &crev, &data_offset)) {
 346                 /* support umc_info 3.1+ */
 347                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
 348                         umc_info = (union umc_info *)
 349                                 (mode_info->atom_context->bios + data_offset);
 350                         ecc_default_enabled =
 351                                 (le32_to_cpu(umc_info->v31.umc_config) &
 352                                  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 353                 }
 354         }
 355
 356         return ecc_default_enabled;
 357 }
 358
 359 union firmware_info {
 360         struct atom_firmware_info_v3_1 v31;
 361         struct atom_firmware_info_v3_2 v32;
 362         struct atom_firmware_info_v3_3 v33;
 363         struct atom_firmware_info_v3_4 v34;
 364 };
 365
 366 /*
 367  * Return true if vbios supports sram ecc or false if not
 368  */
 369 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 370 {
 371         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 372         int index;
 373         u16 data_offset, size;
 374         union firmware_info *firmware_info;
 375         u8 frev, crev;
 376         bool sram_ecc_supported = false;
 377
 378         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 379                         firmwareinfo);
 380
 381         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 382                                 index, &size, &frev, &crev, &data_offset)) {
 383                 /* support firmware_info 3.1 + */
 384                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 385                         firmware_info = (union firmware_info *)
 386                                 (mode_info->atom_context->bios + data_offset);
 387                         sram_ecc_supported =
 388                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 389                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 390                 }
 391         }
 392
 393         return sram_ecc_supported;
 394 }
 395
 396 union smu_info {
 397         struct atom_smu_info_v3_1 v31;
 398 };
 399
 400 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 401 {
 402         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 403         struct amdgpu_pll *spll = &adev->clock.spll;
 404         struct amdgpu_pll *mpll = &adev->clock.mpll;
 405         uint8_t frev, crev;
 406         uint16_t data_offset;
 407         int ret = -EINVAL, index;
 408
 409         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 410                                             firmwareinfo);
 411         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 412                                    &frev, &crev, &data_offset)) {
 413                 union firmware_info *firmware_info =
 414                         (union firmware_info *)(mode_info->atom_context->bios +
 415                                                 data_offset);
 416
 417                 adev->clock.default_sclk =
 418                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 419                 adev->clock.default_mclk =
 420                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 421
 422                 adev->pm.current_sclk = adev->clock.default_sclk;
 423                 adev->pm.current_mclk = adev->clock.default_mclk;
 424
 425                 /* not technically a clock, but... */
 426                 adev->mode_info.firmware_flags =
 427                         le32_to_cpu(firmware_info->v31.firmware_capability);
 428
 429                 ret = 0;
 430         }
 431
 432         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 433                                             smu_info);
 434         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 435                                    &frev, &crev, &data_offset)) {
 436                 union smu_info *smu_info =
 437                         (union smu_info *)(mode_info->atom_context->bios +
 438                                            data_offset);
 439
 440                 /* system clock */
 441                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 442
 443                 spll->reference_div = 0;
 444                 spll->min_post_div = 1;
 445                 spll->max_post_div = 1;
 446                 spll->min_ref_div = 2;
 447                 spll->max_ref_div = 0xff;
 448                 spll->min_feedback_div = 4;
 449                 spll->max_feedback_div = 0xff;
 450                 spll->best_vco = 0;
 451
 452                 ret = 0;
 453         }
 454
 455         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 456                                             umc_info);
 457         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 458                                    &frev, &crev, &data_offset)) {
 459                 union umc_info *umc_info =
 460                         (union umc_info *)(mode_info->atom_context->bios +
 461                                            data_offset);
 462
 463                 /* memory clock */
 464                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 465
 466                 mpll->reference_div = 0;
 467                 mpll->min_post_div = 1;
 468                 mpll->max_post_div = 1;
 469                 mpll->min_ref_div = 2;
 470                 mpll->max_ref_div = 0xff;
 471                 mpll->min_feedback_div = 4;
 472                 mpll->max_feedback_div = 0xff;
 473                 mpll->best_vco = 0;
 474
 475                 ret = 0;
 476         }
 477
 478         return ret;
 479 }
 480
 481 union gfx_info {
 482         struct  atom_gfx_info_v2_4 v24;
 483 };
 484
 485 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 486 {
 487         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 488         int index;
 489         uint8_t frev, crev;
 490         uint16_t data_offset;
 491
 492         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 493                                             gfx_info);
 494         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 495                                    &frev, &crev, &data_offset)) {
 496                 union gfx_info *gfx_info = (union gfx_info *)
 497                         (mode_info->atom_context->bios + data_offset);
 498                 switch (crev) {
 499                 case 4:
 500                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 501                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 502                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 503                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 504                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 505                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 506                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 507                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 508                         adev->gfx.config.gs_prim_buffer_depth =
 509                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 510                         adev->gfx.config.double_offchip_lds_buf =
 511                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 512                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 513                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 514                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 515                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 516                         return 0;
 517                 default:
 518                         return -EINVAL;
 519                 }
 520
 521         }
 522         return -EINVAL;
 523 }
 524
 525 /*
 526  * Check if VBIOS supports GDDR6 training data save/restore
 527  */
 528 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 529 {
 530         uint16_t data_offset;
 531         int index;
 532
 533         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 534                                             firmwareinfo);
 535         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 536                                           NULL, NULL, &data_offset)) {
 537                 struct atom_firmware_info_v3_1 *firmware_info =
 538                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 539                                                            data_offset);
 540
 541                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 542                           le32_to_cpu(firmware_info->firmware_capability));
 543
 544                 if (le32_to_cpu(firmware_info->firmware_capability) &
 545                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 546                         return true;
 547         }
 548
 549         return false;
 550 }
 551
 552 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 553 {
 554         int ret;
 555         uint32_t major, minor, revision, hw_v;
 556
 557         if (gddr6_mem_train_vbios_support(adev)) {
 558                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 559                 hw_v = HW_REV(major, minor, revision);
 560                 /*
 561                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 562                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 563                  * none of the functions will be initialized, it should not cause any problems
 564                  */
 565                 switch (hw_v) {
 566                 case HW_REV(11, 0, 0):
 567                 case HW_REV(11, 0, 5):
 568                 case HW_REV(11, 0, 7):
 569                 case HW_REV(11, 0, 11):
 570                 case HW_REV(11, 0, 12):
 571                         ret = 1;
 572                         break;
 573                 default:
 574                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 575                                   " doesn't support!\n", hw_v);
 576                         ret = -1;
 577                         break;
 578                 }
 579         } else {
 580                 ret = 0;
 581                 hw_v = -1;
 582         }
 583
 584
 585         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 586         return ret;
 587 }
 588
 589 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 590 {
 591         struct atom_context *ctx = adev->mode_info.atom_context;
 592         union firmware_info *firmware_info;
 593         int index;
 594         u16 data_offset, size;
 595         u8 frev, crev;
 596         int fw_reserved_fb_size;
 597
 598         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 599                         firmwareinfo);
 600
 601         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 602                                 &frev, &crev, &data_offset))
 603                 /* fail to parse data_header */
 604                 return 0;
 605
 606         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 607
 608         if (frev !=3)
 609                 return -EINVAL;
 610
 611         switch (crev) {
 612         case 4:
 613                 fw_reserved_fb_size =
 614                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 615                 break;
 616         default:
 617                 fw_reserved_fb_size = 0;
 618                 break;
 619         }
 620
 621         return fw_reserved_fb_size;
 622 }