drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 103 {
 104         struct ras_err_data err_data = {0, 0, 0, NULL};
 105         struct eeprom_table_record err_rec;
 106
 107         if ((address >= adev->gmc.mc_vram_size) ||
 108             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 109                 dev_warn(adev->dev,
 110                          "RAS WARN: input address 0x%llx is invalid.\n",
 111                          address);
 112                 return -EINVAL;
 113         }
 114
 115         if (amdgpu_ras_check_bad_page(adev, address)) {
 116                 dev_warn(adev->dev,
 117                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 118                          address);
 119                 return 0;
 120         }
 121
 122         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 123
 124         err_rec.address = address;
 125         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 126         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 127         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 128
 129         err_data.err_addr = &err_rec;
 130         err_data.err_addr_cnt = 1;
 131
 132         if (amdgpu_bad_page_threshold != 0) {
 133                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 134                                          err_data.err_addr_cnt);
 135                 amdgpu_ras_save_bad_pages(adev);
 136         }
 137
 138         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 139         dev_warn(adev->dev, "Clear EEPROM:\n");
 140         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 141
 142         return 0;
 143 }
 144
 145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 146                                         size_t size, loff_t *pos)
 147 {
 148         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 149         struct ras_query_if info = {
 150                 .head = obj->head,
 151         };
 152         ssize_t s;
 153         char val[128];
 154
 155         if (amdgpu_ras_query_error_status(obj->adev, &info))
 156                 return -EINVAL;
 157
 158         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 159                         "ue", info.ue_count,
 160                         "ce", info.ce_count);
 161         if (*pos >= s)
 162                 return 0;
 163
 164         s -= *pos;
 165         s = min_t(u64, s, size);
 166
 167
 168         if (copy_to_user(buf, &val[*pos], s))
 169                 return -EINVAL;
 170
 171         *pos += s;
 172
 173         return s;
 174 }
 175
 176 static const struct file_operations amdgpu_ras_debugfs_ops = {
 177         .owner = THIS_MODULE,
 178         .read = amdgpu_ras_debugfs_read,
 179         .write = NULL,
 180         .llseek = default_llseek
 181 };
 182
 183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 184 {
 185         int i;
 186
 187         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 188                 *block_id = i;
 189                 if (strcmp(name, ras_block_str(i)) == 0)
 190                         return 0;
 191         }
 192         return -EINVAL;
 193 }
 194
 195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 196                 const char __user *buf, size_t size,
 197                 loff_t *pos, struct ras_debug_if *data)
 198 {
 199         ssize_t s = min_t(u64, 64, size);
 200         char str[65];
 201         char block_name[33];
 202         char err[9] = "ue";
 203         int op = -1;
 204         int block_id;
 205         uint32_t sub_block;
 206         u64 address, value;
 207
 208         if (*pos)
 209                 return -EINVAL;
 210         *pos = size;
 211
 212         memset(str, 0, sizeof(str));
 213         memset(data, 0, sizeof(*data));
 214
 215         if (copy_from_user(str, buf, s))
 216                 return -EINVAL;
 217
 218         if (sscanf(str, "disable %32s", block_name) == 1)
 219                 op = 0;
 220         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 221                 op = 1;
 222         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 223                 op = 2;
 224         else if (strstr(str, "retire_page") != NULL)
 225                 op = 3;
 226         else if (str[0] && str[1] && str[2] && str[3])
 227                 /* ascii string, but commands are not matched. */
 228                 return -EINVAL;
 229
 230         if (op != -1) {
 231                 if (op == 3) {
 232                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 233                             sscanf(str, "%*s %llu", &address) != 1)
 234                                 return -EINVAL;
 235
 236                         data->op = op;
 237                         data->inject.address = address;
 238
 239                         return 0;
 240                 }
 241
 242                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 243                         return -EINVAL;
 244
 245                 data->head.block = block_id;
 246                 /* only ue and ce errors are supported */
 247                 if (!memcmp("ue", err, 2))
 248                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 249                 else if (!memcmp("ce", err, 2))
 250                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 251                 else
 252                         return -EINVAL;
 253
 254                 data->op = op;
 255
 256                 if (op == 2) {
 257                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 258                                    &sub_block, &address, &value) != 3 &&
 259                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 260                                    &sub_block, &address, &value) != 3)
 261                                 return -EINVAL;
 262                         data->head.sub_block_index = sub_block;
 263                         data->inject.address = address;
 264                         data->inject.value = value;
 265                 }
 266         } else {
 267                 if (size < sizeof(*data))
 268                         return -EINVAL;
 269
 270                 if (copy_from_user(data, buf, sizeof(*data)))
 271                         return -EINVAL;
 272         }
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * DOC: AMDGPU RAS debugfs control interface
 279  *
 280  * The control interface accepts struct ras_debug_if which has two members.
 281  *
 282  * First member: ras_debug_if::head or ras_debug_if::inject.
 283  *
 284  * head is used to indicate which IP block will be under control.
 285  *
 286  * head has four members, they are block, type, sub_block_index, name.
 287  * block: which IP will be under control.
 288  * type: what kind of error will be enabled/disabled/injected.
 289  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 290  * name: the name of IP.
 291  *
 292  * inject has two more members than head, they are address, value.
 293  * As their names indicate, inject operation will write the
 294  * value to the address.
 295  *
 296  * The second member: struct ras_debug_if::op.
 297  * It has three kinds of operations.
 298  *
 299  * - 0: disable RAS on the block. Take ::head as its data.
 300  * - 1: enable RAS on the block. Take ::head as its data.
 301  * - 2: inject errors on the block. Take ::inject as its data.
 302  *
 303  * How to use the interface?
 304  *
 305  * In a program
 306  *
 307  * Copy the struct ras_debug_if in your code and initialize it.
 308  * Write the struct to the control interface.
 309  *
 310  * From shell
 311  *
 312  * .. code-block:: bash
 313  *
 314  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 315  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 316  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 317  *
 318  * Where N, is the card which you want to affect.
 319  *
 320  * "disable" requires only the block.
 321  * "enable" requires the block and error type.
 322  * "inject" requires the block, error type, address, and value.
 323  * The block is one of: umc, sdma, gfx, etc.
 324  *      see ras_block_string[] for details
 325  * The error type is one of: ue, ce, where,
 326  *      ue is multi-uncorrectable
 327  *      ce is single-correctable
 328  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 329  * The address and value are hexadecimal numbers, leading 0x is optional.
 330  *
 331  * For instance,
 332  *
 333  * .. code-block:: bash
 334  *
 335  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 336  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 337  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 338  *
 339  * How to check the result of the operation?
 340  *
 341  * To check disable/enable, see "ras" features at,
 342  * /sys/class/drm/card[0/1/2...]/device/ras/features
 343  *
 344  * To check inject, see the corresponding error count at,
 345  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 346  *
 347  * .. note::
 348  *      Operations are only allowed on blocks which are supported.
 349  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 350  *      to see which blocks support RAS on a particular asic.
 351  *
 352  */
 353 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 354                 size_t size, loff_t *pos)
 355 {
 356         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 357         struct ras_debug_if data;
 358         int ret = 0;
 359
 360         if (!amdgpu_ras_get_error_query_ready(adev)) {
 361                 dev_warn(adev->dev, "RAS WARN: error injection "
 362                                 "currently inaccessible\n");
 363                 return size;
 364         }
 365
 366         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 367         if (ret)
 368                 return -EINVAL;
 369
 370         if (data.op == 3) {
 371                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 372                 if (!ret)
 373                         return size;
 374                 else
 375                         return ret;
 376         }
 377
 378         if (!amdgpu_ras_is_supported(adev, data.head.block))
 379                 return -EINVAL;
 380
 381         switch (data.op) {
 382         case 0:
 383                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 384                 break;
 385         case 1:
 386                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 387                 break;
 388         case 2:
 389                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 390                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 391                         dev_warn(adev->dev, "RAS WARN: input address "
 392                                         "0x%llx is invalid.",
 393                                         data.inject.address);
 394                         ret = -EINVAL;
 395                         break;
 396                 }
 397
 398                 /* umc ce/ue error injection for a bad page is not allowed */
 399                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 400                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 401                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 402                                         "as bad before error injection!\n",
 403                                         data.inject.address);
 404                         break;
 405                 }
 406
 407                 /* data.inject.address is offset instead of absolute gpu address */
 408                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 409                 break;
 410         default:
 411                 ret = -EINVAL;
 412                 break;
 413         }
 414
 415         if (ret)
 416                 return -EINVAL;
 417
 418         return size;
 419 }
 420
 421 /**
 422  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 423  *
 424  * Some boards contain an EEPROM which is used to persistently store a list of
 425  * bad pages which experiences ECC errors in vram.  This interface provides
 426  * a way to reset the EEPROM, e.g., after testing error injection.
 427  *
 428  * Usage:
 429  *
 430  * .. code-block:: bash
 431  *
 432  *      echo 1 > ../ras/ras_eeprom_reset
 433  *
 434  * will reset EEPROM table to 0 entries.
 435  *
 436  */
 437 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 438                 size_t size, loff_t *pos)
 439 {
 440         struct amdgpu_device *adev =
 441                 (struct amdgpu_device *)file_inode(f)->i_private;
 442         int ret;
 443
 444         ret = amdgpu_ras_eeprom_reset_table(
 445                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 446
 447         if (ret == 1) {
 448                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 449                 return size;
 450         } else {
 451                 return -EIO;
 452         }
 453 }
 454
 455 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 456         .owner = THIS_MODULE,
 457         .read = NULL,
 458         .write = amdgpu_ras_debugfs_ctrl_write,
 459         .llseek = default_llseek
 460 };
 461
 462 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 463         .owner = THIS_MODULE,
 464         .read = NULL,
 465         .write = amdgpu_ras_debugfs_eeprom_write,
 466         .llseek = default_llseek
 467 };
 468
 469 /**
 470  * DOC: AMDGPU RAS sysfs Error Count Interface
 471  *
 472  * It allows the user to read the error count for each IP block on the gpu through
 473  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 474  *
 475  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 476  * (ce) error counts.
 477  *
 478  * The format of one line is below,
 479  *
 480  * [ce|ue]: count
 481  *
 482  * Example:
 483  *
 484  * .. code-block:: bash
 485  *
 486  *      ue: 0
 487  *      ce: 1
 488  *
 489  */
 490 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 491                 struct device_attribute *attr, char *buf)
 492 {
 493         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 494         struct ras_query_if info = {
 495                 .head = obj->head,
 496         };
 497
 498         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 499                 return sysfs_emit(buf, "Query currently inaccessible\n");
 500
 501         if (amdgpu_ras_query_error_status(obj->adev, &info))
 502                 return -EINVAL;
 503
 504         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 505                           "ce", info.ce_count);
 506 }
 507
 508 /* obj begin */
 509
 510 #define get_obj(obj) do { (obj)->use++; } while (0)
 511 #define alive_obj(obj) ((obj)->use)
 512
 513 static inline void put_obj(struct ras_manager *obj)
 514 {
 515         if (obj && (--obj->use == 0))
 516                 list_del(&obj->node);
 517         if (obj && (obj->use < 0))
 518                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 519 }
 520
 521 /* make one obj and return it. */
 522 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 523                 struct ras_common_if *head)
 524 {
 525         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 526         struct ras_manager *obj;
 527
 528         if (!adev->ras_features || !con)
 529                 return NULL;
 530
 531         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 532                 return NULL;
 533
 534         obj = &con->objs[head->block];
 535         /* already exist. return obj? */
 536         if (alive_obj(obj))
 537                 return NULL;
 538
 539         obj->head = *head;
 540         obj->adev = adev;
 541         list_add(&obj->node, &con->head);
 542         get_obj(obj);
 543
 544         return obj;
 545 }
 546
 547 /* return an obj equal to head, or the first when head is NULL */
 548 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 549                 struct ras_common_if *head)
 550 {
 551         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 552         struct ras_manager *obj;
 553         int i;
 554
 555         if (!adev->ras_features || !con)
 556                 return NULL;
 557
 558         if (head) {
 559                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 560                         return NULL;
 561
 562                 obj = &con->objs[head->block];
 563
 564                 if (alive_obj(obj)) {
 565                         WARN_ON(head->block != obj->head.block);
 566                         return obj;
 567                 }
 568         } else {
 569                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 570                         obj = &con->objs[i];
 571                         if (alive_obj(obj)) {
 572                                 WARN_ON(i != obj->head.block);
 573                                 return obj;
 574                         }
 575                 }
 576         }
 577
 578         return NULL;
 579 }
 580 /* obj end */
 581
 582 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 583                                          const char* invoke_type,
 584                                          const char* block_name,
 585                                          enum ta_ras_status ret)
 586 {
 587         switch (ret) {
 588         case TA_RAS_STATUS__SUCCESS:
 589                 return;
 590         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 591                 dev_warn(adev->dev,
 592                         "RAS WARN: %s %s currently unavailable\n",
 593                         invoke_type,
 594                         block_name);
 595                 break;
 596         default:
 597                 dev_err(adev->dev,
 598                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 599                         invoke_type,
 600                         block_name,
 601                         ret);
 602         }
 603 }
 604
 605 /* feature ctl begin */
 606 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 607                 struct ras_common_if *head)
 608 {
 609         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 610
 611         return con->hw_supported & BIT(head->block);
 612 }
 613
 614 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 615                 struct ras_common_if *head)
 616 {
 617         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 618
 619         return con->features & BIT(head->block);
 620 }
 621
 622 /*
 623  * if obj is not created, then create one.
 624  * set feature enable flag.
 625  */
 626 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 627                 struct ras_common_if *head, int enable)
 628 {
 629         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 630         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 631
 632         /* If hardware does not support ras, then do not create obj.
 633          * But if hardware support ras, we can create the obj.
 634          * Ras framework checks con->hw_supported to see if it need do
 635          * corresponding initialization.
 636          * IP checks con->support to see if it need disable ras.
 637          */
 638         if (!amdgpu_ras_is_feature_allowed(adev, head))
 639                 return 0;
 640         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 641                 return 0;
 642
 643         if (enable) {
 644                 if (!obj) {
 645                         obj = amdgpu_ras_create_obj(adev, head);
 646                         if (!obj)
 647                                 return -EINVAL;
 648                 } else {
 649                         /* In case we create obj somewhere else */
 650                         get_obj(obj);
 651                 }
 652                 con->features |= BIT(head->block);
 653         } else {
 654                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 655                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 656                          * will clean later
 657                          */
 658                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 659                                 con->features &= ~BIT(head->block);
 660                         put_obj(obj);
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 /* wrapper of psp_ras_enable_features */
 668 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 669                 struct ras_common_if *head, bool enable)
 670 {
 671         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 672         union ta_ras_cmd_input *info;
 673         int ret;
 674
 675         if (!con)
 676                 return -EINVAL;
 677
 678         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 679         if (!info)
 680                 return -ENOMEM;
 681
 682         if (!enable) {
 683                 info->disable_features = (struct ta_ras_disable_features_input) {
 684                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 685                         .error_type = amdgpu_ras_error_to_ta(head->type),
 686                 };
 687         } else {
 688                 info->enable_features = (struct ta_ras_enable_features_input) {
 689                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 690                         .error_type = amdgpu_ras_error_to_ta(head->type),
 691                 };
 692         }
 693
 694         /* Do not enable if it is not allowed. */
 695         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 696         /* Are we alerady in that state we are going to set? */
 697         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 698                 ret = 0;
 699                 goto out;
 700         }
 701
 702         if (!amdgpu_ras_intr_triggered()) {
 703                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 704                 if (ret) {
 705                         amdgpu_ras_parse_status_code(adev,
 706                                                      enable ? "enable":"disable",
 707                                                      ras_block_str(head->block),
 708                                                     (enum ta_ras_status)ret);
 709                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 710                                 ret = -EAGAIN;
 711                         else
 712                                 ret = -EINVAL;
 713
 714                         goto out;
 715                 }
 716         }
 717
 718         /* setup the obj */
 719         __amdgpu_ras_feature_enable(adev, head, enable);
 720         ret = 0;
 721 out:
 722         kfree(info);
 723         return ret;
 724 }
 725
 726 /* Only used in device probe stage and called only once. */
 727 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 728                 struct ras_common_if *head, bool enable)
 729 {
 730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 731         int ret;
 732
 733         if (!con)
 734                 return -EINVAL;
 735
 736         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 737                 if (enable) {
 738                         /* There is no harm to issue a ras TA cmd regardless of
 739                          * the currecnt ras state.
 740                          * If current state == target state, it will do nothing
 741                          * But sometimes it requests driver to reset and repost
 742                          * with error code -EAGAIN.
 743                          */
 744                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 745                         /* With old ras TA, we might fail to enable ras.
 746                          * Log it and just setup the object.
 747                          * TODO need remove this WA in the future.
 748                          */
 749                         if (ret == -EINVAL) {
 750                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 751                                 if (!ret)
 752                                         dev_info(adev->dev,
 753                                                 "RAS INFO: %s setup object\n",
 754                                                 ras_block_str(head->block));
 755                         }
 756                 } else {
 757                         /* setup the object then issue a ras TA disable cmd.*/
 758                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 759                         if (ret)
 760                                 return ret;
 761
 762                         /* gfx block ras dsiable cmd must send to ras-ta */
 763                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 764                                 con->features |= BIT(head->block);
 765
 766                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 767                 }
 768         } else
 769                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 770
 771         return ret;
 772 }
 773
 774 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 775                 bool bypass)
 776 {
 777         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 778         struct ras_manager *obj, *tmp;
 779
 780         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 781                 /* bypass psp.
 782                  * aka just release the obj and corresponding flags
 783                  */
 784                 if (bypass) {
 785                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 786                                 break;
 787                 } else {
 788                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 789                                 break;
 790                 }
 791         }
 792
 793         return con->features;
 794 }
 795
 796 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 797                 bool bypass)
 798 {
 799         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 800         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 801         int i;
 802         const enum amdgpu_ras_error_type default_ras_type =
 803                 AMDGPU_RAS_ERROR__NONE;
 804
 805         for (i = 0; i < ras_block_count; i++) {
 806                 struct ras_common_if head = {
 807                         .block = i,
 808                         .type = default_ras_type,
 809                         .sub_block_index = 0,
 810                 };
 811                 strcpy(head.name, ras_block_str(i));
 812                 if (bypass) {
 813                         /*
 814                          * bypass psp. vbios enable ras for us.
 815                          * so just create the obj
 816                          */
 817                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 818                                 break;
 819                 } else {
 820                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 821                                 break;
 822                 }
 823         }
 824
 825         return con->features;
 826 }
 827 /* feature ctl end */
 828
 829 /* query/inject/cure begin */
 830 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 831         struct ras_query_if *info)
 832 {
 833         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 834         struct ras_err_data err_data = {0, 0, 0, NULL};
 835         int i;
 836
 837         if (!obj)
 838                 return -EINVAL;
 839
 840         switch (info->head.block) {
 841         case AMDGPU_RAS_BLOCK__UMC:
 842                 if (adev->umc.ras_funcs &&
 843                     adev->umc.ras_funcs->query_ras_error_count)
 844                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 845                 /* umc query_ras_error_address is also responsible for clearing
 846                  * error status
 847                  */
 848                 if (adev->umc.ras_funcs &&
 849                     adev->umc.ras_funcs->query_ras_error_address)
 850                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 851                 break;
 852         case AMDGPU_RAS_BLOCK__SDMA:
 853                 if (adev->sdma.funcs->query_ras_error_count) {
 854                         for (i = 0; i < adev->sdma.num_instances; i++)
 855                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 856                                                                         &err_data);
 857                 }
 858                 break;
 859         case AMDGPU_RAS_BLOCK__GFX:
 860                 if (adev->gfx.ras_funcs &&
 861                     adev->gfx.ras_funcs->query_ras_error_count)
 862                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 863
 864                 if (adev->gfx.ras_funcs &&
 865                     adev->gfx.ras_funcs->query_ras_error_status)
 866                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 867                 break;
 868         case AMDGPU_RAS_BLOCK__MMHUB:
 869                 if (adev->mmhub.ras_funcs &&
 870                     adev->mmhub.ras_funcs->query_ras_error_count)
 871                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 872
 873                 if (adev->mmhub.ras_funcs &&
 874                     adev->mmhub.ras_funcs->query_ras_error_status)
 875                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 876                 break;
 877         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 878                 if (adev->nbio.ras_funcs &&
 879                     adev->nbio.ras_funcs->query_ras_error_count)
 880                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 881                 break;
 882         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 883                 if (adev->gmc.xgmi.ras_funcs &&
 884                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 885                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 886                 break;
 887         default:
 888                 break;
 889         }
 890
 891         obj->err_data.ue_count += err_data.ue_count;
 892         obj->err_data.ce_count += err_data.ce_count;
 893
 894         info->ue_count = obj->err_data.ue_count;
 895         info->ce_count = obj->err_data.ce_count;
 896
 897         if (err_data.ce_count) {
 898                 dev_info(adev->dev, "%ld correctable hardware errors "
 899                                         "detected in %s block, no user "
 900                                         "action is needed.\n",
 901                                         obj->err_data.ce_count,
 902                                         ras_block_str(info->head.block));
 903         }
 904         if (err_data.ue_count) {
 905                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 906                                         "detected in %s block\n",
 907                                         obj->err_data.ue_count,
 908                                         ras_block_str(info->head.block));
 909         }
 910
 911         return 0;
 912 }
 913
 914 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 915                 enum amdgpu_ras_block block)
 916 {
 917         if (!amdgpu_ras_is_supported(adev, block))
 918                 return -EINVAL;
 919
 920         switch (block) {
 921         case AMDGPU_RAS_BLOCK__GFX:
 922                 if (adev->gfx.ras_funcs &&
 923                     adev->gfx.ras_funcs->reset_ras_error_count)
 924                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 925
 926                 if (adev->gfx.ras_funcs &&
 927                     adev->gfx.ras_funcs->reset_ras_error_status)
 928                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 929                 break;
 930         case AMDGPU_RAS_BLOCK__MMHUB:
 931                 if (adev->mmhub.ras_funcs &&
 932                     adev->mmhub.ras_funcs->reset_ras_error_count)
 933                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 934                 break;
 935         case AMDGPU_RAS_BLOCK__SDMA:
 936                 if (adev->sdma.funcs->reset_ras_error_count)
 937                         adev->sdma.funcs->reset_ras_error_count(adev);
 938                 break;
 939         default:
 940                 break;
 941         }
 942
 943         return 0;
 944 }
 945
 946 /* Trigger XGMI/WAFL error */
 947 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 948                                  struct ta_ras_trigger_error_input *block_info)
 949 {
 950         int ret;
 951
 952         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 953                 dev_warn(adev->dev, "Failed to disallow df cstate");
 954
 955         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 956                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 957
 958         ret = psp_ras_trigger_error(&adev->psp, block_info);
 959
 960         if (amdgpu_ras_intr_triggered())
 961                 return ret;
 962
 963         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 964                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 965
 966         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 967                 dev_warn(adev->dev, "Failed to allow df cstate");
 968
 969         return ret;
 970 }
 971
 972 /* wrapper of psp_ras_trigger_error */
 973 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 974                 struct ras_inject_if *info)
 975 {
 976         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 977         struct ta_ras_trigger_error_input block_info = {
 978                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 979                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 980                 .sub_block_index = info->head.sub_block_index,
 981                 .address = info->address,
 982                 .value = info->value,
 983         };
 984         int ret = 0;
 985
 986         if (!obj)
 987                 return -EINVAL;
 988
 989         /* Calculate XGMI relative offset */
 990         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 991                 block_info.address =
 992                         amdgpu_xgmi_get_relative_phy_addr(adev,
 993                                                           block_info.address);
 994         }
 995
 996         switch (info->head.block) {
 997         case AMDGPU_RAS_BLOCK__GFX:
 998                 if (adev->gfx.ras_funcs &&
 999                     adev->gfx.ras_funcs->ras_error_inject)
1000                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1001                 else
1002                         ret = -EINVAL;
1003                 break;
1004         case AMDGPU_RAS_BLOCK__UMC:
1005         case AMDGPU_RAS_BLOCK__SDMA:
1006         case AMDGPU_RAS_BLOCK__MMHUB:
1007         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1008                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1009                 break;
1010         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1011                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1012                 break;
1013         default:
1014                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1015                          ras_block_str(info->head.block));
1016                 ret = -EINVAL;
1017         }
1018
1019         amdgpu_ras_parse_status_code(adev,
1020                                      "inject",
1021                                      ras_block_str(info->head.block),
1022                                      (enum ta_ras_status)ret);
1023
1024         return ret;
1025 }
1026
1027 /* get the total error counts on all IPs */
1028 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1029                 bool is_ce)
1030 {
1031         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1032         struct ras_manager *obj;
1033         struct ras_err_data data = {0, 0};
1034
1035         if (!adev->ras_features || !con)
1036                 return 0;
1037
1038         list_for_each_entry(obj, &con->head, node) {
1039                 struct ras_query_if info = {
1040                         .head = obj->head,
1041                 };
1042
1043                 if (amdgpu_ras_query_error_status(adev, &info))
1044                         return 0;
1045
1046                 data.ce_count += info.ce_count;
1047                 data.ue_count += info.ue_count;
1048         }
1049
1050         return is_ce ? data.ce_count : data.ue_count;
1051 }
1052 /* query/inject/cure end */
1053
1054
1055 /* sysfs begin */
1056
1057 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1058                 struct ras_badpage **bps, unsigned int *count);
1059
1060 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1061 {
1062         switch (flags) {
1063         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1064                 return "R";
1065         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1066                 return "P";
1067         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1068         default:
1069                 return "F";
1070         }
1071 }
1072
1073 /**
1074  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1075  *
1076  * It allows user to read the bad pages of vram on the gpu through
1077  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1078  *
1079  * It outputs multiple lines, and each line stands for one gpu page.
1080  *
1081  * The format of one line is below,
1082  * gpu pfn : gpu page size : flags
1083  *
1084  * gpu pfn and gpu page size are printed in hex format.
1085  * flags can be one of below character,
1086  *
1087  * R: reserved, this gpu page is reserved and not able to use.
1088  *
1089  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1090  * in next window of page_reserve.
1091  *
1092  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1093  *
1094  * Examples:
1095  *
1096  * .. code-block:: bash
1097  *
1098  *      0x00000001 : 0x00001000 : R
1099  *      0x00000002 : 0x00001000 : P
1100  *
1101  */
1102
1103 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1104                 struct kobject *kobj, struct bin_attribute *attr,
1105                 char *buf, loff_t ppos, size_t count)
1106 {
1107         struct amdgpu_ras *con =
1108                 container_of(attr, struct amdgpu_ras, badpages_attr);
1109         struct amdgpu_device *adev = con->adev;
1110         const unsigned int element_size =
1111                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1112         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1113         unsigned int end = div64_ul(ppos + count - 1, element_size);
1114         ssize_t s = 0;
1115         struct ras_badpage *bps = NULL;
1116         unsigned int bps_count = 0;
1117
1118         memset(buf, 0, count);
1119
1120         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1121                 return 0;
1122
1123         for (; start < end && start < bps_count; start++)
1124                 s += scnprintf(&buf[s], element_size + 1,
1125                                 "0x%08x : 0x%08x : %1s\n",
1126                                 bps[start].bp,
1127                                 bps[start].size,
1128                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1129
1130         kfree(bps);
1131
1132         return s;
1133 }
1134
1135 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1136                 struct device_attribute *attr, char *buf)
1137 {
1138         struct amdgpu_ras *con =
1139                 container_of(attr, struct amdgpu_ras, features_attr);
1140
1141         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1142 }
1143
1144 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1145 {
1146         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1147
1148         sysfs_remove_file_from_group(&adev->dev->kobj,
1149                                 &con->badpages_attr.attr,
1150                                 RAS_FS_NAME);
1151 }
1152
1153 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1154 {
1155         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1156         struct attribute *attrs[] = {
1157                 &con->features_attr.attr,
1158                 NULL
1159         };
1160         struct attribute_group group = {
1161                 .name = RAS_FS_NAME,
1162                 .attrs = attrs,
1163         };
1164
1165         sysfs_remove_group(&adev->dev->kobj, &group);
1166
1167         return 0;
1168 }
1169
1170 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1171                 struct ras_fs_if *head)
1172 {
1173         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1174
1175         if (!obj || obj->attr_inuse)
1176                 return -EINVAL;
1177
1178         get_obj(obj);
1179
1180         memcpy(obj->fs_data.sysfs_name,
1181                         head->sysfs_name,
1182                         sizeof(obj->fs_data.sysfs_name));
1183
1184         obj->sysfs_attr = (struct device_attribute){
1185                 .attr = {
1186                         .name = obj->fs_data.sysfs_name,
1187                         .mode = S_IRUGO,
1188                 },
1189                         .show = amdgpu_ras_sysfs_read,
1190         };
1191         sysfs_attr_init(&obj->sysfs_attr.attr);
1192
1193         if (sysfs_add_file_to_group(&adev->dev->kobj,
1194                                 &obj->sysfs_attr.attr,
1195                                 RAS_FS_NAME)) {
1196                 put_obj(obj);
1197                 return -EINVAL;
1198         }
1199
1200         obj->attr_inuse = 1;
1201
1202         return 0;
1203 }
1204
1205 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1206                 struct ras_common_if *head)
1207 {
1208         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1209
1210         if (!obj || !obj->attr_inuse)
1211                 return -EINVAL;
1212
1213         sysfs_remove_file_from_group(&adev->dev->kobj,
1214                                 &obj->sysfs_attr.attr,
1215                                 RAS_FS_NAME);
1216         obj->attr_inuse = 0;
1217         put_obj(obj);
1218
1219         return 0;
1220 }
1221
1222 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1223 {
1224         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1225         struct ras_manager *obj, *tmp;
1226
1227         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1228                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1229         }
1230
1231         if (amdgpu_bad_page_threshold != 0)
1232                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1233
1234         amdgpu_ras_sysfs_remove_feature_node(adev);
1235
1236         return 0;
1237 }
1238 /* sysfs end */
1239
1240 /**
1241  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1242  *
1243  * Normally when there is an uncorrectable error, the driver will reset
1244  * the GPU to recover.  However, in the event of an unrecoverable error,
1245  * the driver provides an interface to reboot the system automatically
1246  * in that event.
1247  *
1248  * The following file in debugfs provides that interface:
1249  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1250  *
1251  * Usage:
1252  *
1253  * .. code-block:: bash
1254  *
1255  *      echo true > .../ras/auto_reboot
1256  *
1257  */
1258 /* debugfs begin */
1259 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1260 {
1261         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1262         struct dentry *dir;
1263         struct drm_minor *minor = adev_to_drm(adev)->primary;
1264
1265         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1266         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1267                             &amdgpu_ras_debugfs_ctrl_ops);
1268         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1269                             &amdgpu_ras_debugfs_eeprom_ops);
1270         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1271                            &con->bad_page_cnt_threshold);
1272
1273         /*
1274          * After one uncorrectable error happens, usually GPU recovery will
1275          * be scheduled. But due to the known problem in GPU recovery failing
1276          * to bring GPU back, below interface provides one direct way to
1277          * user to reboot system automatically in such case within
1278          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1279          * will never be called.
1280          */
1281         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1282
1283         /*
1284          * User could set this not to clean up hardware's error count register
1285          * of RAS IPs during ras recovery.
1286          */
1287         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1288                             &con->disable_ras_err_cnt_harvest);
1289         return dir;
1290 }
1291
1292 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1293                                       struct ras_fs_if *head,
1294                                       struct dentry *dir)
1295 {
1296         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1297
1298         if (!obj || !dir)
1299                 return;
1300
1301         get_obj(obj);
1302
1303         memcpy(obj->fs_data.debugfs_name,
1304                         head->debugfs_name,
1305                         sizeof(obj->fs_data.debugfs_name));
1306
1307         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1308                             obj, &amdgpu_ras_debugfs_ops);
1309 }
1310
1311 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1312 {
1313         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1314         struct dentry *dir;
1315         struct ras_manager *obj;
1316         struct ras_fs_if fs_info;
1317
1318         /*
1319          * it won't be called in resume path, no need to check
1320          * suspend and gpu reset status
1321          */
1322         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1323                 return;
1324
1325         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1326
1327         list_for_each_entry(obj, &con->head, node) {
1328                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1329                         (obj->attr_inuse == 1)) {
1330                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1331                                         ras_block_str(obj->head.block));
1332                         fs_info.head = obj->head;
1333                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1334                 }
1335         }
1336 }
1337
1338 /* debugfs end */
1339
1340 /* ras fs */
1341 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1342                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1343 static DEVICE_ATTR(features, S_IRUGO,
1344                 amdgpu_ras_sysfs_features_read, NULL);
1345 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1346 {
1347         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1348         struct attribute_group group = {
1349                 .name = RAS_FS_NAME,
1350         };
1351         struct attribute *attrs[] = {
1352                 &con->features_attr.attr,
1353                 NULL
1354         };
1355         struct bin_attribute *bin_attrs[] = {
1356                 NULL,
1357                 NULL,
1358         };
1359         int r;
1360
1361         /* add features entry */
1362         con->features_attr = dev_attr_features;
1363         group.attrs = attrs;
1364         sysfs_attr_init(attrs[0]);
1365
1366         if (amdgpu_bad_page_threshold != 0) {
1367                 /* add bad_page_features entry */
1368                 bin_attr_gpu_vram_bad_pages.private = NULL;
1369                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1370                 bin_attrs[0] = &con->badpages_attr;
1371                 group.bin_attrs = bin_attrs;
1372                 sysfs_bin_attr_init(bin_attrs[0]);
1373         }
1374
1375         r = sysfs_create_group(&adev->dev->kobj, &group);
1376         if (r)
1377                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1378
1379         return 0;
1380 }
1381
1382 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1383 {
1384         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1385         struct ras_manager *con_obj, *ip_obj, *tmp;
1386
1387         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1388                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1389                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1390                         if (ip_obj)
1391                                 put_obj(ip_obj);
1392                 }
1393         }
1394
1395         amdgpu_ras_sysfs_remove_all(adev);
1396         return 0;
1397 }
1398 /* ras fs end */
1399
1400 /* ih begin */
1401 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1402 {
1403         struct ras_ih_data *data = &obj->ih_data;
1404         struct amdgpu_iv_entry entry;
1405         int ret;
1406         struct ras_err_data err_data = {0, 0, 0, NULL};
1407
1408         while (data->rptr != data->wptr) {
1409                 rmb();
1410                 memcpy(&entry, &data->ring[data->rptr],
1411                                 data->element_size);
1412
1413                 wmb();
1414                 data->rptr = (data->aligned_element_size +
1415                                 data->rptr) % data->ring_size;
1416
1417                 /* Let IP handle its data, maybe we need get the output
1418                  * from the callback to udpate the error type/count, etc
1419                  */
1420                 if (data->cb) {
1421                         ret = data->cb(obj->adev, &err_data, &entry);
1422                         /* ue will trigger an interrupt, and in that case
1423                          * we need do a reset to recovery the whole system.
1424                          * But leave IP do that recovery, here we just dispatch
1425                          * the error.
1426                          */
1427                         if (ret == AMDGPU_RAS_SUCCESS) {
1428                                 /* these counts could be left as 0 if
1429                                  * some blocks do not count error number
1430                                  */
1431                                 obj->err_data.ue_count += err_data.ue_count;
1432                                 obj->err_data.ce_count += err_data.ce_count;
1433                         }
1434                 }
1435         }
1436 }
1437
1438 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1439 {
1440         struct ras_ih_data *data =
1441                 container_of(work, struct ras_ih_data, ih_work);
1442         struct ras_manager *obj =
1443                 container_of(data, struct ras_manager, ih_data);
1444
1445         amdgpu_ras_interrupt_handler(obj);
1446 }
1447
1448 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1449                 struct ras_dispatch_if *info)
1450 {
1451         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1452         struct ras_ih_data *data = &obj->ih_data;
1453
1454         if (!obj)
1455                 return -EINVAL;
1456
1457         if (data->inuse == 0)
1458                 return 0;
1459
1460         /* Might be overflow... */
1461         memcpy(&data->ring[data->wptr], info->entry,
1462                         data->element_size);
1463
1464         wmb();
1465         data->wptr = (data->aligned_element_size +
1466                         data->wptr) % data->ring_size;
1467
1468         schedule_work(&data->ih_work);
1469
1470         return 0;
1471 }
1472
1473 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1474                 struct ras_ih_if *info)
1475 {
1476         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1477         struct ras_ih_data *data;
1478
1479         if (!obj)
1480                 return -EINVAL;
1481
1482         data = &obj->ih_data;
1483         if (data->inuse == 0)
1484                 return 0;
1485
1486         cancel_work_sync(&data->ih_work);
1487
1488         kfree(data->ring);
1489         memset(data, 0, sizeof(*data));
1490         put_obj(obj);
1491
1492         return 0;
1493 }
1494
1495 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1496                 struct ras_ih_if *info)
1497 {
1498         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1499         struct ras_ih_data *data;
1500
1501         if (!obj) {
1502                 /* in case we registe the IH before enable ras feature */
1503                 obj = amdgpu_ras_create_obj(adev, &info->head);
1504                 if (!obj)
1505                         return -EINVAL;
1506         } else
1507                 get_obj(obj);
1508
1509         data = &obj->ih_data;
1510         /* add the callback.etc */
1511         *data = (struct ras_ih_data) {
1512                 .inuse = 0,
1513                 .cb = info->cb,
1514                 .element_size = sizeof(struct amdgpu_iv_entry),
1515                 .rptr = 0,
1516                 .wptr = 0,
1517         };
1518
1519         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1520
1521         data->aligned_element_size = ALIGN(data->element_size, 8);
1522         /* the ring can store 64 iv entries. */
1523         data->ring_size = 64 * data->aligned_element_size;
1524         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1525         if (!data->ring) {
1526                 put_obj(obj);
1527                 return -ENOMEM;
1528         }
1529
1530         /* IH is ready */
1531         data->inuse = 1;
1532
1533         return 0;
1534 }
1535
1536 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1537 {
1538         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1539         struct ras_manager *obj, *tmp;
1540
1541         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1542                 struct ras_ih_if info = {
1543                         .head = obj->head,
1544                 };
1545                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1546         }
1547
1548         return 0;
1549 }
1550 /* ih end */
1551
1552 /* traversal all IPs except NBIO to query error counter */
1553 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1554 {
1555         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1556         struct ras_manager *obj;
1557
1558         if (!adev->ras_features || !con)
1559                 return;
1560
1561         list_for_each_entry(obj, &con->head, node) {
1562                 struct ras_query_if info = {
1563                         .head = obj->head,
1564                 };
1565
1566                 /*
1567                  * PCIE_BIF IP has one different isr by ras controller
1568                  * interrupt, the specific ras counter query will be
1569                  * done in that isr. So skip such block from common
1570                  * sync flood interrupt isr calling.
1571                  */
1572                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1573                         continue;
1574
1575                 amdgpu_ras_query_error_status(adev, &info);
1576         }
1577 }
1578
1579 /* Parse RdRspStatus and WrRspStatus */
1580 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1581                                           struct ras_query_if *info)
1582 {
1583         /*
1584          * Only two block need to query read/write
1585          * RspStatus at current state
1586          */
1587         switch (info->head.block) {
1588         case AMDGPU_RAS_BLOCK__GFX:
1589                 if (adev->gfx.ras_funcs &&
1590                     adev->gfx.ras_funcs->query_ras_error_status)
1591                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1592                 break;
1593         case AMDGPU_RAS_BLOCK__MMHUB:
1594                 if (adev->mmhub.ras_funcs &&
1595                     adev->mmhub.ras_funcs->query_ras_error_status)
1596                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1597                 break;
1598         default:
1599                 break;
1600         }
1601 }
1602
1603 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1604 {
1605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1606         struct ras_manager *obj;
1607
1608         if (!adev->ras_features || !con)
1609                 return;
1610
1611         list_for_each_entry(obj, &con->head, node) {
1612                 struct ras_query_if info = {
1613                         .head = obj->head,
1614                 };
1615
1616                 amdgpu_ras_error_status_query(adev, &info);
1617         }
1618 }
1619
1620 /* recovery begin */
1621
1622 /* return 0 on success.
1623  * caller need free bps.
1624  */
1625 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1626                 struct ras_badpage **bps, unsigned int *count)
1627 {
1628         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1629         struct ras_err_handler_data *data;
1630         int i = 0;
1631         int ret = 0, status;
1632
1633         if (!con || !con->eh_data || !bps || !count)
1634                 return -EINVAL;
1635
1636         mutex_lock(&con->recovery_lock);
1637         data = con->eh_data;
1638         if (!data || data->count == 0) {
1639                 *bps = NULL;
1640                 ret = -EINVAL;
1641                 goto out;
1642         }
1643
1644         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1645         if (!*bps) {
1646                 ret = -ENOMEM;
1647                 goto out;
1648         }
1649
1650         for (; i < data->count; i++) {
1651                 (*bps)[i] = (struct ras_badpage){
1652                         .bp = data->bps[i].retired_page,
1653                         .size = AMDGPU_GPU_PAGE_SIZE,
1654                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1655                 };
1656                 status = amdgpu_vram_mgr_query_page_status(
1657                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1658                                 data->bps[i].retired_page);
1659                 if (status == -EBUSY)
1660                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1661                 else if (status == -ENOENT)
1662                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1663         }
1664
1665         *count = data->count;
1666 out:
1667         mutex_unlock(&con->recovery_lock);
1668         return ret;
1669 }
1670
1671 static void amdgpu_ras_do_recovery(struct work_struct *work)
1672 {
1673         struct amdgpu_ras *ras =
1674                 container_of(work, struct amdgpu_ras, recovery_work);
1675         struct amdgpu_device *remote_adev = NULL;
1676         struct amdgpu_device *adev = ras->adev;
1677         struct list_head device_list, *device_list_handle =  NULL;
1678
1679         if (!ras->disable_ras_err_cnt_harvest) {
1680                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1681
1682                 /* Build list of devices to query RAS related errors */
1683                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1684                         device_list_handle = &hive->device_list;
1685                 } else {
1686                         INIT_LIST_HEAD(&device_list);
1687                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1688                         device_list_handle = &device_list;
1689                 }
1690
1691                 list_for_each_entry(remote_adev,
1692                                 device_list_handle, gmc.xgmi.head) {
1693                         amdgpu_ras_query_err_status(remote_adev);
1694                         amdgpu_ras_log_on_err_counter(remote_adev);
1695                 }
1696
1697                 amdgpu_put_xgmi_hive(hive);
1698         }
1699
1700         if (amdgpu_device_should_recover_gpu(ras->adev))
1701                 amdgpu_device_gpu_recover(ras->adev, NULL);
1702         atomic_set(&ras->in_recovery, 0);
1703 }
1704
1705 /* alloc/realloc bps array */
1706 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1707                 struct ras_err_handler_data *data, int pages)
1708 {
1709         unsigned int old_space = data->count + data->space_left;
1710         unsigned int new_space = old_space + pages;
1711         unsigned int align_space = ALIGN(new_space, 512);
1712         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1713
1714         if (!bps) {
1715                 kfree(bps);
1716                 return -ENOMEM;
1717         }
1718
1719         if (data->bps) {
1720                 memcpy(bps, data->bps,
1721                                 data->count * sizeof(*data->bps));
1722                 kfree(data->bps);
1723         }
1724
1725         data->bps = bps;
1726         data->space_left += align_space - old_space;
1727         return 0;
1728 }
1729
1730 /* it deal with vram only. */
1731 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1732                 struct eeprom_table_record *bps, int pages)
1733 {
1734         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1735         struct ras_err_handler_data *data;
1736         int ret = 0;
1737         uint32_t i;
1738
1739         if (!con || !con->eh_data || !bps || pages <= 0)
1740                 return 0;
1741
1742         mutex_lock(&con->recovery_lock);
1743         data = con->eh_data;
1744         if (!data)
1745                 goto out;
1746
1747         for (i = 0; i < pages; i++) {
1748                 if (amdgpu_ras_check_bad_page_unlock(con,
1749                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1750                         continue;
1751
1752                 if (!data->space_left &&
1753                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1754                         ret = -ENOMEM;
1755                         goto out;
1756                 }
1757
1758                 amdgpu_vram_mgr_reserve_range(
1759                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1760                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1761                         AMDGPU_GPU_PAGE_SIZE);
1762
1763                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1764                 data->count++;
1765                 data->space_left--;
1766         }
1767 out:
1768         mutex_unlock(&con->recovery_lock);
1769
1770         return ret;
1771 }
1772
1773 /*
1774  * write error record array to eeprom, the function should be
1775  * protected by recovery_lock
1776  */
1777 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1778 {
1779         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1780         struct ras_err_handler_data *data;
1781         struct amdgpu_ras_eeprom_control *control;
1782         int save_count;
1783
1784         if (!con || !con->eh_data)
1785                 return 0;
1786
1787         control = &con->eeprom_control;
1788         data = con->eh_data;
1789         save_count = data->count - control->num_recs;
1790         /* only new entries are saved */
1791         if (save_count > 0) {
1792                 if (amdgpu_ras_eeprom_process_recods(control,
1793                                                         &data->bps[control->num_recs],
1794                                                         true,
1795                                                         save_count)) {
1796                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1797                         return -EIO;
1798                 }
1799
1800                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1801         }
1802
1803         return 0;
1804 }
1805
1806 /*
1807  * read error record array in eeprom and reserve enough space for
1808  * storing new bad pages
1809  */
1810 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1811 {
1812         struct amdgpu_ras_eeprom_control *control =
1813                                         &adev->psp.ras.ras->eeprom_control;
1814         struct eeprom_table_record *bps = NULL;
1815         int ret = 0;
1816
1817         /* no bad page record, skip eeprom access */
1818         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1819                 return ret;
1820
1821         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1822         if (!bps)
1823                 return -ENOMEM;
1824
1825         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1826                 control->num_recs)) {
1827                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1828                 ret = -EIO;
1829                 goto out;
1830         }
1831
1832         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1833
1834 out:
1835         kfree(bps);
1836         return ret;
1837 }
1838
1839 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1840                                 uint64_t addr)
1841 {
1842         struct ras_err_handler_data *data = con->eh_data;
1843         int i;
1844
1845         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1846         for (i = 0; i < data->count; i++)
1847                 if (addr == data->bps[i].retired_page)
1848                         return true;
1849
1850         return false;
1851 }
1852
1853 /*
1854  * check if an address belongs to bad page
1855  *
1856  * Note: this check is only for umc block
1857  */
1858 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1859                                 uint64_t addr)
1860 {
1861         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1862         bool ret = false;
1863
1864         if (!con || !con->eh_data)
1865                 return ret;
1866
1867         mutex_lock(&con->recovery_lock);
1868         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1869         mutex_unlock(&con->recovery_lock);
1870         return ret;
1871 }
1872
1873 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1874                                         uint32_t max_length)
1875 {
1876         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1877         int tmp_threshold = amdgpu_bad_page_threshold;
1878         u64 val;
1879
1880         /*
1881          * Justification of value bad_page_cnt_threshold in ras structure
1882          *
1883          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1884          * in eeprom, and introduce two scenarios accordingly.
1885          *
1886          * Bad page retirement enablement:
1887          *    - If amdgpu_bad_page_threshold = -1,
1888          *      bad_page_cnt_threshold = typical value by formula.
1889          *
1890          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1891          *      max record length in eeprom, use it directly.
1892          *
1893          * Bad page retirement disablement:
1894          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1895          *      functionality is disabled, and bad_page_cnt_threshold will
1896          *      take no effect.
1897          */
1898
1899         if (tmp_threshold < -1)
1900                 tmp_threshold = -1;
1901         else if (tmp_threshold > max_length)
1902                 tmp_threshold = max_length;
1903
1904         if (tmp_threshold == -1) {
1905                 val = adev->gmc.mc_vram_size;
1906                 do_div(val, RAS_BAD_PAGE_RATE);
1907                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1908                                                 max_length);
1909         } else {
1910                 con->bad_page_cnt_threshold = tmp_threshold;
1911         }
1912 }
1913
1914 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1915 {
1916         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1917         struct ras_err_handler_data **data;
1918         uint32_t max_eeprom_records_len = 0;
1919         bool exc_err_limit = false;
1920         int ret;
1921
1922         if (adev->ras_features && con)
1923                 data = &con->eh_data;
1924         else
1925                 return 0;
1926
1927         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1928         if (!*data) {
1929                 ret = -ENOMEM;
1930                 goto out;
1931         }
1932
1933         mutex_init(&con->recovery_lock);
1934         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1935         atomic_set(&con->in_recovery, 0);
1936         con->adev = adev;
1937
1938         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1939         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1940
1941         /* Todo: During test the SMU might fail to read the eeprom through I2C
1942          * when the GPU is pending on XGMI reset during probe time
1943          * (Mostly after second bus reset), skip it now
1944          */
1945         if (adev->gmc.xgmi.pending_reset)
1946                 return 0;
1947         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1948         /*
1949          * This calling fails when exc_err_limit is true or
1950          * ret != 0.
1951          */
1952         if (exc_err_limit || ret)
1953                 goto free;
1954
1955         if (con->eeprom_control.num_recs) {
1956                 ret = amdgpu_ras_load_bad_pages(adev);
1957                 if (ret)
1958                         goto free;
1959         }
1960
1961         return 0;
1962
1963 free:
1964         kfree((*data)->bps);
1965         kfree(*data);
1966         con->eh_data = NULL;
1967 out:
1968         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1969
1970         /*
1971          * Except error threshold exceeding case, other failure cases in this
1972          * function would not fail amdgpu driver init.
1973          */
1974         if (!exc_err_limit)
1975                 ret = 0;
1976         else
1977                 ret = -EINVAL;
1978
1979         return ret;
1980 }
1981
1982 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1983 {
1984         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1985         struct ras_err_handler_data *data = con->eh_data;
1986
1987         /* recovery_init failed to init it, fini is useless */
1988         if (!data)
1989                 return 0;
1990
1991         cancel_work_sync(&con->recovery_work);
1992
1993         mutex_lock(&con->recovery_lock);
1994         con->eh_data = NULL;
1995         kfree(data->bps);
1996         kfree(data);
1997         mutex_unlock(&con->recovery_lock);
1998
1999         return 0;
2000 }
2001 /* recovery end */
2002
2003 /* return 0 if ras will reset gpu and repost.*/
2004 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2005                 unsigned int block)
2006 {
2007         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2008
2009         if (!ras)
2010                 return -EINVAL;
2011
2012         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2013         return 0;
2014 }
2015
2016 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2017 {
2018         return adev->asic_type == CHIP_VEGA10 ||
2019                 adev->asic_type == CHIP_VEGA20 ||
2020                 adev->asic_type == CHIP_ARCTURUS ||
2021                 adev->asic_type == CHIP_ALDEBARAN ||
2022                 adev->asic_type == CHIP_SIENNA_CICHLID;
2023 }
2024
2025 /*
2026  * check hardware's ras ability which will be saved in hw_supported.
2027  * if hardware does not support ras, we can skip some ras initializtion and
2028  * forbid some ras operations from IP.
2029  * if software itself, say boot parameter, limit the ras ability. We still
2030  * need allow IP do some limited operations, like disable. In such case,
2031  * we have to initialize ras as normal. but need check if operation is
2032  * allowed or not in each function.
2033  */
2034 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2035                 uint32_t *hw_supported, uint32_t *supported)
2036 {
2037         *hw_supported = 0;
2038         *supported = 0;
2039
2040         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2041             !amdgpu_ras_asic_supported(adev))
2042                 return;
2043
2044         if (!adev->gmc.xgmi.connected_to_cpu) {
2045                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2046                         dev_info(adev->dev, "MEM ECC is active.\n");
2047                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2048                                         1 << AMDGPU_RAS_BLOCK__DF);
2049                 } else {
2050                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2051                 }
2052
2053                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2054                         dev_info(adev->dev, "SRAM ECC is active.\n");
2055                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2056                                         1 << AMDGPU_RAS_BLOCK__DF);
2057                 } else {
2058                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2059                 }
2060         } else {
2061                 /* driver only manages a few IP blocks RAS feature
2062                  * when GPU is connected cpu through XGMI */
2063                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
2064                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2065                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
2066         }
2067
2068         /* hw_supported needs to be aligned with RAS block mask. */
2069         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2070
2071         *supported = amdgpu_ras_enable == 0 ?
2072                         0 : *hw_supported & amdgpu_ras_mask;
2073         adev->ras_features = *supported;
2074 }
2075
2076 int amdgpu_ras_init(struct amdgpu_device *adev)
2077 {
2078         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2079         int r;
2080
2081         if (con)
2082                 return 0;
2083
2084         con = kmalloc(sizeof(struct amdgpu_ras) +
2085                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2086                         GFP_KERNEL|__GFP_ZERO);
2087         if (!con)
2088                 return -ENOMEM;
2089
2090         con->objs = (struct ras_manager *)(con + 1);
2091
2092         amdgpu_ras_set_context(adev, con);
2093
2094         amdgpu_ras_check_supported(adev, &con->hw_supported,
2095                         &con->supported);
2096         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2097                 /* set gfx block ras context feature for VEGA20 Gaming
2098                  * send ras disable cmd to ras ta during ras late init.
2099                  */
2100                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2101                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2102
2103                         return 0;
2104                 }
2105
2106                 r = 0;
2107                 goto release_con;
2108         }
2109
2110         con->features = 0;
2111         INIT_LIST_HEAD(&con->head);
2112         /* Might need get this flag from vbios. */
2113         con->flags = RAS_DEFAULT_FLAGS;
2114
2115         /* initialize nbio ras function ahead of any other
2116          * ras functions so hardware fatal error interrupt
2117          * can be enabled as early as possible */
2118         switch (adev->asic_type) {
2119         case CHIP_VEGA20:
2120         case CHIP_ARCTURUS:
2121         case CHIP_ALDEBARAN:
2122                 if (!adev->gmc.xgmi.connected_to_cpu)
2123                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2124                 break;
2125         default:
2126                 /* nbio ras is not available */
2127                 break;
2128         }
2129
2130         if (adev->nbio.ras_funcs &&
2131             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2132                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2133                 if (r)
2134                         goto release_con;
2135         }
2136
2137         if (adev->nbio.ras_funcs &&
2138             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2139                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2140                 if (r)
2141                         goto release_con;
2142         }
2143
2144         if (amdgpu_ras_fs_init(adev)) {
2145                 r = -EINVAL;
2146                 goto release_con;
2147         }
2148
2149         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2150                         "hardware ability[%x] ras_mask[%x]\n",
2151                         con->hw_supported, con->supported);
2152         return 0;
2153 release_con:
2154         amdgpu_ras_set_context(adev, NULL);
2155         kfree(con);
2156
2157         return r;
2158 }
2159
2160 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2161 {
2162         if (adev->gmc.xgmi.connected_to_cpu)
2163                 return 1;
2164         return 0;
2165 }
2166
2167 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2168                                         struct ras_common_if *ras_block)
2169 {
2170         struct ras_query_if info = {
2171                 .head = *ras_block,
2172         };
2173
2174         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2175                 return 0;
2176
2177         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2178                 DRM_WARN("RAS init harvest failure");
2179
2180         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2181                 DRM_WARN("RAS init harvest reset failure");
2182
2183         return 0;
2184 }
2185
2186 /* helper function to handle common stuff in ip late init phase */
2187 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2188                          struct ras_common_if *ras_block,
2189                          struct ras_fs_if *fs_info,
2190                          struct ras_ih_if *ih_info)
2191 {
2192         int r;
2193
2194         /* disable RAS feature per IP block if it is not supported */
2195         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2196                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2197                 return 0;
2198         }
2199
2200         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2201         if (r) {
2202                 if (r == -EAGAIN) {
2203                         /* request gpu reset. will run again */
2204                         amdgpu_ras_request_reset_on_boot(adev,
2205                                         ras_block->block);
2206                         return 0;
2207                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2208                         /* in resume phase, if fail to enable ras,
2209                          * clean up all ras fs nodes, and disable ras */
2210                         goto cleanup;
2211                 } else
2212                         return r;
2213         }
2214
2215         /* check for errors on warm reset edc persisant supported ASIC */
2216         amdgpu_persistent_edc_harvesting(adev, ras_block);
2217
2218         /* in resume phase, no need to create ras fs node */
2219         if (adev->in_suspend || amdgpu_in_reset(adev))
2220                 return 0;
2221
2222         if (ih_info->cb) {
2223                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2224                 if (r)
2225                         goto interrupt;
2226         }
2227
2228         r = amdgpu_ras_sysfs_create(adev, fs_info);
2229         if (r)
2230                 goto sysfs;
2231
2232         return 0;
2233 cleanup:
2234         amdgpu_ras_sysfs_remove(adev, ras_block);
2235 sysfs:
2236         if (ih_info->cb)
2237                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2238 interrupt:
2239         amdgpu_ras_feature_enable(adev, ras_block, 0);
2240         return r;
2241 }
2242
2243 /* helper function to remove ras fs node and interrupt handler */
2244 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2245                           struct ras_common_if *ras_block,
2246                           struct ras_ih_if *ih_info)
2247 {
2248         if (!ras_block || !ih_info)
2249                 return;
2250
2251         amdgpu_ras_sysfs_remove(adev, ras_block);
2252         if (ih_info->cb)
2253                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2254         amdgpu_ras_feature_enable(adev, ras_block, 0);
2255 }
2256
2257 /* do some init work after IP late init as dependence.
2258  * and it runs in resume/gpu reset/booting up cases.
2259  */
2260 void amdgpu_ras_resume(struct amdgpu_device *adev)
2261 {
2262         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2263         struct ras_manager *obj, *tmp;
2264
2265         if (!adev->ras_features || !con) {
2266                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2267                 amdgpu_release_ras_context(adev);
2268
2269                 return;
2270         }
2271
2272         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2273                 /* Set up all other IPs which are not implemented. There is a
2274                  * tricky thing that IP's actual ras error type should be
2275                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2276                  * ERROR_NONE make sense anyway.
2277                  */
2278                 amdgpu_ras_enable_all_features(adev, 1);
2279
2280                 /* We enable ras on all hw_supported block, but as boot
2281                  * parameter might disable some of them and one or more IP has
2282                  * not implemented yet. So we disable them on behalf.
2283                  */
2284                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2285                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2286                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2287                                 /* there should be no any reference. */
2288                                 WARN_ON(alive_obj(obj));
2289                         }
2290                 }
2291         }
2292
2293         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2294                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2295                 /* setup ras obj state as disabled.
2296                  * for init_by_vbios case.
2297                  * if we want to enable ras, just enable it in a normal way.
2298                  * If we want do disable it, need setup ras obj as enabled,
2299                  * then issue another TA disable cmd.
2300                  * See feature_enable_on_boot
2301                  */
2302                 amdgpu_ras_disable_all_features(adev, 1);
2303                 amdgpu_ras_reset_gpu(adev);
2304         }
2305 }
2306
2307 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2308 {
2309         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2310
2311         if (!adev->ras_features || !con)
2312                 return;
2313
2314         amdgpu_ras_disable_all_features(adev, 0);
2315         /* Make sure all ras objects are disabled. */
2316         if (con->features)
2317                 amdgpu_ras_disable_all_features(adev, 1);
2318 }
2319
2320 /* do some fini work before IP fini as dependence */
2321 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2322 {
2323         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2324
2325         if (!adev->ras_features || !con)
2326                 return 0;
2327
2328         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2329         amdgpu_ras_disable_all_features(adev, 0);
2330         amdgpu_ras_recovery_fini(adev);
2331         return 0;
2332 }
2333
2334 int amdgpu_ras_fini(struct amdgpu_device *adev)
2335 {
2336         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2337
2338         if (!adev->ras_features || !con)
2339                 return 0;
2340
2341         amdgpu_ras_fs_fini(adev);
2342         amdgpu_ras_interrupt_remove_all(adev);
2343
2344         WARN(con->features, "Feature mask is not cleared");
2345
2346         if (con->features)
2347                 amdgpu_ras_disable_all_features(adev, 1);
2348
2349         amdgpu_ras_set_context(adev, NULL);
2350         kfree(con);
2351
2352         return 0;
2353 }
2354
2355 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2356 {
2357         uint32_t hw_supported, supported;
2358
2359         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2360         if (!hw_supported)
2361                 return;
2362
2363         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2364                 dev_info(adev->dev, "uncorrectable hardware error"
2365                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2366
2367                 amdgpu_ras_reset_gpu(adev);
2368         }
2369 }
2370
2371 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2372 {
2373         if (adev->asic_type == CHIP_VEGA20 &&
2374             adev->pm.fw_version <= 0x283400) {
2375                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2376                                 amdgpu_ras_intr_triggered();
2377         }
2378
2379         return false;
2380 }
2381
2382 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2383 {
2384         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2385
2386         if (!con)
2387                 return;
2388
2389         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2390                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2391                 amdgpu_ras_set_context(adev, NULL);
2392                 kfree(con);
2393         }
2394 }