arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *  Maintained by: Borislav Petkov <[email protected]>
   9  *
  10  *  All MC4_MISCi registers are shared between cores on a node.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/notifier.h>
  14 #include <linux/kobject.h>
  15 #include <linux/percpu.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/cpu.h>
  22 #include <linux/smp.h>
  23 #include <linux/string.h>
  24
  25 #include <asm/amd_nb.h>
  26 #include <asm/apic.h>
  27 #include <asm/idle.h>
  28 #include <asm/mce.h>
  29 #include <asm/msr.h>
  30 #include <asm/trace/irq_vectors.h>
  31
  32 #define NR_BLOCKS         5
  33 #define THRESHOLD_MAX     0xFFF
  34 #define INT_TYPE_APIC     0x00020000
  35 #define MASK_VALID_HI     0x80000000
  36 #define MASK_CNTP_HI      0x40000000
  37 #define MASK_LOCKED_HI    0x20000000
  38 #define MASK_LVTOFF_HI    0x00F00000
  39 #define MASK_COUNT_EN_HI  0x00080000
  40 #define MASK_INT_TYPE_HI  0x00060000
  41 #define MASK_OVERFLOW_HI  0x00010000
  42 #define MASK_ERR_COUNT_HI 0x00000FFF
  43 #define MASK_BLKPTR_LO    0xFF000000
  44 #define MCG_XBLK_ADDR     0xC0000400
  45
  46 /* Deferred error settings */
  47 #define MSR_CU_DEF_ERR          0xC0000410
  48 #define MASK_DEF_LVTOFF         0x000000F0
  49 #define MASK_DEF_INT_TYPE       0x00000006
  50 #define DEF_LVT_OFF             0x2
  51 #define DEF_INT_TYPE_APIC       0x2
  52
  53 /* Scalable MCA: */
  54
  55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  56 #define SMCA_THR_LVT_OFF        0xF000
  57
  58 static const char * const th_names[] = {
  59         "load_store",
  60         "insn_fetch",
  61         "combined_unit",
  62         "",
  63         "northbridge",
  64         "execution_unit",
  65 };
  66
  67 static const char * const smca_umc_block_names[] = {
  68         "dram_ecc",
  69         "misc_umc"
  70 };
  71
  72 struct smca_bank_name {
  73         const char *name;       /* Short name for sysfs */
  74         const char *long_name;  /* Long name for pretty-printing */
  75 };
  76
  77 static struct smca_bank_name smca_names[] = {
  78         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
  79         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
  80         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
  81         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
  82         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
  83         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
  84         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
  85         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
  86         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
  87         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
  88         [SMCA_PB]       = { "param_block",      "Parameter Block" },
  89         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
  90         [SMCA_SMU]      = { "smu",              "System Management Unit" },
  91 };
  92
  93 const char *smca_get_name(enum smca_bank_types t)
  94 {
  95         if (t >= N_SMCA_BANK_TYPES)
  96                 return NULL;
  97
  98         return smca_names[t].name;
  99 }
 100
 101 const char *smca_get_long_name(enum smca_bank_types t)
 102 {
 103         if (t >= N_SMCA_BANK_TYPES)
 104                 return NULL;
 105
 106         return smca_names[t].long_name;
 107 }
 108 EXPORT_SYMBOL_GPL(smca_get_long_name);
 109
 110 static struct smca_hwid smca_hwid_mcatypes[] = {
 111         /* { bank_type, hwid_mcatype, xec_bitmap } */
 112
 113         /* ZN Core (HWID=0xB0) MCA types */
 114         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
 115         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
 116         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
 117         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
 118         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 119         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
 120         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
 121         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 122
 123         /* Data Fabric MCA types */
 124         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
 125         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
 126
 127         /* Unified Memory Controller MCA type */
 128         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
 129
 130         /* Parameter Block MCA type */
 131         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
 132
 133         /* Platform Security Processor MCA type */
 134         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
 135
 136         /* System Management Unit MCA type */
 137         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
 138 };
 139
 140 struct smca_bank smca_banks[MAX_NR_BANKS];
 141 EXPORT_SYMBOL_GPL(smca_banks);
 142
 143 /*
 144  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 145  * So to define a unique name for each bank, we use a temp c-string to append
 146  * the MCA_IPID[InstanceId] to type's name in get_name().
 147  *
 148  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 149  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 150  */
 151 #define MAX_MCATYPE_NAME_LEN    30
 152 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 153
 154 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 155 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
 156
 157 static void amd_threshold_interrupt(void);
 158 static void amd_deferred_error_interrupt(void);
 159
 160 static void default_deferred_error_interrupt(void)
 161 {
 162         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 163 }
 164 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 165
 166 static void get_smca_bank_info(unsigned int bank)
 167 {
 168         unsigned int i, hwid_mcatype, cpu = smp_processor_id();
 169         struct smca_hwid *s_hwid;
 170         u32 high, instance_id;
 171
 172         /* Collect bank_info using CPU 0 for now. */
 173         if (cpu)
 174                 return;
 175
 176         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) {
 177                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 178                 return;
 179         }
 180
 181         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 182                                     (high & MCI_IPID_MCATYPE) >> 16);
 183
 184         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 185                 s_hwid = &smca_hwid_mcatypes[i];
 186                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 187
 188                         WARN(smca_banks[bank].hwid,
 189                              "Bank %s already initialized!\n",
 190                              smca_get_name(s_hwid->bank_type));
 191
 192                         smca_banks[bank].hwid = s_hwid;
 193                         smca_banks[bank].id = instance_id;
 194                         break;
 195                 }
 196         }
 197 }
 198
 199 struct thresh_restart {
 200         struct threshold_block  *b;
 201         int                     reset;
 202         int                     set_lvt_off;
 203         int                     lvt_off;
 204         u16                     old_limit;
 205 };
 206
 207 static inline bool is_shared_bank(int bank)
 208 {
 209         /*
 210          * Scalable MCA provides for only one core to have access to the MSRs of
 211          * a shared bank.
 212          */
 213         if (mce_flags.smca)
 214                 return false;
 215
 216         /* Bank 4 is for northbridge reporting and is thus shared */
 217         return (bank == 4);
 218 }
 219
 220 static const char *bank4_names(const struct threshold_block *b)
 221 {
 222         switch (b->address) {
 223         /* MSR4_MISC0 */
 224         case 0x00000413:
 225                 return "dram";
 226
 227         case 0xc0000408:
 228                 return "ht_links";
 229
 230         case 0xc0000409:
 231                 return "l3_cache";
 232
 233         default:
 234                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 235                 return "";
 236         }
 237 };
 238
 239
 240 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 241 {
 242         /*
 243          * bank 4 supports APIC LVT interrupts implicitly since forever.
 244          */
 245         if (bank == 4)
 246                 return true;
 247
 248         /*
 249          * IntP: interrupt present; if this bit is set, the thresholding
 250          * bank can generate APIC LVT interrupts
 251          */
 252         return msr_high_bits & BIT(28);
 253 }
 254
 255 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 256 {
 257         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 258
 259         if (apic < 0) {
 260                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 261                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 262                        b->bank, b->block, b->address, hi, lo);
 263                 return 0;
 264         }
 265
 266         if (apic != msr) {
 267                 /*
 268                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 269                  * the BIOS provides the value. The original field where LVT offset
 270                  * was set is reserved. Return early here:
 271                  */
 272                 if (mce_flags.smca)
 273                         return 0;
 274
 275                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 276                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 277                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 278                 return 0;
 279         }
 280
 281         return 1;
 282 };
 283
 284 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 285 static void threshold_restart_bank(void *_tr)
 286 {
 287         struct thresh_restart *tr = _tr;
 288         u32 hi, lo;
 289
 290         rdmsr(tr->b->address, lo, hi);
 291
 292         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 293                 tr->reset = 1;  /* limit cannot be lower than err count */
 294
 295         if (tr->reset) {                /* reset err count and overflow bit */
 296                 hi =
 297                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 298                     (THRESHOLD_MAX - tr->b->threshold_limit);
 299         } else if (tr->old_limit) {     /* change limit w/o reset */
 300                 int new_count = (hi & THRESHOLD_MAX) +
 301                     (tr->old_limit - tr->b->threshold_limit);
 302
 303                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 304                     (new_count & THRESHOLD_MAX);
 305         }
 306
 307         /* clear IntType */
 308         hi &= ~MASK_INT_TYPE_HI;
 309
 310         if (!tr->b->interrupt_capable)
 311                 goto done;
 312
 313         if (tr->set_lvt_off) {
 314                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 315                         /* set new lvt offset */
 316                         hi &= ~MASK_LVTOFF_HI;
 317                         hi |= tr->lvt_off << 20;
 318                 }
 319         }
 320
 321         if (tr->b->interrupt_enable)
 322                 hi |= INT_TYPE_APIC;
 323
 324  done:
 325
 326         hi |= MASK_COUNT_EN_HI;
 327         wrmsr(tr->b->address, lo, hi);
 328 }
 329
 330 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 331 {
 332         struct thresh_restart tr = {
 333                 .b                      = b,
 334                 .set_lvt_off            = 1,
 335                 .lvt_off                = offset,
 336         };
 337
 338         b->threshold_limit              = THRESHOLD_MAX;
 339         threshold_restart_bank(&tr);
 340 };
 341
 342 static int setup_APIC_mce_threshold(int reserved, int new)
 343 {
 344         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 345                                               APIC_EILVT_MSG_FIX, 0))
 346                 return new;
 347
 348         return reserved;
 349 }
 350
 351 static int setup_APIC_deferred_error(int reserved, int new)
 352 {
 353         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 354                                               APIC_EILVT_MSG_FIX, 0))
 355                 return new;
 356
 357         return reserved;
 358 }
 359
 360 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 361 {
 362         u32 low = 0, high = 0;
 363         int def_offset = -1, def_new;
 364
 365         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 366                 return;
 367
 368         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 369         if (!(low & MASK_DEF_LVTOFF)) {
 370                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 371                 def_new = DEF_LVT_OFF;
 372                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 373         }
 374
 375         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 376         if ((def_offset == def_new) &&
 377             (deferred_error_int_vector != amd_deferred_error_interrupt))
 378                 deferred_error_int_vector = amd_deferred_error_interrupt;
 379
 380         low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 381         wrmsr(MSR_CU_DEF_ERR, low, high);
 382 }
 383
 384 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
 385                              unsigned int bank, unsigned int block)
 386 {
 387         u32 addr = 0, offset = 0;
 388
 389         if (mce_flags.smca) {
 390                 if (!block) {
 391                         addr = MSR_AMD64_SMCA_MCx_MISC(bank);
 392                 } else {
 393                         /*
 394                          * For SMCA enabled processors, BLKPTR field of the
 395                          * first MISC register (MCx_MISC0) indicates presence of
 396                          * additional MISC register set (MISC1-4).
 397                          */
 398                         u32 low, high;
 399
 400                         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 401                                 return addr;
 402
 403                         if (!(low & MCI_CONFIG_MCAX))
 404                                 return addr;
 405
 406                         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
 407                             (low & MASK_BLKPTR_LO))
 408                                 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 409                 }
 410                 return addr;
 411         }
 412
 413         /* Fall back to method we used for older processors: */
 414         switch (block) {
 415         case 0:
 416                 addr = msr_ops.misc(bank);
 417                 break;
 418         case 1:
 419                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 420                 if (offset)
 421                         addr = MCG_XBLK_ADDR + offset;
 422                 break;
 423         default:
 424                 addr = ++current_addr;
 425         }
 426         return addr;
 427 }
 428
 429 static int
 430 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 431                         int offset, u32 misc_high)
 432 {
 433         unsigned int cpu = smp_processor_id();
 434         u32 smca_low, smca_high, smca_addr;
 435         struct threshold_block b;
 436         int new;
 437
 438         if (!block)
 439                 per_cpu(bank_map, cpu) |= (1 << bank);
 440
 441         memset(&b, 0, sizeof(b));
 442         b.cpu                   = cpu;
 443         b.bank                  = bank;
 444         b.block                 = block;
 445         b.address               = addr;
 446         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 447
 448         if (!b.interrupt_capable)
 449                 goto done;
 450
 451         b.interrupt_enable = 1;
 452
 453         if (!mce_flags.smca) {
 454                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 455                 goto set_offset;
 456         }
 457
 458         smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 459
 460         if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
 461                 /*
 462                  * OS is required to set the MCAX bit to acknowledge that it is
 463                  * now using the new MSR ranges and new registers under each
 464                  * bank. It also means that the OS will configure deferred
 465                  * errors in the new MCx_CONFIG register. If the bit is not set,
 466                  * uncorrectable errors will cause a system panic.
 467                  *
 468                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 469                  */
 470                 smca_high |= BIT(0);
 471
 472                 /*
 473                  * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}
 474                  * registers with the option of additionally logging to
 475                  * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.
 476                  *
 477                  * This bit is usually set by BIOS to retain the old behavior
 478                  * for OSes that don't use the new registers. Linux supports the
 479                  * new registers so let's disable that additional logging here.
 480                  *
 481                  * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high
 482                  * portion of the MSR).
 483                  */
 484                 smca_high &= ~BIT(2);
 485
 486                 /*
 487                  * SMCA sets the Deferred Error Interrupt type per bank.
 488                  *
 489                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 490                  * if the DeferredIntType bit field is available.
 491                  *
 492                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 493                  * high portion of the MSR). OS should set this to 0x1 to enable
 494                  * APIC based interrupt. First, check that no interrupt has been
 495                  * set.
 496                  */
 497                 if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3))
 498                         smca_high |= BIT(5);
 499
 500                 wrmsr(smca_addr, smca_low, smca_high);
 501         }
 502
 503         /* Gather LVT offset for thresholding: */
 504         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 505                 goto out;
 506
 507         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 508
 509 set_offset:
 510         offset = setup_APIC_mce_threshold(offset, new);
 511
 512         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
 513                 mce_threshold_vector = amd_threshold_interrupt;
 514
 515 done:
 516         mce_threshold_block_init(&b, offset);
 517
 518 out:
 519         return offset;
 520 }
 521
 522 /* cpu init entry point, called from mce.c with preempt off */
 523 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 524 {
 525         u32 low = 0, high = 0, address = 0;
 526         unsigned int bank, block, cpu = smp_processor_id();
 527         int offset = -1;
 528
 529         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 530                 if (mce_flags.smca)
 531                         get_smca_bank_info(bank);
 532
 533                 for (block = 0; block < NR_BLOCKS; ++block) {
 534                         address = get_block_address(cpu, address, low, high, bank, block);
 535                         if (!address)
 536                                 break;
 537
 538                         if (rdmsr_safe(address, &low, &high))
 539                                 break;
 540
 541                         if (!(high & MASK_VALID_HI))
 542                                 continue;
 543
 544                         if (!(high & MASK_CNTP_HI)  ||
 545                              (high & MASK_LOCKED_HI))
 546                                 continue;
 547
 548                         offset = prepare_threshold_block(bank, block, address, offset, high);
 549                 }
 550         }
 551
 552         if (mce_flags.succor)
 553                 deferred_error_interrupt_enable(c);
 554 }
 555
 556 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 557 {
 558         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
 559         /* We start from the normalized address */
 560         u64 ret_addr = norm_addr;
 561
 562         u32 tmp;
 563
 564         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
 565         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 566         u8 intlv_addr_sel, intlv_addr_bit;
 567         u8 num_intlv_bits, hashed_bit;
 568         u8 lgcy_mmio_hole_en, base = 0;
 569         u8 cs_mask, cs_id = 0;
 570         bool hash_enabled = false;
 571
 572         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
 573         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 574                 goto out_err;
 575
 576         /* Remove HiAddrOffset from normalized address, if enabled: */
 577         if (tmp & BIT(0)) {
 578                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 579
 580                 if (norm_addr >= hi_addr_offset) {
 581                         ret_addr -= hi_addr_offset;
 582                         base = 1;
 583                 }
 584         }
 585
 586         /* Read D18F0x110 (DramBaseAddress). */
 587         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
 588                 goto out_err;
 589
 590         /* Check if address range is valid. */
 591         if (!(tmp & BIT(0))) {
 592                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
 593                         __func__, tmp);
 594                 goto out_err;
 595         }
 596
 597         lgcy_mmio_hole_en = tmp & BIT(1);
 598         intlv_num_chan    = (tmp >> 4) & 0xF;
 599         intlv_addr_sel    = (tmp >> 8) & 0x7;
 600         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
 601
 602         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
 603         if (intlv_addr_sel > 3) {
 604                 pr_err("%s: Invalid interleave address select %d.\n",
 605                         __func__, intlv_addr_sel);
 606                 goto out_err;
 607         }
 608
 609         /* Read D18F0x114 (DramLimitAddress). */
 610         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 611                 goto out_err;
 612
 613         intlv_num_sockets = (tmp >> 8) & 0x1;
 614         intlv_num_dies    = (tmp >> 10) & 0x3;
 615         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 616
 617         intlv_addr_bit = intlv_addr_sel + 8;
 618
 619         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
 620         switch (intlv_num_chan) {
 621         case 0: intlv_num_chan = 0; break;
 622         case 1: intlv_num_chan = 1; break;
 623         case 3: intlv_num_chan = 2; break;
 624         case 5: intlv_num_chan = 3; break;
 625         case 7: intlv_num_chan = 4; break;
 626
 627         case 8: intlv_num_chan = 1;
 628                 hash_enabled = true;
 629                 break;
 630         default:
 631                 pr_err("%s: Invalid number of interleaved channels %d.\n",
 632                         __func__, intlv_num_chan);
 633                 goto out_err;
 634         }
 635
 636         num_intlv_bits = intlv_num_chan;
 637
 638         if (intlv_num_dies > 2) {
 639                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
 640                         __func__, intlv_num_dies);
 641                 goto out_err;
 642         }
 643
 644         num_intlv_bits += intlv_num_dies;
 645
 646         /* Add a bit if sockets are interleaved. */
 647         num_intlv_bits += intlv_num_sockets;
 648
 649         /* Assert num_intlv_bits <= 4 */
 650         if (num_intlv_bits > 4) {
 651                 pr_err("%s: Invalid interleave bits %d.\n",
 652                         __func__, num_intlv_bits);
 653                 goto out_err;
 654         }
 655
 656         if (num_intlv_bits > 0) {
 657                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
 658                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
 659
 660                 /*
 661                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
 662                  * This is the fabric id for this coherent slave. Use
 663                  * umc/channel# as instance id of the coherent slave
 664                  * for FICAA.
 665                  */
 666                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 667                         goto out_err;
 668
 669                 cs_fabric_id = (tmp >> 8) & 0xFF;
 670                 die_id_bit   = 0;
 671
 672                 /* If interleaved over more than 1 channel: */
 673                 if (intlv_num_chan) {
 674                         die_id_bit = intlv_num_chan;
 675                         cs_mask    = (1 << die_id_bit) - 1;
 676                         cs_id      = cs_fabric_id & cs_mask;
 677                 }
 678
 679                 sock_id_bit = die_id_bit;
 680
 681                 /* Read D18F1x208 (SystemFabricIdMask). */
 682                 if (intlv_num_dies || intlv_num_sockets)
 683                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
 684                                 goto out_err;
 685
 686                 /* If interleaved over more than 1 die. */
 687                 if (intlv_num_dies) {
 688                         sock_id_bit  = die_id_bit + intlv_num_dies;
 689                         die_id_shift = (tmp >> 24) & 0xF;
 690                         die_id_mask  = (tmp >> 8) & 0xFF;
 691
 692                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 693                 }
 694
 695                 /* If interleaved over more than 1 socket. */
 696                 if (intlv_num_sockets) {
 697                         socket_id_shift = (tmp >> 28) & 0xF;
 698                         socket_id_mask  = (tmp >> 16) & 0xFF;
 699
 700                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 701                 }
 702
 703                 /*
 704                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
 705                  * where III is the ID for this CS, and XXXXXXYYYYY are the
 706                  * address bits from the post-interleaved address.
 707                  * "num_intlv_bits" has been calculated to tell us how many "I"
 708                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
 709                  * there are (where "I" starts).
 710                  */
 711                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
 712                 temp_addr_i = (cs_id << intlv_addr_bit);
 713                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
 714                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
 715         }
 716
 717         /* Add dram base address */
 718         ret_addr += dram_base_addr;
 719
 720         /* If legacy MMIO hole enabled */
 721         if (lgcy_mmio_hole_en) {
 722                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
 723                         goto out_err;
 724
 725                 dram_hole_base = tmp & GENMASK(31, 24);
 726                 if (ret_addr >= dram_hole_base)
 727                         ret_addr += (BIT_ULL(32) - dram_hole_base);
 728         }
 729
 730         if (hash_enabled) {
 731                 /* Save some parentheses and grab ls-bit at the end. */
 732                 hashed_bit =    (ret_addr >> 12) ^
 733                                 (ret_addr >> 18) ^
 734                                 (ret_addr >> 21) ^
 735                                 (ret_addr >> 30) ^
 736                                 cs_id;
 737
 738                 hashed_bit &= BIT(0);
 739
 740                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
 741                         ret_addr ^= BIT(intlv_addr_bit);
 742         }
 743
 744         /* Is calculated system address is above DRAM limit address? */
 745         if (ret_addr > dram_limit_addr)
 746                 goto out_err;
 747
 748         *sys_addr = ret_addr;
 749         return 0;
 750
 751 out_err:
 752         return -EINVAL;
 753 }
 754 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 755
 756 static void
 757 __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
 758 {
 759         u32 msr_status = msr_ops.status(bank);
 760         u32 msr_addr = msr_ops.addr(bank);
 761         struct mce m;
 762         u64 status;
 763
 764         WARN_ON_ONCE(deferred_err && threshold_err);
 765
 766         if (deferred_err && mce_flags.smca) {
 767                 msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank);
 768                 msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank);
 769         }
 770
 771         rdmsrl(msr_status, status);
 772
 773         if (!(status & MCI_STATUS_VAL))
 774                 return;
 775
 776         mce_setup(&m);
 777
 778         m.status = status;
 779         m.bank = bank;
 780
 781         if (threshold_err)
 782                 m.misc = misc;
 783
 784         if (m.status & MCI_STATUS_ADDRV) {
 785                 rdmsrl(msr_addr, m.addr);
 786
 787                 /*
 788                  * Extract [55:<lsb>] where lsb is the least significant
 789                  * *valid* bit of the address bits.
 790                  */
 791                 if (mce_flags.smca) {
 792                         u8 lsb = (m.addr >> 56) & 0x3f;
 793
 794                         m.addr &= GENMASK_ULL(55, lsb);
 795                 }
 796         }
 797
 798         if (mce_flags.smca) {
 799                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
 800
 801                 if (m.status & MCI_STATUS_SYNDV)
 802                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
 803         }
 804
 805         mce_log(&m);
 806
 807         wrmsrl(msr_status, 0);
 808 }
 809
 810 static inline void __smp_deferred_error_interrupt(void)
 811 {
 812         inc_irq_stat(irq_deferred_error_count);
 813         deferred_error_int_vector();
 814 }
 815
 816 asmlinkage __visible void smp_deferred_error_interrupt(void)
 817 {
 818         entering_irq();
 819         __smp_deferred_error_interrupt();
 820         exiting_ack_irq();
 821 }
 822
 823 asmlinkage __visible void smp_trace_deferred_error_interrupt(void)
 824 {
 825         entering_irq();
 826         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 827         __smp_deferred_error_interrupt();
 828         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 829         exiting_ack_irq();
 830 }
 831
 832 /* APIC interrupt handler for deferred errors */
 833 static void amd_deferred_error_interrupt(void)
 834 {
 835         unsigned int bank;
 836         u32 msr_status;
 837         u64 status;
 838
 839         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 840                 msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank)
 841                                               : msr_ops.status(bank);
 842
 843                 rdmsrl(msr_status, status);
 844
 845                 if (!(status & MCI_STATUS_VAL) ||
 846                     !(status & MCI_STATUS_DEFERRED))
 847                         continue;
 848
 849                 __log_error(bank, true, false, 0);
 850                 break;
 851         }
 852 }
 853
 854 /*
 855  * APIC Interrupt Handler
 856  */
 857
 858 /*
 859  * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
 860  * the interrupt goes off when error_count reaches threshold_limit.
 861  * the handler will simply log mcelog w/ software defined bank number.
 862  */
 863
 864 static void amd_threshold_interrupt(void)
 865 {
 866         u32 low = 0, high = 0, address = 0;
 867         unsigned int bank, block, cpu = smp_processor_id();
 868         struct thresh_restart tr;
 869
 870         /* assume first bank caused it */
 871         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 872                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 873                         continue;
 874                 for (block = 0; block < NR_BLOCKS; ++block) {
 875                         address = get_block_address(cpu, address, low, high, bank, block);
 876                         if (!address)
 877                                 break;
 878
 879                         if (rdmsr_safe(address, &low, &high))
 880                                 break;
 881
 882                         if (!(high & MASK_VALID_HI)) {
 883                                 if (block)
 884                                         continue;
 885                                 else
 886                                         break;
 887                         }
 888
 889                         if (!(high & MASK_CNTP_HI)  ||
 890                              (high & MASK_LOCKED_HI))
 891                                 continue;
 892
 893                         /*
 894                          * Log the machine check that caused the threshold
 895                          * event.
 896                          */
 897                         if (high & MASK_OVERFLOW_HI)
 898                                 goto log;
 899                 }
 900         }
 901         return;
 902
 903 log:
 904         __log_error(bank, false, true, ((u64)high << 32) | low);
 905
 906         /* Reset threshold block after logging error. */
 907         memset(&tr, 0, sizeof(tr));
 908         tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block];
 909         threshold_restart_bank(&tr);
 910 }
 911
 912 /*
 913  * Sysfs Interface
 914  */
 915
 916 struct threshold_attr {
 917         struct attribute attr;
 918         ssize_t (*show) (struct threshold_block *, char *);
 919         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 920 };
 921
 922 #define SHOW_FIELDS(name)                                               \
 923 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 924 {                                                                       \
 925         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 926 }
 927 SHOW_FIELDS(interrupt_enable)
 928 SHOW_FIELDS(threshold_limit)
 929
 930 static ssize_t
 931 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 932 {
 933         struct thresh_restart tr;
 934         unsigned long new;
 935
 936         if (!b->interrupt_capable)
 937                 return -EINVAL;
 938
 939         if (kstrtoul(buf, 0, &new) < 0)
 940                 return -EINVAL;
 941
 942         b->interrupt_enable = !!new;
 943
 944         memset(&tr, 0, sizeof(tr));
 945         tr.b            = b;
 946
 947         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 948
 949         return size;
 950 }
 951
 952 static ssize_t
 953 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
 954 {
 955         struct thresh_restart tr;
 956         unsigned long new;
 957
 958         if (kstrtoul(buf, 0, &new) < 0)
 959                 return -EINVAL;
 960
 961         if (new > THRESHOLD_MAX)
 962                 new = THRESHOLD_MAX;
 963         if (new < 1)
 964                 new = 1;
 965
 966         memset(&tr, 0, sizeof(tr));
 967         tr.old_limit = b->threshold_limit;
 968         b->threshold_limit = new;
 969         tr.b = b;
 970
 971         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 972
 973         return size;
 974 }
 975
 976 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 977 {
 978         u32 lo, hi;
 979
 980         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
 981
 982         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
 983                                      (THRESHOLD_MAX - b->threshold_limit)));
 984 }
 985
 986 static struct threshold_attr error_count = {
 987         .attr = {.name = __stringify(error_count), .mode = 0444 },
 988         .show = show_error_count,
 989 };
 990
 991 #define RW_ATTR(val)                                                    \
 992 static struct threshold_attr val = {                                    \
 993         .attr   = {.name = __stringify(val), .mode = 0644 },            \
 994         .show   = show_## val,                                          \
 995         .store  = store_## val,                                         \
 996 };
 997
 998 RW_ATTR(interrupt_enable);
 999 RW_ATTR(threshold_limit);
1000
1001 static struct attribute *default_attrs[] = {
1002         &threshold_limit.attr,
1003         &error_count.attr,
1004         NULL,   /* possibly interrupt_enable if supported, see below */
1005         NULL,
1006 };
1007
1008 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1009 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1010
1011 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1012 {
1013         struct threshold_block *b = to_block(kobj);
1014         struct threshold_attr *a = to_attr(attr);
1015         ssize_t ret;
1016
1017         ret = a->show ? a->show(b, buf) : -EIO;
1018
1019         return ret;
1020 }
1021
1022 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1023                      const char *buf, size_t count)
1024 {
1025         struct threshold_block *b = to_block(kobj);
1026         struct threshold_attr *a = to_attr(attr);
1027         ssize_t ret;
1028
1029         ret = a->store ? a->store(b, buf, count) : -EIO;
1030
1031         return ret;
1032 }
1033
1034 static const struct sysfs_ops threshold_ops = {
1035         .show                   = show,
1036         .store                  = store,
1037 };
1038
1039 static struct kobj_type threshold_ktype = {
1040         .sysfs_ops              = &threshold_ops,
1041         .default_attrs          = default_attrs,
1042 };
1043
1044 static const char *get_name(unsigned int bank, struct threshold_block *b)
1045 {
1046         unsigned int bank_type;
1047
1048         if (!mce_flags.smca) {
1049                 if (b && bank == 4)
1050                         return bank4_names(b);
1051
1052                 return th_names[bank];
1053         }
1054
1055         if (!smca_banks[bank].hwid)
1056                 return NULL;
1057
1058         bank_type = smca_banks[bank].hwid->bank_type;
1059
1060         if (b && bank_type == SMCA_UMC) {
1061                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1062                         return smca_umc_block_names[b->block];
1063                 return NULL;
1064         }
1065
1066         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1067                  "%s_%x", smca_get_name(bank_type),
1068                           smca_banks[bank].id);
1069         return buf_mcatype;
1070 }
1071
1072 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1073                                      unsigned int block, u32 address)
1074 {
1075         struct threshold_block *b = NULL;
1076         u32 low, high;
1077         int err;
1078
1079         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1080                 return 0;
1081
1082         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1083                 return 0;
1084
1085         if (!(high & MASK_VALID_HI)) {
1086                 if (block)
1087                         goto recurse;
1088                 else
1089                         return 0;
1090         }
1091
1092         if (!(high & MASK_CNTP_HI)  ||
1093              (high & MASK_LOCKED_HI))
1094                 goto recurse;
1095
1096         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1097         if (!b)
1098                 return -ENOMEM;
1099
1100         b->block                = block;
1101         b->bank                 = bank;
1102         b->cpu                  = cpu;
1103         b->address              = address;
1104         b->interrupt_enable     = 0;
1105         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1106         b->threshold_limit      = THRESHOLD_MAX;
1107
1108         if (b->interrupt_capable) {
1109                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1110                 b->interrupt_enable = 1;
1111         } else {
1112                 threshold_ktype.default_attrs[2] = NULL;
1113         }
1114
1115         INIT_LIST_HEAD(&b->miscj);
1116
1117         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1118                 list_add(&b->miscj,
1119                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1120         } else {
1121                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1122         }
1123
1124         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1125                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1126                                    get_name(bank, b));
1127         if (err)
1128                 goto out_free;
1129 recurse:
1130         address = get_block_address(cpu, address, low, high, bank, ++block);
1131         if (!address)
1132                 return 0;
1133
1134         err = allocate_threshold_blocks(cpu, bank, block, address);
1135         if (err)
1136                 goto out_free;
1137
1138         if (b)
1139                 kobject_uevent(&b->kobj, KOBJ_ADD);
1140
1141         return err;
1142
1143 out_free:
1144         if (b) {
1145                 kobject_put(&b->kobj);
1146                 list_del(&b->miscj);
1147                 kfree(b);
1148         }
1149         return err;
1150 }
1151
1152 static int __threshold_add_blocks(struct threshold_bank *b)
1153 {
1154         struct list_head *head = &b->blocks->miscj;
1155         struct threshold_block *pos = NULL;
1156         struct threshold_block *tmp = NULL;
1157         int err = 0;
1158
1159         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1160         if (err)
1161                 return err;
1162
1163         list_for_each_entry_safe(pos, tmp, head, miscj) {
1164
1165                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1166                 if (err) {
1167                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1168                                 kobject_del(&pos->kobj);
1169
1170                         return err;
1171                 }
1172         }
1173         return err;
1174 }
1175
1176 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1177 {
1178         struct device *dev = per_cpu(mce_device, cpu);
1179         struct amd_northbridge *nb = NULL;
1180         struct threshold_bank *b = NULL;
1181         const char *name = get_name(bank, NULL);
1182         int err = 0;
1183
1184         if (is_shared_bank(bank)) {
1185                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1186
1187                 /* threshold descriptor already initialized on this node? */
1188                 if (nb && nb->bank4) {
1189                         /* yes, use it */
1190                         b = nb->bank4;
1191                         err = kobject_add(b->kobj, &dev->kobj, name);
1192                         if (err)
1193                                 goto out;
1194
1195                         per_cpu(threshold_banks, cpu)[bank] = b;
1196                         atomic_inc(&b->cpus);
1197
1198                         err = __threshold_add_blocks(b);
1199
1200                         goto out;
1201                 }
1202         }
1203
1204         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1205         if (!b) {
1206                 err = -ENOMEM;
1207                 goto out;
1208         }
1209
1210         b->kobj = kobject_create_and_add(name, &dev->kobj);
1211         if (!b->kobj) {
1212                 err = -EINVAL;
1213                 goto out_free;
1214         }
1215
1216         per_cpu(threshold_banks, cpu)[bank] = b;
1217
1218         if (is_shared_bank(bank)) {
1219                 atomic_set(&b->cpus, 1);
1220
1221                 /* nb is already initialized, see above */
1222                 if (nb) {
1223                         WARN_ON(nb->bank4);
1224                         nb->bank4 = b;
1225                 }
1226         }
1227
1228         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1229         if (!err)
1230                 goto out;
1231
1232  out_free:
1233         kfree(b);
1234
1235  out:
1236         return err;
1237 }
1238
1239 /* create dir/files for all valid threshold banks */
1240 static int threshold_create_device(unsigned int cpu)
1241 {
1242         unsigned int bank;
1243         struct threshold_bank **bp;
1244         int err = 0;
1245
1246         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1247                      GFP_KERNEL);
1248         if (!bp)
1249                 return -ENOMEM;
1250
1251         per_cpu(threshold_banks, cpu) = bp;
1252
1253         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1254                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1255                         continue;
1256                 err = threshold_create_bank(cpu, bank);
1257                 if (err)
1258                         return err;
1259         }
1260
1261         return err;
1262 }
1263
1264 static void deallocate_threshold_block(unsigned int cpu,
1265                                                  unsigned int bank)
1266 {
1267         struct threshold_block *pos = NULL;
1268         struct threshold_block *tmp = NULL;
1269         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1270
1271         if (!head)
1272                 return;
1273
1274         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1275                 kobject_put(&pos->kobj);
1276                 list_del(&pos->miscj);
1277                 kfree(pos);
1278         }
1279
1280         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1281         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1282 }
1283
1284 static void __threshold_remove_blocks(struct threshold_bank *b)
1285 {
1286         struct threshold_block *pos = NULL;
1287         struct threshold_block *tmp = NULL;
1288
1289         kobject_del(b->kobj);
1290
1291         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1292                 kobject_del(&pos->kobj);
1293 }
1294
1295 static void threshold_remove_bank(unsigned int cpu, int bank)
1296 {
1297         struct amd_northbridge *nb;
1298         struct threshold_bank *b;
1299
1300         b = per_cpu(threshold_banks, cpu)[bank];
1301         if (!b)
1302                 return;
1303
1304         if (!b->blocks)
1305                 goto free_out;
1306
1307         if (is_shared_bank(bank)) {
1308                 if (!atomic_dec_and_test(&b->cpus)) {
1309                         __threshold_remove_blocks(b);
1310                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1311                         return;
1312                 } else {
1313                         /*
1314                          * the last CPU on this node using the shared bank is
1315                          * going away, remove that bank now.
1316                          */
1317                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1318                         nb->bank4 = NULL;
1319                 }
1320         }
1321
1322         deallocate_threshold_block(cpu, bank);
1323
1324 free_out:
1325         kobject_del(b->kobj);
1326         kobject_put(b->kobj);
1327         kfree(b);
1328         per_cpu(threshold_banks, cpu)[bank] = NULL;
1329 }
1330
1331 static void threshold_remove_device(unsigned int cpu)
1332 {
1333         unsigned int bank;
1334
1335         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1336                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1337                         continue;
1338                 threshold_remove_bank(cpu, bank);
1339         }
1340         kfree(per_cpu(threshold_banks, cpu));
1341 }
1342
1343 /* get notified when a cpu comes on/off */
1344 static void
1345 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
1346 {
1347         switch (action) {
1348         case CPU_ONLINE:
1349         case CPU_ONLINE_FROZEN:
1350                 threshold_create_device(cpu);
1351                 break;
1352         case CPU_DEAD:
1353         case CPU_DEAD_FROZEN:
1354                 threshold_remove_device(cpu);
1355                 break;
1356         default:
1357                 break;
1358         }
1359 }
1360
1361 static __init int threshold_init_device(void)
1362 {
1363         unsigned lcpu = 0;
1364
1365         /* to hit CPUs online before the notifier is up */
1366         for_each_online_cpu(lcpu) {
1367                 int err = threshold_create_device(lcpu);
1368
1369                 if (err)
1370                         return err;
1371         }
1372         threshold_cpu_callback = amd_64_threshold_cpu_callback;
1373
1374         return 0;
1375 }
1376 /*
1377  * there are 3 funcs which need to be _initcalled in a logic sequence:
1378  * 1. xen_late_init_mcelog
1379  * 2. mcheck_init_device
1380  * 3. threshold_init_device
1381  *
1382  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1383  * native mce_chrdev_device registration if running under xen platform;
1384  *
1385  * mcheck_init_device should be inited before threshold_init_device to
1386  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1387  *
1388  * so we use following _initcalls
1389  * 1. device_initcall(xen_late_init_mcelog);
1390  * 2. device_initcall_sync(mcheck_init_device);
1391  * 3. late_initcall(threshold_init_device);
1392  *
1393  * when running under xen, the initcall order is 1,2,3;
1394  * on baremetal, we skip 1 and we do only 2 and 3.
1395  */
1396 late_initcall(threshold_init_device);