drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <[email protected]>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <asm/amd_nb.h>
  14 #include <linux/acpi.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/bits.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/limits.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/rtc.h>
  26 #include <linux/serio.h>
  27 #include <linux/suspend.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/uaccess.h>
  30
  31 /* SMU communication registers */
  32 #define AMD_PMC_REGISTER_MESSAGE        0x538
  33 #define AMD_PMC_REGISTER_RESPONSE       0x980
  34 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  35
  36 /* PMC Scratch Registers */
  37 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  38 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  39
  40 /* STB Registers */
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  43 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  44 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  45 #define AMD_PMC_STB_DUMMY_PC            0xC6000007
  46
  47 /* STB S2D(Spill to DRAM) has different message port offset */
  48 #define STB_SPILL_TO_DRAM               0xBE
  49 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  50 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  51 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  52
  53 /* STB Spill to DRAM Parameters */
  54 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  55 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  56
  57 /* Base address of SMU for mapping physical address to virtual address */
  58 #define AMD_PMC_MAPPING_SIZE            0x01000
  59 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  60 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  61 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  62 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  63 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  64
  65 /* SMU Response Codes */
  66 #define AMD_PMC_RESULT_OK                    0x01
  67 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  68 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  69 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  70 #define AMD_PMC_RESULT_FAILED                0xFF
  71
  72 /* FCH SSC Registers */
  73 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  74 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  75 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  76 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  77 #define FCH_SSC_MAPPING_SIZE            0x800
  78 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  79 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  80
  81 /* SMU Message Definations */
  82 #define SMU_MSG_GETSMUVERSION           0x02
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  84 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  85 #define SMU_MSG_LOG_START               0x06
  86 #define SMU_MSG_LOG_RESET               0x07
  87 #define SMU_MSG_LOG_DUMP_DATA           0x08
  88 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  89 /* List of supported CPU ids */
  90 #define AMD_CPU_ID_RV                   0x15D0
  91 #define AMD_CPU_ID_RN                   0x1630
  92 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  93 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  94 #define AMD_CPU_ID_YC                   0x14B5
  95 #define AMD_CPU_ID_CB                   0x14D8
  96 #define AMD_CPU_ID_PS                   0x14E8
  97 #define AMD_CPU_ID_SP                   0x14A4
  98
  99 #define PMC_MSG_DELAY_MIN_US            50
 100 #define RESPONSE_REGISTER_LOOP_MAX      20000
 101
 102 #define SOC_SUBSYSTEM_IP_MAX    12
 103 #define DELAY_MIN_US            2000
 104 #define DELAY_MAX_US            3000
 105 #define FIFO_SIZE               4096
 106
 107 enum amd_pmc_def {
 108         MSG_TEST = 0x01,
 109         MSG_OS_HINT_PCO,
 110         MSG_OS_HINT_RN,
 111 };
 112
 113 enum s2d_arg {
 114         S2D_TELEMETRY_SIZE = 0x01,
 115         S2D_PHYS_ADDR_LOW,
 116         S2D_PHYS_ADDR_HIGH,
 117         S2D_NUM_SAMPLES,
 118 };
 119
 120 struct amd_pmc_bit_map {
 121         const char *name;
 122         u32 bit_mask;
 123 };
 124
 125 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 126         {"DISPLAY",     BIT(0)},
 127         {"CPU",         BIT(1)},
 128         {"GFX",         BIT(2)},
 129         {"VDD",         BIT(3)},
 130         {"ACP",         BIT(4)},
 131         {"VCN",         BIT(5)},
 132         {"ISP",         BIT(6)},
 133         {"NBIO",        BIT(7)},
 134         {"DF",          BIT(8)},
 135         {"USB0",        BIT(9)},
 136         {"USB1",        BIT(10)},
 137         {"LAPIC",       BIT(11)},
 138         {}
 139 };
 140
 141 struct amd_pmc_dev {
 142         void __iomem *regbase;
 143         void __iomem *smu_virt_addr;
 144         void __iomem *stb_virt_addr;
 145         void __iomem *fch_virt_addr;
 146         bool msg_port;
 147         u32 base_addr;
 148         u32 cpu_id;
 149         u32 active_ips;
 150 /* SMU version information */
 151         u8 smu_program;
 152         u8 major;
 153         u8 minor;
 154         u8 rev;
 155         struct device *dev;
 156         struct pci_dev *rdev;
 157         struct mutex lock; /* generic mutex lock */
 158         struct dentry *dbgfs_dir;
 159 };
 160
 161 static bool enable_stb;
 162 module_param(enable_stb, bool, 0644);
 163 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 164
 165 static bool disable_workarounds;
 166 module_param(disable_workarounds, bool, 0644);
 167 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 168
 169 static struct amd_pmc_dev pmc;
 170 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 171 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 172 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 173
 174 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 175 {
 176         return ioread32(dev->regbase + reg_offset);
 177 }
 178
 179 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 180 {
 181         iowrite32(val, dev->regbase + reg_offset);
 182 }
 183
 184 struct smu_metrics {
 185         u32 table_version;
 186         u32 hint_count;
 187         u32 s0i3_last_entry_status;
 188         u32 timein_s0i2;
 189         u64 timeentering_s0i3_lastcapture;
 190         u64 timeentering_s0i3_totaltime;
 191         u64 timeto_resume_to_os_lastcapture;
 192         u64 timeto_resume_to_os_totaltime;
 193         u64 timein_s0i3_lastcapture;
 194         u64 timein_s0i3_totaltime;
 195         u64 timein_swdrips_lastcapture;
 196         u64 timein_swdrips_totaltime;
 197         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 198         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 199 } __packed;
 200
 201 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 202 {
 203         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 204         u32 size = FIFO_SIZE * sizeof(u32);
 205         u32 *buf;
 206         int rc;
 207
 208         buf = kzalloc(size, GFP_KERNEL);
 209         if (!buf)
 210                 return -ENOMEM;
 211
 212         rc = amd_pmc_read_stb(dev, buf);
 213         if (rc) {
 214                 kfree(buf);
 215                 return rc;
 216         }
 217
 218         filp->private_data = buf;
 219         return rc;
 220 }
 221
 222 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 223                                         loff_t *pos)
 224 {
 225         if (!filp->private_data)
 226                 return -EINVAL;
 227
 228         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 229                                        FIFO_SIZE * sizeof(u32));
 230 }
 231
 232 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 233 {
 234         kfree(filp->private_data);
 235         return 0;
 236 }
 237
 238 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 239         .owner = THIS_MODULE,
 240         .open = amd_pmc_stb_debugfs_open,
 241         .read = amd_pmc_stb_debugfs_read,
 242         .release = amd_pmc_stb_debugfs_release,
 243 };
 244
 245 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 246 {
 247         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 248         u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
 249         int ret;
 250
 251         /* Write dummy postcode while reading the STB buffer */
 252         ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
 253         if (ret)
 254                 dev_err(dev->dev, "error writing to STB: %d\n", ret);
 255
 256         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 257         if (!buf)
 258                 return -ENOMEM;
 259
 260         /* Spill to DRAM num_samples uses separate SMU message port */
 261         dev->msg_port = 1;
 262
 263         /* Get the num_samples to calculate the last push location */
 264         ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
 265         /* Clear msg_port for other SMU operation */
 266         dev->msg_port = 0;
 267         if (ret) {
 268                 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
 269                 kfree(buf);
 270                 return ret;
 271         }
 272
 273         /* Start capturing data from the last push location */
 274         if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
 275                 fsize  = S2D_TELEMETRY_BYTES_MAX;
 276                 stb_rdptr_offset = num_samples - fsize;
 277         } else {
 278                 fsize = num_samples;
 279                 stb_rdptr_offset = 0;
 280         }
 281
 282         memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
 283         filp->private_data = buf;
 284
 285         return 0;
 286 }
 287
 288 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 289                                            loff_t *pos)
 290 {
 291         if (!filp->private_data)
 292                 return -EINVAL;
 293
 294         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 295                                         S2D_TELEMETRY_BYTES_MAX);
 296 }
 297
 298 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 299 {
 300         kfree(filp->private_data);
 301         return 0;
 302 }
 303
 304 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 305         .owner = THIS_MODULE,
 306         .open = amd_pmc_stb_debugfs_open_v2,
 307         .read = amd_pmc_stb_debugfs_read_v2,
 308         .release = amd_pmc_stb_debugfs_release_v2,
 309 };
 310
 311 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 312 {
 313         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 314                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 315                 return -EINVAL;
 316         }
 317
 318         /* Get Active devices list from SMU */
 319         if (!dev->active_ips)
 320                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 321
 322         /* Get dram address */
 323         if (!dev->smu_virt_addr) {
 324                 u32 phys_addr_low, phys_addr_hi;
 325                 u64 smu_phys_addr;
 326
 327                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 328                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 329                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 330
 331                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 332                                                   sizeof(struct smu_metrics));
 333                 if (!dev->smu_virt_addr)
 334                         return -ENOMEM;
 335         }
 336
 337         /* Start the logging */
 338         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 339         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 340
 341         return 0;
 342 }
 343
 344 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 345 {
 346         if (!pdev->smu_virt_addr) {
 347                 int ret = amd_pmc_setup_smu_logging(pdev);
 348
 349                 if (ret)
 350                         return ret;
 351         }
 352
 353         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 354                 return -ENODEV;
 355         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 356         return 0;
 357 }
 358
 359 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 360 {
 361         struct smu_metrics table;
 362
 363         if (get_metrics_table(pdev, &table))
 364                 return;
 365
 366         if (!table.s0i3_last_entry_status)
 367                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 368         pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
 369                                 table.timein_s0i3_lastcapture : 0);
 370 }
 371
 372 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 373 {
 374         int rc;
 375         u32 val;
 376
 377         if (dev->cpu_id == AMD_CPU_ID_PCO)
 378                 return -ENODEV;
 379
 380         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 381         if (rc)
 382                 return rc;
 383
 384         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 385         dev->major = (val >> 16) & GENMASK(7, 0);
 386         dev->minor = (val >> 8) & GENMASK(7, 0);
 387         dev->rev = (val >> 0) & GENMASK(7, 0);
 388
 389         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 390                 dev->smu_program, dev->major, dev->minor, dev->rev);
 391
 392         return 0;
 393 }
 394
 395 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 396                                    char *buf)
 397 {
 398         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 399
 400         if (!dev->major) {
 401                 int rc = amd_pmc_get_smu_version(dev);
 402
 403                 if (rc)
 404                         return rc;
 405         }
 406         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 407 }
 408
 409 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 410                                    char *buf)
 411 {
 412         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 413
 414         if (!dev->major) {
 415                 int rc = amd_pmc_get_smu_version(dev);
 416
 417                 if (rc)
 418                         return rc;
 419         }
 420         return sysfs_emit(buf, "%u\n", dev->smu_program);
 421 }
 422
 423 static DEVICE_ATTR_RO(smu_fw_version);
 424 static DEVICE_ATTR_RO(smu_program);
 425
 426 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
 427 {
 428         struct device *dev = kobj_to_dev(kobj);
 429         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 430
 431         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 432                 return 0;
 433         return 0444;
 434 }
 435
 436 static struct attribute *pmc_attrs[] = {
 437         &dev_attr_smu_fw_version.attr,
 438         &dev_attr_smu_program.attr,
 439         NULL,
 440 };
 441
 442 static struct attribute_group pmc_attr_group = {
 443         .attrs = pmc_attrs,
 444         .is_visible = pmc_attr_is_visible,
 445 };
 446
 447 static const struct attribute_group *pmc_groups[] = {
 448         &pmc_attr_group,
 449         NULL,
 450 };
 451
 452 static int smu_fw_info_show(struct seq_file *s, void *unused)
 453 {
 454         struct amd_pmc_dev *dev = s->private;
 455         struct smu_metrics table;
 456         int idx;
 457
 458         if (get_metrics_table(dev, &table))
 459                 return -EINVAL;
 460
 461         seq_puts(s, "\n=== SMU Statistics ===\n");
 462         seq_printf(s, "Table Version: %d\n", table.table_version);
 463         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 464         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 465                    "Unknown/Fail");
 466         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 467         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 468         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 469                    table.timeto_resume_to_os_lastcapture);
 470
 471         seq_puts(s, "\n=== Active time (in us) ===\n");
 472         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 473                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 474                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 475                                    table.timecondition_notmet_lastcapture[idx]);
 476         }
 477
 478         return 0;
 479 }
 480 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 481
 482 static int s0ix_stats_show(struct seq_file *s, void *unused)
 483 {
 484         struct amd_pmc_dev *dev = s->private;
 485         u64 entry_time, exit_time, residency;
 486
 487         /* Use FCH registers to get the S0ix stats */
 488         if (!dev->fch_virt_addr) {
 489                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 490                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 491                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 492
 493                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 494                 if (!dev->fch_virt_addr)
 495                         return -ENOMEM;
 496         }
 497
 498         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 499         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 500
 501         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 502         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 503
 504         /* It's in 48MHz. We need to convert it */
 505         residency = exit_time - entry_time;
 506         do_div(residency, 48);
 507
 508         seq_puts(s, "=== S0ix statistics ===\n");
 509         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 510         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 511         seq_printf(s, "Residency Time: %lld\n", residency);
 512
 513         return 0;
 514 }
 515 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 516
 517 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 518                                  struct seq_file *s)
 519 {
 520         u32 val;
 521         int rc;
 522
 523         switch (pdev->cpu_id) {
 524         case AMD_CPU_ID_CZN:
 525                 /* we haven't yet read SMU version */
 526                 if (!pdev->major) {
 527                         rc = amd_pmc_get_smu_version(pdev);
 528                         if (rc)
 529                                 return rc;
 530                 }
 531                 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
 532                         val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 533                 else
 534                         return -EINVAL;
 535                 break;
 536         case AMD_CPU_ID_YC:
 537         case AMD_CPU_ID_CB:
 538         case AMD_CPU_ID_PS:
 539                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 540                 break;
 541         default:
 542                 return -EINVAL;
 543         }
 544
 545         if (dev)
 546                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 547
 548         if (s)
 549                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 550
 551         return 0;
 552 }
 553
 554 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 555 {
 556         return amd_pmc_idlemask_read(s->private, NULL, s);
 557 }
 558 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 559
 560 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 561 {
 562         debugfs_remove_recursive(dev->dbgfs_dir);
 563 }
 564
 565 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 566 {
 567         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 568         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 569                             &smu_fw_info_fops);
 570         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 571                             &s0ix_stats_fops);
 572         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 573                             &amd_pmc_idlemask_fops);
 574         /* Enable STB only when the module_param is set */
 575         if (enable_stb) {
 576                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 577                     dev->cpu_id == AMD_CPU_ID_PS)
 578                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 579                                             &amd_pmc_stb_debugfs_fops_v2);
 580                 else
 581                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 582                                             &amd_pmc_stb_debugfs_fops);
 583         }
 584 }
 585
 586 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 587 {
 588         u32 value, message, argument, response;
 589
 590         if (dev->msg_port) {
 591                 message = AMD_S2D_REGISTER_MESSAGE;
 592                 argument = AMD_S2D_REGISTER_ARGUMENT;
 593                 response = AMD_S2D_REGISTER_RESPONSE;
 594         } else {
 595                 message = AMD_PMC_REGISTER_MESSAGE;
 596                 argument = AMD_PMC_REGISTER_ARGUMENT;
 597                 response = AMD_PMC_REGISTER_RESPONSE;
 598         }
 599
 600         value = amd_pmc_reg_read(dev, response);
 601         dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 602
 603         value = amd_pmc_reg_read(dev, argument);
 604         dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 605
 606         value = amd_pmc_reg_read(dev, message);
 607         dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 608 }
 609
 610 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 611 {
 612         int rc;
 613         u32 val, message, argument, response;
 614
 615         mutex_lock(&dev->lock);
 616
 617         if (dev->msg_port) {
 618                 message = AMD_S2D_REGISTER_MESSAGE;
 619                 argument = AMD_S2D_REGISTER_ARGUMENT;
 620                 response = AMD_S2D_REGISTER_RESPONSE;
 621         } else {
 622                 message = AMD_PMC_REGISTER_MESSAGE;
 623                 argument = AMD_PMC_REGISTER_ARGUMENT;
 624                 response = AMD_PMC_REGISTER_RESPONSE;
 625         }
 626
 627         /* Wait until we get a valid response */
 628         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 629                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 630                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 631         if (rc) {
 632                 dev_err(dev->dev, "failed to talk to SMU\n");
 633                 goto out_unlock;
 634         }
 635
 636         /* Write zero to response register */
 637         amd_pmc_reg_write(dev, response, 0);
 638
 639         /* Write argument into response register */
 640         amd_pmc_reg_write(dev, argument, arg);
 641
 642         /* Write message ID to message ID register */
 643         amd_pmc_reg_write(dev, message, msg);
 644
 645         /* Wait until we get a valid response */
 646         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 647                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 648                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 649         if (rc) {
 650                 dev_err(dev->dev, "SMU response timed out\n");
 651                 goto out_unlock;
 652         }
 653
 654         switch (val) {
 655         case AMD_PMC_RESULT_OK:
 656                 if (ret) {
 657                         /* PMFW may take longer time to return back the data */
 658                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 659                         *data = amd_pmc_reg_read(dev, argument);
 660                 }
 661                 break;
 662         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 663                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 664                 rc = -EBUSY;
 665                 goto out_unlock;
 666         case AMD_PMC_RESULT_CMD_UNKNOWN:
 667                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 668                 rc = -EINVAL;
 669                 goto out_unlock;
 670         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 671         case AMD_PMC_RESULT_FAILED:
 672         default:
 673                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 674                 rc = -EIO;
 675                 goto out_unlock;
 676         }
 677
 678 out_unlock:
 679         mutex_unlock(&dev->lock);
 680         amd_pmc_dump_registers(dev);
 681         return rc;
 682 }
 683
 684 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 685 {
 686         switch (dev->cpu_id) {
 687         case AMD_CPU_ID_PCO:
 688                 return MSG_OS_HINT_PCO;
 689         case AMD_CPU_ID_RN:
 690         case AMD_CPU_ID_YC:
 691         case AMD_CPU_ID_CB:
 692         case AMD_CPU_ID_PS:
 693                 return MSG_OS_HINT_RN;
 694         }
 695         return -EINVAL;
 696 }
 697
 698 static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
 699 {
 700         struct device *d;
 701         int rc;
 702
 703         if (!pdev->major) {
 704                 rc = amd_pmc_get_smu_version(pdev);
 705                 if (rc)
 706                         return rc;
 707         }
 708
 709         if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
 710                 return 0;
 711
 712         d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
 713         if (!d)
 714                 return 0;
 715         if (device_may_wakeup(d)) {
 716                 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
 717                 disable_irq_wake(1);
 718                 device_set_wakeup_enable(d, false);
 719         }
 720         put_device(d);
 721
 722         return 0;
 723 }
 724
 725 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 726 {
 727         struct rtc_device *rtc_device;
 728         time64_t then, now, duration;
 729         struct rtc_wkalrm alarm;
 730         struct rtc_time tm;
 731         int rc;
 732
 733         /* we haven't yet read SMU version */
 734         if (!pdev->major) {
 735                 rc = amd_pmc_get_smu_version(pdev);
 736                 if (rc)
 737                         return rc;
 738         }
 739
 740         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 741                 return 0;
 742
 743         rtc_device = rtc_class_open("rtc0");
 744         if (!rtc_device)
 745                 return 0;
 746         rc = rtc_read_alarm(rtc_device, &alarm);
 747         if (rc)
 748                 return rc;
 749         if (!alarm.enabled) {
 750                 dev_dbg(pdev->dev, "alarm not enabled\n");
 751                 return 0;
 752         }
 753         rc = rtc_read_time(rtc_device, &tm);
 754         if (rc)
 755                 return rc;
 756         then = rtc_tm_to_time64(&alarm.time);
 757         now = rtc_tm_to_time64(&tm);
 758         duration = then-now;
 759
 760         /* in the past */
 761         if (then < now)
 762                 return 0;
 763
 764         /* will be stored in upper 16 bits of s0i3 hint argument,
 765          * so timer wakeup from s0i3 is limited to ~18 hours or less
 766          */
 767         if (duration <= 4 || duration > U16_MAX)
 768                 return -EINVAL;
 769
 770         *arg |= (duration << 16);
 771         rc = rtc_alarm_irq_enable(rtc_device, 0);
 772         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 773
 774         return rc;
 775 }
 776
 777 static void amd_pmc_s2idle_prepare(void)
 778 {
 779         struct amd_pmc_dev *pdev = &pmc;
 780         int rc;
 781         u8 msg;
 782         u32 arg = 1;
 783
 784         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 785         amd_pmc_setup_smu_logging(pdev);
 786
 787         /* Activate CZN specific platform bug workarounds */
 788         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 789                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 790                 if (rc) {
 791                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 792                         return;
 793                 }
 794         }
 795
 796         msg = amd_pmc_get_os_hint(pdev);
 797         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 798         if (rc) {
 799                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 800                 return;
 801         }
 802
 803         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 804         if (rc)
 805                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 806 }
 807
 808 static void amd_pmc_s2idle_check(void)
 809 {
 810         struct amd_pmc_dev *pdev = &pmc;
 811         struct smu_metrics table;
 812         int rc;
 813
 814         /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
 815         if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
 816             table.s0i3_last_entry_status)
 817                 usleep_range(10000, 20000);
 818
 819         /* Dump the IdleMask before we add to the STB */
 820         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 821
 822         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 823         if (rc)
 824                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 825 }
 826
 827 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
 828 {
 829         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 830                 return -ENODEV;
 831
 832         return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 833 }
 834
 835 static void amd_pmc_s2idle_restore(void)
 836 {
 837         struct amd_pmc_dev *pdev = &pmc;
 838         int rc;
 839         u8 msg;
 840
 841         msg = amd_pmc_get_os_hint(pdev);
 842         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 843         if (rc)
 844                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 845
 846         /* Let SMU know that we are looking for stats */
 847         amd_pmc_dump_data(pdev);
 848
 849         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 850         if (rc)
 851                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 852
 853         /* Notify on failed entry */
 854         amd_pmc_validate_deepest(pdev);
 855 }
 856
 857 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 858         .prepare = amd_pmc_s2idle_prepare,
 859         .check = amd_pmc_s2idle_check,
 860         .restore = amd_pmc_s2idle_restore,
 861 };
 862
 863 static int amd_pmc_suspend_handler(struct device *dev)
 864 {
 865         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 866
 867         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 868                 int rc = amd_pmc_czn_wa_irq1(pdev);
 869
 870                 if (rc) {
 871                         dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
 872                         return rc;
 873                 }
 874         }
 875
 876         return 0;
 877 }
 878
 879 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
 880
 881 static const struct pci_device_id pmc_pci_ids[] = {
 882         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 883         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 884         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 885         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 886         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 887         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 888         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 889         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
 890         { }
 891 };
 892
 893 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 894 {
 895         u32 phys_addr_low, phys_addr_hi;
 896         u64 stb_phys_addr;
 897         u32 size = 0;
 898
 899         /* Spill to DRAM feature uses separate SMU message port */
 900         dev->msg_port = 1;
 901
 902         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 903         if (size != S2D_TELEMETRY_BYTES_MAX)
 904                 return -EIO;
 905
 906         /* Get STB DRAM address */
 907         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 908         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 909
 910         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 911
 912         /* Clear msg_port for other SMU operation */
 913         dev->msg_port = 0;
 914
 915         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 916         if (!dev->stb_virt_addr)
 917                 return -ENOMEM;
 918
 919         return 0;
 920 }
 921
 922 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 923 {
 924         int err;
 925
 926         err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
 927         if (err) {
 928                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
 929                 return pcibios_err_to_errno(err);
 930         }
 931
 932         return 0;
 933 }
 934
 935 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 936 {
 937         int i, err;
 938
 939         for (i = 0; i < FIFO_SIZE; i++) {
 940                 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
 941                 if (err) {
 942                         dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
 943                         return pcibios_err_to_errno(err);
 944                 }
 945         }
 946
 947         return 0;
 948 }
 949
 950 static int amd_pmc_probe(struct platform_device *pdev)
 951 {
 952         struct amd_pmc_dev *dev = &pmc;
 953         struct pci_dev *rdev;
 954         u32 base_addr_lo, base_addr_hi;
 955         u64 base_addr;
 956         int err;
 957         u32 val;
 958
 959         dev->dev = &pdev->dev;
 960
 961         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 962         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 963                 err = -ENODEV;
 964                 goto err_pci_dev_put;
 965         }
 966
 967         dev->cpu_id = rdev->device;
 968
 969         if (dev->cpu_id == AMD_CPU_ID_SP) {
 970                 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
 971                 err = -ENODEV;
 972                 goto err_pci_dev_put;
 973         }
 974
 975         dev->rdev = rdev;
 976         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
 977         if (err) {
 978                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
 979                 err = pcibios_err_to_errno(err);
 980                 goto err_pci_dev_put;
 981         }
 982
 983         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 984
 985         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
 986         if (err) {
 987                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
 988                 err = pcibios_err_to_errno(err);
 989                 goto err_pci_dev_put;
 990         }
 991
 992         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 993         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 994
 995         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 996                                     AMD_PMC_MAPPING_SIZE);
 997         if (!dev->regbase) {
 998                 err = -ENOMEM;
 999                 goto err_pci_dev_put;
1000         }
1001
1002         mutex_init(&dev->lock);
1003
1004         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
1005                 err = amd_pmc_s2d_init(dev);
1006                 if (err)
1007                         goto err_pci_dev_put;
1008         }
1009
1010         platform_set_drvdata(pdev, dev);
1011         if (IS_ENABLED(CONFIG_SUSPEND)) {
1012                 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1013                 if (err)
1014                         dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1015         }
1016
1017         amd_pmc_dbgfs_register(dev);
1018         pm_report_max_hw_sleep(U64_MAX);
1019         return 0;
1020
1021 err_pci_dev_put:
1022         pci_dev_put(rdev);
1023         return err;
1024 }
1025
1026 static void amd_pmc_remove(struct platform_device *pdev)
1027 {
1028         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1029
1030         if (IS_ENABLED(CONFIG_SUSPEND))
1031                 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1032         amd_pmc_dbgfs_unregister(dev);
1033         pci_dev_put(dev->rdev);
1034         mutex_destroy(&dev->lock);
1035 }
1036
1037 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1038         {"AMDI0005", 0},
1039         {"AMDI0006", 0},
1040         {"AMDI0007", 0},
1041         {"AMDI0008", 0},
1042         {"AMDI0009", 0},
1043         {"AMD0004", 0},
1044         {"AMD0005", 0},
1045         { }
1046 };
1047 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1048
1049 static struct platform_driver amd_pmc_driver = {
1050         .driver = {
1051                 .name = "amd_pmc",
1052                 .acpi_match_table = amd_pmc_acpi_ids,
1053                 .dev_groups = pmc_groups,
1054                 .pm = pm_sleep_ptr(&amd_pmc_pm),
1055         },
1056         .probe = amd_pmc_probe,
1057         .remove_new = amd_pmc_remove,
1058 };
1059 module_platform_driver(amd_pmc_driver);
1060
1061 MODULE_LICENSE("GPL v2");
1062 MODULE_DESCRIPTION("AMD PMC Driver");