drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_trace.h"
  48 #include "bif/bif_4_1_d.h"
  49
  50 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  51
  52 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  53                              struct ttm_mem_reg *mem, unsigned num_pages,
  54                              uint64_t offset, unsigned window,
  55                              struct amdgpu_ring *ring,
  56                              uint64_t *addr);
  57
  58 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  59 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  60
  61 /*
  62  * Global memory.
  63  */
  64 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  65 {
  66         return ttm_mem_global_init(ref->object);
  67 }
  68
  69 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  70 {
  71         ttm_mem_global_release(ref->object);
  72 }
  73
  74 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  75 {
  76         struct drm_global_reference *global_ref;
  77         struct amdgpu_ring *ring;
  78         struct amd_sched_rq *rq;
  79         int r;
  80
  81         adev->mman.mem_global_referenced = false;
  82         global_ref = &adev->mman.mem_global_ref;
  83         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  84         global_ref->size = sizeof(struct ttm_mem_global);
  85         global_ref->init = &amdgpu_ttm_mem_global_init;
  86         global_ref->release = &amdgpu_ttm_mem_global_release;
  87         r = drm_global_item_ref(global_ref);
  88         if (r) {
  89                 DRM_ERROR("Failed setting up TTM memory accounting "
  90                           "subsystem.\n");
  91                 goto error_mem;
  92         }
  93
  94         adev->mman.bo_global_ref.mem_glob =
  95                 adev->mman.mem_global_ref.object;
  96         global_ref = &adev->mman.bo_global_ref.ref;
  97         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  98         global_ref->size = sizeof(struct ttm_bo_global);
  99         global_ref->init = &ttm_bo_global_init;
 100         global_ref->release = &ttm_bo_global_release;
 101         r = drm_global_item_ref(global_ref);
 102         if (r) {
 103                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 104                 goto error_bo;
 105         }
 106
 107         mutex_init(&adev->mman.gtt_window_lock);
 108
 109         ring = adev->mman.buffer_funcs_ring;
 110         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 111         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 112                                   rq, amdgpu_sched_jobs);
 113         if (r) {
 114                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 115                 goto error_entity;
 116         }
 117
 118         adev->mman.mem_global_referenced = true;
 119
 120         return 0;
 121
 122 error_entity:
 123         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 124 error_bo:
 125         drm_global_item_unref(&adev->mman.mem_global_ref);
 126 error_mem:
 127         return r;
 128 }
 129
 130 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 131 {
 132         if (adev->mman.mem_global_referenced) {
 133                 amd_sched_entity_fini(adev->mman.entity.sched,
 134                                       &adev->mman.entity);
 135                 mutex_destroy(&adev->mman.gtt_window_lock);
 136                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 137                 drm_global_item_unref(&adev->mman.mem_global_ref);
 138                 adev->mman.mem_global_referenced = false;
 139         }
 140 }
 141
 142 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 143 {
 144         return 0;
 145 }
 146
 147 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 148                                 struct ttm_mem_type_manager *man)
 149 {
 150         struct amdgpu_device *adev;
 151
 152         adev = amdgpu_ttm_adev(bdev);
 153
 154         switch (type) {
 155         case TTM_PL_SYSTEM:
 156                 /* System memory */
 157                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 158                 man->available_caching = TTM_PL_MASK_CACHING;
 159                 man->default_caching = TTM_PL_FLAG_CACHED;
 160                 break;
 161         case TTM_PL_TT:
 162                 man->func = &amdgpu_gtt_mgr_func;
 163                 man->gpu_offset = adev->mc.gart_start;
 164                 man->available_caching = TTM_PL_MASK_CACHING;
 165                 man->default_caching = TTM_PL_FLAG_CACHED;
 166                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 167                 break;
 168         case TTM_PL_VRAM:
 169                 /* "On-card" video ram */
 170                 man->func = &amdgpu_vram_mgr_func;
 171                 man->gpu_offset = adev->mc.vram_start;
 172                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 173                              TTM_MEMTYPE_FLAG_MAPPABLE;
 174                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 175                 man->default_caching = TTM_PL_FLAG_WC;
 176                 break;
 177         case AMDGPU_PL_GDS:
 178         case AMDGPU_PL_GWS:
 179         case AMDGPU_PL_OA:
 180                 /* On-chip GDS memory*/
 181                 man->func = &ttm_bo_manager_func;
 182                 man->gpu_offset = 0;
 183                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 184                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 185                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 186                 break;
 187         default:
 188                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 189                 return -EINVAL;
 190         }
 191         return 0;
 192 }
 193
 194 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 195                                 struct ttm_placement *placement)
 196 {
 197         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 198         struct amdgpu_bo *abo;
 199         static const struct ttm_place placements = {
 200                 .fpfn = 0,
 201                 .lpfn = 0,
 202                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 203         };
 204
 205         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 206                 placement->placement = &placements;
 207                 placement->busy_placement = &placements;
 208                 placement->num_placement = 1;
 209                 placement->num_busy_placement = 1;
 210                 return;
 211         }
 212         abo = container_of(bo, struct amdgpu_bo, tbo);
 213         switch (bo->mem.mem_type) {
 214         case TTM_PL_VRAM:
 215                 if (adev->mman.buffer_funcs &&
 216                     adev->mman.buffer_funcs_ring &&
 217                     adev->mman.buffer_funcs_ring->ready == false) {
 218                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 219                 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 220                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 221                         unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 222                         struct drm_mm_node *node = bo->mem.mm_node;
 223                         unsigned long pages_left;
 224
 225                         for (pages_left = bo->mem.num_pages;
 226                              pages_left;
 227                              pages_left -= node->size, node++) {
 228                                 if (node->start < fpfn)
 229                                         break;
 230                         }
 231
 232                         if (!pages_left)
 233                                 goto gtt;
 234
 235                         /* Try evicting to the CPU inaccessible part of VRAM
 236                          * first, but only set GTT as busy placement, so this
 237                          * BO will be evicted to GTT rather than causing other
 238                          * BOs to be evicted from VRAM
 239                          */
 240                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 241                                                          AMDGPU_GEM_DOMAIN_GTT);
 242                         abo->placements[0].fpfn = fpfn;
 243                         abo->placements[0].lpfn = 0;
 244                         abo->placement.busy_placement = &abo->placements[1];
 245                         abo->placement.num_busy_placement = 1;
 246                 } else {
 247 gtt:
 248                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 249                 }
 250                 break;
 251         case TTM_PL_TT:
 252         default:
 253                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 254         }
 255         *placement = abo->placement;
 256 }
 257
 258 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 259 {
 260         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 261
 262         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 263                 return -EPERM;
 264         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 265                                           filp->private_data);
 266 }
 267
 268 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 269                              struct ttm_mem_reg *new_mem)
 270 {
 271         struct ttm_mem_reg *old_mem = &bo->mem;
 272
 273         BUG_ON(old_mem->mm_node != NULL);
 274         *old_mem = *new_mem;
 275         new_mem->mm_node = NULL;
 276 }
 277
 278 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 279                                     struct drm_mm_node *mm_node,
 280                                     struct ttm_mem_reg *mem)
 281 {
 282         uint64_t addr = 0;
 283
 284         if (mem->mem_type != TTM_PL_TT ||
 285             amdgpu_gtt_mgr_is_allocated(mem)) {
 286                 addr = mm_node->start << PAGE_SHIFT;
 287                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 288         }
 289         return addr;
 290 }
 291
 292 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 293                             bool evict, bool no_wait_gpu,
 294                             struct ttm_mem_reg *new_mem,
 295                             struct ttm_mem_reg *old_mem)
 296 {
 297         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 298         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 299
 300         struct drm_mm_node *old_mm, *new_mm;
 301         uint64_t old_start, old_size, new_start, new_size;
 302         unsigned long num_pages;
 303         struct dma_fence *fence = NULL;
 304         int r;
 305
 306         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 307
 308         if (!ring->ready) {
 309                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 310                 return -EINVAL;
 311         }
 312
 313         old_mm = old_mem->mm_node;
 314         old_size = old_mm->size;
 315         old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
 316
 317         new_mm = new_mem->mm_node;
 318         new_size = new_mm->size;
 319         new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
 320
 321         num_pages = new_mem->num_pages;
 322         mutex_lock(&adev->mman.gtt_window_lock);
 323         while (num_pages) {
 324                 unsigned long cur_pages = min(min(old_size, new_size),
 325                                               (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
 326                 uint64_t from = old_start, to = new_start;
 327                 struct dma_fence *next;
 328
 329                 if (old_mem->mem_type == TTM_PL_TT &&
 330                     !amdgpu_gtt_mgr_is_allocated(old_mem)) {
 331                         r = amdgpu_map_buffer(bo, old_mem, cur_pages,
 332                                               old_start, 0, ring, &from);
 333                         if (r)
 334                                 goto error;
 335                 }
 336
 337                 if (new_mem->mem_type == TTM_PL_TT &&
 338                     !amdgpu_gtt_mgr_is_allocated(new_mem)) {
 339                         r = amdgpu_map_buffer(bo, new_mem, cur_pages,
 340                                               new_start, 1, ring, &to);
 341                         if (r)
 342                                 goto error;
 343                 }
 344
 345                 r = amdgpu_copy_buffer(ring, from, to,
 346                                        cur_pages * PAGE_SIZE,
 347                                        bo->resv, &next, false, true);
 348                 if (r)
 349                         goto error;
 350
 351                 dma_fence_put(fence);
 352                 fence = next;
 353
 354                 num_pages -= cur_pages;
 355                 if (!num_pages)
 356                         break;
 357
 358                 old_size -= cur_pages;
 359                 if (!old_size) {
 360                         old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
 361                         old_size = old_mm->size;
 362                 } else {
 363                         old_start += cur_pages * PAGE_SIZE;
 364                 }
 365
 366                 new_size -= cur_pages;
 367                 if (!new_size) {
 368                         new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
 369                         new_size = new_mm->size;
 370                 } else {
 371                         new_start += cur_pages * PAGE_SIZE;
 372                 }
 373         }
 374         mutex_unlock(&adev->mman.gtt_window_lock);
 375
 376         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 377         dma_fence_put(fence);
 378         return r;
 379
 380 error:
 381         mutex_unlock(&adev->mman.gtt_window_lock);
 382
 383         if (fence)
 384                 dma_fence_wait(fence, false);
 385         dma_fence_put(fence);
 386         return r;
 387 }
 388
 389 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 390                                 bool evict, bool interruptible,
 391                                 bool no_wait_gpu,
 392                                 struct ttm_mem_reg *new_mem)
 393 {
 394         struct amdgpu_device *adev;
 395         struct ttm_mem_reg *old_mem = &bo->mem;
 396         struct ttm_mem_reg tmp_mem;
 397         struct ttm_place placements;
 398         struct ttm_placement placement;
 399         int r;
 400
 401         adev = amdgpu_ttm_adev(bo->bdev);
 402         tmp_mem = *new_mem;
 403         tmp_mem.mm_node = NULL;
 404         placement.num_placement = 1;
 405         placement.placement = &placements;
 406         placement.num_busy_placement = 1;
 407         placement.busy_placement = &placements;
 408         placements.fpfn = 0;
 409         placements.lpfn = 0;
 410         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 411         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 412                              interruptible, no_wait_gpu);
 413         if (unlikely(r)) {
 414                 return r;
 415         }
 416
 417         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 418         if (unlikely(r)) {
 419                 goto out_cleanup;
 420         }
 421
 422         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 423         if (unlikely(r)) {
 424                 goto out_cleanup;
 425         }
 426         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 427         if (unlikely(r)) {
 428                 goto out_cleanup;
 429         }
 430         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 431 out_cleanup:
 432         ttm_bo_mem_put(bo, &tmp_mem);
 433         return r;
 434 }
 435
 436 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 437                                 bool evict, bool interruptible,
 438                                 bool no_wait_gpu,
 439                                 struct ttm_mem_reg *new_mem)
 440 {
 441         struct amdgpu_device *adev;
 442         struct ttm_mem_reg *old_mem = &bo->mem;
 443         struct ttm_mem_reg tmp_mem;
 444         struct ttm_placement placement;
 445         struct ttm_place placements;
 446         int r;
 447
 448         adev = amdgpu_ttm_adev(bo->bdev);
 449         tmp_mem = *new_mem;
 450         tmp_mem.mm_node = NULL;
 451         placement.num_placement = 1;
 452         placement.placement = &placements;
 453         placement.num_busy_placement = 1;
 454         placement.busy_placement = &placements;
 455         placements.fpfn = 0;
 456         placements.lpfn = 0;
 457         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 458         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 459                              interruptible, no_wait_gpu);
 460         if (unlikely(r)) {
 461                 return r;
 462         }
 463         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 464         if (unlikely(r)) {
 465                 goto out_cleanup;
 466         }
 467         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 468         if (unlikely(r)) {
 469                 goto out_cleanup;
 470         }
 471 out_cleanup:
 472         ttm_bo_mem_put(bo, &tmp_mem);
 473         return r;
 474 }
 475
 476 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 477                         bool evict, bool interruptible,
 478                         bool no_wait_gpu,
 479                         struct ttm_mem_reg *new_mem)
 480 {
 481         struct amdgpu_device *adev;
 482         struct amdgpu_bo *abo;
 483         struct ttm_mem_reg *old_mem = &bo->mem;
 484         int r;
 485
 486         /* Can't move a pinned BO */
 487         abo = container_of(bo, struct amdgpu_bo, tbo);
 488         if (WARN_ON_ONCE(abo->pin_count > 0))
 489                 return -EINVAL;
 490
 491         adev = amdgpu_ttm_adev(bo->bdev);
 492
 493         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 494                 amdgpu_move_null(bo, new_mem);
 495                 return 0;
 496         }
 497         if ((old_mem->mem_type == TTM_PL_TT &&
 498              new_mem->mem_type == TTM_PL_SYSTEM) ||
 499             (old_mem->mem_type == TTM_PL_SYSTEM &&
 500              new_mem->mem_type == TTM_PL_TT)) {
 501                 /* bind is enough */
 502                 amdgpu_move_null(bo, new_mem);
 503                 return 0;
 504         }
 505         if (adev->mman.buffer_funcs == NULL ||
 506             adev->mman.buffer_funcs_ring == NULL ||
 507             !adev->mman.buffer_funcs_ring->ready) {
 508                 /* use memcpy */
 509                 goto memcpy;
 510         }
 511
 512         if (old_mem->mem_type == TTM_PL_VRAM &&
 513             new_mem->mem_type == TTM_PL_SYSTEM) {
 514                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 515                                         no_wait_gpu, new_mem);
 516         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 517                    new_mem->mem_type == TTM_PL_VRAM) {
 518                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 519                                             no_wait_gpu, new_mem);
 520         } else {
 521                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 522         }
 523
 524         if (r) {
 525 memcpy:
 526                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 527                 if (r) {
 528                         return r;
 529                 }
 530         }
 531
 532         if (bo->type == ttm_bo_type_device &&
 533             new_mem->mem_type == TTM_PL_VRAM &&
 534             old_mem->mem_type != TTM_PL_VRAM) {
 535                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 536                  * accesses the BO after it's moved.
 537                  */
 538                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 539         }
 540
 541         /* update statistics */
 542         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 543         return 0;
 544 }
 545
 546 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 547 {
 548         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 549         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 550
 551         mem->bus.addr = NULL;
 552         mem->bus.offset = 0;
 553         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 554         mem->bus.base = 0;
 555         mem->bus.is_iomem = false;
 556         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 557                 return -EINVAL;
 558         switch (mem->mem_type) {
 559         case TTM_PL_SYSTEM:
 560                 /* system memory */
 561                 return 0;
 562         case TTM_PL_TT:
 563                 break;
 564         case TTM_PL_VRAM:
 565                 mem->bus.offset = mem->start << PAGE_SHIFT;
 566                 /* check if it's visible */
 567                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 568                         return -EINVAL;
 569                 mem->bus.base = adev->mc.aper_base;
 570                 mem->bus.is_iomem = true;
 571                 break;
 572         default:
 573                 return -EINVAL;
 574         }
 575         return 0;
 576 }
 577
 578 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 579 {
 580 }
 581
 582 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 583                                            unsigned long page_offset)
 584 {
 585         struct drm_mm_node *mm = bo->mem.mm_node;
 586         uint64_t size = mm->size;
 587         uint64_t offset = page_offset;
 588
 589         page_offset = do_div(offset, size);
 590         mm += offset;
 591         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 592 }
 593
 594 /*
 595  * TTM backend functions.
 596  */
 597 struct amdgpu_ttm_gup_task_list {
 598         struct list_head        list;
 599         struct task_struct      *task;
 600 };
 601
 602 struct amdgpu_ttm_tt {
 603         struct ttm_dma_tt       ttm;
 604         struct amdgpu_device    *adev;
 605         u64                     offset;
 606         uint64_t                userptr;
 607         struct mm_struct        *usermm;
 608         uint32_t                userflags;
 609         spinlock_t              guptasklock;
 610         struct list_head        guptasks;
 611         atomic_t                mmu_invalidations;
 612         uint32_t                last_set_pages;
 613         struct list_head        list;
 614 };
 615
 616 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 617 {
 618         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 619         unsigned int flags = 0;
 620         unsigned pinned = 0;
 621         int r;
 622
 623         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 624                 flags |= FOLL_WRITE;
 625
 626         down_read(&current->mm->mmap_sem);
 627
 628         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 629                 /* check that we only use anonymous memory
 630                    to prevent problems with writeback */
 631                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 632                 struct vm_area_struct *vma;
 633
 634                 vma = find_vma(gtt->usermm, gtt->userptr);
 635                 if (!vma || vma->vm_file || vma->vm_end < end) {
 636                         up_read(&current->mm->mmap_sem);
 637                         return -EPERM;
 638                 }
 639         }
 640
 641         do {
 642                 unsigned num_pages = ttm->num_pages - pinned;
 643                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 644                 struct page **p = pages + pinned;
 645                 struct amdgpu_ttm_gup_task_list guptask;
 646
 647                 guptask.task = current;
 648                 spin_lock(&gtt->guptasklock);
 649                 list_add(&guptask.list, &gtt->guptasks);
 650                 spin_unlock(&gtt->guptasklock);
 651
 652                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 653
 654                 spin_lock(&gtt->guptasklock);
 655                 list_del(&guptask.list);
 656                 spin_unlock(&gtt->guptasklock);
 657
 658                 if (r < 0)
 659                         goto release_pages;
 660
 661                 pinned += r;
 662
 663         } while (pinned < ttm->num_pages);
 664
 665         up_read(&current->mm->mmap_sem);
 666         return 0;
 667
 668 release_pages:
 669         release_pages(pages, pinned, 0);
 670         up_read(&current->mm->mmap_sem);
 671         return r;
 672 }
 673
 674 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 675 {
 676         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 677         unsigned i;
 678
 679         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 680         for (i = 0; i < ttm->num_pages; ++i) {
 681                 if (ttm->pages[i])
 682                         put_page(ttm->pages[i]);
 683
 684                 ttm->pages[i] = pages ? pages[i] : NULL;
 685         }
 686 }
 687
 688 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 689 {
 690         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 691         unsigned i;
 692
 693         for (i = 0; i < ttm->num_pages; ++i) {
 694                 struct page *page = ttm->pages[i];
 695
 696                 if (!page)
 697                         continue;
 698
 699                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 700                         set_page_dirty(page);
 701
 702                 mark_page_accessed(page);
 703         }
 704 }
 705
 706 /* prepare the sg table with the user pages */
 707 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 708 {
 709         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 710         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 711         unsigned nents;
 712         int r;
 713
 714         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 715         enum dma_data_direction direction = write ?
 716                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 717
 718         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 719                                       ttm->num_pages << PAGE_SHIFT,
 720                                       GFP_KERNEL);
 721         if (r)
 722                 goto release_sg;
 723
 724         r = -ENOMEM;
 725         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 726         if (nents != ttm->sg->nents)
 727                 goto release_sg;
 728
 729         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 730                                          gtt->ttm.dma_address, ttm->num_pages);
 731
 732         return 0;
 733
 734 release_sg:
 735         kfree(ttm->sg);
 736         return r;
 737 }
 738
 739 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 740 {
 741         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 742         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 743
 744         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 745         enum dma_data_direction direction = write ?
 746                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 747
 748         /* double check that we don't free the table twice */
 749         if (!ttm->sg->sgl)
 750                 return;
 751
 752         /* free the sg table and pages again */
 753         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 754
 755         amdgpu_ttm_tt_mark_user_pages(ttm);
 756
 757         sg_free_table(ttm->sg);
 758 }
 759
 760 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 761                                    struct ttm_mem_reg *bo_mem)
 762 {
 763         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 764         uint64_t flags;
 765         int r = 0;
 766
 767         if (gtt->userptr) {
 768                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 769                 if (r) {
 770                         DRM_ERROR("failed to pin userptr\n");
 771                         return r;
 772                 }
 773         }
 774         if (!ttm->num_pages) {
 775                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 776                      ttm->num_pages, bo_mem, ttm);
 777         }
 778
 779         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 780             bo_mem->mem_type == AMDGPU_PL_GWS ||
 781             bo_mem->mem_type == AMDGPU_PL_OA)
 782                 return -EINVAL;
 783
 784         if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
 785                 return 0;
 786
 787         spin_lock(&gtt->adev->gtt_list_lock);
 788         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 789         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 790         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 791                 ttm->pages, gtt->ttm.dma_address, flags);
 792
 793         if (r) {
 794                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 795                           ttm->num_pages, gtt->offset);
 796                 goto error_gart_bind;
 797         }
 798
 799         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 800 error_gart_bind:
 801         spin_unlock(&gtt->adev->gtt_list_lock);
 802         return r;
 803 }
 804
 805 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 806 {
 807         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 808
 809         return gtt && !list_empty(&gtt->list);
 810 }
 811
 812 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 813 {
 814         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 815         struct ttm_tt *ttm = bo->ttm;
 816         struct ttm_mem_reg tmp;
 817
 818         struct ttm_placement placement;
 819         struct ttm_place placements;
 820         int r;
 821
 822         if (!ttm || amdgpu_ttm_is_bound(ttm))
 823                 return 0;
 824
 825         tmp = bo->mem;
 826         tmp.mm_node = NULL;
 827         placement.num_placement = 1;
 828         placement.placement = &placements;
 829         placement.num_busy_placement = 1;
 830         placement.busy_placement = &placements;
 831         placements.fpfn = 0;
 832         placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
 833         placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
 834
 835         r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
 836         if (unlikely(r))
 837                 return r;
 838
 839         r = ttm_bo_move_ttm(bo, true, false, &tmp);
 840         if (unlikely(r))
 841                 ttm_bo_mem_put(bo, &tmp);
 842         else
 843                 bo->offset = (bo->mem.start << PAGE_SHIFT) +
 844                         bo->bdev->man[bo->mem.mem_type].gpu_offset;
 845
 846         return r;
 847 }
 848
 849 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 850 {
 851         struct amdgpu_ttm_tt *gtt, *tmp;
 852         struct ttm_mem_reg bo_mem;
 853         uint64_t flags;
 854         int r;
 855
 856         bo_mem.mem_type = TTM_PL_TT;
 857         spin_lock(&adev->gtt_list_lock);
 858         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 859                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 860                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 861                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 862                                      flags);
 863                 if (r) {
 864                         spin_unlock(&adev->gtt_list_lock);
 865                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 866                                   gtt->ttm.ttm.num_pages, gtt->offset);
 867                         return r;
 868                 }
 869         }
 870         spin_unlock(&adev->gtt_list_lock);
 871         return 0;
 872 }
 873
 874 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 875 {
 876         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 877         int r;
 878
 879         if (gtt->userptr)
 880                 amdgpu_ttm_tt_unpin_userptr(ttm);
 881
 882         if (!amdgpu_ttm_is_bound(ttm))
 883                 return 0;
 884
 885         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 886         spin_lock(&gtt->adev->gtt_list_lock);
 887         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 888         if (r) {
 889                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 890                           gtt->ttm.ttm.num_pages, gtt->offset);
 891                 goto error_unbind;
 892         }
 893         list_del_init(&gtt->list);
 894 error_unbind:
 895         spin_unlock(&gtt->adev->gtt_list_lock);
 896         return r;
 897 }
 898
 899 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 900 {
 901         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 902
 903         ttm_dma_tt_fini(&gtt->ttm);
 904         kfree(gtt);
 905 }
 906
 907 static struct ttm_backend_func amdgpu_backend_func = {
 908         .bind = &amdgpu_ttm_backend_bind,
 909         .unbind = &amdgpu_ttm_backend_unbind,
 910         .destroy = &amdgpu_ttm_backend_destroy,
 911 };
 912
 913 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 914                                     unsigned long size, uint32_t page_flags,
 915                                     struct page *dummy_read_page)
 916 {
 917         struct amdgpu_device *adev;
 918         struct amdgpu_ttm_tt *gtt;
 919
 920         adev = amdgpu_ttm_adev(bdev);
 921
 922         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 923         if (gtt == NULL) {
 924                 return NULL;
 925         }
 926         gtt->ttm.ttm.func = &amdgpu_backend_func;
 927         gtt->adev = adev;
 928         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 929                 kfree(gtt);
 930                 return NULL;
 931         }
 932         INIT_LIST_HEAD(&gtt->list);
 933         return &gtt->ttm.ttm;
 934 }
 935
 936 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 937 {
 938         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 939         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 940         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 941
 942         if (ttm->state != tt_unpopulated)
 943                 return 0;
 944
 945         if (gtt && gtt->userptr) {
 946                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 947                 if (!ttm->sg)
 948                         return -ENOMEM;
 949
 950                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 951                 ttm->state = tt_unbound;
 952                 return 0;
 953         }
 954
 955         if (slave && ttm->sg) {
 956                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 957                                                  gtt->ttm.dma_address, ttm->num_pages);
 958                 ttm->state = tt_unbound;
 959                 return 0;
 960         }
 961
 962 #ifdef CONFIG_SWIOTLB
 963         if (swiotlb_nr_tbl()) {
 964                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 965         }
 966 #endif
 967
 968         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
 969 }
 970
 971 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 972 {
 973         struct amdgpu_device *adev;
 974         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 975         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 976
 977         if (gtt && gtt->userptr) {
 978                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
 979                 kfree(ttm->sg);
 980                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 981                 return;
 982         }
 983
 984         if (slave)
 985                 return;
 986
 987         adev = amdgpu_ttm_adev(ttm->bdev);
 988
 989 #ifdef CONFIG_SWIOTLB
 990         if (swiotlb_nr_tbl()) {
 991                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 992                 return;
 993         }
 994 #endif
 995
 996         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
 997 }
 998
 999 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1000                               uint32_t flags)
1001 {
1002         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1003
1004         if (gtt == NULL)
1005                 return -EINVAL;
1006
1007         gtt->userptr = addr;
1008         gtt->usermm = current->mm;
1009         gtt->userflags = flags;
1010         spin_lock_init(&gtt->guptasklock);
1011         INIT_LIST_HEAD(&gtt->guptasks);
1012         atomic_set(&gtt->mmu_invalidations, 0);
1013         gtt->last_set_pages = 0;
1014
1015         return 0;
1016 }
1017
1018 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1019 {
1020         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1021
1022         if (gtt == NULL)
1023                 return NULL;
1024
1025         return gtt->usermm;
1026 }
1027
1028 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1029                                   unsigned long end)
1030 {
1031         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1032         struct amdgpu_ttm_gup_task_list *entry;
1033         unsigned long size;
1034
1035         if (gtt == NULL || !gtt->userptr)
1036                 return false;
1037
1038         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1039         if (gtt->userptr > end || gtt->userptr + size <= start)
1040                 return false;
1041
1042         spin_lock(&gtt->guptasklock);
1043         list_for_each_entry(entry, &gtt->guptasks, list) {
1044                 if (entry->task == current) {
1045                         spin_unlock(&gtt->guptasklock);
1046                         return false;
1047                 }
1048         }
1049         spin_unlock(&gtt->guptasklock);
1050
1051         atomic_inc(&gtt->mmu_invalidations);
1052
1053         return true;
1054 }
1055
1056 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1057                                        int *last_invalidated)
1058 {
1059         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1060         int prev_invalidated = *last_invalidated;
1061
1062         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1063         return prev_invalidated != *last_invalidated;
1064 }
1065
1066 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1067 {
1068         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1069
1070         if (gtt == NULL || !gtt->userptr)
1071                 return false;
1072
1073         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1074 }
1075
1076 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1077 {
1078         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1079
1080         if (gtt == NULL)
1081                 return false;
1082
1083         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1084 }
1085
1086 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1087                                  struct ttm_mem_reg *mem)
1088 {
1089         uint64_t flags = 0;
1090
1091         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1092                 flags |= AMDGPU_PTE_VALID;
1093
1094         if (mem && mem->mem_type == TTM_PL_TT) {
1095                 flags |= AMDGPU_PTE_SYSTEM;
1096
1097                 if (ttm->caching_state == tt_cached)
1098                         flags |= AMDGPU_PTE_SNOOPED;
1099         }
1100
1101         flags |= adev->gart.gart_pte_flags;
1102         flags |= AMDGPU_PTE_READABLE;
1103
1104         if (!amdgpu_ttm_tt_is_readonly(ttm))
1105                 flags |= AMDGPU_PTE_WRITEABLE;
1106
1107         return flags;
1108 }
1109
1110 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1111                                             const struct ttm_place *place)
1112 {
1113         unsigned long num_pages = bo->mem.num_pages;
1114         struct drm_mm_node *node = bo->mem.mm_node;
1115
1116         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1117                 return ttm_bo_eviction_valuable(bo, place);
1118
1119         switch (bo->mem.mem_type) {
1120         case TTM_PL_TT:
1121                 return true;
1122
1123         case TTM_PL_VRAM:
1124                 /* Check each drm MM node individually */
1125                 while (num_pages) {
1126                         if (place->fpfn < (node->start + node->size) &&
1127                             !(place->lpfn && place->lpfn <= node->start))
1128                                 return true;
1129
1130                         num_pages -= node->size;
1131                         ++node;
1132                 }
1133                 break;
1134
1135         default:
1136                 break;
1137         }
1138
1139         return ttm_bo_eviction_valuable(bo, place);
1140 }
1141
1142 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1143                                     unsigned long offset,
1144                                     void *buf, int len, int write)
1145 {
1146         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
1147         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1148         struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
1149         uint32_t value = 0;
1150         int ret = 0;
1151         uint64_t pos;
1152         unsigned long flags;
1153
1154         if (bo->mem.mem_type != TTM_PL_VRAM)
1155                 return -EIO;
1156
1157         while (offset >= (nodes->size << PAGE_SHIFT)) {
1158                 offset -= nodes->size << PAGE_SHIFT;
1159                 ++nodes;
1160         }
1161         pos = (nodes->start << PAGE_SHIFT) + offset;
1162
1163         while (len && pos < adev->mc.mc_vram_size) {
1164                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1165                 uint32_t bytes = 4 - (pos & 3);
1166                 uint32_t shift = (pos & 3) * 8;
1167                 uint32_t mask = 0xffffffff << shift;
1168
1169                 if (len < bytes) {
1170                         mask &= 0xffffffff >> (bytes - len) * 8;
1171                         bytes = len;
1172                 }
1173
1174                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1175                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1176                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1177                 if (!write || mask != 0xffffffff)
1178                         value = RREG32_NO_KIQ(mmMM_DATA);
1179                 if (write) {
1180                         value &= ~mask;
1181                         value |= (*(uint32_t *)buf << shift) & mask;
1182                         WREG32_NO_KIQ(mmMM_DATA, value);
1183                 }
1184                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1185                 if (!write) {
1186                         value = (value & mask) >> shift;
1187                         memcpy(buf, &value, bytes);
1188                 }
1189
1190                 ret += bytes;
1191                 buf = (uint8_t *)buf + bytes;
1192                 pos += bytes;
1193                 len -= bytes;
1194                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1195                         ++nodes;
1196                         pos = (nodes->start << PAGE_SHIFT);
1197                 }
1198         }
1199
1200         return ret;
1201 }
1202
1203 static struct ttm_bo_driver amdgpu_bo_driver = {
1204         .ttm_tt_create = &amdgpu_ttm_tt_create,
1205         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1206         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1207         .invalidate_caches = &amdgpu_invalidate_caches,
1208         .init_mem_type = &amdgpu_init_mem_type,
1209         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1210         .evict_flags = &amdgpu_evict_flags,
1211         .move = &amdgpu_bo_move,
1212         .verify_access = &amdgpu_verify_access,
1213         .move_notify = &amdgpu_bo_move_notify,
1214         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1215         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1216         .io_mem_free = &amdgpu_ttm_io_mem_free,
1217         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1218         .access_memory = &amdgpu_ttm_access_memory
1219 };
1220
1221 int amdgpu_ttm_init(struct amdgpu_device *adev)
1222 {
1223         uint64_t gtt_size;
1224         int r;
1225         u64 vis_vram_limit;
1226
1227         r = amdgpu_ttm_global_init(adev);
1228         if (r) {
1229                 return r;
1230         }
1231         /* No others user of address space so set it to 0 */
1232         r = ttm_bo_device_init(&adev->mman.bdev,
1233                                adev->mman.bo_global_ref.ref.object,
1234                                &amdgpu_bo_driver,
1235                                adev->ddev->anon_inode->i_mapping,
1236                                DRM_FILE_PAGE_OFFSET,
1237                                adev->need_dma32);
1238         if (r) {
1239                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1240                 return r;
1241         }
1242         adev->mman.initialized = true;
1243         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1244                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1245         if (r) {
1246                 DRM_ERROR("Failed initializing VRAM heap.\n");
1247                 return r;
1248         }
1249
1250         /* Reduce size of CPU-visible VRAM if requested */
1251         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1252         if (amdgpu_vis_vram_limit > 0 &&
1253             vis_vram_limit <= adev->mc.visible_vram_size)
1254                 adev->mc.visible_vram_size = vis_vram_limit;
1255
1256         /* Change the size here instead of the init above so only lpfn is affected */
1257         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1258
1259         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1260                                     AMDGPU_GEM_DOMAIN_VRAM,
1261                                     &adev->stolen_vga_memory,
1262                                     NULL, NULL);
1263         if (r)
1264                 return r;
1265         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1266                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1267
1268         if (amdgpu_gtt_size == -1)
1269                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1270                                adev->mc.mc_vram_size);
1271         else
1272                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1273         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1274         if (r) {
1275                 DRM_ERROR("Failed initializing GTT heap.\n");
1276                 return r;
1277         }
1278         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1279                  (unsigned)(gtt_size / (1024 * 1024)));
1280
1281         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1282         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1283         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1284         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1285         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1286         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1287         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1288         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1289         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1290         /* GDS Memory */
1291         if (adev->gds.mem.total_size) {
1292                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1293                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1294                 if (r) {
1295                         DRM_ERROR("Failed initializing GDS heap.\n");
1296                         return r;
1297                 }
1298         }
1299
1300         /* GWS */
1301         if (adev->gds.gws.total_size) {
1302                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1303                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1304                 if (r) {
1305                         DRM_ERROR("Failed initializing gws heap.\n");
1306                         return r;
1307                 }
1308         }
1309
1310         /* OA */
1311         if (adev->gds.oa.total_size) {
1312                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1313                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1314                 if (r) {
1315                         DRM_ERROR("Failed initializing oa heap.\n");
1316                         return r;
1317                 }
1318         }
1319
1320         r = amdgpu_ttm_debugfs_init(adev);
1321         if (r) {
1322                 DRM_ERROR("Failed to init debugfs\n");
1323                 return r;
1324         }
1325         return 0;
1326 }
1327
1328 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1329 {
1330         int r;
1331
1332         if (!adev->mman.initialized)
1333                 return;
1334         amdgpu_ttm_debugfs_fini(adev);
1335         if (adev->stolen_vga_memory) {
1336                 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1337                 if (r == 0) {
1338                         amdgpu_bo_unpin(adev->stolen_vga_memory);
1339                         amdgpu_bo_unreserve(adev->stolen_vga_memory);
1340                 }
1341                 amdgpu_bo_unref(&adev->stolen_vga_memory);
1342         }
1343         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1344         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1345         if (adev->gds.mem.total_size)
1346                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1347         if (adev->gds.gws.total_size)
1348                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1349         if (adev->gds.oa.total_size)
1350                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1351         ttm_bo_device_release(&adev->mman.bdev);
1352         amdgpu_gart_fini(adev);
1353         amdgpu_ttm_global_fini(adev);
1354         adev->mman.initialized = false;
1355         DRM_INFO("amdgpu: ttm finalized\n");
1356 }
1357
1358 /* this should only be called at bootup or when userspace
1359  * isn't running */
1360 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1361 {
1362         struct ttm_mem_type_manager *man;
1363
1364         if (!adev->mman.initialized)
1365                 return;
1366
1367         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1368         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1369         man->size = size >> PAGE_SHIFT;
1370 }
1371
1372 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1373 {
1374         struct drm_file *file_priv;
1375         struct amdgpu_device *adev;
1376
1377         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1378                 return -EINVAL;
1379
1380         file_priv = filp->private_data;
1381         adev = file_priv->minor->dev->dev_private;
1382         if (adev == NULL)
1383                 return -EINVAL;
1384
1385         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1386 }
1387
1388 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1389                              struct ttm_mem_reg *mem, unsigned num_pages,
1390                              uint64_t offset, unsigned window,
1391                              struct amdgpu_ring *ring,
1392                              uint64_t *addr)
1393 {
1394         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1395         struct amdgpu_device *adev = ring->adev;
1396         struct ttm_tt *ttm = bo->ttm;
1397         struct amdgpu_job *job;
1398         unsigned num_dw, num_bytes;
1399         dma_addr_t *dma_address;
1400         struct dma_fence *fence;
1401         uint64_t src_addr, dst_addr;
1402         uint64_t flags;
1403         int r;
1404
1405         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1406                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1407
1408         *addr = adev->mc.gart_start;
1409         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1410                 AMDGPU_GPU_PAGE_SIZE;
1411
1412         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1413         while (num_dw & 0x7)
1414                 num_dw++;
1415
1416         num_bytes = num_pages * 8;
1417
1418         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1419         if (r)
1420                 return r;
1421
1422         src_addr = num_dw * 4;
1423         src_addr += job->ibs[0].gpu_addr;
1424
1425         dst_addr = adev->gart.table_addr;
1426         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1427         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1428                                 dst_addr, num_bytes);
1429
1430         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1431         WARN_ON(job->ibs[0].length_dw > num_dw);
1432
1433         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1434         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1435         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1436                             &job->ibs[0].ptr[num_dw]);
1437         if (r)
1438                 goto error_free;
1439
1440         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1441                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1442         if (r)
1443                 goto error_free;
1444
1445         dma_fence_put(fence);
1446
1447         return r;
1448
1449 error_free:
1450         amdgpu_job_free(job);
1451         return r;
1452 }
1453
1454 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1455                        uint64_t dst_offset, uint32_t byte_count,
1456                        struct reservation_object *resv,
1457                        struct dma_fence **fence, bool direct_submit,
1458                        bool vm_needs_flush)
1459 {
1460         struct amdgpu_device *adev = ring->adev;
1461         struct amdgpu_job *job;
1462
1463         uint32_t max_bytes;
1464         unsigned num_loops, num_dw;
1465         unsigned i;
1466         int r;
1467
1468         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1469         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1470         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1471
1472         /* for IB padding */
1473         while (num_dw & 0x7)
1474                 num_dw++;
1475
1476         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1477         if (r)
1478                 return r;
1479
1480         job->vm_needs_flush = vm_needs_flush;
1481         if (resv) {
1482                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1483                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1484                 if (r) {
1485                         DRM_ERROR("sync failed (%d).\n", r);
1486                         goto error_free;
1487                 }
1488         }
1489
1490         for (i = 0; i < num_loops; i++) {
1491                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1492
1493                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1494                                         dst_offset, cur_size_in_bytes);
1495
1496                 src_offset += cur_size_in_bytes;
1497                 dst_offset += cur_size_in_bytes;
1498                 byte_count -= cur_size_in_bytes;
1499         }
1500
1501         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1502         WARN_ON(job->ibs[0].length_dw > num_dw);
1503         if (direct_submit) {
1504                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1505                                        NULL, fence);
1506                 job->fence = dma_fence_get(*fence);
1507                 if (r)
1508                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1509                 amdgpu_job_free(job);
1510         } else {
1511                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1512                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1513                 if (r)
1514                         goto error_free;
1515         }
1516
1517         return r;
1518
1519 error_free:
1520         amdgpu_job_free(job);
1521         return r;
1522 }
1523
1524 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1525                        uint64_t src_data,
1526                        struct reservation_object *resv,
1527                        struct dma_fence **fence)
1528 {
1529         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1530         uint32_t max_bytes = 8 *
1531                         adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
1532         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1533
1534         struct drm_mm_node *mm_node;
1535         unsigned long num_pages;
1536         unsigned int num_loops, num_dw;
1537
1538         struct amdgpu_job *job;
1539         int r;
1540
1541         if (!ring->ready) {
1542                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1543                 return -EINVAL;
1544         }
1545
1546         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1547                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1548                 if (r)
1549                         return r;
1550         }
1551
1552         num_pages = bo->tbo.num_pages;
1553         mm_node = bo->tbo.mem.mm_node;
1554         num_loops = 0;
1555         while (num_pages) {
1556                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1557
1558                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1559                 num_pages -= mm_node->size;
1560                 ++mm_node;
1561         }
1562
1563         /* num of dwords for each SDMA_OP_PTEPDE cmd */
1564         num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1565
1566         /* for IB padding */
1567         num_dw += 64;
1568
1569         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1570         if (r)
1571                 return r;
1572
1573         if (resv) {
1574                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1575                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1576                 if (r) {
1577                         DRM_ERROR("sync failed (%d).\n", r);
1578                         goto error_free;
1579                 }
1580         }
1581
1582         num_pages = bo->tbo.num_pages;
1583         mm_node = bo->tbo.mem.mm_node;
1584
1585         while (num_pages) {
1586                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1587                 uint64_t dst_addr;
1588
1589                 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1590
1591                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1592                 while (byte_count) {
1593                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1594
1595                         amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1596                                         dst_addr, 0,
1597                                         cur_size_in_bytes >> 3, 0,
1598                                         src_data);
1599
1600                         dst_addr += cur_size_in_bytes;
1601                         byte_count -= cur_size_in_bytes;
1602                 }
1603
1604                 num_pages -= mm_node->size;
1605                 ++mm_node;
1606         }
1607
1608         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1609         WARN_ON(job->ibs[0].length_dw > num_dw);
1610         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1611                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1612         if (r)
1613                 goto error_free;
1614
1615         return 0;
1616
1617 error_free:
1618         amdgpu_job_free(job);
1619         return r;
1620 }
1621
1622 #if defined(CONFIG_DEBUG_FS)
1623
1624 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1625 {
1626         struct drm_info_node *node = (struct drm_info_node *)m->private;
1627         unsigned ttm_pl = *(int *)node->info_ent->data;
1628         struct drm_device *dev = node->minor->dev;
1629         struct amdgpu_device *adev = dev->dev_private;
1630         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1631         struct drm_printer p = drm_seq_file_printer(m);
1632
1633         man->func->debug(man, &p);
1634         return 0;
1635 }
1636
1637 static int ttm_pl_vram = TTM_PL_VRAM;
1638 static int ttm_pl_tt = TTM_PL_TT;
1639
1640 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1641         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1642         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1643         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1644 #ifdef CONFIG_SWIOTLB
1645         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1646 #endif
1647 };
1648
1649 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1650                                     size_t size, loff_t *pos)
1651 {
1652         struct amdgpu_device *adev = file_inode(f)->i_private;
1653         ssize_t result = 0;
1654         int r;
1655
1656         if (size & 0x3 || *pos & 0x3)
1657                 return -EINVAL;
1658
1659         if (*pos >= adev->mc.mc_vram_size)
1660                 return -ENXIO;
1661
1662         while (size) {
1663                 unsigned long flags;
1664                 uint32_t value;
1665
1666                 if (*pos >= adev->mc.mc_vram_size)
1667                         return result;
1668
1669                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1670                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1671                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1672                 value = RREG32_NO_KIQ(mmMM_DATA);
1673                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1674
1675                 r = put_user(value, (uint32_t *)buf);
1676                 if (r)
1677                         return r;
1678
1679                 result += 4;
1680                 buf += 4;
1681                 *pos += 4;
1682                 size -= 4;
1683         }
1684
1685         return result;
1686 }
1687
1688 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1689                                     size_t size, loff_t *pos)
1690 {
1691         struct amdgpu_device *adev = file_inode(f)->i_private;
1692         ssize_t result = 0;
1693         int r;
1694
1695         if (size & 0x3 || *pos & 0x3)
1696                 return -EINVAL;
1697
1698         if (*pos >= adev->mc.mc_vram_size)
1699                 return -ENXIO;
1700
1701         while (size) {
1702                 unsigned long flags;
1703                 uint32_t value;
1704
1705                 if (*pos >= adev->mc.mc_vram_size)
1706                         return result;
1707
1708                 r = get_user(value, (uint32_t *)buf);
1709                 if (r)
1710                         return r;
1711
1712                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1713                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1714                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1715                 WREG32_NO_KIQ(mmMM_DATA, value);
1716                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1717
1718                 result += 4;
1719                 buf += 4;
1720                 *pos += 4;
1721                 size -= 4;
1722         }
1723
1724         return result;
1725 }
1726
1727 static const struct file_operations amdgpu_ttm_vram_fops = {
1728         .owner = THIS_MODULE,
1729         .read = amdgpu_ttm_vram_read,
1730         .write = amdgpu_ttm_vram_write,
1731         .llseek = default_llseek,
1732 };
1733
1734 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1735
1736 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1737                                    size_t size, loff_t *pos)
1738 {
1739         struct amdgpu_device *adev = file_inode(f)->i_private;
1740         ssize_t result = 0;
1741         int r;
1742
1743         while (size) {
1744                 loff_t p = *pos / PAGE_SIZE;
1745                 unsigned off = *pos & ~PAGE_MASK;
1746                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1747                 struct page *page;
1748                 void *ptr;
1749
1750                 if (p >= adev->gart.num_cpu_pages)
1751                         return result;
1752
1753                 page = adev->gart.pages[p];
1754                 if (page) {
1755                         ptr = kmap(page);
1756                         ptr += off;
1757
1758                         r = copy_to_user(buf, ptr, cur_size);
1759                         kunmap(adev->gart.pages[p]);
1760                 } else
1761                         r = clear_user(buf, cur_size);
1762
1763                 if (r)
1764                         return -EFAULT;
1765
1766                 result += cur_size;
1767                 buf += cur_size;
1768                 *pos += cur_size;
1769                 size -= cur_size;
1770         }
1771
1772         return result;
1773 }
1774
1775 static const struct file_operations amdgpu_ttm_gtt_fops = {
1776         .owner = THIS_MODULE,
1777         .read = amdgpu_ttm_gtt_read,
1778         .llseek = default_llseek
1779 };
1780
1781 #endif
1782
1783 static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
1784                                    size_t size, loff_t *pos)
1785 {
1786         struct amdgpu_device *adev = file_inode(f)->i_private;
1787         int r;
1788         uint64_t phys;
1789         struct iommu_domain *dom;
1790
1791         // always return 8 bytes
1792         if (size != 8)
1793                 return -EINVAL;
1794
1795         // only accept page addresses
1796         if (*pos & 0xFFF)
1797                 return -EINVAL;
1798
1799         dom = iommu_get_domain_for_dev(adev->dev);
1800         if (dom)
1801                 phys = iommu_iova_to_phys(dom, *pos);
1802         else
1803                 phys = *pos;
1804
1805         r = copy_to_user(buf, &phys, 8);
1806         if (r)
1807                 return -EFAULT;
1808
1809         return 8;
1810 }
1811
1812 static const struct file_operations amdgpu_ttm_iova_fops = {
1813         .owner = THIS_MODULE,
1814         .read = amdgpu_iova_to_phys_read,
1815         .llseek = default_llseek
1816 };
1817
1818 static const struct {
1819         char *name;
1820         const struct file_operations *fops;
1821         int domain;
1822 } ttm_debugfs_entries[] = {
1823         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
1824 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1825         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
1826 #endif
1827         { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
1828 };
1829
1830 #endif
1831
1832 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1833 {
1834 #if defined(CONFIG_DEBUG_FS)
1835         unsigned count;
1836
1837         struct drm_minor *minor = adev->ddev->primary;
1838         struct dentry *ent, *root = minor->debugfs_root;
1839
1840         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
1841                 ent = debugfs_create_file(
1842                                 ttm_debugfs_entries[count].name,
1843                                 S_IFREG | S_IRUGO, root,
1844                                 adev,
1845                                 ttm_debugfs_entries[count].fops);
1846                 if (IS_ERR(ent))
1847                         return PTR_ERR(ent);
1848                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
1849                         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1850                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
1851                         i_size_write(ent->d_inode, adev->mc.gart_size);
1852                 adev->mman.debugfs_entries[count] = ent;
1853         }
1854
1855         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1856
1857 #ifdef CONFIG_SWIOTLB
1858         if (!swiotlb_nr_tbl())
1859                 --count;
1860 #endif
1861
1862         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1863 #else
1864         return 0;
1865 #endif
1866 }
1867
1868 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1869 {
1870 #if defined(CONFIG_DEBUG_FS)
1871         unsigned i;
1872
1873         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
1874                 debugfs_remove(adev->mman.debugfs_entries[i]);
1875 #endif
1876 }