drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40
  41         psp_set_funcs(adev);
  42
  43         return 0;
  44 }
  45
  46 static int psp_sw_init(void *handle)
  47 {
  48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  49         struct psp_context *psp = &adev->psp;
  50         int ret;
  51
  52         switch (adev->asic_type) {
  53         case CHIP_VEGA10:
  54                 psp->init_microcode = psp_v3_1_init_microcode;
  55                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  56                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  57                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  58                 psp->ring_init = psp_v3_1_ring_init;
  59                 psp->ring_create = psp_v3_1_ring_create;
  60                 psp->ring_stop = psp_v3_1_ring_stop;
  61                 psp->ring_destroy = psp_v3_1_ring_destroy;
  62                 psp->cmd_submit = psp_v3_1_cmd_submit;
  63                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  64                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  65                 psp->mode1_reset = psp_v3_1_mode1_reset;
  66                 break;
  67         case CHIP_RAVEN:
  68                 psp->init_microcode = psp_v10_0_init_microcode;
  69                 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
  70                 psp->ring_init = psp_v10_0_ring_init;
  71                 psp->ring_create = psp_v10_0_ring_create;
  72                 psp->ring_stop = psp_v10_0_ring_stop;
  73                 psp->ring_destroy = psp_v10_0_ring_destroy;
  74                 psp->cmd_submit = psp_v10_0_cmd_submit;
  75                 psp->compare_sram_data = psp_v10_0_compare_sram_data;
  76                 psp->mode1_reset = psp_v10_0_mode1_reset;
  77                 break;
  78         default:
  79                 return -EINVAL;
  80         }
  81
  82         psp->adev = adev;
  83
  84         ret = psp_init_microcode(psp);
  85         if (ret) {
  86                 DRM_ERROR("Failed to load psp firmware!\n");
  87                 return ret;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int psp_sw_fini(void *handle)
  94 {
  95         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  96
  97         release_firmware(adev->psp.sos_fw);
  98         adev->psp.sos_fw = NULL;
  99         release_firmware(adev->psp.asd_fw);
 100         adev->psp.asd_fw = NULL;
 101         return 0;
 102 }
 103
 104 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 105                  uint32_t reg_val, uint32_t mask, bool check_changed)
 106 {
 107         uint32_t val;
 108         int i;
 109         struct amdgpu_device *adev = psp->adev;
 110
 111         for (i = 0; i < adev->usec_timeout; i++) {
 112                 val = RREG32(reg_index);
 113                 if (check_changed) {
 114                         if (val != reg_val)
 115                                 return 0;
 116                 } else {
 117                         if ((val & mask) == reg_val)
 118                                 return 0;
 119                 }
 120                 udelay(1);
 121         }
 122
 123         return -ETIME;
 124 }
 125
 126 static int
 127 psp_cmd_submit_buf(struct psp_context *psp,
 128                    struct amdgpu_firmware_info *ucode,
 129                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 130                    int index)
 131 {
 132         int ret;
 133
 134         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 135
 136         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 137
 138         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 139                              fence_mc_addr, index);
 140
 141         while (*((unsigned int *)psp->fence_buf) != index) {
 142                 msleep(1);
 143         }
 144
 145         return ret;
 146 }
 147
 148 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 149                                  uint64_t tmr_mc, uint32_t size)
 150 {
 151         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 152         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 153         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 154         cmd->cmd.cmd_setup_tmr.buf_size = size;
 155 }
 156
 157 /* Set up Trusted Memory Region */
 158 static int psp_tmr_init(struct psp_context *psp)
 159 {
 160         int ret;
 161
 162         /*
 163          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 164          * physical).
 165          *
 166          * Note: this memory need be reserved till the driver
 167          * uninitializes.
 168          */
 169         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 170                                       AMDGPU_GEM_DOMAIN_VRAM,
 171                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 172
 173         return ret;
 174 }
 175
 176 static int psp_tmr_load(struct psp_context *psp)
 177 {
 178         int ret;
 179         struct psp_gfx_cmd_resp *cmd;
 180
 181         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 182         if (!cmd)
 183                 return -ENOMEM;
 184
 185         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 186
 187         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 188                                  psp->fence_buf_mc_addr, 1);
 189         if (ret)
 190                 goto failed;
 191
 192         kfree(cmd);
 193
 194         return 0;
 195
 196 failed:
 197         kfree(cmd);
 198         return ret;
 199 }
 200
 201 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 202                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 203                                  uint32_t size, uint32_t shared_size)
 204 {
 205         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 206         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 207         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 208         cmd->cmd.cmd_load_ta.app_len = size;
 209
 210         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 211         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 212         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 213 }
 214
 215 static int psp_asd_init(struct psp_context *psp)
 216 {
 217         int ret;
 218
 219         /*
 220          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 221          * physical) for shared ASD <-> Driver
 222          */
 223         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 224                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 225                                       &psp->asd_shared_bo,
 226                                       &psp->asd_shared_mc_addr,
 227                                       &psp->asd_shared_buf);
 228
 229         return ret;
 230 }
 231
 232 static int psp_asd_load(struct psp_context *psp)
 233 {
 234         int ret;
 235         struct psp_gfx_cmd_resp *cmd;
 236
 237         /* If PSP version doesn't match ASD version, asd loading will be failed.
 238          * add workaround to bypass it for sriov now.
 239          * TODO: add version check to make it common
 240          */
 241         if (amdgpu_sriov_vf(psp->adev))
 242                 return 0;
 243
 244         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 245         if (!cmd)
 246                 return -ENOMEM;
 247
 248         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 249         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 250
 251         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 252                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 253
 254         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 255                                  psp->fence_buf_mc_addr, 2);
 256
 257         kfree(cmd);
 258
 259         return ret;
 260 }
 261
 262 static int psp_hw_start(struct psp_context *psp)
 263 {
 264         struct amdgpu_device *adev = psp->adev;
 265         int ret;
 266
 267         if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
 268                 ret = psp_bootloader_load_sysdrv(psp);
 269                 if (ret)
 270                         return ret;
 271
 272                 ret = psp_bootloader_load_sos(psp);
 273                 if (ret)
 274                         return ret;
 275         }
 276
 277         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 278         if (ret)
 279                 return ret;
 280
 281         ret = psp_tmr_load(psp);
 282         if (ret)
 283                 return ret;
 284
 285         ret = psp_asd_load(psp);
 286         if (ret)
 287                 return ret;
 288
 289         return 0;
 290 }
 291
 292 static int psp_np_fw_load(struct psp_context *psp)
 293 {
 294         int i, ret;
 295         struct amdgpu_firmware_info *ucode;
 296         struct amdgpu_device* adev = psp->adev;
 297
 298         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 299                 ucode = &adev->firmware.ucode[i];
 300                 if (!ucode->fw)
 301                         continue;
 302
 303                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 304                     psp_smu_reload_quirk(psp))
 305                         continue;
 306                 if (amdgpu_sriov_vf(adev) &&
 307                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 308                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 309                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 310                         /*skip ucode loading in SRIOV VF */
 311                         continue;
 312
 313                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 314                 if (ret)
 315                         return ret;
 316
 317                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 318                                          psp->fence_buf_mc_addr, i + 3);
 319                 if (ret)
 320                         return ret;
 321
 322 #if 0
 323                 /* check if firmware loaded sucessfully */
 324                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 325                         return -EINVAL;
 326 #endif
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int psp_load_fw(struct amdgpu_device *adev)
 333 {
 334         int ret;
 335         struct psp_context *psp = &adev->psp;
 336
 337         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 338         if (!psp->cmd)
 339                 return -ENOMEM;
 340
 341         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 342                                       AMDGPU_GEM_DOMAIN_GTT,
 343                                       &psp->fw_pri_bo,
 344                                       &psp->fw_pri_mc_addr,
 345                                       &psp->fw_pri_buf);
 346         if (ret)
 347                 goto failed;
 348
 349         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 350                                       AMDGPU_GEM_DOMAIN_VRAM,
 351                                       &psp->fence_buf_bo,
 352                                       &psp->fence_buf_mc_addr,
 353                                       &psp->fence_buf);
 354         if (ret)
 355                 goto failed_mem2;
 356
 357         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 358                                       AMDGPU_GEM_DOMAIN_VRAM,
 359                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 360                                       (void **)&psp->cmd_buf_mem);
 361         if (ret)
 362                 goto failed_mem1;
 363
 364         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 365
 366         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 367         if (ret)
 368                 goto failed_mem;
 369
 370         ret = psp_tmr_init(psp);
 371         if (ret)
 372                 goto failed_mem;
 373
 374         ret = psp_asd_init(psp);
 375         if (ret)
 376                 goto failed_mem;
 377
 378         ret = psp_hw_start(psp);
 379         if (ret)
 380                 goto failed_mem;
 381
 382         ret = psp_np_fw_load(psp);
 383         if (ret)
 384                 goto failed_mem;
 385
 386         return 0;
 387
 388 failed_mem:
 389         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 390                               &psp->cmd_buf_mc_addr,
 391                               (void **)&psp->cmd_buf_mem);
 392 failed_mem1:
 393         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 394                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 395 failed_mem2:
 396         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 397                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 398 failed:
 399         kfree(psp->cmd);
 400         psp->cmd = NULL;
 401         return ret;
 402 }
 403
 404 static int psp_hw_init(void *handle)
 405 {
 406         int ret;
 407         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 408
 409
 410         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 411                 return 0;
 412
 413         mutex_lock(&adev->firmware.mutex);
 414
 415         ret = psp_load_fw(adev);
 416         if (ret) {
 417                 DRM_ERROR("PSP firmware loading failed\n");
 418                 goto failed;
 419         }
 420
 421         mutex_unlock(&adev->firmware.mutex);
 422         return 0;
 423
 424 failed:
 425         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 426         mutex_unlock(&adev->firmware.mutex);
 427         return -EINVAL;
 428 }
 429
 430 static int psp_hw_fini(void *handle)
 431 {
 432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 433         struct psp_context *psp = &adev->psp;
 434
 435         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 436                 return 0;
 437
 438         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 439
 440         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 441         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 442                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 443         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 444                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 445         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 446                               &psp->asd_shared_buf);
 447         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 448                               (void **)&psp->cmd_buf_mem);
 449
 450         kfree(psp->cmd);
 451         psp->cmd = NULL;
 452
 453         return 0;
 454 }
 455
 456 static int psp_suspend(void *handle)
 457 {
 458         int ret;
 459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 460         struct psp_context *psp = &adev->psp;
 461
 462         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 463         if (ret) {
 464                 DRM_ERROR("PSP ring stop failed\n");
 465                 return ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int psp_resume(void *handle)
 472 {
 473         int ret;
 474         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 475         struct psp_context *psp = &adev->psp;
 476
 477         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 478                 return 0;
 479
 480         DRM_INFO("PSP is resuming...\n");
 481
 482         mutex_lock(&adev->firmware.mutex);
 483
 484         ret = psp_hw_start(psp);
 485         if (ret)
 486                 goto failed;
 487
 488         ret = psp_np_fw_load(psp);
 489         if (ret)
 490                 goto failed;
 491
 492         mutex_unlock(&adev->firmware.mutex);
 493
 494         return 0;
 495
 496 failed:
 497         DRM_ERROR("PSP resume failed\n");
 498         mutex_unlock(&adev->firmware.mutex);
 499         return ret;
 500 }
 501
 502 static bool psp_check_reset(void* handle)
 503 {
 504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 505
 506         if (adev->flags & AMD_IS_APU)
 507                 return true;
 508
 509         return false;
 510 }
 511
 512 static int psp_reset(void* handle)
 513 {
 514         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 515         return psp_mode1_reset(&adev->psp);
 516 }
 517
 518 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 519                                         enum AMDGPU_UCODE_ID ucode_type)
 520 {
 521         struct amdgpu_firmware_info *ucode = NULL;
 522
 523         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 524                 DRM_INFO("firmware is not loaded by PSP\n");
 525                 return true;
 526         }
 527
 528         if (!adev->firmware.fw_size)
 529                 return false;
 530
 531         ucode = &adev->firmware.ucode[ucode_type];
 532         if (!ucode->fw || !ucode->ucode_size)
 533                 return false;
 534
 535         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 536 }
 537
 538 static int psp_set_clockgating_state(void *handle,
 539                                      enum amd_clockgating_state state)
 540 {
 541         return 0;
 542 }
 543
 544 static int psp_set_powergating_state(void *handle,
 545                                      enum amd_powergating_state state)
 546 {
 547         return 0;
 548 }
 549
 550 const struct amd_ip_funcs psp_ip_funcs = {
 551         .name = "psp",
 552         .early_init = psp_early_init,
 553         .late_init = NULL,
 554         .sw_init = psp_sw_init,
 555         .sw_fini = psp_sw_fini,
 556         .hw_init = psp_hw_init,
 557         .hw_fini = psp_hw_fini,
 558         .suspend = psp_suspend,
 559         .resume = psp_resume,
 560         .is_idle = NULL,
 561         .check_soft_reset = psp_check_reset,
 562         .wait_for_idle = NULL,
 563         .soft_reset = psp_reset,
 564         .set_clockgating_state = psp_set_clockgating_state,
 565         .set_powergating_state = psp_set_powergating_state,
 566 };
 567
 568 static const struct amdgpu_psp_funcs psp_funcs = {
 569         .check_fw_loading_status = psp_check_fw_loading_status,
 570 };
 571
 572 static void psp_set_funcs(struct amdgpu_device *adev)
 573 {
 574         if (NULL == adev->firmware.funcs)
 575                 adev->firmware.funcs = &psp_funcs;
 576 }
 577
 578 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 579 {
 580         .type = AMD_IP_BLOCK_TYPE_PSP,
 581         .major = 3,
 582         .minor = 1,
 583         .rev = 0,
 584         .funcs = &psp_ip_funcs,
 585 };
 586
 587 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 588 {
 589         .type = AMD_IP_BLOCK_TYPE_PSP,
 590         .major = 10,
 591         .minor = 0,
 592         .rev = 0,
 593         .funcs = &psp_ip_funcs,
 594 };